JP6451426B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  To reduce the size and increase the functionality of electronic devices, research and development of three-dimensional mounting semiconductor technology for mounting chip-shaped semiconductor devices in three dimensions has progressed, and through-silicon vias (TSV) suitable for three-dimensional mounting have been developed. Via) is known. The TSV has a structure in which high integration can be realized by stacking by electrically connecting the circuits on the front and back surfaces with vias penetrating the silicon chip and joining the semiconductor devices with micro bumps or the like.

  In addition, since the electrode pads appearing on the surface of the semiconductor device become narrower with higher integration, C4 (having a diameter of about 80 μm to 100 μm as a member for connecting the electrodes of two semiconductor devices connected to face each other ( It is desired to use solder bumps called “Controlled Collapse Chip Connection”.

  The electrode pad to which the solder bump is connected is preferably formed of a material having good wettability with respect to the solder in order to increase the connection area with the solder. Furthermore, when the volume of the electrode is small while the volume of the solder is large, it is preferable that a barrier layer is interposed to suppress the generation of these alloys. In addition, the wiring and the electrode pad connected to the wiring are preferably formed from a low-resistance metal material.

  Although there is aluminum as a low-resistance metal material, the wettability may not be good depending on the selected solder material, so use a two-layer structure of metal-coated thin film and under bump metal film as the electrode pad structure. It has been known. The metal coating film is formed in a shape that exposes the surface of the substrate from a part thereof, and is covered with an under bump metal film from above. The under bump metal coating covers the metal coating film and covers the substrate through a part of the metal coating film. As an example of such an under bump metallization, there is a structure in which a titanium adhesion layer, a platinum diffusion barrier layer, and a gold layer are sequentially laminated on a substrate. In the structure, the gold layer is made of a solder material and a material having good wettability.

  Further, when wiring boards having different thermal expansion coefficients are joined together, the solder balls connected between the electrode pads are likely to generate cracks, progress, and break due to temperature changes. In order to prevent the occurrence of cracks, etc., a structure is known in which the electrode pads on the wiring board are separated into a plurality of pad portions, the pad portions are arranged in a ring shape, and the solder balls are supported by these pad portions. Yes. In this case, each pad portion is formed in a raised shape, and a region surrounded by the pad portions is lower than the upper surface of each pad portion.

  According to such an electrode pad structure, the solder balls are repelled by the insulating film at the center of the plurality of pad portions and soldered across the plurality of pad portions. In this case, since the lowermost end portion of the solder ball is lower than the upper surface of each pad portion, the solder ball is fitted into each pad portion, and is strong in lateral strength. Further, since the thermal stress is dispersed in each pad portion, the solder ball is hardly cracked.

JP, 2014-239118, A JP 2004-188497 A JP 2008-537636 A JP 10-303330 A

  As described above, in the structure in which the electrode pad is divided into a plurality of pad portions, separated and arranged in a ring shape, and the solder ball is lifted by the pad portion, the connection area between the solder ball and the electrode pad is small. Connection resistance increases. Furthermore, since the solder ball can only be joined to an electrode of its own size, it becomes impossible to reduce the amount of solder to expand and reduce the connection resistance.

  An object of the present invention is to provide a semiconductor device capable of preventing a decrease in connection resistance between a solder and an electrode pad in a structure in which the electrode pad is divided, and a manufacturing method thereof.

According to one aspect of the present embodiment, the first surface side electrode pad formed on the first surface side of the semiconductor substrate and the second surface side of the semiconductor substrate are different from the first surface side electrode pad. A split electrode pad having a plurality of split electrodes formed through slits and an insulating film formed on the second surface side of the semiconductor substrate and having an opening exposing the split electrode pads; , Formed in at least an edge portion of the plurality of divided electrodes of the divided electrode pad that is exposed from the opening of the insulating film and on a side partitioned by the slits, and from the plurality of divided electrodes to the solder. a metal coating formed from wettable material, through the opening, the semiconductor device is provided of having a solder which is formed on at least said metal coating of the metal coating and the split electrode pads That.
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention.

  According to this embodiment, it is possible to prevent a decrease in the connection resistance between the solder and the electrode pad in the structure in which the electrode pad is divided.

FIG. 1A to FIG. 1C are cross-sectional views illustrating manufacturing processes of a semiconductor device according to the embodiment. 2A and 2B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment. 3A and 3B are cross-sectional views illustrating the manufacturing process of the semiconductor device according to the embodiment. 4A and 4B are cross-sectional views illustrating the manufacturing process of the semiconductor device according to the embodiment. FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment. FIGS. 6A1 to 6A3 and 6B1 to 6B3 are a plan view and a cross-sectional view illustrating a divided electrode pad forming process in the manufacturing process of the semiconductor device according to the embodiment. 7A1 to 7A3 and 7B1 to 7B3 are a plan view and a cross-sectional view illustrating a step of forming a divided electrode pad in the manufacturing process of the semiconductor device according to the embodiment. FIGS. 8A1 to 8A3 and 8B1 to 8B3 are a plan view and a cross-sectional view illustrating a divided electrode pad forming process and a solder bump connecting process in the manufacturing process of the semiconductor device according to the embodiment. is there. FIGS. 9A and 9B are a plan view and a cross-sectional view showing a modification of the semiconductor device according to the embodiment. FIG. 10 is a plan view and a cross-sectional view illustrating a semiconductor device according to a comparative example. FIGS. 11A to 11C are plan views illustrating modifications of the divided electrode pad of the semiconductor device according to the embodiment.

  Embodiments will be described below with reference to the drawings. In the drawings, similar components are given the same reference numerals.

1 to 5 are cross-sectional views showing the manufacturing process of the semiconductor device according to this embodiment.
Next, steps required until a structure shown in FIG.

  First, the first surface 1a of the silicon wafer 1, which is a semiconductor substrate, is subjected to processing such as film formation, photolithography, etching, ion implantation, etc., so that a semiconductor integrated circuit (not shown) is provided in the surface direction on the first surface 1a side. Repeatedly formed. Further, a plurality of through-silicon vias (TSV) 2 are formed from the first surface 1a to the second surface 1b of the silicon wafer 1 at intervals.

  A plurality of TSVs 2 are formed, for example, after a MOS transistor (not shown) serving as a semiconductor integrated circuit is formed on the first surface 1a side of the silicon wafer 1 and before or during wiring formation. ) Method. TSV2 may be a via last method after a semiconductor integrated circuit is formed.

  The TSV 2 is formed, for example, by forming a via hole 1h from the first surface 1a to the second surface 1b of the silicon wafer 1 and then embedding a conductive material, for example, copper (Cu) therein by plating or the like. For example, via holes 1h are formed halfway up to the second surface 1b by reactive ion etching or the like, and the inner peripheral surface and bottom surface of the via holes 1h are covered with a Cu diffusion prevention insulating layer (not shown), and then Cu is contained therein. Embed. The thickness of the silicon wafer 1 is, for example, about 775 μm when the wafer diameter is 300 mm in the initial state, and the diameter of the via hole 1 h formed therein is, for example, about 5 μm and the depth is about 55 μm.

  The conductive material formed on the first surface 1a simultaneously with the via hole 1h of the silicon wafer 1 is removed by chemical mechanical polishing (CMP) or the like. In this way, when removing the conductive material on the first surface 1a, the first end of the TSV 2 is slightly exposed from the first surface 1a of the silicon wafer 1.

  Thereafter, the multilayer wiring structure 4 is formed on the first surface 1a of the silicon wafer 1, and a plurality of electrode pads 3a and 3b exposed from the uppermost insulating film are formed. The plurality of electrode pads 3a and 3b are formed, for example, in a square planar shape having a side of about 50 μm, and a part of the group of electrode pads 3a is arranged at a pitch of about 80 μm, for example. The electrode pads 3a and 3b are exposed from a protective insulating film 5 formed on the multilayer wiring structure 4, for example, an opening 5a of a polyimide film.

  Next, as shown in FIG. 1B, micro bumps 6 are formed on each of the electrode pads 3 a and 3 b on the first surface 1 a side of the silicon wafer 1. These micro bumps 6 are formed with a plane diameter of, for example, about 40 μm and a pitch of, for example, about 80 μm.

For example, the micro bump 6 uses a resist mask (not shown), and a columnar Cu protrusion layer 6a having a protrusion amount of about 20 μm and a thickness of 15 μm on the electrode pads 3a and 3b via a Ti film (not shown). The solder layer 6b has a two-layer structure. The Cu protrusion layer 6a is formed by, for example, an electrolytic plating method, and the solder layer 6b is formed by, for example, a plating method or the like from SnAg (tin silver), SnAgCu (tin silver copper) or the like on the Cu protrusion layer 6a. Rounded by reflow. A nickel (Ni) layer may be formed between the Cu electrode pads 3a and 3b and the solder layer 6b, and a gold (Au) layer may be formed on the solder layer 6b.

  Next, as shown in FIG. 1C, the silicon wafer 1 is attached to a support wafer 51 formed of silicon, glass or the like via a temporary adhesive 52. In this case, the micro bumps 6 on the first surface 1a side of the silicon wafer 1 are attached so as to bite into the temporary adhesive 52, and the second surface 1b of the silicon wafer 1 is exposed.

Next, steps required until a structure shown in FIG.
First, the second surface 1b of the silicon wafer 1 is polished by, for example, a CMP method to reduce the thickness of about 775 μm to about 50 μm. The thinning is performed until just before the Cu diffusion prevention insulating layer (not shown) formed at the bottom of the via hole 1h is exposed, and then the second surface 1b of the silicon wafer 1 is etched back by etching, and the second TSV2 is etched. The two ends are slightly protruded. Further, in order to prevent diffusion of Cu from TSV 2 to the silicon wafer 1, an inorganic insulating film such as a silicon oxide film or a silicon nitride film or an organic insulating film such as benzocyclobutene (BCB) as the Cu diffusion preventing insulating film 7. Form. Thereafter, a portion of the diffusion preventing insulating film 7 protruding above the TSV2 is polished by CMP or the like to expose the second end of the TSV2.

  Next, as shown in FIGS. 2B and 3A, electrode pads 13 and 14 connected to the second end of the TSV 2 are formed on the Cu diffusion preventing insulating film 7. The electrode pads 13 and 14 are wider than the electrode pads 3a and 3b on the first surface 1a side, and are formed by, for example, the following semi-additive (SAP) method.

  First, as shown in the cross section of FIG. 2B, a titanium (Ti) adhesion layer 8 is formed to a thickness of, for example, about 0.1 μm on the Cu diffusion preventing insulating film 7 by sputtering, and a Cu seed layer is further formed. For example, 9 is formed to a thickness of about 0.2 μm. Subsequently, a photoresist is applied on the Cu seed layer 9, and exposure, development, and the like are applied to the photoresist to expose the second ends of the plurality of TSVs 2 and the periphery thereof, and a plurality of electrode forming openings 11, 12 are exposed. A resist pattern 10 having the following is formed.

  As illustrated in the plane of FIG. 6A1 and the cross section of FIG. 6B1, some of the plurality of electrode forming openings 11 are divided into four plane shapes by the cross-shaped resist portions 10a. It has the division | segmentation opening parts 11a-11d. In FIG. 6 and FIGS. 7 and 8 described later, (b1) to (b3) indicate cross sections taken along the line II shown in (a1).

  Each of the four polarization openings 11a to 11d is formed at a position above the different TSV2. Further, the electrode forming opening 12 that is not divided is formed, for example, in a size that overlaps the second ends of the plurality of TSVs 2. The electrode forming openings 11 having the divided openings 11a to 11d are formed in a region where the electrode pad density is high, and the electrode forming openings 12 which are not divided are formed in a region where the electrode pad density is low. Also good. Each of the divided openings 11a to 11d is formed and connected on one different TSV2, but each may be formed and connected on a plurality of TSV2.

  After the resist pattern 10 is formed, a plurality of electrode openings of the resist pattern 10 are illustrated in the cross-sectional views of FIGS. 3A and 6B2 and the plan view of FIG. 6A2. A Cu film having a thickness of about 5 μm is formed on the Cu seed layer 9 exposed from 11 and 12 by electrolytic plating. In this case, as shown in FIG. 6 (a2), Cu films are individually formed in the four divided openings 11a to 11d partitioned by the cross-shaped resist portion 10a.

  As a result, the Cu films formed in the four divided openings 11a to 11d of the electrode opening 11 are used as the divided electrodes 13a to 13d, respectively, which are adjacent to each other through the cross-shaped slit. Each of the plurality of divided electrodes 13a to 13d is connected to a different TSV2, thereby forming a divided electrode pad 13. Further, a Cu film formed in the electrode opening 12 that is not divided is used as the non-divided electrode pad 14. Note that all electrode pads formed on the second surface 1 b of the silicon wafer 1 may be divided electrode pads 13. In this step, a wiring opening (not shown) may be formed in the resist pattern 10, and a wiring (not shown) may be formed on the Cu diffusion preventing insulating film 7.

  Next, as shown in FIGS. 6A3 and 6B3, the resist pattern 10 is removed. Thereafter, as shown in FIGS. 7A1 and 7B1, the divided electrode pad 13, the non-divided pad 14, the wiring (not shown), and the like are used as a mask, thereby the Cu seed layer 9 and the Ti adhesion layer 8 are used. Are removed by etching. During this etching, the Cu film which becomes the electric divided electrode pad 13, the non-divided electrode pad 14, the wiring (not shown) and the like is thinned, and it is preferable that the film thickness is determined in advance so as to allow for this. Note that the Cu seed layer 9 and the Ti adhesion layer 8 that remain under the divided electrode pad 13 and the non-divided electrode pad 14 become a part of the divided electrode pad 13 and the non-divided pad 14. Omitted.

  Thus, the divided electrode pad 13 is formed from divided electrodes 13a to 13d that are physically divided into four through a cross-shaped slit 13e, and each of the divided electrodes 13a to 13d is connected to a different TSV2. Has been. The Cu diffusion preventing insulating film 7 is exposed from the slit 13e.

Next, steps required until a structure shown in FIG.
First, as shown in FIGS. 7A2 and 7B2, a photoresist is applied on the Cu diffusion preventing insulating film 7, the divided electrode pad 13 and the non-divided electrode pad 14 on the second surface 1 b side of the silicon wafer 1. The resist pattern 16 is formed by coating and exposing and developing the coating. The resist pattern 16 has an opening 16 a on each of the divided electrode pad 13 and the non-divided electrode pad 14.

  The opening 16a is designed to have a position and a size that do not expose the outer peripheral edges of the divided electrode pad 13 and the non-divided electrode pad 14. Further, the opening 16a on the divided electrode pad 13 includes, for example, a circular portion that overlaps the divided pads 13a to 13d at the center and the periphery of the slit 13e, and the divided electrodes 13a to 13d from the portion along the slit 13e. A part of is exposed in a cross shape.

Next, an under bump metal film 17 is formed on the exposed surface of the divided electrode pad 13 and the non-divided pad 14 from the opening 16a. As shown in FIGS. 7A3 and 7B3, the under bump metal film 17 completely fills the slits 13e of the divided electrodes 13a to 13d in the divided electrode pad 13 having the plurality of divided electrodes 13a to 13d. Moreover, it is also formed on the side surfaces of the divided electrodes 13a to 13d exposed from the opening 16a. Similarly, an under bump metal film 17 is formed on the non-divided electrode pad 14.

  The under bump metal film 17 is formed of a material having better wettability than the material of the divided electrode pad 13 and the non-divided pad 14, improves the wettability of solder bumps to be connected later, and the divided electrode pad 13 and the non-divided electrode pad. 14 and formed to prevent solder diffusion to TSV2. Further, the under bump metal film 17 is not formed on the resist pattern 16 and in the central portion of the slit 13e, but is selectively formed on the upper surface and side surfaces of the divided electrode pad 13 and the non-divided electrode pad 14 in the portion exposed from the opening 16a. The materials and methods formed are used.

  The under bump metal film 17 is formed by, for example, an electroless plating method that is selectively formed on the exposed portions of the divided electrode pads 13 and the non-divided pads 14. Examples of the under bump metal film 17 include a structure in which an Au film having a thickness of about 0.05 μm is formed on a NiP film having a thickness of about 3 μm, and a structure in which palladium (Pd) is interposed between these films. . Further, there are a structure in which a Pd film is formed on a NiP film, a structure in which an Au film is formed on a NiB film, and a single structure of a NiB film. When using the electrolytic plating method, after forming a Ni adhesion film (not shown) and a Cu seed film (not shown) on the Cu diffusion preventing insulating film 7, the divided electrode pad 13, and the non-divided pad 14, for example, FIG. 6 is formed by the SAP method using a resist pattern (not shown) having substantially the same shape as the resist pattern 10 shown in FIG.

  Accordingly, as shown in FIGS. 7A3 and 7B3, in the divided electrode pad 13, the upper surface and the side edge of the portion of the four divided electrodes 13 a to 13 d exposed from the opening 16 a of the resist pattern 16 are formed. Under bump metal film 17 is formed. Further, the under bump metal film 17 is also formed on the side surfaces of the polarization electrodes 13a to 13d partially exposed from the slit 13e extending in four directions from the circular portion at the center of the opening 16a, and the width thereof is narrowed. Thus, the Cu diffusion preventing insulating film 7 remains exposed from the slit 13e. Thereafter, the resist pattern 16 is removed.

  Next, as shown in FIGS. 8A1 and 8B1, a protective insulating film 15 is formed on the insulating film 7 for preventing Cu diffusion, the divided electrode pad 13, and the non-divided electrode pad 14 to a thickness of about 10 μm, for example. Form. As the protective insulating film 15, a material obtained by applying an organic material such as PBO, polyimide (PI), phenol resin (PF) or the like to the second surface 1 b side of the silicon wafer 1 and thermosetting it is used. Note that an inorganic material film such as silicon oxide or silicon nitride may be formed as the protective insulating film 15.

  Furthermore, a photoresist is applied on the protective insulating film 15, and exposure, development, and the like are applied thereto, thereby exposing the divided electrode pads 13 and the non-divided electrode pads 14 on the second surface 1b side of the silicon wafer 1. A resist pattern 20 having a portion 20a is formed. The opening 20a in this case is formed in the same shape as the opening 16a of the resist pattern 16 shown in FIGS. 7 (a2) and (b2).

  Thereafter, the protective insulating film 15 is etched using the resist pattern 20 as a mask to expose part of the divided electrode pad 13 and the non-divided electrode pad 14 through the opening 20a, and then the resist pattern 20 is removed. Thereby, as shown in FIG. 3B, FIG. 8A2 and FIG. 8B2, on the divided electrode pad 13, a part of the four divided electrodes 13a to 13d around the central portion of the slit 13e and the periphery thereof. The protective insulating film 15 is formed with a circular portion that exposes and an opening 15a having a cross-shaped extending portion from the portion along the slit 13e. In the non-divided electrode pad 14, an opening 15 b that exposes a part thereof is formed in the protective insulating film 15. Note that a photosensitive resin may be used as the protective insulating film 15. In this case, the openings 15 a and 15 b are formed in the protective insulating film 15 by performing the same exposure, development, and the like as the photoresist 20.

  By the way, the protective insulating film 15 is used as a mask instead of the resist pattern 16, and the electroless plating or the like is performed on the divided electrode pads 13 and the non-divided pads 14 exposed from the openings 15a and 15b in the same manner as described above. The under bump metal film 17 may be formed by a method. Also in this case, the under bump metal film 17 is used for preventing Cu diffusion without completely filling the slit 13e between the adjacent divided electrodes 13a to 13d in the divided electrode pad 13 including the plurality of divided electrodes 13a to 13d. It is formed on the side surfaces of the divided electrodes 13a to 13d so as to expose the insulating film 7.

  Next, as illustrated in FIG. 4A, after the second surface 1 b of the silicon wafer 1 is attached to a dicing tape (not shown), the silicon wafer 1 is peeled from the temporary adhesive 52 of the support wafer 51. . Thereafter, the semiconductor chip 1C on which the semiconductor integrated circuit is formed is formed by using a dicing saw along a dicing line (not shown) that partitions the plurality of semiconductor integrated circuits formed on the silicon wafer 1. Thereafter, the semiconductor chip is peeled off from the dicing tape (not shown) using a pickup device (not shown).

  Next, a second semiconductor chip 61 on which a semiconductor integrated circuit is formed and having second micro bumps 64 is prepared. The second micro bump 64 has, for example, a stacked structure of an electrode pad film 62 and a solder film 63, like the micro bump 6 of the first semiconductor chip 1C. Then, the first micro bump 6 of the first semiconductor chip 1C and the second micro bump 64 of the second semiconductor chip 61 are temporarily joined by a bonder (not shown).

Next, steps required until a structure shown in FIG.
First, in a reflow furnace (not shown), for example, the first micro bump 1c and the second micro bump 64 are bonded at 250 ° C. for 5 minutes. As a result, the first semiconductor chip 1C and the second semiconductor chip 61 are electrically and mechanically connected. Further, the underfill 65 is supplied between the first semiconductor chip 1C and the second semiconductor chip 61, and the underfill 65 is solidified by heating, for example, at about 150 ° C. for 3 minutes.

Next, the divided electrode pads 13 and the non-divided electrode pads 14 of the first semiconductor chip 1C are connected to the electrode pads 68 of the package substrate 67 via the C4 solder bumps 18. In this case, the diameter _{D 1} of the solder bumps 18 of C4 is greater than the solder layer 6b of the micro bumps 6 of the first surface 1a side, and the widest of the respective divided electrodes 13a~13d connected thereto mutual TSV2 interval distance _{D 2} is smaller than the diameter, for example of about 100 [mu] m, joining the reflow furnace split electrode pads 13 and the solder bumps 18 under the conditions of 5 minutes at for example 250 ° C. (not shown), the non-split electrode pads 14 and the solder bumps 18.

  The molten solder bump 18 is spread and joined on the surface of the under bump metal film 17 on the divided electrode pad 13 and the non-divided electrode pad 14. In particular, in the divided electrode pad 13, as shown in FIGS. 8A3 and 8B3, an under bump metal film 17 is formed to extend outward from the central portion on the edge of the divided electrodes 13a to 13d. Therefore, the solder bump 18 spreads along the slits 13e of the four divided electrodes 13a to 13d.

  Further, as shown in FIGS. 9A and 9B, the opening 15a of the protective insulating film 15 on the four divided electrodes 13a to 13d is made, for example, substantially circular, and the surrounding slit 13e is formed in the protective insulating film 15. You may make it the shape covered by. According to this structure, the solder bump 18 enters between the organic insulating film 15 and the under bump metal film 17 when melted, and spreads outward of the four divided electrodes 13a to 13d. Thereby, the electrical connection area of the solder bump 18 and the divided electrode pad 13 is widened, and the electrical connection resistance can be reduced. FIG. 9B is a sectional view taken along line III-III in FIG.

  As described above, according to the present embodiment, at least a part of the electrode pads 13 and 14 connected to the plurality of TSVs 2 is separated into the plurality of divided electrodes 13a to 13d by the slit 13e. Forming. Furthermore, an under bump metal film 17 is selectively formed on an edge portion of the plurality of divided electrodes 13a to 13d facing each other with the slit 13e interposed therebetween.

  For this reason, the solder bump 18 bonded to the divided electrode pad 13 spreads along the slits 13e of the divided electrodes 13a to 13d when melted, and the protrusion and deformation due to the spread of the solder bump 18 are reduced. Will be better. Moreover, since the TSV2 is connected to each of the divided electrodes 13a to 13d, current concentration at the solder bumps 18 can be avoided.

  Further, as shown in FIG. 9, after the under bump metal film 17 is formed along the edges facing each other in the divided electrodes 13 a to 13 d forming the divided electrode pad 13, the outer peripheral edge portion of the divided electrode pad 13 is formed. It is covered with a protective insulating film 15 made of an organic insulating material. In this structure, since the melted solder bump 18 enters between the protective insulating film 15 and the under bump metal film 17, the divided electrodes 13 a to 13 d and the solder are prevented from leaking outside the divided electrode pad 13. The connection area of the bump 18 can be increased.

  By the way, in the comparative example shown in FIG. 10, all of the second surface 1 b side of the silicon wafer 1 thinned to about 50 μm is the non-divided electrode pad 14. For this reason, the total area of the electrode pads 14 on the second surface 1b side is larger than that of the electrode pads 3a and 3b on the first surface 1a side as compared with the present embodiment. For this reason, the thin silicon wafer 1 is likely to warp when the solder bumps 18 are joined due to the difference in thermal expansion coefficient between the silicon wafer 1 and the non-divided electrode pad 14. When such warpage occurs, the first surface 1a on the side where the microbumps 6 are formed is curved outward, for example, so that the microbumps 6 and the microbumps 64 of the second semiconductor chip 61 as described above are positioned. Deviation occurs, making them difficult to join.

  On the other hand, in this embodiment, since the divided electrode pad 13 is formed on the second surface 1b side, the difference in thermal expansion between the divided electrode pad 13 and the silicon wafer 1 is absorbed by the slits 13e of the divided electrodes 13a to 13d, In addition, since the difference in electrode formation area with the electrode pads 3a and 3b on the first surface 1a side is reduced, the warpage is greatly reduced. As a result, as shown in FIGS. 4B and 5, the positions of the micro bumps 6 of the first semiconductor chip 1 </ b> C and the micro bumps 64 on the second semiconductor chip 61 side bonded thereto are caused by thermal expansion. It is possible to prevent deviation.

  By the way, as the divided electrode pad 13, in the above structure, the divided electrodes 13 a to 13 d divided into four via the cross-shaped slit 13 e are formed, but the structure is not limited to such a structure. For example, as shown in FIG. 11A, a plurality of divided electrodes 13p may be formed by being divided into five or more in a lattice shape. In the plurality of divided electrodes 13p having this structure, the under bump metal film 17 is formed on at least the edges facing each other via the lattice-like slits 13e and the substantially circular portion at the center of the opening 15a of the protective insulating film 15. . TSV2 is connected to each of the plurality of divided electrodes 13p.

  Accordingly, when the solder bumps 18 and the divided electrode pads 13 are joined, the flow of solder can be controlled along the path along the lattice-like slits 13e when the solder bumps 18 and the divided electrode pads 13 are joined. 18 and the divided electrode pad 13 can be widened, and an increase in their connection resistance can be suppressed. In addition, similarly to the above, warping of the semiconductor chip 1C can be prevented.

  As the divided electrode pad 13, as shown in FIG. 11B, a plurality of triangular divided electrodes 13q divided diagonally by cross-shaped slits 13e are formed in a square region, and at least the edges that define the slits 13e An under bump metal film 17 may be formed on the part. Further, as shown in FIG. 11C, eight triangular separation electrodes 13r separated by slits 13e formed radially in eight directions from the center of the square region where the divided electrode pads 13 are formed are provided. It may be formed. Also in these cases, the under bump metal film 17 is formed on at least the edge of the separation electrodes 13q and 13r defined by the slit 13e. TSV2 is connected to each of the plurality of divided electrodes 13q and 13r.

  Accordingly, when the solder bumps 18 and the divided electrode pads 13 are joined, the flow of the solder is controlled along the path along the lattice-like slits 13e when the solder bumps 18 and the divided electrode pads 13 are joined. The bonding area of the electrode pad 13 can be increased, and an increase in connection resistance thereof can be suppressed. In addition, similarly to the above, warping of the semiconductor chip 1C can be prevented.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is interpreted without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, it will be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the invention.

Next, features of the embodiment of the present invention will be described.
(Supplementary Note 1) A first surface side electrode pad formed on the first surface side of the semiconductor substrate and a second surface side of the semiconductor substrate formed in a different area from the first surface side electrode pad. A split electrode pad having a plurality of split electrodes split through the insulating substrate, an insulating film formed on the second surface side of the semiconductor substrate and having an opening exposing the split electrode pad, and the split electrode pad Of the plurality of divided electrodes, the insulating film is formed from a material that is exposed from the opening and at least an edge on the side partitioned by the slit, and is formed of a material having better wettability with the solder than the plurality of divided electrodes. And a coated metal film.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the metal film formed on the edge of the plurality of divided electrodes is covered with an organic insulating film in an outer peripheral portion of the divided electrode pad. .
(Supplementary Note 3) The first surface side electrode pad is connected to a first through via formed in the semiconductor substrate, and the plurality of divided electrodes of the divided electrode pad are formed in the semiconductor substrate. The semiconductor device according to appendix 1 or appendix 2, wherein the semiconductor device is individually connected to the through via.
(Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein the slit of the divided electrode pad has a shape extending in a plurality of directions from a central portion or a shape having a cross shape. .
(Supplementary note 5) In any one of Supplementary notes 1 to 4, the first solder bonded to the divided electrode pad is larger than the second solder bonded to the first surface side electrode pad. The semiconductor device described.
(Supplementary note 6) The first solder bonded to the divided electrode pad before is smaller than the maximum size of the interval between the second through vias connected to each of the plurality of divided electrodes. The semiconductor device according to appendix 5.
(Supplementary note 7) The semiconductor device according to any one of supplementary notes 1 to 6, wherein at least an uppermost layer of the metal coating is made of Au, NiB, or Pd.
(Supplementary Note 8) A first surface side electrode pad formed on the first surface side of the semiconductor substrate and a second surface side of the semiconductor substrate having a width different from that of the first surface side electrode pad, through a slit. A divided electrode pad having a plurality of divided electrodes divided, an insulating film formed on the second surface side of the semiconductor substrate and having an opening exposing the divided electrode pad, and the plurality of divided electrode pads Of the divided electrodes, the insulating film is formed at a portion exposed from the opening and at least an edge on a side partitioned by the slit, and is formed of a material having better wettability with the solder than the divided electrodes. A step of aligning the solder on the metal film in the opening of the insulating film in the semiconductor device having the metal film, melting the solder on the metal film, and applying the solder to the divided electrode The method of manufacturing a semiconductor device, characterized in that it comprises a step of spreading from the center of the head along the metal coating on the edge portion of the plurality of the divided electrodes.
(Supplementary Note 9) The metal film on the edge of the plurality of divided electrodes is covered with an organic insulating film, and the molten solder is allowed to enter between the organic insulating film and the metal film on the edge. 9. The method for manufacturing a semiconductor device according to appendix 8, wherein the semiconductor device is spread.

1 Silicon wafer 1C Semiconductor chip 2 TSV
3a, 3b Electrode pad 6 Micro bump 7 Cu diffusion preventing insulating film 8 Ti adhesion layer 9 Cu seed layer 10 Resist pattern 11, 12 Opening portion 13 Divided electrode pads 13a-13d, 13p, 13q, 13r Divided electrode 13e Slit 14 Non Divided electrode pad 15 Protective insulating film 15a15b Openings 16, 20 Resist pattern 17 Under bump metal coating 18 Solder bump 51 Support wafer 52 Temporary adhesive 61 Semiconductor chip 64 Micro bump

Claims (5)

A first surface side electrode pad formed on the first surface side of the semiconductor substrate;
A divided electrode pad formed on the second surface side of the semiconductor substrate and having a plurality of divided electrodes formed in different widths from the first surface side electrode pad and divided through slits;
An insulating film formed on the second surface side of the semiconductor substrate and having an opening exposing the divided electrode pad;
Of the plurality of divided electrodes of the divided electrode pad, formed on at least an edge portion of the insulating film exposed from the opening and a side partitioned by the slit, and wetted with solder from the plurality of divided electrodes A metal film formed from a good material,
Solder formed on at least the metal film among the divided electrode pads and the metal film through the opening,
A semiconductor device. 2. The semiconductor device according to claim 1, wherein the metal film formed on the edge of the plurality of divided electrodes is covered with an organic insulating film in an outer peripheral portion of the divided electrode pad. The first surface side electrode pad is connected to a first through via formed in the semiconductor substrate,
3. The semiconductor device according to claim 1, wherein each of the plurality of divided electrodes of the divided electrode pad is connected to a second through via formed in the semiconductor substrate. The first surface side electrode pad formed on the first surface side of the semiconductor substrate and the second surface side of the semiconductor substrate are formed to have a different width from the first surface side electrode pad, and are divided through a slit. A divided electrode pad having a plurality of divided electrodes, an insulating film formed on the second surface side of the semiconductor substrate and having an opening exposing the divided electrode pad, and the plurality of divided electrodes of the divided electrode pad A metal film formed from a material exposed to the opening of the insulating film and at least an edge on a side partitioned by the slit, and made of a material having better wettability with the solder than the plurality of divided electrodes And aligning the solder on the metal film in the opening of the insulating film in a semiconductor device having:
Melting the solder on the metal coating, and spreading the solder along the metal coating on the edge of the plurality of split electrodes from the center of the split electrode pad;
A method for manufacturing a semiconductor device, comprising:   The metal coating on the edge of the plurality of divided electrodes is covered with an organic insulating film, and the melted solder is spread between the organic insulating film and the metal coating on the edge. The method of manufacturing a semiconductor device according to claim 4.

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