JP5254372B2 - データ処理の方法及び装置 - Google Patents
データ処理の方法及び装置 Download PDFInfo
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- JP5254372B2 JP5254372B2 JP2011001428A JP2011001428A JP5254372B2 JP 5254372 B2 JP5254372 B2 JP 5254372B2 JP 2011001428 A JP2011001428 A JP 2011001428A JP 2011001428 A JP2011001428 A JP 2011001428A JP 5254372 B2 JP5254372 B2 JP 5254372B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/55—Detecting local intrusion or implementing counter-measures
- G06F21/552—Detecting local intrusion or implementing counter-measures involving long-term monitoring or reporting
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Health & Medical Sciences (AREA)
- Health & Medical Sciences (AREA)
- Bioethics (AREA)
- Storage Device Security (AREA)
- Debugging And Monitoring (AREA)
Description
図1ではメモリ4、6がそれぞれ別々のバスを介してマイクロプロセッサ2と接続している。但し、共通のバスを介して接続することも可能である。
‐方法の正常な進行に相当する第1の枝(ステップE402乃至ステップE420);
‐少なくとも一部が異常の検知後に実施されるステップから成る第2の枝(ステップE450乃至ステップE458)。
Claims (9)
- プロセッサが機能の異常を検知するステップ(E308)と、
異常が検知された場合にプロセッサがエラーフラグを更新するステップ(E310)と、
異常が検知された場合にプロセッサにより実行される中間ステップ(E314)であって、異常が検知されない場合に実行される第1動作と共通の特性を有する第2動作を実行することを含む中間ステップ(E314)と、
プロセッサが前記エラーフラグをテストするステップ(E316)と、
テストするステップが異常が検知されたことを示す場合にプロセッサにより実行される処理のステップ(E320)とを含むデータを処理する方法であって、
前記処理ステップはプロセッサがデータを物理的メモリに書き込むことを含む、方法。 - 前記共通の特性は前記第1動作を実行する命令のタイプである請求項1記載の方法。
- 前記第1動作および前記第2動作は、正常機能においても異常が検知された場合にも実行されるステップである請求項1記載の方法。
- 前記第1動作および前記第2動作は書き換え型メモリの或るアドレスにおいて読み出しを行うことにある請求項1記載の方法。
- 異常が検知された場合、前記アドレスは見掛けゾーンを指している請求項4記載の方法。
- 前記処理ステップにおいて書き込まれる前記データはロックデータである請求項1〜5のいずれか1項記載の方法。
- 超小型回路カードのマイクロプロセッサによって実施される請求項1〜6のいずれか1項記載の方法。
- 機能の異常を検知する手段と、
異常が検知された場合にエラーフラグを更新する手段と、
異常が検知された場合中間ステップ(E314)を実行する手段であって、該実行する手段は、異常が検知されない場合に実行される第1動作と共通の特性を有する第2動作を実行するよう適合されている、手段と、
エラーフラグをテストする手段と、
前記テスト手段が異常が検知されたことを示す場合に起動されるよう適合された処理手段と、を含むデータ処理のための装置であって、
前記処理手段はデータを物理的メモリに書き込むよう設計されている、装置。 - 装置が超小型回路カードである請求項8記載の装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0408928A FR2874440B1 (fr) | 2004-08-17 | 2004-08-17 | Procede et dispositif de traitement de donnees |
FR0408928 | 2004-08-17 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007526510A Division JP4790717B2 (ja) | 2004-08-17 | 2005-08-12 | データ処理の方法及び装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2011076636A JP2011076636A (ja) | 2011-04-14 |
JP2011076636A5 JP2011076636A5 (ja) | 2011-10-13 |
JP5254372B2 true JP5254372B2 (ja) | 2013-08-07 |
Family
ID=34948280
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007526510A Active JP4790717B2 (ja) | 2004-08-17 | 2005-08-12 | データ処理の方法及び装置 |
JP2011001428A Active JP5254372B2 (ja) | 2004-08-17 | 2011-01-06 | データ処理の方法及び装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007526510A Active JP4790717B2 (ja) | 2004-08-17 | 2005-08-12 | データ処理の方法及び装置 |
Country Status (8)
Country | Link |
---|---|
US (2) | US20070220603A1 (ja) |
EP (2) | EP1779284B1 (ja) |
JP (2) | JP4790717B2 (ja) |
CA (1) | CA2575143C (ja) |
ES (2) | ES2543210T3 (ja) |
FR (1) | FR2874440B1 (ja) |
PL (2) | PL2309409T3 (ja) |
WO (1) | WO2006021686A2 (ja) |
Families Citing this family (10)
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CN101606162A (zh) * | 2007-01-05 | 2009-12-16 | 质子世界国际公司 | 电子电路的临时锁定 |
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-
2004
- 2004-08-17 FR FR0408928A patent/FR2874440B1/fr active Active
-
2005
- 2005-08-12 ES ES10177462.8T patent/ES2543210T3/es active Active
- 2005-08-12 WO PCT/FR2005/002083 patent/WO2006021686A2/fr active Application Filing
- 2005-08-12 CA CA2575143A patent/CA2575143C/fr active Active
- 2005-08-12 US US11/660,218 patent/US20070220603A1/en not_active Abandoned
- 2005-08-12 EP EP05798504.6A patent/EP1779284B1/fr active Active
- 2005-08-12 EP EP20100177462 patent/EP2309409B1/fr active Active
- 2005-08-12 ES ES05798504.6T patent/ES2473326T3/es active Active
- 2005-08-12 PL PL10177462T patent/PL2309409T3/pl unknown
- 2005-08-12 PL PL05798504T patent/PL1779284T3/pl unknown
- 2005-08-12 JP JP2007526510A patent/JP4790717B2/ja active Active
-
2011
- 2011-01-06 JP JP2011001428A patent/JP5254372B2/ja active Active
-
2013
- 2013-03-18 US US13/845,914 patent/US9454663B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
FR2874440B1 (fr) | 2008-04-25 |
FR2874440A1 (fr) | 2006-02-24 |
EP1779284B1 (fr) | 2014-03-19 |
CA2575143C (fr) | 2016-05-31 |
JP2008510242A (ja) | 2008-04-03 |
CA2575143A1 (fr) | 2006-03-02 |
PL1779284T3 (pl) | 2014-09-30 |
US20130219522A1 (en) | 2013-08-22 |
US20070220603A1 (en) | 2007-09-20 |
WO2006021686A3 (fr) | 2006-04-13 |
ES2473326T3 (es) | 2014-07-04 |
EP2309409B1 (fr) | 2015-04-22 |
JP2011076636A (ja) | 2011-04-14 |
US9454663B2 (en) | 2016-09-27 |
PL2309409T3 (pl) | 2015-10-30 |
WO2006021686A2 (fr) | 2006-03-02 |
ES2543210T3 (es) | 2015-08-17 |
JP4790717B2 (ja) | 2011-10-12 |
EP2309409A1 (fr) | 2011-04-13 |
EP1779284A2 (fr) | 2007-05-02 |
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