JP5252867B2 - 半導体基板の製造方法 - Google Patents

半導体基板の製造方法 Download PDF

Info

Publication number
JP5252867B2
JP5252867B2 JP2007246069A JP2007246069A JP5252867B2 JP 5252867 B2 JP5252867 B2 JP 5252867B2 JP 2007246069 A JP2007246069 A JP 2007246069A JP 2007246069 A JP2007246069 A JP 2007246069A JP 5252867 B2 JP5252867 B2 JP 5252867B2
Authority
JP
Japan
Prior art keywords
semiconductor wafer
layer
substrate
insulating layer
ions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007246069A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009076784A (ja
JP2009076784A5 (https=
Inventor
舜平 山崎
工 稲田
昭治 宮永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2007246069A priority Critical patent/JP5252867B2/ja
Publication of JP2009076784A publication Critical patent/JP2009076784A/ja
Publication of JP2009076784A5 publication Critical patent/JP2009076784A5/ja
Application granted granted Critical
Publication of JP5252867B2 publication Critical patent/JP5252867B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Thin Film Transistor (AREA)
JP2007246069A 2007-09-21 2007-09-21 半導体基板の製造方法 Expired - Fee Related JP5252867B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007246069A JP5252867B2 (ja) 2007-09-21 2007-09-21 半導体基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007246069A JP5252867B2 (ja) 2007-09-21 2007-09-21 半導体基板の製造方法

Publications (3)

Publication Number Publication Date
JP2009076784A JP2009076784A (ja) 2009-04-09
JP2009076784A5 JP2009076784A5 (https=) 2010-10-21
JP5252867B2 true JP5252867B2 (ja) 2013-07-31

Family

ID=40611456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007246069A Expired - Fee Related JP5252867B2 (ja) 2007-09-21 2007-09-21 半導体基板の製造方法

Country Status (1)

Country Link
JP (1) JP5252867B2 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8318588B2 (en) * 2009-08-25 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
US8735263B2 (en) * 2011-01-21 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP6579086B2 (ja) * 2016-11-15 2019-09-25 信越半導体株式会社 デバイス形成方法
JP6686962B2 (ja) * 2017-04-25 2020-04-22 信越半導体株式会社 貼り合わせウェーハの製造方法
CN112599655A (zh) * 2019-03-13 2021-04-02 电子科技大学 多功能单晶薄膜、其制备方法和谐振器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150835A (ja) * 1998-11-05 2000-05-30 Fujitsu Ltd 非単結晶シリコン薄膜の製造方法
FR2877491B1 (fr) * 2004-10-29 2007-01-19 Soitec Silicon On Insulator Structure composite a forte dissipation thermique
KR20080042095A (ko) * 2005-07-27 2008-05-14 실리콘 제너시스 코포레이션 제어된 클리빙 처리를 이용하여 플레이트 상에 다수의 타일영역을 제작하는 방법 및 구조

Also Published As

Publication number Publication date
JP2009076784A (ja) 2009-04-09

Similar Documents

Publication Publication Date Title
KR101400699B1 (ko) 반도체 기판 및 반도체 장치 및 그 제조 방법
CN101663733B (zh) 制造绝缘体上硅衬底和半导体器件的方法
JP5289805B2 (ja) 半導体装置製造用基板の作製方法
CN101425454B (zh) Soi衬底的制造方法
KR101574138B1 (ko) Ｓｏｉ 기판의 제조방법
CN101303967B (zh) 半导体装置的制造方法
KR101561855B1 (ko) Ｓｏｉ기판의 제작방법
JP5305712B2 (ja) 半導体基板の作製方法
JP5460972B2 (ja) Ｓｏｉ基板の作製方法、及び半導体装置の作製方法
CN101281912A (zh) Soi衬底及其制造方法以及半导体装置
KR20100038165A (ko) Ｓｏｉ 기판의 제작 방법
CN101308782A (zh) Soi衬底的制造方法、以及半导体装置的制造方法
JP2009099965A (ja) 半導体装置及びその作製方法
JP5252867B2 (ja) 半導体基板の製造方法
JP5264018B2 (ja) 半導体基板の作製方法
JP2010153811A (ja) 半導体装置の作製方法
JP5137461B2 (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100903

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100903

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130305

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130320

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130409

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130416

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160426

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees