JP5245970B2 - LIGHT EMITTING DIODE, ITS MANUFACTURING METHOD, AND LAMP - Google Patents

Description

  The present invention relates to a light emitting diode, a method for manufacturing the same, and a lamp.

Conventionally, as a light emitting diode (LED) that emits red, orange, yellow, or yellowish green visible light, for example, aluminum phosphide, gallium indium (composition formula (Al _X Ga _1-X ) _Y In _1-YP ; A compound semiconductor LED having a light emitting layer composed of 0 ≦ X ≦ 1, 0 <Y ≦ 1) is known. In such an LED, for example, a compound semiconductor layer including a light-emitting layer made of (Al _X Ga _1-X ) _Y In _1-YP (0 ≦ X ≦ 1, 0 <Y ≦ 1) is generally formed from a light-emitting layer. It is formed on a substrate made of a material such as gallium arsenide (GaAs) that is optically opaque to the emitted light and that is not mechanically strong.

  Therefore, recently, for the purpose of obtaining a brighter visible LED and further improving the mechanical strength of the device, the substrate material opaque to the emitted light is removed, and then the emitted light is transmitted or reflected. In addition, a technique is disclosed in which a support (substrate) made of a material having excellent mechanical strength is bonded to the compound semiconductor layer to form a bonded LED (for example, see Patent Documents 1 to 7). . Here, the cited document 4 discloses the use of a substrate made of Si or GaP as the substrate, and the cited document 6 discloses the use of a substrate made of a metal material.

  In recent years, in the technical field of light emitting diode packages as described above, packages that can withstand high current and that emphasize heat dissipation have become widespread.

Japanese Patent No. 3230638 JP-A-6-302857 JP 2002-246640 A JP 2001-339100 A JP 2001-57441 A JP 2007-81010 A JP 2006-32952 A

In the light emitting diode as described in each of the above patent documents, the design flexibility of the substrate is increased by the development of the substrate bonding technology, so that a high current can be applied, a metal substrate with high heat dissipation, a ceramic substrate, Composite substrates and the like have been proposed. However, since the substrate with high heat dissipation as described above has a large difference in thermal expansion coefficient with the semiconductor layer including the light emitting layer, the semiconductor layer is cracked at the time of bonding the substrate or in the heat treatment process, yield. There is a problem that decreases.
Further, in the light emitting diode as described above, when the substrate is made of a metal material having high heat dissipation such as copper, aluminum, gold, silver, etc., these materials are soft and sticky materials, In the process of cutting the wafer into chips, there are problems such as generation of burrs and shortening the life of the blade used for cutting, which makes it difficult to cut accurately with high yield.

The present invention has been made in view of the above problems, and is excellent in heat dissipation and workability of the substrate, can prevent damage such as cracks in the semiconductor layer in the manufacturing process, and can be applied with a high current. An object of the present invention is to provide a light emitting diode which has luminous efficiency and excellent yield.
It is another object of the present invention to provide a method for manufacturing a light emitting diode, which can obtain a light emitting diode having high light emission efficiency as described above at a high yield and low cost.
Another object of the present invention is to provide a lamp using the light emitting diode of the present invention.

As a result of extensive studies by the present inventors in order to solve the above-mentioned problems, a compound semiconductor layer including a light-emitting layer has a thermal expansion coefficient substantially equal to that of a substrate having excellent workability and bonded to the compound semiconductor layer. It has been found that cracks and the like can be prevented in the compound semiconductor layer. In addition, the substrate has a three-dimensional structure consisting of a base part and an embedded part, and is made of a material with excellent heat dissipation, so that a large current can be applied to the light emitting diode and the luminous efficiency is further improved. As a result, the present invention has been completed.
That is, the present invention employs each configuration described below.

[1] A light-emitting diode having a chip structure in which a compound semiconductor layer including at least a light-emitting layer is stacked on a substrate, and an upper surface side of the compound semiconductor layer is a light-emitting surface. Rutotomoni such from the embedded portion surrounded by the base portion, the concave portion is formed on the lower surface side of the base portion, the embedded portion is provided in the recess, and, the thickness of the embedded portion, the base 70% or more of the thickness of the material part, and the substrate is made of different metal materials for the base part and the embedded part, and the base part is more than the embedded part. thermal expansion coefficient Ri is Do a small material, the compound semiconductor layer, in the substrate, on the upper surface of the base portion, at least, p-type semiconductor layer, each layer of the light-emitting layer and the n-type semiconductor layer are stacked light emitting diodes, characterized in that Rukoto.
[ 2 ] The light emitting diode according to the above [1], wherein the difference in thermal expansion coefficient between the base material portion and the compound semiconductor layer is ± 1.5 ppm / K or less.
[ 3 ] The light-emitting diode according to any one of [1] or [2] , wherein the substrate has a thermal conductivity of 200 W / m · K or more.
[ 4 ] The light-emitting diode according to any one of [1] to [ 3 ], wherein the base portion is made of molybdenum, tungsten, or an alloy material thereof.

[ 5 ] The embedded portion according to any one of [1] to [ 4 ], wherein the embedded portion is made of a material containing at least one of gold, silver, copper, and aluminum. Light emitting diode.
[ 6 ] The light-emitting diode according to [ 5 ], wherein the embedded portion is a plated layer containing at least one of gold, silver, copper, and aluminum .

[ 7 ] The light emitting diode according to any one of [1] to [ 6 ], wherein the light emitting layer included in the compound semiconductor layer is made of a material containing AlGaInP or AlGaAs.
[ 8 ] The light-emitting diode according to any one of [1] to [ 7 ], wherein the substrate has a substantially rectangular shape in plan view with a length of 500 μm or more per side.
[ 9 ] Further, an n-type electrode layer that is a negative electrode is provided on the n-type semiconductor layer of the compound semiconductor layer, the substrate is a positive electrode, and a density of 0.5 W / mm ² or more is provided between the electrodes. The light emitting diode according to any one of the above [1] to [8] , wherein a power having the following is applied.
[ 10 ] The light-emitting diode according to any one of [1] to [ 9 ], wherein the substrate and the compound semiconductor layer are bonded by a metal bonding layer.
[ 11 ] The light-emitting diode according to any one of [1] to [ 9 ], wherein the substrate and the compound semiconductor layer are directly bonded.

[ 12 ] A compound semiconductor layer including the light-emitting layer is formed by sequentially stacking at least an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer on the substrate for stacking , and a second provided in the compound semiconductor layer. after forming the second electrode having ohmic characteristics on the semiconductor layer, forming a laminate by laminating the bonding layer to cover the second electrode, at least the lower surface of the base portion some form a concave portion by etching method, to form a buried portion surrounded by the base portion inside the concave portion, the thickness of the embedded portion 70 of the thickness of the base portion %, The step of bonding the stacked body and the substrate by bonding the bonding layer of the stacked body and the upper surface side of the substrate, and the stacking substrate from the compound semiconductor layer The first semiconductor layer peeled off and provided in the compound semiconductor layer A step of forming a first electrode on the light extraction surface after exposing the light extraction surface of the semiconductor layer; and dividing the compound semiconductor layer and the bonding layer into a plurality of the plurality of compound semiconductor layers. And cutting the position of the base material portion in the substrate along the dividing groove formed between each of the substrate, and dividing the element unit, and the substrate comprises the base material portion and The method for manufacturing a light-emitting diode, wherein the embedded portion is made of a different metal material, and the base material portion is made of a material having a smaller thermal expansion coefficient than the embedded portion.

[ 13 ] A semiconductor layer forming step of forming a compound semiconductor layer by sequentially stacking at least an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a stacking substrate, and the p-type semiconductor provided in the compound semiconductor layer After forming a p-type ohmic electrode on the layer, a laminated body forming step of forming a laminated body by laminating a bonding layer so as to cover the p-type ohmic electrode, and at least a part on the lower surface side of the substrate portion after forming the concave portion by an etching method, to form a buried portion surrounded by the base portion inside the concave portion, the thickness of the embedded portion, 70% of the thickness of the base portion A substrate forming step of forming a substrate as a bonding step, a bonding step of bonding the compound semiconductor layer and the substrate by bonding the bonding layer of the stacked body and the upper surface side of the substrate, and Peel from compound semiconductor layer Removing the step of exposing the light extraction surface of the n-type semiconductor layer provided in the compound semiconductor layer, forming an n-type electrode layer on the light extraction surface of the n-type semiconductor layer, After dividing the compound semiconductor layer and the bonding layer into a plurality of parts, a dividing step of cutting the position of the base material portion in the substrate along a dividing groove formed between each of the plurality of compound semiconductor layers. The substrate includes the base part and the embedded part made of different metal materials, and the base part is made of a material having a smaller thermal expansion coefficient than the embedded part. A method for manufacturing a light emitting diode.

[ 14 ] The method for manufacturing a light-emitting diode according to [ 13 ], wherein the substrate forming step forms the embedded portion using a plating method inside the concave portion of the base material portion.
[ 15 ] The method for manufacturing a light-emitting diode according to the above [ 13 ] or [ 14 ], wherein in the substrate forming step, the base portion is formed from molybdenum, tungsten, or an alloy material thereof.
[ 16 ] The above [ 13 ] to [ 15 ], wherein in the substrate forming step, the embedded portion is formed of a material containing at least one of gold, silver, copper, and aluminum. The manufacturing method of the light emitting diode of any one of these.
[ 17 ] The above [ 13 ] to [ 16 ], wherein a roughening step for roughening the light extraction surface of the n-type semiconductor layer is provided between the electrode forming step and the dividing step. The manufacturing method of the light emitting diode as described in any one of Claims 1-3.

[ 18 ] A light-emitting diode obtained by the manufacturing method according to any one of [ 12 ] to [ 17 ].
[ 19 ] A lamp using the light-emitting diode according to any one of [1] to [ 11 ] or [ 18 ].

  According to the light emitting diode of the present invention, the compound semiconductor layer including at least the light emitting layer is laminated on the substrate, the substrate is composed of the base portion and the embedded portion surrounded by the base portion, and the base portion is embedded. By being made of a material having a smaller thermal expansion coefficient than the part, it is possible to achieve both workability and heat dissipation of the substrate. Thereby, it is possible to prevent the compound semiconductor layer from being damaged, such as cracks, in the manufacturing process, to improve the yield, and to realize a light emitting diode capable of applying a high current and having high light emission efficiency.

  Further, according to the method for producing a light emitting diode of the present invention, a laminate in which a compound semiconductor layer and a bonding layer are laminated on a lamination substrate, a base material portion, and a recess or a penetration portion formed in the base material portion A step of bonding the compound semiconductor layer and the substrate by bonding to a substrate formed of an embedded portion provided inside the substrate, and separating the substrate for stacking from the compound semiconductor layer to extract light from the first semiconductor layer A step of exposing a surface, and a step of cutting a position of a base material portion in a substrate along a dividing groove formed between each of the plurality of compound semiconductor layers, wherein the base material portion is an embedded portion Since it is made of a material having a smaller coefficient of thermal expansion than the above, damage such as cracks can be prevented from occurring in the compound semiconductor layer, yield can be improved, and a light emitting diode excellent in heat dissipation of the substrate can be manufactured. . As a result, a light emitting diode capable of applying a high current and having excellent luminous efficiency can be manufactured with high manufacturing efficiency.

  Moreover, according to the lamp of the present invention, since the light emitting diode of the present invention is used, the light emitting characteristics are excellent.

It is a cross-sectional schematic diagram which shows an example of the light emitting diode which concerns on this invention. It is process drawing explaining an example of the manufacturing method of the light emitting diode which concerns on this invention. It is process drawing explaining an example of the manufacturing method of the light emitting diode which concerns on this invention. It is process drawing explaining an example of the manufacturing method of the light emitting diode which concerns on this invention. It is process drawing explaining an example of the manufacturing method of the light emitting diode which concerns on this invention. It is process drawing explaining an example of the manufacturing method of the light emitting diode which concerns on this invention. It is process drawing explaining an example of the manufacturing method of the light emitting diode which concerns on this invention. It is process drawing explaining an example of the manufacturing method of the light emitting diode which concerns on this invention. It is process drawing explaining an example of the manufacturing method of the light emitting diode which concerns on this invention. It is process drawing explaining an example of the manufacturing method of the light emitting diode which concerns on this invention. It is a cross-sectional schematic diagram which shows an example of the lamp | ramp comprised using the light emitting diode which concerns on this invention.

  Hereinafter, a light-emitting diode, a manufacturing method thereof, and a lamp, which are embodiments of the present invention, will be described with reference to the drawings as appropriate. 1A is a schematic cross-sectional view of the light-emitting diode of this embodiment, FIG. 1B is a plan view of FIG. 1A, and FIGS. 2 to 10 are steps for explaining a method of manufacturing the light-emitting diode. FIG. 11 is a schematic cross-sectional view of a light-emitting diode lamp using the diode of the embodiment of the present invention. The drawings referred to in the following description are for explaining the light emitting diode and the manufacturing method thereof, and the size, thickness, dimensions, etc. of each part shown in the drawings are different from the dimensional relationships of the actual light emitting diodes and the like. ing.

[Light emitting diode]
The light emitting diode A in the example shown in FIGS. 1A and 1B includes a base material portion 2 and an embedded portion 3 surrounded by the base material portion 2, and a heat sink substrate (base material of the light emitting diode A) ( Substrate) 1, bonding layer 4 disposed on upper surface 2 a of heat sink substrate 1, compound semiconductor layer 11 disposed above bonding layer 4, and n-type disposed above and below compound semiconductor layer 11. The electrode layer 9 and the p-type ohmic electrode 5 are roughly configured. Further, the light emitting diode A is configured such that the base material part 2 forming the heat sink substrate 1 is made of a material having a smaller thermal expansion coefficient than the embedded part 3.

  Here, the compound semiconductor layer 11 is formed by stacking a p-type semiconductor layer 6, a light emitting layer 7 and an n-type semiconductor layer 8. The upper surface of the compound semiconductor layer 11 is a light extraction surface 11a for extracting light from the light emitting layer 7 to the outside, and the n-type electrode layer 9 is formed on the light extraction surface 11a. Although not shown in detail, the light extraction surface 11a is roughened by means such as etching, and the light extraction efficiency of the light-emitting diode A is further enhanced.

  The n-type electrode layer 9 becomes an anode of the compound semiconductor layer 11 by making ohmic contact with the n-type semiconductor layer 8 of the compound semiconductor layer 11. In general, when an electrode is provided in a semiconductor element such as a light emitting diode, for example, AuGe or AuSi can be used as an n-type ohmic electrode provided in an n-type compound semiconductor. In addition, AuBe, AuZn, or the like can be used as the p-type ohmic electrode (see the p-type ohmic electrode 5 in FIG. 1) provided on the p-type compound semiconductor. The layer structure and material of the n-type electrode layer 9 shown in FIGS. 1 (a) and 1 (b) are not particularly limited, but are preferably made of a metal material containing Au in consideration of connection by wire bonding. It is preferable to use such AuGe or AuSi.

  Further, as the n-type electrode layer 9, for example, a so-called barrier metal such as Ti or Pt is formed on an electrode material having ohmic characteristics as described above, and Au is further formed thereon. More preferably. As a formation method at this time, a conventionally known vapor deposition method, sputtering method, or the like can be employed without any limitation. The film thickness of each layer is not particularly limited, but the ohmic electrode material (AuGe, AuSi) is 0.1 to 0.5 μm, the barrier metal is 0.1 to 0.5 μm, and the Au layer is 1 to 3 μm. It is preferable from the viewpoints of film thickness controllability, productivity (cost), and the like.

The n-type electrode layer 9 preferably has an appropriate arrangement and shape with respect to the compound semiconductor layer 11 in order to uniformly diffuse the current to the compound semiconductor layer 11 including the light-emitting layer 7. The shape is not particularly limited, and a conventionally known technique can be applied.
Further, between the n-type electrode layer 9 and the light emitting layer 7, an n-type semiconductor layer 8 that is a contact layer for reducing the resistance at the time of ohmic contact is provided. Further, between the n-type electrode layer 9 and the compound semiconductor layer 11 (n-type semiconductor layer 8), a driving current supplied from the n-type electrode layer 9 is diffused in a plane across the entire compound semiconductor layer 11. A configuration in which a current diffusion layer or, conversely, a current blocking layer or a current confinement layer for limiting a region through which a driving current flows may be provided.

  In addition, the n-type electrode layer 9 in the example shown in FIGS. 1A and 1B has a shape in which four branch portions extend in a cross shape from a substantially circular central portion in plan view. However, the present invention is not limited to this, and may be adopted as appropriate in consideration of current diffusion to the compound semiconductor layer 11.

  Next, as shown in FIGS. 1A and 1B, the p-type ohmic electrode 5 is formed so as to be in contact with the lower side of the compound semiconductor layer 11, that is, the lower side of the p-type semiconductor layer 6. Although not shown in detail, the p-type ohmic electrode 5 is formed in a circular shape in plan view, and a plurality of p-type ohmic electrodes 5 are provided at predetermined intervals in contact with the lower side of the p-type semiconductor layer 6. Near the four corners of A, it is provided at a total of four locations. As a material of such a p-type ohmic electrode 5, various structures such as a laminated film made of an AuBe alloy film and an Au film are well known, and can be provided by a conventional means well known in this technical field. .

The p-type ohmic electrode 5 preferably has an appropriate arrangement and shape with respect to the compound semiconductor layer 11 in order to diffuse current uniformly into the compound semiconductor layer 11 including the light emitting layer 7. The arrangement form and shape are not particularly limited, and conventionally known techniques can be applied.
In general, the arrangement and shape of the p-type ohmic electrode 5 and the n-type electrode layer 9 are preferably combined so that a current flows uniformly in the region of the light-emitting layer 7 where light is easily extracted. Here, for example, it is not preferable to dispose the p-type ohmic electrode 5 immediately below the n-type electrode layer 9 because current tends to concentrate.

  Next, as shown in FIG. 1A, the bonding layer 4 is disposed on the lower side of the compound semiconductor layer 11, that is, on the lower side of the p-type semiconductor layer 6 so as to cover the p-type ohmic electrode 5 described above. Has been. In the example shown in FIG. 1A, the bonding layer 4 includes the light-transmitting thin film layer 4a, the reflective layer 4b, the barrier layer 4c, the Au layer 4d, and the metal bonding layer 4e from the compound semiconductor layer 11 side. The laminated films are arranged in this order, and the metal bonding layer 4 e is bonded to the heat sink substrate 1. In the example shown in FIG. 1A, the tip of the p-type ohmic electrode 5 described above is configured to be in contact with the translucent thin film layer 4 a constituting the bonding layer 4. In the light-emitting diode A of the present embodiment, the provision of the bonding layer 4 ensures that the compound semiconductor layer 11 and the heat sink substrate 1 are bonded with low contact resistance, and light generated by the light-emitting layer 7 is extracted from the light extraction surface. It can be reflected to the 11a side.

  In addition, the bonding layer 4 is electrically connected to the compound semiconductor layer 11 and the heat sink substrate 1 by the translucent thin film layer 4a and the metal bonding layer 4e, so that the heat sink substrate 1 serves as the extraction electrode on the positive electrode side. ing. Further, the bonding layer 4, the heat sink substrate 1, and the n-type electrode layer 9 are arranged on the opposite side in the thickness direction of the compound semiconductor layer 11. Thereby, the light emitting diode A of this embodiment is a light emitting diode having a so-called upper and lower electrode structure.

Since the bonding layer 4 used for the light emitting diode A bonds the heat sink substrate 1 on the positive electrode side and the compound semiconductor layer 11, it is preferable that the bonding layer 4 is made of a material having low electrical resistance. The bonding layer 4 is preferably provided with a metal bonding layer 4e made of a material capable of bonding to the heat sink substrate 1 at a low temperature in consideration of stress applied to the compound semiconductor layer 11.
Further, in the light emitting diode A of the present embodiment, it is preferable that the bonding layer 4 has a structure with high reflectivity from the viewpoint of achieving high luminance. For this reason, it is preferable to provide the bonding layer 4 with a reflective layer 4b made of a reflective material, and it is also possible to combine a translucent thin film layer 4a made of a translucent conductive material using a conventionally known method. It is.

The translucent thin film layer 4a is a layer for preventing reaction and diffusion between the compound semiconductor layer 11 and the reflective layer 4b. As such a translucent thin film layer 4a, for example, the refractive index of a translucent conductive material such as ITO (indium tin oxide), SiO ₂ (silicon oxide), TiO ₂ (titanium oxide), SiN (silicon nitride), or the like. An oxide film or a nitride film having a so-called cold mirror action utilizing the difference can be used. The translucent thin film layer 4a can be a multilayer film of the above material. Furthermore, the translucent thin film layer 4a can also be suitably used from the point that a high reflectance can be obtained, such as white Al ₂ O ₃ (alumina), AlN (aluminum nitride), and a combination of various materials. Can also be used.
The thickness of the translucent thin film layer 4a is preferably, for example, about 10 to 500 nm, and more preferably about 30 to 200 nm.

The reflection layer 4b is a reflection film made of a metal material having high reflection characteristics with respect to light emitted from the compound semiconductor layer 11, such as Ag, Au, Pt, Al, Cu, and the like. 11 is transmitted through the light-transmitting thin film layer 4a and reflected toward the heat sink substrate 1 side toward the compound semiconductor layer 11 side. In addition, the material of the reflective layer 4b can be used alone or as an alloy material in consideration of the emission wavelength of the compound semiconductor layer 11 (light emitting layer 7).
For example, the thickness of the reflective layer 4b is preferably about 100 to 800 nm, and more preferably about 200 to 500 nm.

  In the present embodiment, the light-emitting diode A is provided by providing the bonding layer 4 including the reflective layer 4b and the light-transmitting thin film layer 4a having the above-described structure between the compound semiconductor layer 11 including the light-emitting layer 7 and the heat sink substrate 1. An excellent effect of improving the luminance of the image can be obtained. The reflectance of the bonding layer 4 having such a reflection structure is preferably 90% or more, for example.

  The barrier layer 4c is formed in order to prevent mutual diffusion between constituent elements of the reflective layer 4b and constituent elements of the Au layer 4d and the metal bonding layer 4e described later. As the barrier layer 4c, for example, a conventionally known barrier metal such as Mo (molybdenum), W (tungsten), titanium (Ti), chromium (Cr), or Pt (platinum) can be used. Moreover, as thickness of the barrier layer 4c, it is preferable that it is about 50-500 nm, for example, and it is more preferable that it is about 100-300 nm.

The Au layer 4d is a layer that becomes a contact layer when the heat sink substrate 1 is bonded by a metal bonding layer 4e to be described in detail later, and is made of Au having a low contact resistance. Further, for example, a layer made of another metal material having a low contact resistance can be provided in place of the Au layer 4d.
For example, the thickness of the Au layer 4d is preferably about 100 to 1000 nm, and more preferably about 200 to 500 nm.

  The metal bonding layer 4e is a layer bonded to the heat sink substrate 1 and is made of a material that can be bonded at a low temperature as described above. For this reason, the metal bonding layer 4e is preferably composed of an Au-based eutectic metal material or a solder material that is chemically stable and has a low melting point. As a material for forming the metal bonding layer 4e, for example, it is preferable to use a metal material having a low eutectic composition such as AuSn, AuIn, AuGe, AuSi, or an alloy such as a general solder material. is there. As thickness of the metal joining layer 4e, it is preferable that it is about 300-2000 nm, for example, and it is more preferable that it is about 500-1500 nm.

  The total thickness of the bonding layer 4 having the above-described configuration is not particularly limited, and may be set as appropriate according to, for example, the number of layers to be combined and the material.

  Moreover, it does not specifically limit as a method of joining the joining layer 4 (metal joining layer 4e) and the heat sink board | substrate 1, For example, conventionally well-known techniques, such as a joining using diffusion bonding and an adhesive agent, and a normal temperature joining method, are employ | adopted. It is possible to select appropriately while taking the element structure into consideration.

  Further, in the light emitting diode A according to the present invention, the base layer 2 of the heat sink substrate 1 and the p-type semiconductor layer 6 of the compound semiconductor layer 11 are directly bonded without providing the bonding layer 4 as described above. A configuration is also possible. However, in the case of such a configuration, the p-type ohmic electrode 5 as described above is provided in order to improve ohmic contact between the heat sink substrate 1 serving as the p-side electrode and the p-type semiconductor layer 6. Is preferred.

  Next, as described above, the heat sink substrate (substrate) 1 includes the base portion 2 and the embedded portion 3 surrounded by the base portion 2, and is the base of the light emitting diode A of the present embodiment. Further, in the light emitting diode A according to the present invention, the base material portion 2 is made of a material having a smaller thermal expansion coefficient than the embedded portion 3.

  The inventors of the present invention have made extensive studies in order to realize a substrate that can achieve both excellent heat dissipation and workability and can obtain a light emitting diode with a high yield. The compound semiconductor layer 11 is cracked or the like when the heat sink substrate 1 including the light emitting layer 7 has substantially the same thermal expansion coefficient as that of the compound semiconductor layer 11 and is excellent in workability. It was found that this can be prevented. Further, the heat sink substrate 1 has a three-dimensional structure composed of the base portion 2 and the embedded portion 3 and is made of a material having excellent heat dissipation, so that a large current can be applied to the light emitting diode A, It has been found that the luminous efficiency is further improved.

  In the heat sink substrate 1, the base material portion 2 and the embedded portion 3 are preferably made of different metal materials. Moreover, it is more preferable that the difference in thermal expansion coefficient between the base material portion 2 provided in the heat sink substrate 1 and the compound semiconductor layer 11 described later in detail is ± 1.5 ppm / K or less. Further, the heat sink substrate 1 is more preferably configured to have a thermal conductivity of 200 W / m · K or more.

When the present inventors diligently researched about the structure of the board | substrate which can satisfy | fill said each characteristic, although there was no thing which matched with all these conditions with a single material, some metal materials It was found that the above-mentioned conditions were met by using a composite structure using.
In the light-emitting diode A according to the present invention, first, a metal having a thermal expansion coefficient close to the group III-V compound semiconductor forming the compound semiconductor layer 11 is selected as the material of the base material portion 2, and further, the heat is higher than the base material portion 2. A metal having a high conductivity was selected and combined as a material for the embedded portion 3. By setting the heat sink substrate 1 to the above-described configuration, a substrate that is suitable for the light-emitting diode that can meet the above-described conditions can be obtained. As a suitable example, for example, the thermal expansion coefficient of a compound semiconductor made of an AlGaInP-based composition is about 5.3 ppm / K. Therefore, as a metal material of the base portion 2 constituting the heat sink substrate 1, molybdenum ( Mo: coefficient of thermal expansion = 5.1 ppm / K), tungsten (W: coefficient of thermal expansion = 4.3 ppm / K), or alloys thereof.

  Further, the difference in thermal expansion coefficient between the base material portion 2 constituting the heat sink substrate 1 and the semiconductor material is preferably within a range of ± 1.5 ppm, and more preferably within a range of ± 1 ppm. Further, the thermal conductivity of the embedded portion 3 is preferably 200 W / m · K or more, and more preferably 230 W / m · K or more.

  The base material part 2 is formed with a recess 21 by a method such as etching with respect to a metal plate made of the above material. The shape of the recess 21 in plan view is not particularly limited, and any of quadrangular and hexagonal shapes can be applied. However, in order to ensure uniform heat dissipation, it is preferable that the shape is a target shape in all directions. A circle is most preferred. Also, the cross-sectional shape of the concave portion 21 is not particularly limited, for example, a substantially mortar shape.

  Further, as in the example shown in FIGS. 1A and 1B, one recess 21 may be provided for each light emitting diode A chip, but a plurality of recesses 21 may be provided. Also, the depth of the recess is not particularly limited. For example, the recess may be formed as a penetrating part so as to penetrate the base material part in the thickness direction, and the base part may be configured in a substantially cylindrical shape. It is preferable to use the recessed portion 21 that remains thin because the process of forming the embedded portion 3 by plating is simplified. In this case, the position of leaving the bottom portion in the thickness direction of the base material portion 2 may be, for example, any of the upper surface 2a side, the lower surface 2b side, or the vicinity of the center, but the bottom portion on the upper surface 2a side to be bonded to the compound semiconductor layer 11 Is preferable from the viewpoint of minimizing stress due to thermal expansion.

The embedded portion 3 is disposed so as to be surrounded by the base material portion 2, and is formed so as to embed the entire concave portion 21 of the base material portion 2 in the example shown in FIGS.
The buried portion 3 has a metal having a large thermal conductivity of 230 W / m · K or more, for example, silver (Ag: thermal conductivity = 420 W / m · K), copper (Cu: thermal conductivity = 398 W / m · K). K), gold (Au: thermal conductivity = 320 W / m · K), aluminum (Al: thermal conductivity = 236 W / m · K), and a material containing at least one of them. The buried portion 3 can also use an alloy material composed of a plurality of the above elements, and can be configured as a plating layer containing at least one of the above elements.

  In the heat sink substrate 1, the ratio of the thickness of the embedded portion 3 to the thickness of the base material portion 2 is preferably 70% or more. By setting the thickness of the embedded portion 3 with respect to the entire thickness of the base material portion 2 to the above ratio, it is possible to realize the light emitting diode A having excellent heat dissipation and excellent workability when divided into element units.

  The heat sink substrate 1 is formed of at least a part of the side surface region of the light emitting diode A in a chip unit with the metal forming the base portion 2, and the inner region of the heat sink substrate 1 and the central region of the lower surface 1b are It is comprised with the said metal which makes the burying part 3. FIG. Although the metal material forming the base material portion 2 is a hard metal, it is a metal that can be easily divided by cutting, and is therefore disposed on the side surface of the light emitting diode A chip. In addition, since the base material portion 2 surrounds the embedded portion 3, the thermal expansion characteristics of the entire light emitting diode A are almost determined by the physical properties of the metal material forming the base material portion 2. In addition, with respect to the heat conduction characteristics, it is possible to obtain good characteristics by using the metal material forming the embedded portion 3 provided inside the heat sink substrate 1.

Moreover, as thickness of the heat sink board | substrate 1, it is preferable that it is the range of 30-300 micrometers, and it is more preferable that it is the range of 50-150 micrometers. Moreover, in this embodiment, it is preferable to make the thickness of the base material part 2 into the said range similar to the thickness of the heat sink board | substrate 1 whole. By setting the thickness of the entire heat sink substrate 1 and the thickness of the base material portion 2 within the above ranges, the strength as a wafer and the heat radiation characteristics when the embedded portion 3 is provided can be secured, and the manufacturing method described later is provided. In the dividing step, it is possible to easily divide the element. If the thickness of the heat sink substrate 1 as a whole and the thickness of the base material part 2 are less than 30 μm, the strength may be insufficient, and if it exceeds 300 μm, the splitting property in the splitting process is lowered and it is difficult to make a chip. There is a risk of becoming.
In addition, the embedded part 3 embedded in the base material part 2 can be set as the structure whose exposed surface is the same surface as the surface of the base material part 2, like the example shown to Fig.1 (a).

  Further, the heat sink substrate 1 may be formed as a substantially rectangular shape in a plan view having a length per side of 500 μm or more, which is preferable when the light emitting diode A is configured by providing the compound semiconductor layer 11 with a similar shape thereon. It is preferable from the viewpoints of obtaining heat dissipation and light emission characteristics and ease of division processing in the manufacturing process.

  Next, the compound semiconductor layer 11 is a compound semiconductor stacked structure including the light emitting layer 7 and having a pn junction structure. As illustrated in the schematic cross-sectional view illustrated in FIG. The layer 7 and the n-type semiconductor layer 8 are sequentially stacked.

  The compound semiconductor layer 11 described in the present embodiment is a layer formed in advance on the epitaxial growth substrate 30 (see FIG. 2 and FIG. 3). The light emitting diode A is formed by joining a p-type semiconductor layer 6 provided in a compound semiconductor layer 11 formed in advance on a top surface 2 a of a heat sink substrate 1 (base material portion 2) via a bonding layer 4. is there.

Although the compound semiconductor layer 11 can be composed of a compound semiconductor of either n-type or p-type conductivity, in the present invention, the emission efficiency of the light-emitting layer is particularly excellent, and a substrate bonding technique has been established. , general formula _{(Al X Ga 1-X)} Y in 1-Y P (0 ≦ X ≦ 1,0 <Y ≦ 1) can be suitably used a group III-V compound semiconductor represented by. On the other hand, the element structure of this embodiment can also be applied to a compound semiconductor layer including a light emitting layer of Al _X Ga _(1-X) As (0 ≦ X ≦ 1) from which red and infrared light emission can be obtained. Is possible.
Specifically, the compound semiconductor layer 11 has a structure as described below.

The p-type semiconductor layer 6 has p-type characteristics doped with a predetermined amount of Mg, Zn or the like, and is a p-type contact layer made of, for example, GaP. As a raw material for doping Mg, for example, known biscyclopentadienyl magnesium (bis- (C ₅ H ₅ ) ₂ Mg) or the like is used. In the present invention, the GaP is preferably used for the p-type semiconductor layer 6 in order to further improve the luminance. However, for example, any III-V group compound semiconductor crystal such as AlGaAs, AlGaInP, etc. It is possible to employ without limitation.

  In addition, the thickness of the p-type semiconductor layer 6 is preferably in the range of 0.5 to 20 μm, and more preferably in the range of 1 to 10 μm. When the thickness of the p-type semiconductor layer 6 is within this range, a thin film having good crystallinity is obtained, the light emission efficiency of the light emitting layer 7 described later is improved, and the light emission characteristics of the light emitting diode A are improved.

The light emitting layer 7 is provided on the p-type semiconductor layer 6 and has p-type characteristics doped with, for example, Mg, Zn, etc. in order from the p-type semiconductor layer 6 side, and (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P and (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P thin film p-type cladding layer 7c, undoped (Al _0.2 Ga _0.8 ) _0.5 In _0.5 P well layers and (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P barrier layers are alternately stacked in 10 pairs. configuration in which the multi-quantum well layer 7b, Si, and an n-type cladding layer 7a formed of _{(Al 0.7 Ga 0.3) 0.5 In} 0.5 P having an n-type characteristics doped with Te or the like, are laminated It is said that. Here, without the known luminescent layer 7 having a structure such as multi-well layer (multi-quantum well layer _{7b), (Al X Ga 1} -X) Y In 1-Y P (0 ≦ X ≦ 1,0 <Y ≦ The structure of the barrier layer and the well layer having the composition 1) can be appropriately determined so as to obtain a desired emission wavelength. Further, the composition, thickness, carrier concentration, and the like of the barrier layer forming the p-type cladding layer 7c, the n-type cladding layer 7a, and the multiple well layer 7b may be appropriately adjusted so that the light emission efficiency is increased. Moreover, in the light emitting diode of this embodiment, it is also possible to set it as the layer structure which switched the said n-type and p-type polarity.

  The light emitting layer 7 provided in the light emitting diode A of the present embodiment has a so-called pn junction type double heterojunction structure including the p-type cladding layer 7c, the multiple well layer 7b, and the n-type cladding layer 7a. . Since the light emitting layer 7 confines carriers responsible for radiative recombination, a known structure such as a double hetero (DH) structure or a multiple quantum well structure can be applied.

The multi-well layer 7b described above can be composed of a compound semiconductor of either n-type or p-type conductivity.
In addition, the light emitting layer 7 of the present embodiment is configured to include the multiple well layer 7b having the multiple well structure described above, but the light emitting structure is not limited thereto. For example, in addition to the multiple well structure, a single quantum well (SQW) structure can be adopted, but a multiple quantum well structure is more preferable in order to obtain excellent light emission.

  Further, the material of the light emitting layer 7 is not limited to the above-mentioned example, but other conventionally known materials such as GaInN-based and AlGaAs-based materials can also be used. In consideration of the above, it is preferable to select a material that can be directly grown on the laminated substrate. The light emitting layer 7 made of the material as described above can be formed on the surface of a single crystal substrate such as a lattice-matched III-V group compound semiconductor such as GaAs. In addition to the structure of the light emitting layer, a functional layer that is a conventionally known technique, for example, a contact layer, a current diffusion layer, a current blocking layer, a reflective layer, and the like can be provided.

  When the light emitting layer 7 is configured as a multiple well structure including the multiple well layer 7b as described above, the thickness of the barrier layer is set to a range of 10 to 100 nm and the thickness of the well layer is set to 10 to 100 nm. It is preferable to set it as the range. Moreover, it is preferable to set it as the range of 100-2000 nm as a film thickness of the multiple well layer 7b whole.

  The thickness of the p-type cladding layer 7c is preferably in the range of 200 to 2000 nm, and the thickness of the n-type cladding layer 7a is preferably in the range of 200 to 2000 nm. The film thickness of the entire light emitting layer 7 is preferably in the range of 500 to 1500 nm. By setting the thickness of the light emitting layer 7 and each layer constituting the light emitting layer 7 within the above range, the light emitting layer 7 having excellent crystallinity and excellent light emission efficiency can be obtained.

The n-type semiconductor layer 8 is provided on the light-emitting layer 7 and has an n-type characteristic in which Si, Te, and Sn are doped with a predetermined amount, for example, Si-doped (Al _0.5 Ga _{0. 5} ) An n-type contact layer made of _0.5 In _0.5 P. For example, disilane (Si ₂ H ₆ ) is used as a raw material for doping Si.

  The thickness of the n-type semiconductor layer 8 is preferably in the range of 100 to 8000 nm, and more preferably in the range of 500 to 3000 nm. When the thickness of the n-type semiconductor layer 8 is within this range, a thin film having good crystallinity is obtained, the light emission efficiency of the light emitting layer 7 is improved, and the light emission characteristics of the light emitting diode A are improved.

  As described above, according to the light emitting diode A of the present embodiment, the compound semiconductor layer 11 including at least the light emitting layer 7 is laminated on the upper surface 2a of the heat sink substrate 1, and the heat sink substrate 1 is connected to the base portion 2 and the substrate. In addition to the embedded portion 3 surrounded by the material portion 2, the base material portion 2 is made of a material having a smaller thermal expansion coefficient than that of the embedded portion 3, thereby achieving both workability and heat dissipation of the heat sink substrate 1. can do. As a result, it is possible to prevent the compound semiconductor layer 11 from being damaged such as cracks in the manufacturing process, improve the yield, and realize the light-emitting diode A capable of applying a high current and having high light emission efficiency.

The light emitting diode A according to the present embodiment has a high-density power of 0.5 W / mm ² or more between the electrodes between the heat sink substrate 1 serving as the positive electrode and the n-type electrode layer 9 serving as the negative electrode. Even when it is applied, the heat sinking action can be effectively obtained by the heat sink substrate 1. Therefore, the effect that the light emission luminance of the light emitting diode A is remarkably improved can be obtained.

[Method for manufacturing light-emitting diode]
Next, an example of a method for manufacturing the light-emitting diode A will be described with reference to FIGS.
In the method for manufacturing the light-emitting diode A according to the present invention, a compound semiconductor layer 11 including at least the light-emitting layer 7 is formed on a stacking substrate (see reference numeral 30 in FIG. 2 and the like). After a p-type ohmic electrode (second electrode) 5 is formed on the p-type semiconductor layer (second semiconductor layer) 6, the bonding layer 4 is laminated so as to cover the p-type ohmic electrode 5, and the laminated body 40. Forming a recess (see reference numeral 21 in FIG. 1 and the like) or a penetrating portion in at least a part of the base material portion 2 by an etching method, and forming the embedded portion 3 in the recess or the penetrating portion. After forming the heat sink substrate (substrate: see reference numeral 1 in FIG. 4 and the like), the laminate 40 and the heat sink are joined by joining the bonding layer 4 of the laminate 40 and the upper surface 2a side (one surface side) of the heat sink substrate 1. Bonding the substrate 1 and The substrate 11 for lamination is peeled off from the compound semiconductor layer 11 to expose the light extraction surface 11a of the n-type semiconductor layer (first semiconductor layer) 8 provided in the compound semiconductor layer 11, and then the light extraction surface 11a. Forming an n-type electrode layer (first electrode) 9 on the substrate, dividing the compound semiconductor layer 11 and the bonding layer 4 into a plurality of parts, and then forming between the plurality of compound semiconductor layers 11 A step of cutting the position of the base material portion 2 in the heat sink substrate 1 along the dividing groove 11b to divide it into element units, and the base material portion 2 has a coefficient of thermal expansion higher than that of the embedded portion 3. Is a method consisting of small materials.

  In addition, in the manufacturing method of the light-emitting diode A of the example described in the present embodiment, at least the n-type semiconductor layer 8, the light-emitting layer 7, and the p-type semiconductor layer 6 are sequentially stacked on the stacking substrate 30. Forming a p-type ohmic electrode 5 on the p-type semiconductor layer 6 of the compound semiconductor layer 11, and then laminating the bonding layer 4 so as to cover the p-type ohmic electrode 5. The heat sink substrate 1 is formed by forming a laminated body forming step of forming the body 40, and forming the recessed portion 21 in at least a part of the base material portion 2 by an etching method and then forming the embedded portion 3 in the recessed portion 21 by a plating method. A substrate forming step to be formed, and a bonding step of bonding the compound semiconductor layer 11 and the heat sink substrate 1 by bonding the bonding layer 4 of the laminate 40 and the upper surface 2a side of the heat sink substrate 1 The removing step of peeling the stacking substrate 30 from the compound semiconductor layer 11 to expose the light extraction surface 11a of the n-type semiconductor layer 8, and the n-type electrode layer 9 on the n-type semiconductor layer 8 provided in the compound semiconductor layer 11 After forming the electrode forming step of forming the compound semiconductor layer 11 and the bonding layer 4 into a plurality of parts, a base material in the heat sink substrate 1 is formed along the dividing grooves 11b formed between each of the plurality of compound semiconductor layers 11. A dividing step of cutting the position of the portion 2, and the base material portion 2 is made of a material having a smaller thermal expansion coefficient than the embedded portion 3.

In the example described in the present embodiment, a roughening step for roughening the light extraction surface 11a of the n-type semiconductor layer 8 is provided between the electrode forming step and the dividing step.
Hereafter, each process is demonstrated, referring drawings for an example of the manufacturing method of the light emitting diode of this embodiment.

"Semiconductor layer formation process"
In the semiconductor layer forming step, as shown in FIG. 2, an n-type semiconductor layer 8, a light emitting layer 7, and a p-type semiconductor layer 6 are sequentially stacked on a stacking substrate 30 capable of epitaxially growing a semiconductor crystal. Layer 11 is formed.

  Specifically, first, a lamination substrate 30 made of GaAs single crystal having n-type characteristics doped with Si and having a surface inclined by 15 ° from the (100) plane is prepared. Then, as illustrated in FIG. 2A, the compound semiconductor layer 11 is formed by stacking the n-type semiconductor layer 8, the light emitting layer 7, and the p-type semiconductor layer 6 in this order on the stacking substrate 30.

Here, as a material of the stacking substrate 30 for growing a semiconductor crystal, for example, sapphire (α-Al ₂ O ₃ single crystal), silicon carbide (SiC), gallium phosphide ( A substrate material capable of epitaxially growing a III-V group semiconductor crystal on the surface, such as GaP) and GaN, can be appropriately selected and used. The size of the laminated substrate 30 is usually about 2 inches or 3 inches in diameter, and a plurality of compound semiconductor layers are formed thereon, but the invention is not limited to this. It is also possible to use a larger substrate such as a 4-6 inch circular or rectangular substrate.

In the present embodiment, as the semiconductor layer forming step, first, a buffer layer (not shown) made of n-type GaAs doped with Si is formed on the lamination substrate 30, and a Si-doped (Al ₀₎ is formed thereon. _.5 Ga _0.5 ) _0.5 In _0.5 P n-type semiconductor layer 8, having Si-doped n-type characteristics (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P N-type cladding layer 7a, a well layer made of undoped (Al _0.2 Ga _0.8 ) _0.5 In _0.5 P, and (Al _0.7 Ga _0.3 ) _0.5 In _0.5 A multi-well layer 7b in which 10 pairs of barrier layers made of P are alternately stacked, and has Mg-doped p-type characteristics, and is made of (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P It becomes the second cladding layer and _{(Al 0.5} Ga _0.5) of 0.5 _{an in 0.5} P An example in which a light emitting layer 7 formed by laminating a p-type cladding layer 7c made of a film and a p-type semiconductor layer 6 made of GaP doped with Mg and having p-type characteristics will be described in order (FIG. 1A). See also).

The growth method of the n-type semiconductor layer 8, the light emitting layer 7 and the p-type semiconductor layer 6 constituting the compound semiconductor layer 11 is not particularly limited, and sputtering, MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor phase). All methods known to grow GaN-based semiconductors, such as a growth method), MBE (molecular beam epitaxy method), and LPE (liquid phase epitaxy method) can be applied. A preferable growth method includes MOCVD from the viewpoint of film thickness controllability and mass productivity.
In this embodiment, when forming each of the buffer layer, the n-type semiconductor layer 8, the light emitting layer 7, and the p-type semiconductor layer 6 having the above composition, trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) Each layer is formed on the stacking substrate 30 by a low pressure metal organic chemical vapor deposition method (MOCVD method) used as a raw material for ₃ Ga) and trimethylindium ((CH ₃ ) ₃ In) group III constituent elements. Can do.

As described above, biscyclopentadienylmagnesium (bis- (C ₅ H ₅ ) ₂ Mg) is used as a raw material for Mg to be doped when forming the p-type cladding layer 7 c and the p-type semiconductor layer 6. Can do. Further, disilane (Si ₂ H ₆ ) can be used as a raw material of Si to be doped when forming the n-type semiconductor layer 8 and the n-type cladding layer 7a.
In addition, phosphine (PH ₃ ) or arsine (AsH ₃ ) can be used as a raw material for the group V constituent element.

  As a growth temperature when forming the compound semiconductor layer 11, for example, the p-type semiconductor layer 6 made of GaP can be grown at a temperature of about 700 to 780 ° C., preferably about 750 ° C. The growth temperature of the other layers, that is, the layers including the n-type semiconductor layer 8 and the light emitting layer 7 and the buffer layer can also be about 700 to 780 ° C., preferably about 730 ° C.

Here, the buffer layer made of GaAs has a carrier concentration of about 0.1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ , which is about the same as that of a single crystal substrate, and a film thickness of about 0.1 to 1 μm. can do.
The n-type semiconductor layer 8 made of (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P has a carrier concentration of about 0.1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ^−3. The film thickness can be about 1 to 8 μm.

The n-type cladding layer 7a constituting the light emitting layer 7 can have a carrier concentration of about 1 × 10 ¹⁷ cm ⁻³ to 30 × 10 ¹⁷ cm ⁻³ and a film thickness of about 0.1 to 2 μm. The multiwell layer 7b is undoped and can have a thickness of about 0.2 to 2 μm. The p-type cladding layer 7c can have a carrier concentration of about 1 × 10 ¹⁷ cm ^{−3 to} 20 × 10 ¹⁷ cm ⁻³ and a film thickness of about 0.1 to ³ μm.

The p-type semiconductor layer 6 can have a carrier concentration of about 0.5 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ and a film thickness of about 0.5 to 20 μm. If the thickness of the p-type semiconductor layer 6 is small, current diffusion becomes insufficient and current is not uniformly supplied to the light emitting layer 7, which may cause a reduction in light emission efficiency. Further, when the film thickness is unnecessarily thick, the cost increases, and the layer growth may be technically difficult. Furthermore, when the carrier concentration of the p-type semiconductor layer 6 is low, current diffusion becomes insufficient, and when it is too high, the crystal quality may be deteriorated.

"Laminate formation process"
In the stacked body forming step, as shown in FIGS. 3A and 3B, after forming the p-type ohmic electrode 5 on each p-type semiconductor layer 6 of the compound semiconductor layer 11, the p-type ohmic electrode is formed. The laminated body 40 is formed by laminating the bonding layer 4 so as to cover 5.

  Specifically, as shown in FIG. 3A, first, a laminated film composed of an AuBe alloy film and an Au film is sequentially laminated on the p-type semiconductor layer 6 by a photolithography technique and patterned. A p-type ohmic electrode 5 is formed. At this time, it is preferable from the viewpoint of current diffusion that a plurality of p-type ohmic electrodes 5 are formed, for example, in a circular shape at a predetermined interval on the p-type semiconductor layer 6. In addition, it is preferable that mirror processing is performed on the p-type semiconductor layer 6 in advance because good contact can be obtained between the p-type semiconductor layer 6, the p-type ohmic electrode 5, and the bonding layer 4.

Next, as illustrated in FIG. 3B, the bonding layer 4 is further formed on each of the compound semiconductor layers 11.
Specifically, first, a translucent thin film layer 4 a made of ITO or the like is formed so as to cover the p-type ohmic electrode 5 formed on the p-type semiconductor layer 6 of the compound semiconductor layer 11. Then, a bonding layer 4 is formed by sequentially laminating a reflective layer 4b made of Ag or the like, a barrier layer 4c made of Mo or the like, an Au layer 4d, and a metal bonding layer 4e made of AuSn material or the like. As a method for forming each layer constituting the bonding layer 4, a conventionally known method can be employed without any limitation.

  By the above procedure, the stacked body 40 is formed by stacking the p-type ohmic electrode 5 and the bonding layer 4 on each of the compound semiconductor layers 11 formed on the stacking substrate 30.

"Substrate formation process"
In the laminated body forming step, as shown in FIGS. 4A and 4B, the recessed portion 21 is formed on at least a part of the base portion 2 by an etching method, and then the embedded portion 3 is formed inside the recessed portion 21. Thus, the heat sink substrate 1 is formed.

Specifically, first, the metal Mo lump is subjected to a rolling process, and the obtained rolled plate is punched out with a press to obtain the flat substrate portion 2. At this time, a conventionally known method can be used without any limitation as a method for rolling metal Mo.
Next, as shown in FIG. 4A, the concave portion 21 is formed on the lower surface 2 b of the base material portion 2. Here, in the light emitting diode A of the example shown in FIGS. 1A and 1B, the recess 21 is formed in a circular cross section. In this case, as a processing method of the base material portion 2, for example, a well-known technique such as an etching method or a mechanical processing method or a high-power laser drilling method can be applied, which is suitable for mass production. Etching is preferable from the viewpoint of low cost.

Next, as shown in FIG. 4B, the embedded portion 3 is formed by embedding a Cu material in the concave portion 21 formed on the lower surface 2 b side of the base portion 2.
Specifically, for example, a Cu material is embedded in the recess 21 using a plating method, a printing method, or the like, and the embedded portion 3 is formed. A method for forming the embedded portion 3 at this time is not particularly limited, but a plating method is preferable from the viewpoint of mass productivity. In particular, the electrolytic plating method is used because the processing speed is high and the productivity is improved. More preferred.

  Moreover, after embedding Cu material in the recessed part 21 of the base material part 2 and forming the embedding part 3, it is good also as a method of forming plating as it is to the lower surface 2b. Or it is good also as a method of covering the lower surface 2b of the base material part 2, and the surface of the burying part 3 with other metal materials more stable, for example, Au, Ag, Ni, Pt, Cu etc. On the other hand, depending on the surface state of the embedded portion 3, it is preferable that the surface is mirror-finished from the viewpoint that good bonding properties can be obtained in the bonding step described later. Further, by adding a eutectic metal for die bonding in addition to the Cu material, the process can be simplified.

  Moreover, in the board | substrate formation process of this embodiment, although the example which uses Mo material for the base material part 2 and uses Cu material as the embedding part 3 is demonstrated, it is not limited to this. For example, as described above, W having a thermal expansion coefficient characteristic approximate to that of the Mo material or an alloy material of Mo and W can be adopted as the base material portion 2. Similarly, the embedded portion 3 can be formed from a material containing at least one of Au, Ag, Cu, and Al, and can be selected and adopted as appropriate. .

  In the present embodiment, an example in which the recessed portion 21 is formed in the base material portion 2 to provide the embedded portion 3 in the substrate forming step before the bonding step described later is described, but the present invention is not limited to this. For example, in the joining step, after the laminate 20 and the upper surface 2a of the base material portion 2 are joined, the recessed portion 21 is formed on the lower surface 2b and the embedded portion 3 is provided. In such a case, for example, first, after joining the bonding layer 4 of the laminate 20 and the upper surface 2a of the base member 2 in the laminating process, a removing process and an electrode forming process described later are performed, and in the dividing process Before the element is divided, the recess 21 is formed on the lower surface 2b of the base member 2 by using an etching method. And it can be set as the method of forming the heat sink board | substrate 1 by providing the embedding part 3 by embedding Cu material inside the recessed part 21, and performing a plating process.

  Moreover, in the process of forming the recessed part 21 in the base material part 2 and providing the embedded part 3, the position of the embedded part 3 and the position of the compound semiconductor 11 can be performed either before or after the bonding process as described above. Needs to be formed while adjusting the position.

"Joining process"
In the joining step, as shown in FIG. 5, the compound semiconductor layer 11 and the heat sink substrate 1 are joined by joining the joining layer 4 of the laminate 40 and the upper surface 2 a that is one side of the heat sink substrate 1. .

  Specifically, as shown in FIG. 5, the metal bonding layer 4e forming the bonding layer 4 of the stacked body 20 and the upper surface 2a of the heat sink substrate 1 are bonded by, for example, AuSn eutectic bonding. At this time, it is preferable to form a film of Pt, Ni or the like on the upper surface 2a in advance by a sputtering method, a vapor deposition method, a plating method, or the like from the viewpoint of stabilizing the surface of the upper surface 2a and improving the bondability.

When performing AuSn eutectic bonding as described above, first, the substrate (laminated body 20 and heat sink substrate 1) is introduced into the substrate bonding apparatus and evacuated until the apparatus internal pressure becomes 3 × 10 ⁻⁵ Pa or less. To do. And it can be set as the method of performing eutectic bonding by heating substrate temperature to about 400 degreeC and applying a load of about 100 g / cm < ² >. Accordingly, the bonding layer 4 and the heat sink substrate 1 are in ohmic contact, and the stacked body 40 (compound semiconductor layer 11) and the heat sink substrate 1 are integrally formed.

  In the present embodiment, an example in which the compound semiconductor layer 11 and the heat sink substrate 1 are bonded by eutectic bonding of the bonding layer 4 and the heat sink substrate 1 by the above method is described. It is not limited to this. For example, for bonding the compound semiconductor layer 11 and the heat sink substrate 1, a known method using a thermocompression bonding method or an adhesive can be employed without any limitation.

"Removal process"
In the removing step, as shown in FIGS. 6A and 6B, the stacking substrate 30 and the buffer layer (not shown) are peeled off from the compound semiconductor layer 11 to expose the light extraction surface 11 a of the n-type semiconductor layer 8. .

  As a method of removing the buffer layer and the lamination substrate 30 (not shown), a known technique such as a mechanical polishing method, an etching method using an ammonia-based etchant, or a laser lift-off method can be used without any limitation. It is preferable to use an etching method from the viewpoint.

  Specifically, as shown in FIG. 6A, the buffer for the n-type semiconductor layer 8 is removed by removing the laminated substrate 30 and the buffer layer made of GaAs single crystal using an etchant of ammonia or hydrogen peroxide. The interface with the layer, that is, the light extraction surface 11a is exposed.

"Electrode formation process"
In the electrode forming step, as shown in FIG. 7, an AuGe / Ni alloy film having a thickness of 0.1 to 1 μm and a thickness of 1 to 3 μm are formed on the light extraction surface 11a of the n-type semiconductor layer 8. After the Au film is deposited by vacuum evaporation, the n-type electrode layer 9 is formed by patterning using a general photolithography means. In addition, the n-type electrode layer 9 is not limited to the above layer structure, and may be formed using other materials, and may be formed using, for example, a sputtering method or a vapor deposition method.

"Roughening process"
In the roughening step, the light extraction surface 11a of the n-type semiconductor layer 8 is roughened. As a method of the light extraction surface 11a, a method conventionally employed in this field can be used without any limitation.

"Division process"
In the dividing step, as shown in FIGS. 8 to 10, after at least a part of the compound semiconductor layer 11 is removed by etching and divided into a plurality of parts, the dicing saw 11b is exposed along the dividing groove 11b where the surface of the heat sink substrate 1 is exposed. The position of the base material portion 2 of the heat sink substrate 1 is cut by, for example, and divided into chips in element units to form a light emitting diode A. Then, after the division, this chip (element) is washed to remove the deposits generated during cutting.

  Further, in the substrate forming step for forming the heat sink substrate 1 described above, the Cu plating layer formed on the lower surface 2b of the base member 2 and the surface of the embedded portion 3 is removed.

  Next, as shown in FIG. 9, the position of the base material portion 2 of the heat sink substrate 1 is aligned along the dividing groove 11 b formed between each of the plurality of compound semiconductor layers 11 using, for example, a dicing saw. Disconnect. By performing such a dividing step, a substantially rectangular shape having a side length of 500 μm or more as shown in FIG. 10 (see also FIGS. 1A and 1B) (example shown in FIG. 1B). A plurality of light emitting diodes A, which are substantially square), are obtained.

  Here, in the method for manufacturing the light emitting diode A according to the present invention, the base material portion 2 is made of a material having a smaller thermal expansion coefficient than the embedded portion 3. Thus, in the dividing process as described above, the position at which the heat sink substrate 1 is cut becomes the position of the base material portion 2 that is excellent in workability. Therefore, the cutting process can be easily performed without applying stress to the compound semiconductor layer 11. Can be performed. As a result, since the compound semiconductor layer 11 is not damaged, the light emitting diode A having high light emission efficiency can be manufactured with high yield.

  As described above, according to the method for manufacturing the light emitting diode A of the present embodiment, the stacked body 20 in which the compound semiconductor layer 11 and the bonding layer 4 are stacked on the stacking substrate 30, the base material portion 2, Joining the compound semiconductor layer 11 and the heat sink substrate 1 by joining the heat sink substrate 1 including the embedded portion 3 provided inside the recess 21 (or the penetrating portion) formed in the base material portion 2. A step of separating the stacking substrate 30 from the compound semiconductor layer 11 to expose the light extraction surface 11a of the n-type semiconductor layer 8, and a dividing groove 11b formed between each of the plurality of compound semiconductor layers 11. And the dividing step of cutting the position of the base material portion 2 in the heat sink substrate 1, and since the base material portion 2 is made of a material having a smaller thermal expansion coefficient than the embedded portion 3, the compound semiconductor layer 11 Ni Tsu possible to prevent the damage of the click and the like occur, thereby improving yield, it is possible to manufacture a light emitting diode A having excellent heat radiation property of the heat sink substrate 1. As a result, it is possible to manufacture the light-emitting diode A that is capable of applying a high current and has excellent light emission efficiency with high production efficiency.

[Light emitting diode lamp]
Using the light emitting diode according to the present invention, a lamp can be constituted by means well known to those skilled in the art. As such a lamp, it can be used for any purpose such as a bullet type for general use, a side view type for portable equipment, and a top view type used for a display.

  For example, as in the example shown in FIG. 11, when the upper and lower electrode type light emitting diodes A are mounted in the top view type, the n electrode terminals 84 and the p electrode terminals 83 provided on the surface of the mounting substrate 85. On the other hand, in the illustrated example, the heat sink substrate 1 side of the light-emitting diode A is bonded to the p-electrode terminal 83, and the n-type electrode layer 9 of the light-emitting diode A is bonded to the n-electrode terminal 84 with a wire 86. Then, by molding the periphery of the light emitting diode A with a mold resin 81 made of a transparent resin, a top view type light emitting diode lamp (lamp) 80 as shown in FIG. 11 can be manufactured.

  In the light emitting diode lamp 80 shown in FIG. 11 (see also FIGS. 1A and 1B), the voltage applied between the n electrode terminal 83 and the p electrode terminal 84 is on the negative electrode side due to the above configuration. The light emitting layer 7 emits light by being applied to the compound semiconductor layer 11 through the n-type electrode layer 9 and the heat sink substrate 1 on the positive electrode side. The light emitted from the light emitting layer 7 is extracted toward the front direction F of the light emitting diode lamp 80.

Since the light-emitting diode lamp 80 according to the present embodiment uses the light-emitting diode A according to the present invention, the light-emitting diode lamp 80 has extremely high luminance and excellent light emission characteristics. In particular, even when power is applied at a high density of 0.5 W / mm ² or more between the electrodes, the heat generated by light emission is effectively dissipated, resulting in excellent luminous efficiency, high output, and high brightness. The light emitting diode lamp 80 is obtained.

In the light emitting diode lamp 80 having the above configuration, it is more preferable to adjust the material of the mounting substrate 85 so that the thermal resistance becomes 9 ° C./W or less, for example. As a result, when the light emitting diode A is caused to emit light by applying a high density power of 0.5 W / mm ² or more, for example, in addition to the heat dissipation effect by the heat sink substrate 1, the mounting substrate 85 Since a heat dissipation effect can be obtained, it becomes possible to further improve the light emission efficiency of the light-emitting diode A incorporated therein. The shape of the mounting substrate is formed in a plate shape in the example shown in FIG. 11, but is not limited to this, and other shapes can be adopted.

  Hereinafter, embodiments of a light-emitting diode, a manufacturing method thereof, and a lamp according to the present invention will be described in detail with reference to FIGS. 1 to 11 as appropriate, but the present invention is limited to the embodiments described below. It is not a thing.

[Example]
1A and 1B are schematic views of a light-emitting diode manufactured in this example, FIG. 1A is a cross-sectional view, and FIG. 1B is a plan view. FIG. 11 is a schematic cross-sectional view of a light-emitting diode lamp manufactured using the light-emitting diodes shown in FIGS.
In this embodiment, a heat sink substrate 1 composed of a laminated body made of a compound semiconductor layer provided on a laminated substrate made of GaAs, and a base part made of Mo material and an embedded part 3 made of a Cu plating layer is provided. By bonding, a light emitting element having an upper and lower electrode structure was manufactured. That is, the light emitting layer 7 is made of an AlGaInP-based compound semiconductor, and a light emitting diode A that emits red light is manufactured. Further, a top view type light emitting diode lamp 80 is manufactured using the light emitting diode A.

"Growth of compound semiconductor layer (semiconductor layer formation process)"
First, a laminated substrate 30 made of GaAs single crystal having n-type characteristics doped with Si and having a surface inclined by 15 ° from the (100) plane was prepared.
A buffer layer made of n-type GaAs doped with Si is first formed on the stacking substrate 30, and a Si-doped (Al _0.5 Ga _0.5 ) _0.5 In ₀ is formed thereon. _.5 having n-type characteristics of the n-type semiconductor layer 8, Si-doped consisting _{P (Al 0.7 Ga 0.3) 0.5} in 0.5 and n-type clad layer 7a composed of P, an undoped (Al 10 pairs of well layers composed of _0.2 Ga _0.8 ) _0.5 In _0.5 P and barrier layers composed of (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P A laminated multi-well layer 7b and a p-type cladding layer 7c having Mg-doped p-type characteristics and made of (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P are laminated. And a p-type semiconductor layer made of GaP doped with Mg and having p-type characteristics 6 were sequentially laminated.

In this example, when the buffer layer, the n-type semiconductor layer 8, the light emitting layer 7, and the p-type semiconductor layer 6 having the above composition are formed, trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) Each layer was formed on the stacking substrate 30 by a low pressure metal organic chemical vapor deposition method (MOCVD method) used as a raw material for ₃ Ga ₃ ) and trimethylindium ((CH ₃ ) ₃ In) group III constituent elements.

Biscyclopentadienyl magnesium (bis- (C ₅ H ₅ ) ₂ Mg) is used as a raw material for Mg doped into the p-type cladding layer 7 c and the p-type semiconductor layer 6, and the n-type semiconductor layer 8 and the n-type cladding are used. Disilane (Si ₂ H ₆ ) was used as a raw material for Si doped into the layer 7a. Further, phosphine (PH ₃ ) or arsine (AsH ₃ ) was used as a raw material for the group V constituent element. As the growth temperature of each layer, the p-type semiconductor layer 6 made of GaP was grown at 750 ° C., and the layers including the n-type semiconductor layer 8 and the light emitting layer 7 and the barrier layer were grown at 730 ° C.

In the film forming process, the buffer layer made of GaAs was formed with a carrier concentration of about 5 × 10 ¹⁸ cm ⁻³ and a film thickness of about 0.2 μm. The n-type semiconductor layer 8 was formed with a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ and a film thickness of about 1.5 μm. The n-type cladding layer 7a constituting the light emitting layer 7 has a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a film thickness of about 1 μm. The multi-well layer 7b is composed of undoped (Al _0.2 Ga _0.8 ) _0.5 In _0.5 P and (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P. Ten pairs of laminated structures were formed, and the layer thickness was 0.8 μm. The p-type cladding layer 7c is made of Mg-doped p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P, has a carrier concentration of 2 × 10 ¹⁷ cm ⁻³ , and has a layer thickness of It was 1 μm. The p-type semiconductor layer 6 is a p-type GaP layer doped with Mg, has a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ , and a layer thickness of 3 μm.

  Through the above process steps, the n-type semiconductor layer 8, the light emitting layer 7, and the p-type semiconductor layer 6 were stacked in this order on the stacking substrate 30 to form the compound semiconductor layer 11.

"Formation of laminate (laminate formation process)"
Next, the p-type semiconductor layer 6 of the compound semiconductor layer 11 formed in the above process is mirror-finished by polishing a region extending from the surface to a depth of 1 μm, thereby reducing the surface roughness of the p-type semiconductor layer 6 to 0. About 18 nm.
Next, a p-type ohmic electrode 5 was formed by sequentially laminating and patterning a laminated film made of an AuBe alloy film and an Au film on the mirror-polished p-type semiconductor layer 6 by a photolithography technique. At this time, the thicknesses of the AuBe alloy film / Au film were set to 0.4 μm / 0.2 μm, respectively, and a plurality of p-type ohmic electrodes 5 having a diameter of 20 μm were formed at regular intervals of 80 μm.

  Next, the junction layer 4 was formed on the p-type semiconductor layer 6 so as to cover the p-type ohmic electrode 5 formed on the p-type semiconductor layer 6 of the compound semiconductor layer 11. First, a transparent conductive thin film layer 4a made of ITO is formed so as to completely cover the plurality of p-type ohmic electrodes 5, and then subjected to heat treatment at a temperature of 450 ° C. Formed. Next, a 0.5 μm reflective layer 4b made of an Ag alloy, a barrier layer 4c in which W and Pt are stacked by 0.1 μm each, a 0.5 μm Au layer 4d, and an AuGe material (melting point: 386 ° C.) Each layer of the 1 μm metal bonding layer 4e made of the above was sequentially laminated using a vapor deposition method to form the bonding layer 4.

"Formation of heat sink substrate (substrate formation process)"
Next, the metal Mo lump was subjected to a rolling process, and the obtained rolled plate was punched out with a press to obtain a flat substrate portion 2 having a thickness of 80 μm. Next, a circular pattern having a diameter of 300 μm was formed on the lower surface 2 b side of the base material portion 2 at intervals of 500 μm. And the recessed part 21 of 65 micrometers in depth (residual thickness of the base-material part 2: 15 micrometers) was formed using the etching method. At this time, the diameter on the lower surface 2b side after the etching process was enlarged to 400 μm, and the vertical section became trapezoidal.

Next, an embedded portion 3 made of a Cu plating layer is embedded in the concave portion 21 formed in the base material portion 2 by an electrolytic plating method. Further, the entire surface of the bottom surface 2b of the base material portion 2 and the embedded portion 3 has a thickness of 1 μm. The heat sink substrate 1 was obtained by plating. This heat sink substrate 1 had a thermal expansion coefficient of 5.5 ppm / K and a thermal conductivity of 220 W / m · K.
Then, 0.1 μm of Pt was formed on the upper surface 2a side by a sputtering method to stabilize the surface.

“Bonding of compound semiconductor layer and heat sink substrate (joining process)”
Next, the compound semiconductor layer 11 and the heat sink substrate 1 were bonded by eutectic bonding of the metal bonding layer 4e provided in the bonding layer 4 of the stacked body 20 and the upper surface 2a side of the heat sink substrate 1. In this eutectic bonding, first, (the laminated body 20 and the heat sink substrate 1) was introduced into the substrate bonding apparatus, and evacuation was performed until the internal pressure of the apparatus became 3 × 10 ⁻⁵ Pa or less. Next, after heating the substrate temperature to about 400 ° C., a load of about 100 g / cm ² was applied to eutectic bond the upper surface 2a of the heat sink substrate 1 and the metal bonding layer 4e.

"Removal of substrate for lamination (removal process)"
Next, the lamination substrate 30 was removed from the compound semiconductor layer 11 to expose the light emitting surface 11a. At this time, the stacking substrate 30, the buffer layer (not shown), and the base layer were selectively removed using an ammonia-based etchant or the like.

“Formation of n-type electrode layer (electrode formation process)”
Next, an n-type electrode layer 9 was formed on the n-type semiconductor layer 8. At this time, first, 0.15 μm AuGe (Ge mass ratio 12%), 0.05 μm Ni, and 1 μm Au were sequentially stacked on the n-type semiconductor layer 8 by vacuum deposition. Then, after patterning using a general photolithography method, alloying was performed by performing a heat treatment at 420 ° C. for 3 minutes to form an n-type electrode layer 9 having a low contact resistance. At this time, the heat sink substrate 1 was also alloyed.

"Chip division (division process)"
Next, the wafer produced by each of the above steps was cut by dicing and divided into chips in element units so as to be a substantially square (rectangular shape) in plan view.
First, after removing the compound semiconductor layer 11 and the bonding layer 4 by etching along a cutting line, a base material portion 2 made of a Mo material in the exposed heat sink substrate 1 using a dicing saw equipped with a diamond blade. Was cut at a pitch of 0.5 mm. And the cut surface was wash | cleaned by the wet method, protecting the compound semiconductor layer 11 by sticking the adhesive sheet to the side surface of the compound semiconductor layer 11. FIG.
Through the above procedures, a chip-shaped light emitting diode A having a shape of a plan view and a substantially square shape with a side of 500 μm was manufactured.

"Production of lamp"
By mounting the light emitting diode A obtained by the above procedure, a top view type light emitting diode lamp 80 as shown in FIG. 11 was produced.
First, the heat sink substrate 1 side of the light-emitting diode A is bonded to a p-electrode terminal 83 provided on the surface of the mounting substrate 85 having a thermal resistance of 9 ° C./W, and the n-type electrode layer 9 of the light-emitting diode A is bonded. Was bonded to the n-electrode terminal 84 with a wire 86. Then, a top view type light emitting diode lamp (lamp) 80 as shown in FIG. 11 was manufactured by molding the periphery of the light emitting diode A with a mold resin 81 made of a transparent resin.

"Measurement of luminous characteristics"
With respect to the light emitting diode lamp 80 on which the light emitting diode A obtained by the above procedure is mounted, the forward direction is established between the electrodes of the n-type electrode layer 9 and the heat sink substrate 1 through the n electrode terminal 84 and the p electrode terminal 83. When an electric current was passed, red light having a dominant wavelength of 620 nm was emitted. Further, the luminous efficiency when a forward current of 150 mA was passed between each electrode at a forward voltage of 2.2 V was about 70 lm / W, and it was revealed that the luminous efficiency was high. The power density at this time was 1.43 W / mm ² .

[Comparative Example 1]
In Comparative Example 1, a light-emitting diode was fabricated in the same manner as in the above-described example except that the entire substrate was made of a Cu material and a heat sink substrate having a thickness of 80 μm was used, and this light-emitting diode was further used. A top view type light emitting diode lamp was manufactured in the same manner as in the above example. The heat sink substrate made of the Cu material used in this comparative example had a thermal conductivity of 398 W / m · K and a thermal expansion coefficient of 16.8 ppm / K.

  In this comparative example, after joining the heat sink substrate and the laminated body including the compound semiconductor layer in the joining step, cracks occurred in the compound semiconductor layer. This is presumably because the compound semiconductor layer was cracked due to a large stress generated because the difference in thermal expansion coefficient between the heat sink substrate and the compound semiconductor layer was large. In this comparative example, when the chips were divided in the dividing process, the blade of the dicing saw was consumed very much, chipping occurred frequently, and only a small amount of chips could be produced, resulting in a low yield. Thus, in this comparative example, most of the chips after the division were rejected, and it became clear that this was not a practical process.

  In addition, regarding the lamp on which the light emitting diode of this comparative example, which was able to be manufactured without causing damage in the dividing process, is mounted on each of the n-type electrode layer and the heat sink substrate via the n-electrode terminal and the p-electrode terminal. When a forward current was passed between the electrodes, red light having a dominant wavelength of 620 nm was emitted. Further, the luminous efficiency when a forward current of 150 mA was passed between each electrode at a forward voltage of 2.2 V was about 72 lm / W, and there was no problem in terms of luminous efficiency, but as described above, In the comparative example, most of the chips after the division failed and were not practical from the viewpoint of industrial productivity.

[Comparative Example 2]
In Comparative Example 2, a light emitting diode was manufactured in the same manner as in the above example except that the entire substrate was made of Mo material and a heat sink substrate having a thickness of 80 μm was used. A top view type light emitting diode lamp was manufactured in the same manner as in the above example. The heat sink substrate made of the Mo material used in this comparative example had a thermal conductivity of 138 W / m · K.

  In this comparative example, since the difference in thermal expansion coefficient between the heat sink substrate made of Mo material and the compound semiconductor layer is small, the compound semiconductor layer is not damaged in the joining process, and the processability in the dividing process The yield was also good and the yield was high.

  In addition, when a forward current was passed between each electrode of the n-type electrode layer and the heat sink substrate through the n-electrode terminal and the p-electrode terminal for the lamp on which the light-emitting diode of this comparative example was mounted, the dominant wavelength was Red light having a wavelength of 620 nm was emitted. Further, the luminous efficiency when a forward current of 150 mA was passed between each electrode at a forward voltage of 2.2 V was about 62 lm / W, and it became clear that the luminous efficiency was inferior to the above examples. This is presumably because the entire heat sink substrate is made of Mo material, so that the workability at the time of division is excellent, but since the heat dissipation is not sufficient, the luminous efficiency is low.

  From the above results, it is clear that the light emitting diode according to the present invention and the lamp using the light emitting diode have excellent luminous efficiency and high luminance, and the method for manufacturing the light emitting diode according to the present invention is excellent in yield. It is.

  Since the light-emitting diode of the present invention provides an unprecedented high-brightness and high-efficiency light-emitting diode with excellent heat dissipation characteristics, it can be suitably used for various display lamps and lighting fixtures.

DESCRIPTION OF SYMBOLS 1 ... Heat sink substrate (board | substrate), 2 ... Base material part, 21 ... Recessed part, 2a ... Upper surface (one surface side), 2b ... Lower surface, 3 ... Embedded part, 4 ... Bonding layer, 5 ... p-type ohmic electrode, 6 ... p Type semiconductor layer, 7 ... light emitting layer, 8 ... n type semiconductor layer, 9 ... n type electrode layer, 11 ... compound semiconductor layer, 11a ... light extraction surface, 11b ... dividing groove, 30 ... substrate for lamination, A ... light emitting diode , 80 ... Light-emitting diode lamp (lamp)

Claims (19)

A light emitting diode having a chip structure in which a compound semiconductor layer including at least a light emitting layer is stacked on a substrate, and an upper surface side of the compound semiconductor layer is a light emitting surface,
The substrate comprises a substrate portion, Rutotomoni such from the embedded portion surrounded by the base material portion, the concave portion is formed on the lower surface side of the base portion, the embedded portion is provided in the recess, and, The thickness of the embedded portion is 70% or more of the thickness of the base material portion,
Further, the substrate includes a said base portion and said embedded portion is, it becomes a different metal materials, respectively, the base portion is Ri Do a small material coefficient of thermal expansion than the embedded portion,
The compound semiconductor layer, in the substrate, on the upper surface of the base portion, at least, p-type semiconductor layer, light-emitting diodes each light-emitting layer and the n-type semiconductor layer is characterized Rukoto such are stacked. 2. The light emitting diode according to claim 1, wherein a difference in thermal expansion coefficient between the base material portion and the compound semiconductor layer is ± 1.5 ppm / K or less. The substrate, the light emitting diode of claim 1 or claim 2 thermal conductivity, characterized in that it is 200 W / m · K or more. The light emitting diode according to any one of claims 1 to 3 , wherein the base portion is made of molybdenum, tungsten, or an alloy material thereof. The embedded portion is gold, silver, copper, or aluminum-emitting diode according to any one of claims 1 to 4, characterized in that a material containing at least any one or more of the. The light emitting diode according to claim 5 , wherein the embedded portion is a plated layer containing at least one of gold, silver, copper, and aluminum . The light emitting diode according to any one of claims 1 to 6 , wherein the light emitting layer included in the compound semiconductor layer is made of a material containing AlGaInP or AlGaAs. The light emitting diode according to any one of claims 1 to 7 , wherein the substrate has a substantially square shape in a plan view with a length per side of 500 µm or more . Further, an n-type electrode layer that is a negative electrode is provided on the n-type semiconductor layer of the compound semiconductor layer, and the substrate is a positive electrode, and power having a density of 0.5 W / mm ² or more between the electrodes. The light emitting diode according to any one of claims 1 to 8, wherein is applied. The light emitting diode according to any one of claims 1 to 9 , wherein the substrate and the compound semiconductor layer are bonded together by a metal bonding layer. The light emitting diode according to any one of claims 1 to 9 , wherein the substrate and the compound semiconductor layer are directly bonded to each other. A compound semiconductor layer including the light-emitting layer is formed by sequentially stacking at least an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer on the stacking substrate , and a second semiconductor layer provided in the compound semiconductor layer Forming a stacked body by forming a second electrode having ohmic characteristics on the substrate and then laminating a bonding layer so as to cover the second electrode ;
Together to form a concave portion by etching at least a portion of the lower surface side of the base portion to form a buried portion surrounded by the base portion inside the concave portion, the thickness of the embedded portion, the After the substrate is formed as 70% or more of the thickness of the base material portion, the step of joining the laminate and the substrate by joining the joining layer of the laminate and the upper surface side of the substrate;
The stacking substrate is peeled from the compound semiconductor layer to expose the light extraction surface of the first semiconductor layer provided in the compound semiconductor layer, and then a first electrode is formed on the light extraction surface. Process,
After the compound semiconductor layer and the bonding layer are divided into a plurality of elements, the position of the base material portion in the substrate is cut along a dividing groove formed between each of the plurality of compound semiconductor layers. Dividing the process into
In the light-emitting diode, the substrate includes the base portion and the embedded portion made of different metal materials, and the base portion is made of a material having a smaller thermal expansion coefficient than the embedded portion. Production method. A semiconductor layer forming step of forming a compound semiconductor layer by sequentially stacking at least an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a stacking substrate;
A laminated body forming step of forming a laminated body by forming a p-type ohmic electrode on the p-type semiconductor layer provided in the compound semiconductor layer and then laminating a bonding layer so as to cover the p-type ohmic electrode;
After forming the concave portion by etching at least a portion of the lower surface side of the base portion, thereby forming a buried portion surrounded by the base portion inside the concave portion, the thickness of the embedded portion, A substrate forming step of forming a substrate as 70% or more of the thickness of the base material portion ;
A bonding step of bonding the compound semiconductor layer and the substrate by bonding the bonding layer of the laminate and the upper surface side of the substrate;
Removing the stacking substrate from the compound semiconductor layer to expose a light extraction surface of the n-type semiconductor layer provided in the compound semiconductor layer;
Forming an n-type electrode layer on the light extraction surface of the n-type semiconductor layer;
After dividing the compound semiconductor layer and the bonding layer into a plurality, a dividing step of cutting the position of the base material portion in the substrate along a dividing groove formed between each of the plurality of compound semiconductor layers; It has
In the light-emitting diode, the substrate includes the base portion and the embedded portion made of different metal materials, and the base portion is made of a material having a smaller thermal expansion coefficient than the embedded portion. Production method. The method for manufacturing a light-emitting diode according to claim 13 , wherein in the substrate forming step, the embedded portion is formed in a concave portion of the base portion using a plating method. The method for manufacturing a light emitting diode according to claim 13 or 14 , wherein, in the substrate forming step, the base portion is formed from molybdenum, tungsten, or an alloy material thereof. Said substrate forming step, the embedded portion, gold, silver, copper, or any of claims 13 to claim 15, wherein the forming a material containing at least any one or more of the aluminum 1 The manufacturing method of the light emitting diode as described in a term. In between the dividing step and the electrode forming step, any one of claims 13 to claim 16, characterized by providing roughening step of roughening the light extraction surface of the n-type semiconductor layer 1 The manufacturing method of the light emitting diode as described in a term. Emitting diode obtained by the process according to any one of claims 12 to claim 17. A lamp comprising the light emitting diode according to any one of claims 1 to 11 or claim 18 .

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