TWI513038B - Light-emitting device - Google Patents
Light-emitting device Download PDFInfo
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- TWI513038B TWI513038B TW101100762A TW101100762A TWI513038B TW I513038 B TWI513038 B TW I513038B TW 101100762 A TW101100762 A TW 101100762A TW 101100762 A TW101100762 A TW 101100762A TW I513038 B TWI513038 B TW I513038B
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- illuminating device
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- 239000004065 semiconductor Substances 0.000 claims description 73
- 239000000758 substrate Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 3
- 238000002474 experimental method Methods 0.000 description 21
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910005540 GaP Inorganic materials 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XTDKZSUYCXHXJM-UHFFFAOYSA-N 2-methoxyoxane Chemical compound COC1CCCCO1 XTDKZSUYCXHXJM-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004205 dimethyl polysiloxane Substances 0.000 description 1
- 235000013870 dimethyl polysiloxane Nutrition 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- CXQXSVUQTKDNFP-UHFFFAOYSA-N octamethyltrisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)O[Si](C)(C)C CXQXSVUQTKDNFP-UHFFFAOYSA-N 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000004987 plasma desorption mass spectroscopy Methods 0.000 description 1
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Description
本發明係關於一種發光裝置，更具體而言，係關於一種具有複數個凹槽的發光裝置。 The present invention relates to a light-emitting device, and more particularly to a light-emitting device having a plurality of grooves.
固態發光元件中之發光二極體元件(Light Emitting Diode；LED)具有低耗電量、低發熱量、操作壽命長、耐撞擊、體積小、反應速度快、以及可發出穩定波長的色光等良好光電特性，因此常應用於家電、儀表之指示燈及光電產品等領域。然而，如何去改善發光元件的發光效率在此領域中仍是一項很重要的議題。 Light Emitting Diode (LED) in solid-state light-emitting elements has low power consumption, low heat generation, long operating life, impact resistance, small volume, fast response, and good color light with stable wavelength. Photoelectric characteristics, so it is often used in the fields of home appliances, instrument indicators and optoelectronic products. However, how to improve the luminous efficiency of the light-emitting element is still an important issue in this field.
一發光裝置，包含：一基板；一透明導電層，設置於基板上；一半導體窗戶層，形成於透明導電層上且具有一平坦表面及複數個凹槽，其中每一凹槽具有一側壁表面；及一發光疊層，形成於半導體窗戶層上且包含一第一半導體層、一第二半導體層、一位於第一和第二半導體之間的活性層。此些凹槽中之至少其中一個之側壁表面相對於平坦表面傾斜，且平坦表面與透明導電層之間的接觸電阻係小於側壁表面與透明導電層之間的接觸電阻。 An illuminating device comprises: a substrate; a transparent conductive layer disposed on the substrate; a semiconductor window layer formed on the transparent conductive layer and having a flat surface and a plurality of grooves, wherein each groove has a sidewall surface And a light-emitting layer formed on the semiconductor window layer and comprising a first semiconductor layer, a second semiconductor layer, and an active layer between the first and second semiconductors. The sidewall surface of at least one of the grooves is inclined with respect to the flat surface, and the contact resistance between the flat surface and the transparent conductive layer is less than the contact resistance between the sidewall surface and the transparent conductive layer.
本發明另提供一種發光裝置，包含：一基板；一透明導電層，設置於基板上；一半導體窗戶層，形成於透明導電層上且具有一平坦表面及複數個凹槽，其中每一凹槽具有一側壁表面；一歐姆接觸層，形成於半導體窗戶層與透明導電層之間；及一發光疊層，形成於半導體窗戶層上且包含一第一半導體層、一第二半導體層、一位於第一和第二半導體之間的活性層。半導體窗戶層與歐姆接觸層包含相同材料。 The invention further provides a light-emitting device, comprising: a substrate; a transparent conductive layer disposed on the substrate; a semiconductor window layer formed on the transparent conductive layer and having a flat surface and a plurality of grooves, wherein each groove Having a sidewall surface; an ohmic contact layer formed between the semiconductor window layer and the transparent conductive layer; and a light emitting layer formed on the semiconductor window layer and including a first semiconductor layer, a second semiconductor layer, and a layer An active layer between the first and second semiconductors. The semiconductor window layer and the ohmic contact layer comprise the same material.
100、200、300‧‧‧發光裝置 100, 200, 300‧‧‧ illuminating devices
10‧‧‧基板 10‧‧‧Substrate
11‧‧‧反射層 11‧‧‧reflective layer
12‧‧‧透明導電層 12‧‧‧Transparent conductive layer
13‧‧‧歐姆接觸層 13‧‧‧Ohm contact layer
14‧‧‧半導體窗戶層 14‧‧‧Semiconductor window layer
141‧‧‧平坦表面 141‧‧‧flat surface
142‧‧‧凹槽 142‧‧‧ Groove
1421‧‧‧側壁表面 1421‧‧‧ sidewall surface
1422‧‧‧凹槽表面 1422‧‧‧ Groove surface
15‧‧‧發光疊層 15‧‧‧Lighting laminate
151‧‧‧p型半導體層 151‧‧‧p-type semiconductor layer
152‧‧‧活性層 152‧‧‧Active layer
153‧‧‧n型半導體層 153‧‧‧n type semiconductor layer
16‧‧‧n側電極 16‧‧‧n side electrode
160、160'、160"‧‧‧打線墊 160, 160', 160" ‧ ‧ line mat
161、161'、161"‧‧‧延伸部 161, 161', 161" ‧ ‧ extension
17‧‧‧p側電極 17‧‧‧p side electrode
18‧‧‧連結層 18‧‧‧Linking layer
第1圖為本發明第一實施例之一發光裝置之一剖面圖。 Fig. 1 is a cross-sectional view showing a light-emitting device according to a first embodiment of the present invention.
第2圖為本發明第二實施例之一發光裝置之一剖面圖。 Figure 2 is a cross-sectional view showing a light-emitting device of a second embodiment of the present invention.
第3圖為本發明第三實施例之一發光裝置之一剖面圖。 Figure 3 is a cross-sectional view showing a light-emitting device of a third embodiment of the present invention.
第4A-4C圖顯示本發明凹槽之俯視圖。 Figures 4A-4C show top views of the grooves of the present invention.
第5A-5G圖為本發明第二實施例之發光裝置的製造方法剖面圖。 5A-5G are cross-sectional views showing a method of manufacturing a light-emitting device according to a second embodiment of the present invention.
以下實施例將伴隨著圖式說明本發明之概念，在圖式或說明中，相似或相同之部分係使用相同之標號，並且在圖式中，元件之形狀或厚度可擴大或縮小。需特別注意的是，圖中未繪示或描述之元件，可以是熟習此技藝之人士所知之形式。 The present invention will be described with reference to the drawings, in which the same or the same reference numerals are used in the drawings or the description, and in the drawings, the shape or thickness of the elements may be enlarged or reduced. It is to be noted that elements not shown or described in the figures may be in a form known to those skilled in the art.
第1圖為本發明第一實施例之一發光裝置100之示意圖。發光裝置100包含一永久基板10、一連結層18、一反射層11、一透明導電層12、一歐姆接觸層13、一半導體窗戶層14及一發光疊層15。發光疊層15包含一p型半導體層151、一n型半導體層153及一位於p型半導體層151與n型半導體層153之間的活性 層152。半導體窗戶層14具有一平坦表面141及複數個凹槽142。每一凹槽142具有一側壁表面1421，係相對於平坦表面141傾斜且與之夾一大於90°而小於180°的角度(Θ)。較佳地，角度(Θ)介於110°到160°之間。在本實施例中，凹槽142之剖面為三角形。歐姆接觸層13形成於半導體窗戶層14與透明導電層12間，且對應於半導體窗戶層14之平坦表面141的位置上。歐姆接觸層13之表面積與半導體窗戶層14之表面積的面積比介於10%至90%。凹槽142具有一深度(H)且凹槽142之深度與半導體窗戶層14之厚度(T)的一深度比介於20%至80%。 1 is a schematic view of a light-emitting device 100 according to a first embodiment of the present invention. The light emitting device 100 includes a permanent substrate 10, a bonding layer 18, a reflective layer 11, a transparent conductive layer 12, an ohmic contact layer 13, a semiconductor window layer 14, and a light emitting laminate 15. The light emitting laminate 15 includes a p-type semiconductor layer 151, an n-type semiconductor layer 153, and an active layer between the p-type semiconductor layer 151 and the n-type semiconductor layer 153. Layer 152. The semiconductor window layer 14 has a flat surface 141 and a plurality of grooves 142. Each of the recesses 142 has a side wall surface 1421 that is inclined relative to the flat surface 141 and is angled by more than 90° and less than 180°. Preferably, the angle (Θ) is between 110° and 160°. In the present embodiment, the groove 142 has a triangular cross section. The ohmic contact layer 13 is formed between the semiconductor window layer 14 and the transparent conductive layer 12 and corresponds to the position of the flat surface 141 of the semiconductor window layer 14. The area ratio of the surface area of the ohmic contact layer 13 to the surface area of the semiconductor window layer 14 is between 10% and 90%. The groove 142 has a depth (H) and a depth ratio of the depth of the groove 142 to the thickness (T) of the semiconductor window layer 14 is between 20% and 80%.
根據第1圖，發光裝置100更包含一形成於發光疊層15上之n側電極16、一形成於永久基板10上之p側電極17。n側電極16包含一打線墊160及一自打線墊延伸之延伸部161形成於發光疊層15並對應於凹槽142的位置上。本實施例中，歐姆接觸層13實質上與半導體窗戶層14為同一材料。此外，歐姆接觸層13更包含摻雜物，以與透明導電層12形成歐姆接觸。因此，平坦表面141與透明導電層12之間的接觸電阻(contact resistance)係小於側壁表面1421與透明導電層12之間的接觸電阻，藉此，當一電源供應器連結至n側電極16與p側電極17時，大部分的電流係流經過半導體窗戶層14之平坦表面141，而在側壁表面1421與透明導電層12之間形成一電流阻擋(current blocking)的效應。更者，發自發光疊層15的光會於側壁表面1421反射且直接脫離發光疊層15之一發光表面，以增加光取出效率(light extraxtion efficiency)。半導體窗戶層14之材料包含磷化鎵(GaP)、磷化鎵銦(InGaP)、砷化鎵(GaAs)、砷化鋁鎵(AlGaAs)、及其組合。摻雜物包含鎂、鈹、鋅、碳、及其組合。 According to FIG. 1 , the light-emitting device 100 further includes an n-side electrode 16 formed on the light-emitting layer 15 and a p-side electrode 17 formed on the permanent substrate 10. The n-side electrode 16 includes a wire pad 160 and an extension portion 161 extending from the wire bonding pad formed at the position of the light emitting laminate 15 and corresponding to the recess 142. In the present embodiment, the ohmic contact layer 13 is substantially the same material as the semiconductor window layer 14. Further, the ohmic contact layer 13 further contains a dopant to form an ohmic contact with the transparent conductive layer 12. Therefore, the contact resistance between the flat surface 141 and the transparent conductive layer 12 is smaller than the contact resistance between the sidewall surface 1421 and the transparent conductive layer 12, whereby a power supply is coupled to the n-side electrode 16 and At the p-side electrode 17, most of the current flows through the flat surface 141 of the semiconductor window layer 14, creating a current blocking effect between the sidewall surface 1421 and the transparent conductive layer 12. Moreover, the light emitted from the light-emitting layer 15 is reflected by the side wall surface 1421 and directly deviated from one of the light-emitting surfaces of the light-emitting layer 15 to increase light extraxtion efficiency. The material of the semiconductor window layer 14 comprises gallium phosphide (GaP), indium gallium phosphide (InGaP), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), and combinations thereof. The dopants include magnesium, barium, zinc, carbon, and combinations thereof.
第2圖為本發明第二實施例之一發光裝置200之示意圖。第二實施例之發光裝置200與第一實施例之發光裝置100具有相似的結構，除了凹槽142之 剖面為梯形且每一凹槽142更具有一凹槽表面1422。每一凹槽142之凹槽表面1422實質上係與平坦表面141平行。打線墊160'及延伸部161'係形成在對應於凹槽表面1422與側壁表面1421的位置上。選擇性地，n側電極16可僅形成在對應於凹槽表面1422的位置上(圖未示)。凹槽表面1422與透明導電層12之間的接觸電阻(contact resistance)實質上係等於側壁表面1421與透明導電層12之間的接觸電阻。應注意的是，凹槽142的剖面至少包含一選自下列圖形：三角形、梯形、及其組合。 2 is a schematic view of a light emitting device 200 according to a second embodiment of the present invention. The light-emitting device 200 of the second embodiment has a similar structure to the light-emitting device 100 of the first embodiment except for the groove 142 The cross section is trapezoidal and each groove 142 has a groove surface 1422. The groove surface 1422 of each groove 142 is substantially parallel to the flat surface 141. The wire pad 160' and the extension portion 161' are formed at positions corresponding to the groove surface 1422 and the side wall surface 1421. Alternatively, the n-side electrode 16 may be formed only at a position corresponding to the groove surface 1422 (not shown). The contact resistance between the groove surface 1422 and the transparent conductive layer 12 is substantially equal to the contact resistance between the sidewall surface 1421 and the transparent conductive layer 12. It should be noted that the cross section of the recess 142 includes at least one selected from the group consisting of a triangle, a trapezoid, and combinations thereof.
第3圖為本發明第三實施例之一發光裝置300之示意圖。第三實施例之發光裝置300與第一實施例之發光裝置100具有相似的結構，除了部分凹槽142之側壁表面1421並非相對於平坦表面141傾斜。在本實施例中，形成於打線墊160"下方之凹槽142具有實質上垂直於平坦表面141之側壁表面1421；形成於延伸部161"下方之凹槽142具有傾斜於平坦表面141之側壁表面1421。 Fig. 3 is a schematic view showing a light-emitting device 300 according to a third embodiment of the present invention. The light-emitting device 300 of the third embodiment has a similar structure to the light-emitting device 100 of the first embodiment except that the side wall surface 1421 of the partial groove 142 is not inclined with respect to the flat surface 141. In the present embodiment, the groove 142 formed under the wire pad 160" has a sidewall surface 1421 substantially perpendicular to the flat surface 141; the groove 142 formed below the extension portion 161 has a sidewall surface inclined to the flat surface 141. 1421.
第4A圖及第4B圖為n側電極16與凹槽142之俯視圖。顯示於第4B圖之凹槽142具有一第一圖案，其幾何圖形與顯示於第4A圖之n側電極16相似且形成於n側電極16之下方。第4C圖為另一實施例中之凹槽142之俯視圖。在此實施例中，凹槽142更具有一第二圖案。第二圖案為六角形的鑲嵌結構(tesslation of hexagons)。選擇性地，於俯視圖，第二圖案可為圓形；三角形、長方形、或五角形的鑲嵌結構(a tessellation of triangle,rectangle,or pentagon)。根據實際需求，n側電極16的圖案可變化，因此凹槽142之第一圖案也隨著n側電極16的圖案而變化。 4A and 4B are top views of the n-side electrode 16 and the recess 142. The groove 142 shown in Fig. 4B has a first pattern having a geometry similar to that of the n-side electrode 16 shown in Fig. 4A and formed below the n-side electrode 16. Figure 4C is a top plan view of the recess 142 in another embodiment. In this embodiment, the recess 142 has a second pattern. The second pattern is a hexagonal tessellation of hexagons. Optionally, in a top view, the second pattern may be circular; a tessellation of triangle (rectangle, or pentagon). The pattern of the n-side electrode 16 may vary according to actual needs, and thus the first pattern of the recess 142 also varies with the pattern of the n-side electrode 16.
根據本發明第二實施例，第5A圖至第5G圖揭露發光裝置200之製造方法。根據第5A圖，n型半導體層153、活性層152、p型半導體層151、半導體 窗戶層14依序成長於一成長基板20上。根據第5B圖，歐姆接觸層13成長於半導體窗戶層14上。半導體窗戶層14具有一介於1μm至10μm之厚度，歐姆接觸層13具有一小於2000Å之厚度。另，半導體窗戶層14可施行一摻雜處理以形成歐姆接觸層13。根據第5C圖，實行一蝕刻步驟以移除部分歐姆接觸層13，且進一步移除部分半導體窗戶層14，藉此，形成凹槽142於半導體窗戶層14內。根據第5D圖，藉由蒸鍍或濺鍍方法，透明導電層12形成並順應(conformal)於歐姆接觸層13與半導體窗戶層14上。因此，透明導電層12與歐姆接觸層13及半導體窗戶層14互相接觸。需注意的是，當藉由旋轉塗佈法(spin coating)形成透明導電層12時，凹槽142內會填滿透明導電層12。根據第5E圖，反射層11形成於透明導電層12上。根據第5F圖，永久基板10藉由連接層18接合於反射層11上。根據第5G圖，藉由蝕刻將成長基板20與n型半導體層153分離。接著，n側電極16與p側電極17分別形成於n型半導體層153與永久基板10上。連接層18包含金屬或膠材。金屬包含金、銦、錫、及其組合。膠材包含苯環丁烯(BCB)、環氧樹脂(Epoxy)、聚二甲基矽氧烷(PDMS)、矽膠(SiOx)、氧化鋁(Al2O3)、二氧化鈦(TiO2)、氮化矽(SiNx)、及其組合。 According to a second embodiment of the present invention, FIGS. 5A to 5G illustrate a method of manufacturing the light-emitting device 200. According to FIG. 5A, the n-type semiconductor layer 153, the active layer 152, the p-type semiconductor layer 151, and the semiconductor The window layer 14 is sequentially grown on a growth substrate 20. According to FIG. 5B, the ohmic contact layer 13 is grown on the semiconductor window layer 14. The semiconductor window layer 14 has a thickness of between 1 μm and 10 μm, and the ohmic contact layer 13 has a thickness of less than 2000 Å. In addition, the semiconductor window layer 14 may be subjected to a doping treatment to form the ohmic contact layer 13. According to FIG. 5C, an etching step is performed to remove a portion of the ohmic contact layer 13, and a portion of the semiconductor window layer 14 is further removed, thereby forming the recess 142 in the semiconductor window layer 14. According to FIG. 5D, the transparent conductive layer 12 is formed and conformed to the ohmic contact layer 13 and the semiconductor window layer 14 by an evaporation or sputtering method. Therefore, the transparent conductive layer 12 and the ohmic contact layer 13 and the semiconductor window layer 14 are in contact with each other. It should be noted that when the transparent conductive layer 12 is formed by spin coating, the transparent conductive layer 12 is filled in the recess 142. According to FIG. 5E, the reflective layer 11 is formed on the transparent conductive layer 12. According to FIG. 5F, the permanent substrate 10 is bonded to the reflective layer 11 by the connection layer 18. According to the 5Gth diagram, the growth substrate 20 is separated from the n-type semiconductor layer 153 by etching. Next, the n-side electrode 16 and the p-side electrode 17 are formed on the n-type semiconductor layer 153 and the permanent substrate 10, respectively. The tie layer 18 comprises a metal or glue. The metal comprises gold, indium, tin, and combinations thereof. The rubber material includes benzocyclobutene (BCB), epoxy resin (Epoxy), polydimethyl methoxy oxane (PDMS), yttrium (SiOx), alumina (Al2O3), titanium dioxide (TiO2), tantalum nitride (SiNx). ), and combinations thereof.
實驗結果 Experimental result
實驗一experiment one
發光裝置具有一顯示於第2圖之結構。AlInP之n型半導體層153、AlGaInP之活性層152及AlInP之p型半導體層151依序地成長於GaAs之成長基板20上。GaP之半導體窗戶層14具有一10μm的厚度且成長於p型半導體層151上。碳摻雜(carbon-doping)之GaP之歐姆接觸層13係藉由有機金屬化學氣相沉積法(MOCVD)成長於半導體窗戶層14上。進行濕式蝕刻以移除部分之歐姆接 觸層13與半導體窗戶層14，藉此形成凹槽142。凹槽142之深度(H)約為2μm，且凹槽142之深度與半導體窗戶層14之厚度(T)的一深度比例約為20%。ITO之透明導電層12藉由蒸鍍方法形成於半導體窗戶層14上。反射層11為Ag/Ti/Pt/Au之多層結構且形成於透明導電層12上。矽(Si)永久基板藉由金屬接合方法接合至反射層11，之後移除GaAs之成長基板20。接著，n側電極16形成於n型半導體層153且對應於凹槽142的位置上，並具有一實質上相等於凹槽142之第一圖案之圖案(參考第4A圖)。歐姆接觸層13之表面積與半導體窗戶層14之表面積的比例約為85%，亦即，凹槽之表面積約為半導體窗戶層14之總表面積的15%。 The illuminating device has a structure shown in Fig. 2. The n-type semiconductor layer 153 of AlInP, the active layer 152 of AlGaInP, and the p-type semiconductor layer 151 of AlInP are sequentially grown on the growth substrate 20 of GaAs. The semiconductor window layer 14 of GaP has a thickness of 10 μm and is grown on the p-type semiconductor layer 151. The carbon-doping GaP ohmic contact layer 13 is grown on the semiconductor window layer 14 by metalorganic chemical vapor deposition (MOCVD). Wet etching to remove part of the ohmic junction The contact layer 13 and the semiconductor window layer 14 thereby form a recess 142. The depth (H) of the recess 142 is about 2 μm, and the depth ratio of the depth of the recess 142 to the thickness (T) of the semiconductor window layer 14 is about 20%. The transparent conductive layer 12 of ITO is formed on the semiconductor window layer 14 by an evaporation method. The reflective layer 11 is a multilayer structure of Ag/Ti/Pt/Au and is formed on the transparent conductive layer 12. The bismuth (Si) permanent substrate is bonded to the reflective layer 11 by a metal bonding method, and then the GaAs grown substrate 20 is removed. Next, the n-side electrode 16 is formed at the position of the n-type semiconductor layer 153 and corresponding to the recess 142, and has a pattern substantially equal to the first pattern of the recess 142 (refer to FIG. 4A). The ratio of the surface area of the ohmic contact layer 13 to the surface area of the semiconductor window layer 14 is about 85%, i.e., the surface area of the recess is about 15% of the total surface area of the semiconductor window layer 14.
實驗二Experiment 2
實驗二之發光裝置與實驗一之發光裝置具有相似的結構，除了凹槽更具有六角形之第二圖案，而n側電極16並未形成於第二圖案之上方(參考第4C圖)。因此，歐姆接觸層13之表面積與半導體窗戶層14之表面積的比例約為80%，亦即，凹槽之表面積約為半導體窗戶層14之總表面積的20%。 The illuminating device of Experiment 2 has a similar structure to the illuminating device of Experiment 1, except that the groove has a hexagonal second pattern, and the n-side electrode 16 is not formed above the second pattern (refer to FIG. 4C). Thus, the ratio of the surface area of the ohmic contact layer 13 to the surface area of the semiconductor window layer 14 is about 80%, i.e., the surface area of the recess is about 20% of the total surface area of the semiconductor window layer 14.
實驗三Experiment 3
實驗三之發光裝置與實驗一之發光裝置具有相似的結構，除了半導體窗戶層14之厚度為1μm。凹槽142之深度(H)約為0.8μm，且凹槽142之深度與半導體窗戶層14之厚度的一深度比例約為80%。 The illuminating device of Experiment 3 has a similar structure to the illuminating device of Experiment 1, except that the thickness of the semiconductor window layer 14 is 1 μm. The depth (H) of the recess 142 is about 0.8 μm, and the depth ratio of the depth of the recess 142 to the thickness of the semiconductor window layer 14 is about 80%.
實驗四Experiment 4
實驗四之發光裝置與實驗二之發光裝置具有相似的結構，除了半導體窗戶層14之厚度為1μm。 The illuminating device of Experiment 4 has a similar structure to the illuminating device of Experiment 2 except that the thickness of the semiconductor window layer 14 is 1 μm.
對照組一Control group one
對照組一之發光裝置與實驗一之發光裝置具有相似的結構，除了歐姆接觸層13與半導體窗戶層14並未被蝕刻。因此，並無凹槽142形成於半導體窗戶層14內。 The illuminating device of the control group has a similar structure to the illuminating device of the experiment 1, except that the ohmic contact layer 13 and the semiconductor window layer 14 are not etched. Therefore, no recess 142 is formed in the semiconductor window layer 14.
對照組二Control group two
對照組二之發光裝置與實驗三之發光裝置具有相似的結構，除了歐姆接觸層13與半導體窗戶層14並未被蝕刻。因此，並無凹槽142形成於半導體窗戶層14內。 The illuminating device of the control group 2 has a similar structure to the illuminating device of the experiment 3 except that the ohmic contact layer 13 and the semiconductor window layer 14 are not etched. Therefore, no recess 142 is formed in the semiconductor window layer 14.
表一與表二顯示實驗結果。相較於對照組一，實驗一之發光裝置的發光強度為469.18mcd，增加18%；實驗二之發光裝置的發光強度為493.68mcd，增加24%。同樣地，相較於對照組二，實驗三之發光裝置的發光強度為369.08mcd，增加12.5%；實驗四之發光裝置的發光強度為459.21mcd，增加30.4%。藉由形成凹槽142且具有傾斜之側壁表面1421，發自發光疊層15的光有效地於側壁表面1421處反射且脫離發光疊層15之一發光表面，因此發光強度增 加。此外，因凹槽更具有第二圖案，意即實驗二與實驗四的凹槽表面積大於實驗一與實驗三的凹槽表面積(約增加5%)，又每一凹槽142皆具有側壁表面1421，因此有更多的側壁表面1421以反射發自發光疊層15的光。所以，實驗二與實驗四發光裝置之發光強度相對地高。 Tables 1 and 2 show the experimental results. Compared with the control group 1, the illuminating intensity of the illuminating device of Experiment 1 was 469.18mcd, which was increased by 18%; the illuminating intensity of the illuminating device of Experiment 2 was 493.68mcd, which was increased by 24%. Similarly, compared with the control group 2, the illuminating intensity of the illuminating device of Experiment 3 was 369.08 mcd, an increase of 12.5%; the illuminating intensity of the illuminating device of Experiment 4 was 459.21 mcd, an increase of 30.4%. By forming the recess 142 and having the inclined sidewall surface 1421, the light emitted from the light emitting laminate 15 is effectively reflected at the sidewall surface 1421 and deviated from one of the light emitting surfaces of the light emitting laminate 15, thereby increasing the luminous intensity. plus. In addition, since the groove has a second pattern, that is, the groove surface area of Experiment 2 and Experiment 4 is larger than the groove surface area of Experiment 1 and Experiment 3 (about 5% increase), and each groove 142 has a sidewall surface 1421 Thus, there are more sidewall surfaces 1421 to reflect light from the light emitting stack 15. Therefore, the illuminating intensity of the experiment 2 and the experimental four illuminating device is relatively high.
本發明所列舉之各實施例僅用以說明本發明，並非用以限制本發明之範圍。任何人對本發明所作之任何顯而易知之修飾或變更皆不脫離本發明之精神與範圍。 The examples of the invention are intended to be illustrative only and not to limit the scope of the invention. Any changes or modifications of the present invention to those skilled in the art will be made without departing from the spirit and scope of the invention.
100‧‧‧發光裝置 100‧‧‧Lighting device
10‧‧‧基板 10‧‧‧Substrate
11‧‧‧反射層 11‧‧‧reflective layer
12‧‧‧透明導電層 12‧‧‧Transparent conductive layer
13‧‧‧歐姆接觸層 13‧‧‧Ohm contact layer
14‧‧‧半導體窗戶層 14‧‧‧Semiconductor window layer
141‧‧‧平坦表面 141‧‧‧flat surface
142‧‧‧凹槽 142‧‧‧ Groove
1421‧‧‧側壁表面 1421‧‧‧ sidewall surface
15‧‧‧發光疊層 15‧‧‧Lighting laminate
151‧‧‧p型半導體層 151‧‧‧p-type semiconductor layer
152‧‧‧活性層 152‧‧‧Active layer
153‧‧‧n型半導體層 153‧‧‧n type semiconductor layer
16‧‧‧n側電極 16‧‧‧n side electrode
160‧‧‧打線墊 160‧‧‧Line mat
161‧‧‧延伸部 161‧‧‧Extension
17‧‧‧p側電極 17‧‧‧p side electrode
18‧‧‧連結層 18‧‧‧Linking layer
Claims (10)
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| TWI565098B (en) * | 2015-06-10 | 2017-01-01 | 隆達電子股份有限公司 | Light emitting device |
| CN105226154B (en) * | 2015-10-27 | 2019-03-05 | 天津三安光电有限公司 | A kind of LED chip structure and manufacturing method |
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| TW200620423A (en) * | 2004-08-24 | 2006-06-16 | Toshiba Kk | Semiconductor substrate and semiconductor device manufactured by epitaxial growth on the semiconductor substrate |
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| TW200620423A (en) * | 2004-08-24 | 2006-06-16 | Toshiba Kk | Semiconductor substrate and semiconductor device manufactured by epitaxial growth on the semiconductor substrate |
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