JP5557648B2 - Light emitting diode, light emitting diode lamp, and lighting device - Google Patents

Description

  The present invention relates to a light emitting diode having an emission peak wavelength of 850 nm or more, particularly 900 nm or more, and a light emitting diode lamp and an illumination device using the light emitting diode.

Infrared light emitting diodes are widely used for infrared communication, infrared remote control devices, light sources for various sensors, night illumination, and the like.
In the vicinity of such a peak wavelength, there is known a light emitting diode in which a compound semiconductor layer including an AlGaAs active layer is grown on a GaAs substrate by a liquid phase epitaxial method (for example, Patent Documents 1 to 3), and a GaAs substrate used as a growth substrate. A so-called substrate-removed light-emitting diode in which the compound semiconductor layer is composed of only a growth layer that is transparent to the emission wavelength is the highest output infrared light-emitting diode at present (for example, Patent Document 4).
On the other hand, in the case of infrared communication used for transmission / reception between devices, for example, infrared light of 850 to 900 nm is used, and in the case of infrared remote control operation communication, for example, 880 to 880 which is a wavelength band with high sensitivity of the light receiving unit. An infrared ray of 940 nm is used. As an infrared light emitting diode that can be used for both infrared communication and infrared remote control operation communication for terminal devices such as mobile phones that have both functions of infrared communication and infrared remote control operation communication, an effective emission peak wavelength is 880 to 890 nm. One using an AlGaAs active layer containing Ge as an impurity is known (Patent Document 4).
Moreover, what uses an InGaAs active layer is known as an infrared light emitting diode which can have an emission peak wavelength of 900 nm or more (Patent Documents 5 to 7).

JP-A-6-21507 JP 2001-274454 A Japanese Patent Laid-Open No. 7-38148 JP 2006-190792 A JP 2002-26377 A JP 2002-111048 A JP 2002-344013 A

However, as far as the applicant knows, in order to improve the output of infrared light emitting diodes of 850 nm or more, particularly 900 nm or more, a functional substrate is attached (bonded) to the epitaxial wafer and the GaAs substrate used for growth is removed. There is no so-called junction type.
Further, when an AlGaAs active layer containing Ge as an effective impurity is used, it is difficult to set the emission peak wavelength to 900 nm or more (FIG. 3 of Patent Document 4).
In addition, for an infrared light emitting diode using an InGaAs active layer that can have an emission peak wavelength of 900 nm or more, development of a higher light emitting efficiency is desired from the viewpoint of further performance improvement, energy saving, and cost.

  The present invention has been made in view of the above circumstances, and an infrared light-emitting diode that emits infrared light having an emission peak wavelength of 850 nm or more, particularly 900 nm or more, with high output and high efficiency, and light emission using the same. An object of the present invention is to provide a diode lamp and a lighting device.

As a result of intensive research to solve the above problems, the present inventor has a multi-quantum well structure having a well layer made of InGaAs and a barrier layer made of AlGaInP as an active layer, and through a guide layer made of AlGaInP. The active layer is sandwiched between the quaternary mixed crystal AlGaInP and the compound semiconductor layer including the active layer, the guide layer, and the cladding layer is epitaxially grown on the growth substrate, and then the compound semiconductor layer is pasted on the transparent substrate again. An infrared light emitting diode that emits infrared light having an emission peak wavelength of 850 nm or more, particularly 900 nm or more with high output and high efficiency was completed by adopting a configuration in which the growth substrate was removed (bonded).
First, the present inventor adopts a well layer made of InGaAs so as to have an emission peak wavelength of 850 nm or more, particularly 900 nm or more, which is used for infrared communication or the like. Layered.
Further, the barrier layer sandwiching the ternary mixed crystal well layer, and the guide layer and the cladding layer sandwiching the multiple quantum well structure including the well layer and the barrier layer also have a large band gap and are transparent to the emission wavelength. Since it does not contain As, which is easy to make defects, quaternary mixed crystal AlGaInP having good crystallinity was adopted.
Furthermore, the multiple quantum well structure in which the InGaAs layer is a well layer has a strained quantum well structure having a larger lattice constant than GaAs used as a growth substrate. In such a strained quantum well structure, the influence of the composition and thickness of InGaAs on the output and monochromaticity is large, and selection of an appropriate composition, thickness, and number of pairs is important. Therefore, by adding a strain opposite to that of the InGaAs well layer to the AlGaInP barrier layer, the lattice irregularity due to the increase in the number of InGaAs pairs is alleviated throughout the quantum well structure, thereby improving the light emission output characteristics in the high current region. I found out.
Further, as described above, in the conventional infrared light emitting diode using an InGaAs-based active layer, there is no type in which the compound semiconductor layer including the active layer is attached (bonded) to the transparent substrate, and the compound semiconductor layer is grown. The GaAs substrate was used as it was. However, the GaAs substrate is highly doped to increase conductivity, and absorption of light by carriers is inevitable. Therefore, we adopted a type that can be affixed (bonded) to a transparent substrate that can avoid light absorption by the carrier and can be expected to have high output and high efficiency.
In particular, in the case of the junction type, there is an influence of stress from the functional substrate, and thus the element structure design including the optimization of the strain quantum well structure is important.
As a result of further research based on this knowledge, the present inventor has completed the present invention shown in the following configuration.

The present invention provides the following configurations.
(1) the composition formula _{(In X1 Ga 1-X1)} As (0 ≦ X1 ≦ 1) well layer and the composition formula consisting of _{(Al X2 Ga 1-X2)} Y1 In 1-Y1 P (0 ≦ X2 ≦ 1,0 An active layer having a quantum well structure in which barrier layers made of <Y1 ≦ 1) are alternately stacked, and a composition formula (Al _X3 Ga _1-X3 ) _Y2 In _1-Y2 P (0 ≦ X3 ≦) sandwiching the active layer 1 and 0 <Y2 ≦ 1), and a first cladding layer and a second guide sandwiching the active layer through the first guide and the second guide, respectively. A light emitting portion having a cladding layer; a current diffusion layer formed on the light emitting portion; and a functional substrate bonded to the current diffusion layer, wherein the first and second cladding layers have a composition formula (Al _X4 Ga _1-X4 ) _Y3 In _1-Y3 P (0 ≦ X4 ≦ 1,0 <Y 3. A light emitting diode comprising 3 ≦ 1).
(2) The light-emitting diode as described in (1) above, wherein the In composition (X1) of the well layer is 0 ≦ X1 ≦ 0.3.
(3) The light-emitting diode according to item (2), wherein the In composition (X1) of the well layer is 0.1 ≦ X1 ≦ 0.3.
(4) The compositions X2 and Y1 of the barrier layer are 0 ≦ X2 ≦ 0.2 and 0.5 <Y1 ≦ 0.7, respectively, and the compositions X3 and Y2 of the first and second guides are respectively 0.2 ≦ X3 ≦ 0.5, 0.4 <Y2 ≦ 0.6, and the compositions X4 and Y3 of the first and second cladding layers are 0.3 ≦ X4 ≦ 0.7, 0, respectively. 4 <Y3 ≦ 0.6, The light-emitting diode according to any one of the above items (1) to (3).
(5) The light-emitting diode according to any one of (1) to (4), wherein the functional substrate is transparent to an emission wavelength.
(6) The light-emitting diode according to any one of (1) to (5), wherein the functional substrate is made of GaP or SiC.
(7) The side surface of the functional substrate has a vertical surface that is substantially perpendicular to the main light extraction surface on the side close to the light emitting unit, and the main light extraction surface on the side far from the light emitting unit. The light-emitting diode according to any one of (1) to (6), wherein the light-emitting diode has an inclined surface inclined inward.
(8) The light-emitting diode according to (7), wherein the inclined surface includes a rough surface.
(9) formula _{(In X1 Ga 1-X1)} As (0 ≦ X1 ≦ 1) well layer and the composition formula consisting of _{(Al X2 Ga 1-X2)} Y1 In 1-Y1 P (0 ≦ X2 ≦ 1,0 An active layer having a quantum well structure in which barrier layers made of <Y1 ≦ 1) are alternately stacked, and a composition formula (Al _X3 Ga _1-X3 ) _Y2 In _1-Y2 P (0 ≦ X3 ≦) sandwiching the active layer 1 and 0 <Y2 ≦ 1), and a first cladding layer and a second guide sandwiching the active layer through the first guide and the second guide, respectively. A light emitting part having a cladding layer, a current diffusion layer formed on the light emitting part, a reflective layer disposed opposite to the light emitting part and having a reflectance of 90% or more with respect to the emission wavelength, A functional substrate bonded to the current spreading layer, and the first and second Rudd layer composition formula _{(Al X4 Ga 1-X4)} Y3 In 1-Y3 P (0 ≦ X4 ≦ 1,0 <Y3 ≦ 1) light emitting diode, comprising the.
Here, “bonding” further includes the case of bonding through a layer between the current diffusion layer and the functional substrate.
(10) The light-emitting diode as described in (9) above, wherein the In composition (X1) of the well layer is 0 ≦ X1 ≦ 0.3.
(11) The light-emitting diode as described in (10) above, wherein an In composition (X1) of the well layer is 0.1 ≦ X1 ≦ 0.3.
(12) The compositions X2 and Y1 of the barrier layer are 0 ≦ X2 ≦ 0.2 and 0.5 <Y1 ≦ 0.7, respectively, and the compositions X3 and Y2 of the first and second guides are respectively 0.2 ≦ X3 ≦ 0.5, 0.4 <Y2 ≦ 0.6, and the compositions X4 and Y3 of the first and second cladding layers are 0.3 ≦ X4 ≦ 0.7, 0, respectively. 4 <Y3 ≦ 0.6, The light-emitting diode according to any one of (9) to (11) above.
(13) The light-emitting diode according to any one of (9) to (12), wherein the functional substrate includes a layer made of silicon or germanium.
(14) The light-emitting diode according to any one of (9) to (12), wherein the functional substrate includes a metal substrate.
(15) The light-emitting diode according to (14), wherein the metal substrate includes a plurality of metal layers.
(16) The light-emitting diode according to any one of (1) to (15), wherein the current diffusion layer is made of GaP or GaInP.
(17) The light-emitting diode according to any one of (1) to (16), wherein a thickness of the current diffusion layer is in a range of 0.5 to 20 μm.
(18) The light-emitting diode according to any one of (1) to (17), wherein the first electrode and the second electrode are provided on the main light extraction surface side of the light-emitting diode. .
(19) The light-emitting diode according to (18), wherein the first electrode and the second electrode are ohmic electrodes.
(20) The light-emitting diode according to any one of (18) and (19) above, further comprising a third electrode on a surface opposite to the main light extraction surface side of the functional substrate. .
(21) A light-emitting diode lamp comprising the light-emitting diode according to any one of (1) to (20).
(22) A light-emitting diode lamp comprising the light-emitting diode according to (20), wherein the first electrode or the second electrode and the third electrode are connected to substantially the same potential. .
(23) Illumination equipped with a plurality of light emitting diodes according to any one of (1) to (20) and / or at least one of the light emitting diode lamps according to (21) or (22). apparatus.

  In the present invention, the term “functional substrate” means that after growing a compound semiconductor layer on a growth substrate, the growth substrate is removed and bonded to the compound semiconductor layer via a current diffusion layer to support the compound semiconductor layer. When a predetermined layer is formed on the current diffusion layer and then a predetermined substrate is bonded onto the predetermined layer, the substrate including the predetermined layer is referred to as a “functional substrate”.

According to said structure, the following effects are acquired.
Infrared light having an emission peak wavelength of 850 nm or more, particularly 900 nm or more can be emitted with high output and high efficiency.
The active layer is a well layer having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1) and a composition formula (Al _X2 Ga _1-X2 ) _Y1 In _{1 -Y1} P (0 ≦ X2 ≦ 1,0) Since it has a multi-well structure in which barrier layers made of <Y1 ≦ 1) are alternately laminated, the monochromaticity is excellent.
With the configuration in which the functional substrate is transparent with respect to the emission wavelength, high output and high efficiency can be exhibited without absorbing light emitted from the light emitting portion.
Since the barrier layer, the guide layer, and the cladding layer are composed of the composition formula (Al _X Ga _1-X ) _Y In _1-YP (0 ≦ X ≦ 1, 0 <Y ≦ 1), As is easy to produce defects. Since it has no crystallinity, it contributes to high output.
Since the barrier layer, the guide layer, and the cladding layer have a composition formula (Al _X Ga _1-X ) _Y In _1-YP (0 ≦ X ≦ 1, 0 <Y ≦ 1), the barrier layer, the guide layer, and the cladding layer Compared with an infrared light emitting diode whose layer is composed of a ternary mixed crystal, the Al concentration is low, and the moisture resistance is improved.
The active layer is a well layer having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1) and a composition formula (Al _X2 Ga _1-X2 ) _Y1 In _{1 -Y1} P (0 ≦ X2 ≦ 1,0) Since it has a laminated structure with a barrier layer made of <Y1 ≦ 1), it is suitable for mass production using the MOCVD method.

When a GaAs substrate used as a growth substrate for a compound semiconductor layer is used, a barrier layer having a composition formula (Al _X2 Ga _1-X2 ) _Y1 In _1-Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1) The composition X2 and Y1 are set to satisfy 0 ≦ X2 ≦ 0.2 and 0.5 <Y1 ≦ 0.7, respectively, thereby relaxing the strain of the well layer with respect to the GaAs substrate and suppressing the decrease in crystallinity. it can.

Since the functional substrate is made of GaP, SiC, silicon, or germanium, the thermal expansion coefficient is close to that of the light emitting portion, so that stress can be reduced. Moreover, since it is a material which does not corrode easily, moisture resistance improves.
When both the functional substrate and the current diffusion layer are made of GaP, the bonding can be facilitated and the bonding strength can be increased.

  When the current diffusion layer is made of GaInP, the crystallinity can be improved by lattice matching with the InGaAs well layer.

Emitting diode lamp of the present invention is excellent in single color property, and is provided with a high output and high efficiency even in the light emitting diode having excellent moisture resistance and is suitable for sensor applications such as the wide range of applications source.

It is a top view of the light emitting diode lamp using the light emitting diode which is one Embodiment of this invention. It is a cross-sectional schematic diagram along the A-A 'line | wire shown in FIG. 1 of the light emitting diode lamp using the light emitting diode which is one Embodiment of this invention. It is a top view of the light emitting diode which is one Embodiment of this invention. It is a cross-sectional schematic diagram along the B-B 'line | wire shown in FIG. 3 of the light emitting diode which is one Embodiment of this invention. It is a figure for demonstrating the active layer which comprises the light emitting diode which is one Embodiment of this invention. It is a graph which shows the correlation with the layer thickness of the well layer of the light emitting diode which is one Embodiment of this invention, and the light emission peak wavelength. It is a graph which shows the correspondence of In composition (X1) of the well layer of the light emitting diode which is one Embodiment of this invention, well layer thickness, and a light emission peak wavelength. It is a graph which shows the correlation with In composition (X1) of the well layer of the light emitting diode which is one Embodiment of this invention, a light emission peak wavelength, and its light emission output. It is a graph which shows the correlation with the number of pairs of the well layer of the light emitting diode which is one Embodiment of this invention, and a barrier layer, and light emission output. It is a graph which shows the correlation with In composition (Y1) of the barrier layer of the light emitting diode which is one Embodiment of this invention, and light emission output. It is a graph which shows the dependence of the number of pairs of a well layer and a barrier layer with respect to the correlation of the forward current and light emission output of the light emitting diode which is one Embodiment of this invention. It is a cross-sectional schematic diagram of the epiwafer used for the light emitting diode which is one Embodiment of this invention. It is a cross-sectional schematic diagram of the bonded wafer used for the light emitting diode which is one Embodiment of this invention. (A) It is a top view of the light emitting diode which is one Embodiment of this invention, (b) It is a cross-sectional schematic diagram along the C-C 'line | wire shown in (a). It is a cross-sectional schematic diagram of the light emitting diode which is other embodiment of this invention.

  Hereinafter, a light emitting diode according to an embodiment to which the present invention is applied and a light emitting diode lamp using the same will be described in detail with reference to the drawings. In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent.

<Light emitting diode lamp>
1 and 2 are views for explaining a light-emitting diode lamp using a light-emitting diode according to an embodiment to which the present invention is applied. FIG. 1 is a plan view, and FIG. It is sectional drawing along the A 'line.

As shown in FIGS. 1 and 2, in the light-emitting diode lamp 41 using the light-emitting diode 1 of the present embodiment, one or more light-emitting diodes 1 are mounted on the surface of a mount substrate 42.
More specifically, an n electrode terminal 43 and a p electrode terminal 44 are provided on the surface of the mount substrate 42. In addition, the n-type ohmic electrode 4 that is the first electrode of the light-emitting diode 1 and the n-electrode terminal 43 of the mount substrate 42 are connected using a gold wire 45 (wire bonding). On the other hand, the p-type ohmic electrode 5, which is the second electrode of the light emitting diode 1, and the p-electrode terminal 44 of the mount substrate 42 are connected using a gold wire 46. Further, as shown in FIG. 2, a third electrode 6 is provided on the surface of the light emitting diode 1 opposite to the surface on which the n-type and p-type ohmic electrodes 4 and 5 are provided. The light emitting diode 1 is connected to the n electrode terminal 43 by the electrode 6 and fixed to the mount substrate 42. Here, the n-type ohmic electrode 4 and the third electrode 6 are electrically connected by the n-pole electrode terminal 43 so as to be equipotential or substantially equipotential. The third electrode prevents an overcurrent from flowing in the active layer against an excessive reverse voltage, and a current flows between the third electrode and the p-type electrode, thereby preventing the active layer from being damaged. A reflection structure can be added to the third electrode and the substrate interface side to achieve high output. Further, by adding eutectic metal, solder or the like to the surface side of the third electrode, a simpler assembly technique such as eutectic die bonding can be used. The surface of the mount substrate 42 on which the light emitting diode 1 is mounted is sealed with a general sealing resin 47 such as silicon resin or epoxy resin.

<Light Emitting Diode (First Embodiment)>
3 and 4 are diagrams for explaining the light emitting diode according to the first embodiment to which the present invention is applied. FIG. 3 is a plan view, and FIG. 4 is taken along the line BB ′ shown in FIG. FIG. FIG. 5 is a cross-sectional view of a laminated structure of a well layer and a barrier layer.
The light emitting diode according to the first embodiment includes a well layer 17 having a composition formula (In _X1 Ga _{1 -X1} ) As (0 ≦ X1 ≦ 1) and a composition formula (Al _X2 Ga _{1 -X2} ) _Y1 In _{1 -Y1.} An active layer 11 having a quantum well structure in which barrier layers 18 made of P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1) are alternately stacked and a composition formula (Al _X3 Ga _1-X3 ) sandwiching the active layer 11 Via the first guide 10 and the second guide 12 made of _Y2 In _1-Y2 P (0 ≦ X3 ≦ 1, 0 <Y2 ≦ 1), and the first guide 10 and the second guide 12, respectively. A light emitting unit 7 having a first cladding layer 9 and a second cladding layer 13 sandwiching the active layer 11, a current diffusion layer 8 formed on the light emitting unit 7, and a functional substrate bonded to the current diffusion layer 8 3 and a first clad layer 9 and a second clad layer 3 is characterized by comprising the composition formula _{(Al X4 Ga 1-X4)} Y3 In 1-Y3 P (0 ≦ X4 ≦ 1,0 <Y3 ≦ 1).
The light-emitting diode 1 is schematically configured to include an n-type ohmic electrode (first electrode) 4 and a p-type ohmic electrode (second electrode) 5 provided on the main light extraction surface.
In addition, the main light extraction surface in this embodiment is a surface of the compound semiconductor layer 2 opposite to the surface to which the functional substrate 3 is attached.

As shown in FIG. 4, the compound semiconductor layer (also referred to as an epitaxial growth layer) 2 has a structure in which a pn junction type light emitting portion 7 and a current diffusion layer 8 are sequentially stacked. A known functional layer can be added to the structure of the compound semiconductor layer 2 as appropriate. For example, a contact layer for reducing the contact resistance of an ohmic electrode, a current diffusion layer for planarly diffusing the element driving current over the entire light emitting portion, and conversely, limiting a region through which the element driving current flows. Therefore, a known layer structure such as a current blocking layer or a current confinement layer can be provided.
The compound semiconductor layer 2 is preferably formed by epitaxial growth on a GaAs substrate.

  As shown in FIG. 4, the light emitting unit 7 includes at least a p-type lower cladding layer (first cladding layer) 9, a lower guide layer 10, an active layer 11, an upper guide layer 12, n on a current diffusion layer 8. A mold upper clad layer (second clad layer) 13 is sequentially laminated. That is, the light emitting unit 7 includes a lower clad layer 9 disposed to face the lower side and the upper side of the active layer 11 in order to “confine” the carrier (carrier) and light emission that cause radiative recombination in the active layer 11. A so-called double hetero (English abbreviation: DH) structure including the lower guide layer 10, the upper guide layer 12, and the upper cladding layer 13 is preferable in order to obtain high-intensity light emission.

  As shown in FIG. 5, the active layer 11 forms a quantum well structure in order to control the emission wavelength of the light emitting diode (LED). That is, the active layer 11 has a multilayer structure (laminated structure) of a well layer 17 and a barrier layer (also referred to as a barrier layer) 18 having a barrier layer (also referred to as a barrier layer) 18 at both ends.

The layer thickness of the active layer 11 is preferably in the range of 50 to 1000 nm. Further, the conductivity type of the active layer 11 is not particularly limited, and any of undoped, p-type, and n-type can be selected. In order to increase the luminous efficiency, it is desirable that the crystallinity is undoped or the carrier concentration is less than 3 × 10 ¹⁷ cm ⁻³ .

  FIG. 6 shows the correlation between the layer thickness and the emission peak wavelength with the In composition (X1) of the well layer 17 fixed at 0.1. Table 1 shows the values of the data shown in FIG. It can be seen that when the well layer is as thick as 3 nm, 5 nm, and 7 nm, the wavelength monotonously increases to 820 nm, 870 nm, and 920 nm.

  FIG. 7 shows the correlation between the emission peak wavelength of the well layer 17 and its In composition (X1) and layer thickness. FIG. 7 shows a combination of the In composition (X1) and the layer thickness of the well layer 17 in which the emission peak wavelength of the well layer 17 is a predetermined wavelength. Specifically, a combination of the In composition (X1) and the layer thickness of the well layer 17 having a configuration in which the emission peak wavelengths are 920 nm and 960 nm, respectively, is shown. FIG. 7 further shows combinations of In composition (X1) and layer thicknesses at other emission peak wavelengths of 820 nm, 870 nm, 985 nm, and 995 nm. Table 2 shows the values of the data shown in FIG.

In the case of an emission peak wavelength of 920 nm, as the In composition (X1) decreases from 0.3 to 0.05, the corresponding layer thickness monotonously increases from 3 nm to 8 nm. A combination with an emission peak wavelength of 920 nm can be easily found.
Further, when the In composition (X1) is 0.1 and the layer thickness is increased to 3 nm, 5 nm, 7 nm, and 8 nm, the emission peak wavelengths are correspondingly increased to 820 nm, 870 nm, 920 nm, and 960 nm. Further, when the In composition (X1) is 0.2, the emission peak wavelength is correspondingly increased to 920 nm and 960 nm when the layer thickness is increased to 5 nm and 6 nm, and when the In composition (X1) is 0.25, When the layer thickness is increased to 4 nm and 5 nm, the emission peak wavelengths are correspondingly increased to 920 nm and 960 nm, and when the In composition (X1) is 0.3, the layer thickness is increased to 3 nm and 5 nm. The emission peak wavelengths are as long as 920 nm and 985 nm.
Furthermore, when the In composition (X1) increases to 0.1, 0.2, 0.25, and 0.3 when the layer thickness is 5 nm, the emission peak wavelengths are increased to 870 nm, 920 nm, 960 nm, and 985 nm. When the In composition (X1) becomes 0.35, the emission peak wavelength becomes 995 nm.

In FIG. 7, it is shown that when a combination of the In composition (X1) with the emission peak wavelengths of 920 nm and 960 nm and the layer thickness is connected, it becomes a substantially straight line. Further, it is presumed that a line connecting a combination of the In composition (X1) having a predetermined emission peak wavelength in the wavelength band from 850 nm to 1000 nm and the layer thickness is also substantially linear. Further, it is assumed that the line connecting the combinations is located at the lower left as the emission peak wavelength is shorter, and located at the upper right as the longer the emission peak wavelength.
Based on the above regularity, the In composition (X1) and the layer thickness having a desired emission peak wavelength of 850 nm or more and 1000 nm or less can be easily found.

FIG. 8 shows the correlation between the In composition (X1), the emission peak wavelength, and its emission output, with the well layer 17 having a thickness of 5 nm. Table 3 shows the data values shown in FIG.
When the In composition (X1) is increased to 0.12, 0.2, 0.25, 0.3, and 0.35, the emission peak wavelengths are increased to 870 nm, 920 nm, 960 nm, 985 nm, and 995 nm. More specifically, as the In composition (X1) increases from 0.12 to 0.3, the emission peak wavelength increases from 870 nm to 985 nm almost monotonically. However, even if the In composition (X1) is increased from 0.3 to 0.35, the length increases from 985 nm to 995 nm, but the rate of change to long wavelengths is small.
The emission peak wavelength is 870 nm (X1 = 0.12), 920 nm (X1 = 0.2), and 960 nm (X1 = 0.25), and the emission output is as high as 6.5 mW, and 985 nm (X1 = 0). .3) has a practically high value of 5 mW, but was a low value of 2 mW at 995 nm (X1 = 0.35).

6 to 8, the well layer 17 preferably has a composition of (In _X1 Ga _{1 -X1} ) As (0 ≦ X1 ≦ 0.3, where X1 is a desired emission wavelength. Can be adjusted.
When the emission peak wavelength is 900 nm or more, 0.1 ≦ X1 ≦ 0.3 is preferable, and when it is less than 900 nm, 0 ≦ X1 ≦ 0.1 is preferable.

  The thickness of the well layer 17 is preferably in the range of 3 to 20 nm. More preferably, it is the range of 3-10 nm.

Barrier layer ₁₈ has a composition of _{(Al X2 Ga 1-X2)} Y1 In 1-Y1 P (0 ≦ X2 ≦ 1,0 <Y1 ≦ 1). X2 is preferably a composition having a larger band gap than the well layer 17, and more preferably in the range of 0 to 0.2. Y1 is preferably set to 0.5 to 0.7, more preferably in the range of 0.52 to 0.60, in order to relieve strain caused by lattice mismatch of the well layer 17.
The layer thickness of the barrier layer 18 is preferably equal to or thicker than the layer thickness of the well layer 17. Thereby, the luminous efficiency of the well layer 17 can be increased.

In FIG. 9, when the thickness of the well layer 17 is 5 nm, the In composition (X1) = 0.2, and the barrier layer composition X2 = 0.1 and Y1 = 0.55 (that is, (Al _{0. 1} Ga _0.9 ) _0.55 In _0.45 P), the correlation between the number of pairs of well layers and barrier layers and the light emission output. Table 4 shows the values of the data shown in FIG. This is a case where a GaAs substrate is used as the growth substrate.
In order to show the effect of the barrier layer, it is also shown a case of using the _Al 0.3 _{Ga 0.7} As barrier layer as a comparative example.
In the case of the comparative example using Al _0.3 Ga _0.7 As for the barrier layer, the emission output has a high value of 6.5 mW or more when the number of pairs is 1 to 10, but it decreases to 5 mW with 20 pairs. On the other hand, in the case of the present invention, a high value of approximately 6.5 mW or more is maintained up to 20 pairs. Thus, even if the number of pairs is increased, a high light emission output can be maintained because the strain of the well layer composed of the composition formula (In _X1 Ga _{1 -X1} ) As (0 ≦ X1 ≦ 1) with respect to the GaAs growth substrate X2 = 0.1, Y1 = 0.55 _{(i.e., (Al 0.1 Ga 0.9) 0.55} in 0.45 P) barrier layer is relaxed (i.e., the barrier layer is well layer opposite This is because the decrease in crystallinity is suppressed. The effect of strain relaxation will be further described with reference to FIG.

FIG. 10 shows that when the thickness of the well layer 17 is 5 nm, the In composition (X1) = 0.2 (emission wavelength 920 nm), and the Al composition X2 = 0.1 of the barrier layer and 5 pairs, Y1 _{(i.e., (Al 0.1 Ga 0.9) y} in 1-y P) showing the correlation between emission output and. Table 5 shows the data values shown in FIG. This is a case where a GaAs substrate is used as the growth substrate.
In order to show the effect of the barrier layer, as a comparative example, the barrier layer is the same as that of the present invention, but the well layer is a GaAs layer made of the same material as the growth substrate (that is, when the growth substrate is not distorted). Was also shown.
In the case of the present invention, the maximum light emission output is 7 mW, and Y1 of the barrier layer is about 7 mW in the range of 0.52 to 0.60. On the other hand, in the case of the comparative example using the GaAs layer as the well layer, the light emission output is 6.5 mW at the maximum, and the range showing high output is narrower than the case of the present invention.
As a result, in the present invention, since the strain in the well layer is relaxed by the reverse strain in the barrier layer to suppress the decrease in crystallinity, the composition range of the barrier layer exhibiting high light output and high output is wide. On the other hand, in the comparative example, since it is a combination of a well layer having no strain and a barrier layer having a strain, it can be understood that as a result, the crystallinity is lowered and the light emission output characteristics are lowered.

FIG. 11 shows the dependence of the number of well layer and barrier layer pairs on the correlation between the forward current and the light emission output. The data shows that the thickness of the well layer 17 is 5 nm, the In composition (X1) = 0.2, and the barrier layer composition X2 = 0.1, Y1 = 0.55 (that is, Al _0.1 Ga _{0.9 0.55} In _0.45 P), and the values of the data shown in FIG. 11 are shown in Table 6 showing the case where the number of pairs is 3 and 5 pairs.
When the forward current was up to 30 mA, the light emission output increased substantially in proportion to the increase in current in both 3 and 5 pairs. However, at 50 mA and 100 mA, the light emission output increased with increasing current while maintaining approximately proportionality with respect to 5 pairs. However, the light emission output with respect to 3 pairs was higher than that with 5 pairs at 50 mA and 100 mA, respectively. It was 2 mW and 9 mW lower.
Therefore, it was found that five pairs are more suitable than three pairs for high current / high output light emitting diodes. The larger number of pairs is suitable for large current and high output because the strain of the well layer composed of the composition formula (In _X1 Ga _{1 -X1} ) As (0 ≦ X1 ≦ 1) with respect to the growth substrate is expressed by the composition X2 = The barrier layer of 0.1, Y1 = 0.55 (that is, (Al _0.1 Ga _0.9 ) _0.55 In _0.45 P) is relaxed, and the decrease in crystallinity is suppressed. to cause.

  In the multilayer structure of the well layer 17 and the barrier layer 18, the number of pairs in which the well layers 17 and the barrier layers 18 are alternately stacked is not particularly limited. However, based on FIG. The following is preferable. That is, the active layer 11 preferably includes 1 to 20 well layers 17. Here, based on FIG. 9, a single well layer 17 is sufficient as a suitable range for the luminous efficiency of the active layer 11. However, based on FIG. 10, the luminous efficiency is improved particularly under high current conditions. It is preferable that there are a plurality of points. On the other hand, since there is a lattice irregularity between the well layer 17 and the barrier layer 18, if many pairs are formed, crystal defects are generated, so that the light emission efficiency is lowered. For this reason, it is preferable that it is 20 pairs or less, and it is more preferable that it is 10 pairs or less.

  As shown in FIG. 4, the lower guide layer 10 and the upper guide layer 12 are provided on the lower surface and the upper surface of the active layer 11, respectively. Specifically, the lower guide layer 10 is provided on the lower surface of the active layer 11, and the upper guide layer 12 is provided on the upper surface of the active layer 11.

Lower guide layer 10 and the upper guide layer ₁₂ has a composition of _{(Al X3 Ga 1-X3)} Y2 In 1-Y2 P (0 ≦ X3 ≦ 1,0 <Y2 ≦ 1). X3 is preferably a composition having the same band gap as that of the barrier layer 18 or larger than the barrier layer 18, and more preferably in the range of 0.2 to 0.5. Y2 is preferably 0.4 to 0.6.
X3 functions as a clad layer and is selected in a range that is transparent to the emission wavelength, and Y2 is selected as a range in which good crystal growth can be achieved by placing importance on lattice matching with the substrate because the clad layer is thick.

  The lower guide layer 10 and the upper guide layer 12 are provided to reduce the propagation of impurities between the lower clad layer 9 and the upper clad layer 13 and the active layer 11, respectively. That is, in the present invention, the lower clad layer 9 and the upper clad layer 13 are doped with an impurity at a high concentration, and the diffusion of the impurity into the active layer 11 causes the performance of the light emitting diode to deteriorate. In order to effectively reduce the diffusion of impurities, the thickness of the lower guide layer 10 and the upper guide layer 12 is preferably 10 nm or more, and more preferably 20 nm to 100 nm.

The conductivity type of the lower guide layer 10 and the upper guide layer 12 is not particularly limited, and any of undoped, p-type, and n-type can be selected. In order to increase the luminous efficiency, it is desirable that the crystallinity is undoped or the carrier concentration is less than 3 × 10 ¹⁷ cm ⁻³ .

  The lower cladding layer 9 and the upper cladding layer 13 are provided on the lower surface of the lower guide layer 10 and the upper surface of the upper guide layer 12, respectively, as shown in FIG.

As the material of the lower cladding layer 9 and the upper clad layer _13, a semiconductor material _{(Al X4 Ga 1-X4)} Y3 In 1-Y3 P (0 ≦ X4 ≦ 1,0 <Y3 ≦ 1), a barrier layer 15 A material having a larger band gap is preferable, and a material having a larger band gap than the lower guide layer 10 and the upper guide layer 12 is more preferable. As the material, ( _{AlX4Ga1 -X4} ) _{Y3In1 -Y3P} (0≤X4≤1, 0 <Y3≤1) has a composition in which X4 is 0.3 to 0.7. preferable. Y3 is preferably 0.4 to 0.6. X4 functions as a clad layer and is selected in a range that is transparent to the emission wavelength, and Y3 is selected as a range in which good quality crystal growth is possible from the viewpoint of lattice matching with the substrate because the clad layer is thick.

  The lower clad layer 9 and the upper clad layer 13 are configured to have different polarities. The carrier concentration and thickness of the lower clad layer 9 and the upper clad layer 13 can be in a known suitable range, and it is preferable to optimize the conditions so that the luminous efficiency of the active layer 11 is increased. Further, the warpage of the compound semiconductor layer 2 can be reduced by controlling the composition of the lower cladding layer 9 and the upper cladding layer 13.

Specifically, as the lower cladding layer 9, for example, a p-type doped with _{Mg (Al X4a Ga 1-X4a} ) Ya In 1-Ya P (0.3 ≦ X4a ≦ 0.7,0.4 ≦ Y3a It is desirable to use a semiconductor material composed of ≦ 0.6). The carrier concentration is preferably in the range of 2 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ , and the layer thickness is preferably in the range of 0.1 to 1 μm.

On the other hand, the upper clad layer 13, for example, the n-type doped with _{Si ((Al X4b Ga 1-} X4b) Yb In 1-Yb P (0.3 ≦ X4b ≦ 0.7,0.4 ≦ Y3b ≦ 0.6), the carrier concentration is preferably in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ , and the layer thickness is preferably in the range of 0.1 to 1 μm.
The polarities of the lower cladding layer 9 and the upper cladding layer 13 can be selected in consideration of the element structure of the compound semiconductor layer 2.

  Further, above the constituent layers of the light emitting unit 7, a contact layer for lowering the contact resistance of the ohmic electrode, a current diffusion layer for planarly diffusing the element driving current throughout the light emitting unit, and conversely A known layer structure such as a current blocking layer or a current confinement layer for limiting the region through which the element driving current flows can be provided.

As shown in FIG. 4, the current spreading layer 8 is provided below the light emitting unit 7. The current spreading layer 8 can be made of a material that is transparent to the emission wavelength from the light emitting unit 7 (active layer 11), such as GaP or GaInP.
In the case of applying GaP to the current diffusion layer 8, by using the functional substrate 3 as a GaP substrate, bonding can be facilitated and high bonding strength can be obtained.
In addition, when GaInP is applied to the current diffusion layer 8, the lattice constant is made the same as that of InGaAs, which is the material of the well layer 17 on which the current diffusion layer 8 is stacked, by changing the ratio of Ga and In. There is an effect that lattice matching can be achieved. Therefore, it is preferable to select the GaInP composition ratio so that the lattice constant is the same as that of InGaAs having the composition ratio selected from the desired emission peak wavelength.
The thickness of the current spreading layer 8 is preferably in the range of 0.5 to 20 μm. This is because the current diffusion is insufficient when the thickness is 0.5 μm or less, and the cost for crystal growth to the thickness increases when the thickness is 20 μm or more.

The functional substrate 3 is bonded to the surface of the compound semiconductor layer 2 opposite to the main light extraction surface. That is, the functional substrate 3 is bonded to the current diffusion layer 8 side constituting the compound semiconductor layer 2 as shown in FIG. This functional substrate 3 is made of a material that has sufficient strength to mechanically support the light emitting portion 7, has a wide band gap, and is optically transparent to the emission wavelength from the light emitting portion 7. Configure.
The functional substrate 3 is a substrate having a thermal expansion coefficient close to that of the light emitting portion and excellent in moisture resistance, and is preferably made of GaP, GaInP, SiC having good thermal conductivity, and sapphire having high mechanical strength. The functional substrate 3 preferably has a thickness of, for example, about 50 μm or more in order to support the light emitting unit 7 with sufficient mechanical strength. In order to facilitate the mechanical processing of the functional substrate 3 after bonding to the compound semiconductor layer 2, it is preferable that the thickness does not exceed about 300 μm. The functional substrate 3 is optimally composed of an n-type GaP substrate in terms of transparency, stress, and cost with a thickness of about 50 μm or more and about 300 μm or less.

  Further, as shown in FIG. 4, the side surface of the functional substrate 3 is a vertical surface 3 a that is substantially perpendicular to the main light extraction surface on the side close to the compound semiconductor layer 2, and is far from the compound semiconductor layer 2. On the side, the inclined surface 3b is inclined inward with respect to the main light extraction surface. Thereby, the light emitted from the active layer 11 to the functional substrate 3 side can be efficiently extracted to the outside. Further, part of the light emitted from the active layer 11 to the functional substrate 3 side is reflected by the vertical surface 3a and can be extracted by the inclined surface 3b. On the other hand, the light reflected by the inclined surface 3b can be extracted by the vertical surface 3a. Thus, the light extraction efficiency can be increased by the synergistic effect of the vertical surface 3a and the inclined surface 3b.

Moreover, in this embodiment, as shown in FIG. 4, it is preferable to make angle (alpha) which the inclined surface 3b and the surface parallel to a light emission surface make into the range of 55 degree | times-80 degree | times. By setting it as such a range, the light reflected by the bottom part of the functional board | substrate 3 can be efficiently taken out outside.
Moreover, it is preferable to make the width | variety (thickness direction) of the vertical surface 3a into the range of 30 micrometers-100 micrometers. By setting the width of the vertical surface 3a within the above range, the light reflected at the bottom of the functional substrate 3 can be efficiently returned to the light emitting surface at the vertical surface 3a, and further emitted from the main light extraction surface. It becomes possible. For this reason, the light emission efficiency of the light emitting diode 1 can be improved.

  The inclined surface 3b of the functional substrate 3 is preferably roughened. By roughening the inclined surface 3b, an effect of increasing the light extraction efficiency at the inclined surface 3b can be obtained. That is, by roughening the inclined surface 3b, total reflection on the inclined surface 3b can be suppressed and light extraction efficiency can be increased.

In addition, the functional substrate 3 can include a reflective layer (not shown) having a reflectance of 90% or more with respect to the emission wavelength and disposed to face the light emitting unit. With this configuration, light can be efficiently extracted from the main light extraction surface.
The reflective layer is made of, for example, silver (Ag), aluminum (Al), gold (Au), or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective layer 23 can be 90% or more.
The functional substrate 3 can use a combination of eutectic metal such as AuIn, AuGe, AuSn, and the like and bonded to an inexpensive substrate such as silicon or germanium having a thermal expansion coefficient close to that of the light emitting portion. In particular, AuIn has a low bonding temperature and a thermal expansion coefficient different from that of the light emitting part, but is an optimal combination for bonding the cheapest silicon substrate (silicon layer).
For the functional substrate 3, for example, a refractory metal such as Ti, W, Pt or a transparent conductive oxide such as ITO may be inserted so that the current diffusion layer, the reflective metal and the eutectic metal do not interdiffuse. Desirable because of its stability.

  The bonding interface between the compound semiconductor layer 2 and the functional substrate 3 may be a high resistance layer. That is, a high resistance layer (not shown) may be provided between the compound semiconductor layer 2 and the functional substrate 3. This high resistance layer exhibits a higher resistance value than that of the functional substrate 3, and when the high resistance layer is provided, the compound semiconductor layer 2 has a reverse direction from the current diffusion layer 8 side to the functional substrate 3 side. It has a function of reducing current. Moreover, although the junction structure which exhibits a withstand voltage with respect to the voltage of the reverse direction applied carelessly from the functional board | substrate 3 side is comprised, the breakdown voltage is a pn junction. It is preferable to configure so that the value is lower than the reverse voltage of the light emitting unit 7 of the mold.

  The n-type ohmic electrode (first electrode) 4 and the p-type ohmic electrode (second electrode) 5 are low-resistance ohmic contact electrodes provided on the main light extraction surface of the light-emitting diode 1. Here, the n-type ohmic electrode 4 is provided above the upper cladding layer 11, and for example, an alloy made of AuGe, Ni alloy / Au can be used. On the other hand, as shown in FIG. 4, the p-type ohmic electrode 5 can use AuBe / Au or an alloy made of AuZn / Au on the exposed surface of the current diffusion layer 8.

  Here, in the light emitting diode 1 of this embodiment, it is preferable to form the p-type ohmic electrode 5 on the current diffusion layer 8 as the second electrode. By setting it as such a structure, the effect of reducing an operating voltage is acquired. In addition, by forming the p-type ohmic electrode 5 on the current diffusion layer 8 made of p-type GaP, a good ohmic contact can be obtained, so that the operating voltage can be lowered.

  In the present embodiment, it is preferable that the polarity of the first electrode is n-type and the polarity of the second electrode is p-type. By adopting such a configuration, it is possible to achieve high brightness of the light emitting diode 1. On the other hand, if the first electrode is p-type, current diffusion is deteriorated, resulting in a decrease in luminance. On the other hand, by making the first electrode n-type, current diffusion is improved, and high luminance of the light emitting diode 1 can be achieved.

  In the light emitting diode 1 of this embodiment, as shown in FIG. 3, it is preferable to arrange so that the n-type ohmic electrode 4 and the p-type ohmic electrode 5 are diagonally positioned. The p-type ohmic electrode 5 is most preferably surrounded by the compound semiconductor layer 2. By setting it as such a structure, the effect of reducing an operating voltage is acquired. Further, by enclosing the four sides of the p-type ohmic electrode 5 with the n-type ohmic electrode 4, the current easily flows in the four directions, and as a result, the operating voltage decreases.

Moreover, in the light emitting diode 1 of this embodiment, as shown in FIG. 3, it is preferable that the n-type ohmic electrode 4 has a mesh such as a honeycomb or a lattice shape. With such a configuration, an effect of improving reliability can be obtained. Further, by using the lattice shape, a current can be uniformly injected into the active layer 11, and as a result, an effect of improving reliability can be obtained.
In the light emitting diode 1 of this embodiment, the n-type ohmic electrode 4 is preferably composed of a pad-shaped electrode (pad electrode) and a linear electrode (linear electrode) having a width of 10 μm or less. With such a configuration, high luminance can be achieved. Furthermore, by reducing the width of the linear electrode, the opening area of the light extraction surface can be increased, and high luminance can be achieved.
The third electrode is formed on the back surface of the functional substrate, and in the case of a transparent substrate, the output can be further increased by reflecting the substrate. As the reflective metal material, materials such as Au, Ag, and Al can be used.
Further, by using eutectic metal such as AuSn and solder material on the electrode surface side, it is not necessary to use a paste in the die bonding process, which is simplified. Furthermore, by connecting with metal, heat conduction is improved, and the heat dissipation characteristics of the light emitting diode are improved.

<Method for manufacturing light-emitting diode>
Next, the manufacturing method of the light emitting diode 1 of this embodiment is demonstrated. FIG. 12 is a cross-sectional view of an epi-wafer used for the light-emitting diode 1 of the present embodiment. FIG. 13 is a cross-sectional view of a bonded wafer used for the light emitting diode 1 of the present embodiment.

(Formation process of compound semiconductor layer)
First, the compound semiconductor layer 2 shown in FIG. 12 is produced. The compound semiconductor layer 2 includes a buffer layer 15 made of GaAs on an GaAs substrate 14, an etching stop layer (not shown) provided for use in selective etching, an n-type contact layer 16 doped with Si, an n-type The upper cladding layer 13, the upper guide layer 12, the active layer 11, the lower guide layer 10, the p-type lower cladding layer 9, and the current diffusion layer 8 made of Mg-doped p-type GaP are sequentially stacked.

As the GaAs substrate 14, a commercially available single crystal substrate manufactured by a known manufacturing method can be used. The surface of the GaAs substrate 14 on which the epitaxial growth is performed is desirably smooth. The surface orientation of the surface of the GaAs substrate 14 is easy to epitaxially grow, and a substrate that is turned off within ± 20 ° from the (100) plane and (100) that are mass-produced is desirable from the standpoint of quality stability. Furthermore, the range of the plane orientation of the GaAs substrate 14 is more preferably 15 ° off ± 5 ° from the (100) direction to the (0-1-1) direction.
In this specification, in the notation of Miller index, “-” means a bar attached to the index immediately after that.

The dislocation density of the GaAs substrate 14 is desirably low in order to improve the crystallinity of the compound semiconductor layer 2. Specifically, for example, 10,000 pieces cm ⁻² or less, preferably 1,000 pieces cm ⁻² or less are suitable.

The GaAs substrate 14 may be n-type or p-type. The carrier concentration of the GaAs substrate 14 can be appropriately selected from desired electrical conductivity and element structure. For example, when the GaAs substrate 14 is a silicon-doped n-type, the carrier concentration is preferably in the range of 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ . On the other hand, when the GaAs substrate 14 is a p-type doped with zinc, the carrier concentration is preferably in the range of 2 × 10 ^{18 to} 5 × 10 ¹⁹ cm ⁻³ .

  The thickness of the GaAs substrate 14 has an appropriate range depending on the size of the substrate. If the thickness of the GaAs substrate 14 is thinner than an appropriate range, the compound semiconductor layer 2 may be broken during the manufacturing process. On the other hand, when the thickness of the GaAs substrate 14 is thicker than an appropriate range, the material cost increases. For this reason, when the substrate size of the GaAs substrate 14 is large, for example, when the diameter is 75 mm, a thickness of 250 to 500 μm is desirable to prevent cracking during handling. Similarly, when the diameter is 50 mm, a thickness of 200 to 400 μm is desirable, and when the diameter is 100 mm, a thickness of 350 to 600 μm is desirable.

  Thus, by increasing the thickness of the substrate according to the substrate size of the GaAs substrate 14, it is possible to reduce the warpage of the compound semiconductor layer 2 caused by the light emitting unit 7. As a result, the temperature distribution during epitaxial growth becomes uniform, so that the in-plane wavelength distribution of the active layer 11 can be reduced. The shape of the GaAs substrate 14 is not particularly limited to a circle, and there is no problem even if it is a rectangle or the like.

  The buffer layer 15 is provided to reduce the propagation of defects between the GaAs substrate 14 and the constituent layers of the light emitting unit 7. For this reason, the buffer layer 15 is not necessarily required if the quality of the substrate and the epitaxial growth conditions are selected. The buffer layer 15 is preferably made of the same material as that of the substrate to be epitaxially grown. Therefore, in the present embodiment, it is preferable to use GaAs for the buffer layer 15 as with the GaAs substrate 14. The buffer layer 15 can also be a multilayer film made of a material different from that of the GaAs substrate 14 in order to reduce the propagation of defects. The thickness of the buffer layer 15 is preferably 0.1 μm or more, and more preferably 0.2 μm or more.

The contact layer 16 (omitted in FIG. 4) is provided to reduce the contact resistance with the electrode. The material of the contact layer 16 is preferably a material having a band gap larger than that of the active layer 11, and Al _X Ga _1-X As, (Al _X Ga _1-X ) _Y In _1-YP (0 ≦ X ≦ 1) , 0 <Y ≦ 1) can be preferably used. The lower limit value of the carrier concentration of the contact layer 16 is preferably 5 × 10 ¹⁷ cm ⁻³ or more, and more preferably 1 × 10 ¹⁸ cm ⁻³ or more in order to reduce the contact resistance with the electrode. The upper limit value of the carrier concentration is desirably 2 × 10 ¹⁹ cm ⁻³ or less at which the crystallinity is likely to decrease. The thickness of the contact layer 16 is preferably 0.5 μm or more, and optimally 1 μm or more. The upper limit value of the thickness of the contact layer 16 is not particularly limited, but is desirably 5 μm or less in order to bring the cost for epitaxial growth to an appropriate range.

  In the present embodiment, a known growth method such as a molecular beam epitaxial method (MBE) or a low pressure metal organic chemical vapor deposition method (MOCVD method) can be applied. Among these, it is most desirable to apply the MOCVD method which is excellent in mass productivity. Specifically, the GaAs substrate 14 used for the epitaxial growth of the compound semiconductor layer 2 is preferably subjected to a pretreatment such as a cleaning process or a heat treatment before the growth to remove surface contamination or a natural oxide film. Each layer constituting the compound semiconductor layer 2 can be laminated by setting a GaAs substrate 14 having a diameter of 50 to 150 mm in an MOCVD apparatus and simultaneously epitaxially growing the layer. As the MOCVD apparatus, a commercially available large-sized apparatus such as a self-revolving type or a high-speed rotating type can be applied.

When each layer of the compound semiconductor layer 2 is epitaxially grown, examples of the group III constituent material include trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) ₃ Ga), and trimethylindium ((CH ₃ ) ₃ In) can be used. Further, as a Mg doping raw material, for example, biscyclopentadienyl magnesium (bis- (C ₅ H ₅ ) ₂ Mg) or the like can be used. Further, as a Si doping material, for example, disilane (Si ₂ H ₆ ) or the like can be used.
In addition, phosphine (PH ₃ ), arsine (AsH ₃ ), or the like can be used as a raw material for the group V constituent element.
As the growth temperature of each layer, 720 to 770 ° C. can be applied when p-type GaP is used as the current diffusion layer 8, and 600 to 700 ° C. can be applied to the other layers.
When p-type GaInP is used as the current diffusion layer 8, 600 to 700 ° C. can be applied.
Furthermore, the carrier concentration, layer thickness, and temperature conditions of each layer can be selected as appropriate.

  The compound semiconductor layer 2 produced in this way has a good surface state with few crystal defects despite having the light emitting portion 7. The compound semiconductor layer 2 may be subjected to surface processing such as polishing corresponding to the element structure.

(Functional substrate bonding process)
Next, the compound semiconductor layer 2 and the functional substrate 3 are bonded.
In joining the compound semiconductor layer 2 and the functional substrate 3, first, the surface of the current diffusion layer 8 constituting the compound semiconductor layer 2 is polished and mirror-finished. Next, the functional substrate 3 to be attached to the mirror-polished surface of the current spreading layer 8 is prepared. The surface of the functional substrate 3 is polished to a mirror surface before being bonded to the current diffusion layer 8. Next, the compound semiconductor layer 2 and the functional substrate 3 are carried into a general semiconductor material pasting apparatus, and electrons are collided with both surfaces which are mirror-polished in a vacuum to make the neutral (neutral) Ar beam. Irradiate. Then, it can join at room temperature by superimposing both surfaces in the sticking apparatus which maintained the vacuum, and applying a load (refer FIG. 13). With respect to bonding, materials having the same bonding surface are more desirable from the viewpoint of stability of bonding conditions.
Bonding (pasting) is optimally performed at room temperature bonding under such a vacuum, but bonding can also be performed using a eutectic metal or an adhesive.

(First and second electrode forming steps)
Next, an n-type ohmic electrode 4 that is a first electrode and a p-type ohmic electrode 5 that is a second electrode are formed.
In forming the n-type ohmic electrode 4 and the p-type ohmic electrode 5, first, the GaAs substrate 14 and the buffer layer 15 are selectively removed from the compound semiconductor layer 2 bonded to the functional substrate 3 with an ammonia-based etchant. Next, the n-type ohmic electrode 4 is formed on the exposed surface of the contact layer 16. Specifically, for example, AuGe, Ni alloy / Pt / Au are laminated by a vacuum deposition method so as to have an arbitrary thickness, and then patterned by using a general photolithography means to form the n-type ohmic electrode 4. Form the shape.

  Next, the current diffusion layer 8 is exposed by selectively removing a predetermined range of the contact layer 16, the upper cladding layer 13, the upper guide layer 12, the active layer 11, the lower guide layer 10, and the p-type lower cladding layer 9. Then, the p-type ohmic electrode 5 is formed on the exposed surface of the current diffusion layer 8. Specifically, for example, AuBe / Au is laminated by vacuum deposition so as to have an arbitrary thickness, and then patterned using a general photolithography means to form the shape of the p-type ohmic electrode 5. . Then, the low resistance n-type ohmic electrode 4 and the p-type ohmic electrode 5 can be formed by heat-processing, for example on the conditions of 400-500 degreeC and 5 to 20 minutes, and alloying.

(Third electrode forming step)
The third electrode is formed on the back surface of the functional substrate. Depending on the structure of the element, functions such as an ohmic electrode, a Schottky electrode, a reflection function, and a eutectic die bond structure can be combined and added. In the transparent substrate, a material such as Au, Ag, or Al is formed to reflect the light. For example, a transparent film such as silicon oxide or ITO can be inserted between the substrate and the material. As a forming method, a known technique such as a sputtering method or a vapor deposition method can be used.
Further, by using eutectic metal such as AuSn, lead-free solder material, etc. on the electrode surface side, it is not necessary to use paste in the die-bonding process, thereby simplifying. As a forming method, known techniques such as sputtering, vapor deposition, plating, and printing can be used.
By connecting with metal, heat conduction is improved and heat dissipation characteristics of the light emitting diode are improved.
In the case of combining the above two functions, it is also preferable to insert a barrier metal and an oxide so that the metal does not diffuse. These can be selected optimally depending on the element structure and the substrate material.

(Functional substrate processing process)
Next, the shape of the functional substrate 3 is processed.
In processing the functional substrate 3, first, V-shaped grooving is performed on the surface on which the third electrode 6 is not formed. At this time, the inner surface of the V-shaped groove on the third electrode 6 side becomes an inclined surface 3b having an angle α formed with a surface parallel to the light emitting surface. Next, dicing is performed from the compound semiconductor layer 2 side at predetermined intervals to form chips. In addition, the vertical surface 3a of the functional substrate 3 is formed by dicing at the time of chip formation.

  The formation method of the inclined surface 3b is not particularly limited, and conventional methods such as wet etching, dry etching, scribing, and laser processing can be used in combination, but the shape controllability and productivity can be improved. Most preferably, a high dicing method is applied. By applying the dicing method, the manufacturing yield can be improved.

The method for forming the vertical surface 3a is not particularly limited, but it is preferably formed by laser processing, a scribe / break method or a dicing method.
By employing the laser processing and the scribe / break method, the manufacturing cost can be reduced. That is, since it is not necessary to provide a margin for chip separation and many light emitting diodes can be manufactured, the manufacturing cost can be reduced.
On the other hand, the dicing method is excellent in cutting stability.

  Finally, the crushed layer and dirt are removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide as necessary. In this way, the light emitting diode 1 is manufactured.

As described above, according to the light-emitting diode 1 of the present embodiment, the compound semiconductor layer including the light-emitting portion 7 having the well layer 17 having the composition formula (In _X1 Ga _{1 -X1} ) As (0 ≦ X1 ≦ 1). 2 is provided.

  Further, in the light emitting diode 1 of the present embodiment, the current diffusion layer 8 is provided on the light emitting unit 7. Since the current spreading layer 8 is transparent with respect to the emission wavelength, the light-emitting diode 1 having high output and high efficiency can be obtained without absorbing the light emitted from the light emitting unit 7. The functional substrate is stable in material and has excellent moisture resistance without worrying about corrosion.

  Therefore, according to the light emitting diode 1 of the present embodiment, it is possible to provide the light emitting diode 1 having a light emission wavelength of 850 nm or more, excellent monochromaticity, high output, high efficiency, and moisture resistance. In addition, according to the light emitting diode 1 of the present embodiment, the high output light emitting diode 1 having a light emission efficiency approximately twice as high as that of the transparent substrate type AlGaAs As light emitting diode manufactured by the conventional liquid phase epitaxial method. Can be provided. Also, high temperature and high humidity reliability was improved.

<Light Emitting Diode (Second Embodiment)>
14A and 14B are views for explaining a light emitting diode according to a second embodiment to which the present invention is applied. FIG. 14A is a plan view and FIG. 14B is a diagram. It is sectional drawing along CC 'line shown in 14 (a) (guide layers 10 and 12 are abbreviate | omitting illustration).
The light emitting diode according to the second embodiment includes a well layer 17 having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1), and a composition formula (Al _X2 Ga _1-X2 ) _Y1 In ₁₋ and _{Y1 P (0 ≦ X2 ≦ 1,0} <Y1 ≦ 1) active layer 11 of quantum well structure and barrier layer 18 are laminated alternately consisting of, sandwiching the active layer 11, the composition formula _{(Al X3 Ga 1-X3} ) The first guide layer 10 and the second guide layer 12 made of _Y2 In _1-Y2 P (0 ≦ X3 ≦ 1, 0 <Y2 ≦ 1), and the first guide layer 10 and the second guide layer 12 The light emitting part 7 having the first clad layer 9 and the second clad layer 13 sandwiching the active layer 11 therebetween, the current diffusion layer 8 formed on the light emitting part 7, and the light emitting part 7. Reflection having a reflectance of 90% or more with respect to the emission wavelength. Comprises 23, comprises a functional substrate 31 which is joined to the current diffusion layer 8, the first cladding layer 9 and the second cladding layer 13 is a composition formula _{(Al X4 Ga 1-X4)} Y3 In 1-Y3 P; 0 ≦ X4 ≦ 1, 0 <Y3 ≦ 1).

The light-emitting diode according to the second embodiment has a functional substrate 31 that has a reflectance of 90% or more with respect to the emission wavelength and includes the reflective layer 23 disposed to face the light-emitting portion 7. Light can be efficiently extracted from the extraction surface.
In the example shown in FIG. 14, the functional substrate 31 includes the second electrode 21 on the lower surface 8 b of the current diffusion layer 8, and further includes the transparent conductive film 22 and the second electrode 21 so as to cover the second electrode 21. A reflective structure in which the reflective layer 23 is laminated, and a layer (substrate) 30 made of silicon or germanium are provided.

  In the light emitting diode according to the second embodiment, the functional substrate 31 preferably includes a layer made of silicon or germanium. This is because the material is not easily corroded, so that the moisture resistance is improved.

The reflective layer 23 is made of, for example, silver (Ag), aluminum (Al), gold (Au), or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective layer 23 can be 90% or more.
In the functional substrate 31, a combination of eutectic metal such as AuIn, AuGe, AuSn and the like and bonded to an inexpensive substrate (layer) such as silicon or germanium can be used for the functional layer 31. In particular, AuIn has a low bonding temperature and a thermal expansion coefficient different from that of the light emitting portion, but is an optimal combination for bonding the cheapest silicon substrate (silicon layer).
The functional substrate 31 is further inserted with a layer made of a refractory metal such as titanium (Ti), tungsten (W), or platinum (Pt) so that the current diffusion layer, the reflective layer metal, and the eutectic metal do not interdiffuse. It is also desirable from the standpoint of quality stability to have a configured configuration.

<Light Emitting Diode (Third Embodiment)>
FIG. 15 is a diagram for explaining a light emitting diode according to a third embodiment to which the present invention is applied.
The light-emitting diode according to the third embodiment includes a well layer 17 having a composition formula (In _X1 Ga _1-X1 ) As (0 ≦ X1 ≦ 1) and a composition formula (Al _X2 Ga _1-X2 ) _Y1 In _1- and _{Y1 P (0 ≦ X2 ≦ 1,0} <Y1 ≦ 1) active layer 11 of quantum well structure and barrier layer 18 are laminated alternately consisting of, sandwiching the active layer 11, the composition formula _{(Al X3 Ga 1-X3} ) The first guide layer 10 and the second guide layer 12 made of _Y2 In _1-Y2 P (0 ≦ X3 ≦ 1, 0 <Y2 ≦ 1), and the first guide layer 10 and the second guide layer 12 The light emitting part 7 having the first clad layer 9 and the second clad layer 13 sandwiching the active layer 11 therebetween, the current diffusion layer 8 formed on the light emitting part 7, and the light emitting part 7. Reflection having a reflectance of 90% or more with respect to the emission wavelength. And a 53 and the metal substrate 50 comprises a functional substrate 51 which is joined to the current diffusion layer 8, the first cladding layer 9 and the second cladding layer 13 is a composition formula _{(Al X4 Ga 1-X4) Y3} In _1-Y3 P; 0 ≦ X4 ≦ 1, 0 <Y3 ≦ 1).

The light-emitting diode according to the third embodiment is a characteristic configuration with respect to the light-emitting diode according to the second embodiment in that the functional substrate includes a metal substrate.
The metal substrate 50 has high heat dissipation, contributes to light emission of the light emitting diode with high luminance, and can extend the life of the light emitting diode.
From the viewpoint of heat dissipation, the metal substrate 50 is particularly preferably made of a metal having a thermal conductivity of 130 W / m · K or more. Examples of metals having a thermal conductivity of 130 W / m · K or more include molybdenum (138 W / m · K), tungsten (174 W / m · K), silver (thermal conductivity = 420 W / m · K), copper ( There are thermal conductivity = 398 W / m · K), gold (thermal conductivity = 320 W / m · K), and aluminum (thermal conductivity = 236 W / m · K).

As shown in FIG. 15, the compound semiconductor layer 2 includes an active layer 11, a first clad layer (lower clad) 9 and a second clad layer sandwiching the active layer 11 via a guide layer (not shown). (Upper clad) 13, the current diffusion layer 8 below the first clad layer (lower clad) 9, and the first electrode 55 above the second clad layer (upper clad) 13 in plan view. A contact layer 56 having substantially the same size.
The functional substrate 51 includes a second electrode 57 on the lower surface 8 b of the current diffusion layer 8, and a transparent conductive film 52 and a reflective layer 53 are laminated so as to cover the second electrode 57. The joining surface 50a of the metal substrate 50 is joined to the surface 53b on the opposite side of the compound semiconductor layer 2 of the reflecting layer 53 constituting the reflecting structure.

  The reflective layer 53 is made of, for example, a metal such as copper, silver, gold, or aluminum, or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective structure can be 90% or more. By forming the reflective layer 53, the light from the active layer 11 is reflected by the reflective layer 53 in the front direction f, and the light extraction efficiency in the front direction f can be improved. Thereby, the brightness of the light emitting diode can be further increased.

The reflective layer 53 preferably has a laminated structure made of Ag, a Ni / Ti barrier layer, and an Au-based eutectic metal (connecting metal) from the transparent conductive film 52 side.
The connection metal is a metal having a low electrical resistance and melting at a low temperature. By using the connecting metal, the metal substrate can be connected without applying thermal stress to the compound semiconductor layer 2.
As the connection metal, an Au-based eutectic metal that is chemically stable and has a low melting point is used. Examples of the Au-based eutectic metal include eutectic compositions (Au-based eutectic metals) of alloys such as AuSn, AuGe, and AuSi.
Further, it is preferable to add a metal such as titanium, chromium, or tungsten to the connection metal. Thereby, metals such as titanium, chromium, and tungsten can function as a barrier metal, and impurities contained in the metal substrate can be prevented from diffusing and reacting on the reflective layer 53 side.

The transparent conductive film 52 is composed of an ITO film, an IZO film, or the like. Note that the reflective structure may be composed of only the reflective layer 53.
Further, instead of the transparent conductive film 52 or together with the transparent conductive film 52, a so-called cold mirror using a difference in refractive index of a transparent material, for example, a multilayer film of titanium oxide film, silicon oxide film, white alumina, AlN May be combined with the reflective layer 53.

The metal substrate 50 can be made of a plurality of metal layers.
As the configuration of the plurality of metal layers, it is preferable that two types of metal layers, that is, the first metal layer 50A and the second metal layer 50B are alternately stacked as in the example shown in FIG.
In particular, it is more preferable that the first metal layer 50A and the second metal layer 50B have an odd number of layers.

In this case, from the viewpoint of warping and cracking of the metal substrate, when a material having a smaller thermal expansion coefficient than the compound semiconductor layer 2 is used as the second metal layer 50B, the first metal layers 50A and 50A are more than the compound semiconductor layer 3. It is preferable to use a material made of a material having a large thermal expansion coefficient. Since the thermal expansion coefficient of the metal substrate as a whole is close to the thermal expansion coefficient of the compound semiconductor layer, it is possible to suppress warping and cracking of the metal substrate when the compound semiconductor layer and the metal substrate are joined, and the light emitting diode This is because the production yield can be improved. Similarly, when a material having a larger thermal expansion coefficient than the compound semiconductor layer 2 is used as the second metal layer 50B, the first metal layers 50A and 50A are made of a material having a smaller thermal expansion coefficient than the compound semiconductor layer 2. It is preferable to use it. Since the thermal expansion coefficient of the metal substrate as a whole is close to the thermal expansion coefficient of the compound semiconductor layer, it is possible to suppress warping and cracking of the metal substrate when joining the compound semiconductor layer and the metal substrate, and the production yield of light emitting diodes It is because it can improve.
From the above viewpoint, any of the two types of metal layers may be the first metal layer or the second metal layer.

Examples of the two metal layers include silver (thermal expansion coefficient = 18.9 ppm / K), copper (thermal expansion coefficient = 16.5 ppm / K), gold (thermal expansion coefficient = 14.2 ppm / K), and aluminum. (Thermal expansion coefficient = 23.1 ppm / K), nickel (thermal expansion coefficient = 13.4 ppm / K) and a metal layer made of any of these alloys, molybdenum (thermal expansion coefficient = 5.1 ppm / K), Combinations of tungsten (thermal expansion coefficient = 4.3 ppm / K), chromium (thermal expansion coefficient = 4.9 ppm / K), and a metal layer made of any of these alloys can be used.
A preferred example is a metal substrate composed of three layers of Cu / Mo / Cu. From the above viewpoint, the same effect can be obtained with a metal substrate composed of three layers of Mo / Cu / Mo, but the metal substrate composed of three layers of Cu / Mo / Cu is a Cu layer that has high mechanical strength and is easy to process Mo. Therefore, there is an advantage that processing such as cutting is easier than a metal substrate composed of three layers of Mo / Cu / Mo.

  The thermal expansion coefficient of the entire metal substrate is, for example, 6.1 ppm / K for a three-layer metal substrate of Cu (30 μm) / Mo (25 μm) / Cu (30 μm), and Mo (25 μm) / Cu (70 μm). In the case of a metal substrate composed of three layers of / Mo (25 μm), it is 5.7 ppm / K.

From the viewpoint of heat dissipation, the metal layer constituting the metal substrate is preferably made of a material having high thermal conductivity. This is because the heat dissipation of the metal substrate can be increased, the light emitting diode can emit light with high brightness, and the life of the light emitting diode can be extended.
For example, silver (thermal conductivity = 420 W / m · K), copper (thermal conductivity = 398 W / m · K), gold (thermal conductivity = 320 W / m · K), aluminum (thermal conductivity = 236 W / m) · K), molybdenum (thermal conductivity = 138 W / m · K), tungsten (thermal conductivity = 174 W / m · K), and alloys thereof are preferably used.

More preferably, the metal layers are made of a material having a thermal expansion coefficient substantially equal to that of the compound semiconductor layer. In particular, the material of the metal layer is preferably a material having a thermal expansion coefficient that is within ± 1.5 ppm / K of the thermal expansion coefficient of the compound semiconductor layer. As a result, it is possible to reduce stress due to heat applied to the light emitting portion when the metal substrate and the compound semiconductor layer are joined, and to suppress cracking of the metal substrate due to heat when the metal substrate is connected to the compound semiconductor layer. The manufacturing yield of the light emitting diode can be improved.
The thermal conductivity of the entire metal substrate is, for example, 250 W / m · K for a three-layer metal substrate of Cu (30 μm) / Mo (25 μm) / Cu (30 μm), and Mo (25 μm) / Cu (70 μm) / In the case of a metal substrate composed of three layers of Mo (25 μm), it is 220 W / m · K.

  Hereinafter, the effect of the present invention will be specifically described with reference to examples. The present invention is not limited to these examples.

  In this example, an example in which a light-emitting diode according to the present invention is manufactured will be specifically described. The light-emitting diode manufactured in this example is an infrared light-emitting diode having an active layer having a quantum well structure of a well layer made of InGaAs and a barrier layer made of AlGaInP. In this example, a compound semiconductor layer grown on a GaAs substrate and a functional substrate were combined to produce a light emitting diode. Then, a light-emitting diode lamp having a light-emitting diode chip mounted on a substrate was prepared for characteristic evaluation.

Example 1
Example 1 is an example of the embodiment shown in FIG.
In the light emitting diode of Example 1, first, an epitaxial wafer was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of an n-type GaAs single crystal doped with Si. In the GaAs substrate, a plane inclined by 15 ° in the (0-1-1) direction from the (100) plane was used as a growth plane, and the carrier concentration was set to 2 × 10 ¹⁸ cm ⁻³ . As the compound semiconductor layer, an n-type buffer layer made of GaAs doped with Si, an n-type contact layer made of Si-doped (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P, Si N-type upper clad layer made of (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P, doped with (Al _0.3 Ga _0.7 ) _0.5 In _0.5 P Upper guide layer, well layer / barrier layer composed of three pairs of In _0.2 Ga _0.8 As / (Al _0.1 Ga _0.9 ) _0.5 In _0.5 P, (Al _0.3 Ga _{0 .7) 0.5} in _0.5 lower guide layer made of P, doped with Mg _{(Al 0.7} Ga _0.3) p-type lower cladding layer composed of _{0.5 in} 0.5 P, (Al _0.5 Ga _0.5) an intermediate layer of a thin film made of _0.5 in _0.5 P, M Using current diffusion layer made of doped p-type GaP.

In this example, a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 76 mm and a thickness of 350 μm by using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer. When growing an epitaxial growth layer, trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) ₃ Ga) and trimethylindium ((CH ₃ ) ₃ In) are used as the raw material for the group III constituent element did. Further, biscyclopentadienyl magnesium (bis- (C ₅ H ₅ ) ₂ Mg) was used as a Mg doping material. Further, disilane (Si ₂ H ₆ ) was used as a Si doping material. Further, phosphine (PH ₃ ) and arsine (AsH ₃ ) were used as raw materials for the group V constituent elements. As the growth temperature of each layer, the current diffusion layer made of p-type GaP was grown at 750 ° C. The other layers were grown at 700 ° C.

The buffer layer made of GaAs has a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 0.5 μm. The contact layer had a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ and a layer thickness of 4 μm. The upper cladding layer had a carrier concentration of about 1 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 0.5 μm. The upper guide layer was undoped and had a thickness of about 50 nm. The well layer is undoped In _0.2 Ga _0.8 As having a thickness of about 5 nm, and the barrier layer is undoped and has a thickness of about 10 nm (Al _0.1 Ga _0.9 ) _0.5 In _{0. 5} P. Three pairs of well layers and barrier layers were alternately laminated. The lower guide layer was undoped and had a thickness of about 50 nm. The lower cladding layer had a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a layer thickness of about 0.5 μm. The intermediate layer had a carrier concentration of about 8 × 10 ¹⁷ cm ⁻³ and a layer thickness of about 50 nm. The current diffusion layer made of GaP has a carrier concentration of about 3 × 10 ¹⁸ cm ⁻³ and a layer thickness of about 10 μm.

Next, the current diffusion layer was polished to a region extending from the surface to a depth of about 1 μm and mirror-finished. By this mirror finishing, the surface roughness (rms) of the current diffusion layer was set to 0.18 nm.
On the other hand, a functional substrate made of n-type GaP to be attached to the mirror-polished surface of the current diffusion layer was prepared. A single crystal having a plane orientation of (111) was used for the functional substrate for pasting, to which Si was added so that the carrier concentration was about 2 × 10 ¹⁷ cm ⁻³ . The functional substrate had a diameter of 76 mm and a thickness of 250 μm. The surface of this functional substrate was polished to a mirror surface before being bonded to the current spreading layer, and the surface roughness (rms) was finished to 0.12 nm.

Next, the functional substrate and the epitaxial wafer were carried into a general semiconductor material pasting apparatus, and the inside of the apparatus was evacuated to 3 × 10 ⁻⁵ Pa.

Next, the surface of both the functional substrate and the current spreading layer was irradiated with an Ar beam neutralized by colliding electrons for 3 minutes. Thereafter, the surfaces of the functional substrate and the current diffusion layer were superposed in a sticking apparatus maintained in vacuum, a load was applied so that the pressure on each surface was 50 g / cm ^2, and both were bonded at room temperature. In this way, a bonded wafer was formed.

  Next, the GaAs substrate and the GaAs buffer layer were selectively removed from the bonded wafer with an ammonia-based etchant. Next, a first electrode was formed on the surface of the contact layer by vacuum deposition so that the thickness of AuGe and Ni alloy was 0.5 μm, Pt was 0.2 μm, and Au was 1 μm. Then, patterning was performed using a general photolithography means, and an n-type ohmic electrode was formed as the first electrode. Next, the surface of the light extraction surface, which is the surface from which the GaAs substrate was removed, was roughened.

  Next, the epi layer in the region where the p-type ohmic electrode was formed as the second electrode was selectively removed to expose the current diffusion layer. A p-type ohmic electrode was formed on the exposed surface of the current diffusion layer by vacuum deposition so that AuBe was 0.2 μm and Au was 1 μm. Thereafter, heat treatment was performed at 450 ° C. for 10 minutes to form an alloy, and low resistance p-type and n-type ohmic electrodes were formed. Furthermore, Au was formed in a thickness of 0.2 μm on the back surface of the functional substrate, and a pattern was formed in a 220 μm square.

  Next, using a dicing saw, the region where the third electrode is not formed from the back surface of the functional substrate is set so that the angle α of the inclined surface becomes 70 ° and the thickness of the vertical surface becomes 80 μm. A letter-shaped grooving was performed. Next, a dicing saw was used to cut from the compound semiconductor layer side at 350 μm intervals to form chips. The crushing layer and dirt by dicing were removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to produce a light emitting diode of Example 1.

  100 light emitting diode lamps each having the light emitting diode chip of Example 1 manufactured as described above mounted on a mount substrate were assembled. In this light-emitting diode lamp, the mount is supported (mounted) by a die bonder, the n-type ohmic electrode of the light-emitting diode and the n-electrode terminal provided on the surface of the mount substrate are wire-bonded with a gold wire, and the p-type ohmic electrode and the p-type electrode are connected. The electrode terminal was wire bonded with a gold wire and then sealed with a general epoxy resin.

Table 7 shows the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp).
As shown in Table 7, when current was passed between the n-type and p-type ohmic electrodes, infrared light having a peak wavelength of 920 nm was emitted. The forward voltage (Vf) when a current of 20 milliamperes (mA) flows in the forward direction is the low resistance at each junction interface between the current diffusion layer constituting the compound semiconductor layer and the functional substrate and each ohmic resistance. Reflecting the good ohmic characteristics of the electrode, it was about 1.22 volts. When the forward current was 20 mA, the light emission output was 7 mW. Furthermore, in a high temperature and high humidity environment with a temperature of 60 ° C. and a humidity of 90%, an energization test (20 mA energization) was conducted for 1000 hours, and the light emission output remained. Table 7 shows the result of measuring the rate.
The 100 lamps were subjected to a high-temperature and high-humidity energization test at 60 ° C., 90 RH%, 20 mA. The average output remaining rate after 1000 hours was 100%.

(Example 2)
Example 2 is an example of the second embodiment shown in FIGS. 14 (a) and 14 (b).
The light emitting diode of Example 2 is a case where a reflective layer and a functional substrate are combined. Other light emitting portions are formed in the same manner as in the first embodiment. The lower guide layer 10 and the upper guide layer 12 are not shown.

On the surface of the current spreading layer 8, eight electrodes (second electrodes) 21 made of 20 μmφ dots of AuBe / Au alloy with a thickness of 0.2 μm are arranged at equal intervals so as to be 50 μm from the end of the light extraction surface. Arranged.
Next, an ITO film 22 which is a transparent conductive film was formed by a sputtering method with a thickness of 0.4 μm. Further, a layer 23 made of silver alloy / Ti / Au was formed to a thickness of 0.2 μm / 0.1 μm / 1 μm to form a reflecting surface 23.

On the other hand, a layer 32 made of Ti / Au / In was formed on the surface of a silicon substrate (functional substrate) 31 with a thickness of 0.1 μm / 0.5 μm / 0.3 μm. A layer 33 made of Ti / Au was formed on the back surface of the silicon substrate 31 with a thickness of 0.1 μm / 0.5 μm. The Au on the light emitting diode wafer side and the In surface on the silicon substrate side were superposed and heated at 320 ° C. and pressurized at 500 g / cm ² to bond the functional substrate to the light emitting diode wafer.

  The GaAs substrate is removed, an AuGe / Au ohmic electrode (first electrode) 25 having a diameter of 100 μm and a thickness of 3 μm is formed on the surface of the contact layer 16, and heat-treated at 420 ° C. for 5 minutes, p, n The ohmic electrode was alloyed.

Next, the surface of the contact layer 16 was roughened.
The semiconductor layer, the reflective layer, and the eutectic metal that were to be cut to be separated into chips were removed, and Ti / AuSn / Au was formed to 0.3 μm / 1 μm / 0.1 μm on the back electrode of the silicon substrate. Dicing saw cut into squares at a pitch of 350 μm.

Table 7 shows the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp).
As shown in Table 7, when current was passed between the upper and lower electrodes, infrared light having a peak wavelength of 920 nm was emitted. The forward voltage (Vf) when a current of 20 milliamperes (mA) flows in the forward direction is the low resistance at each junction interface between the current diffusion layer constituting the compound semiconductor layer and the functional substrate and each ohmic resistance. Reflecting the good ohmic characteristics of the electrode, it was about 1.20 volts (V). The light emission output when the forward current was 20 mA was about 6 mW. Furthermore, Table 7 shows the results of conducting an energization test (20 mA energization) for 1000 hours in a high-temperature and high-humidity environment at a temperature of 60 ° C. and a humidity of 90%, and measuring the residual ratio of light emission output.
Similarly to Example 1, 100 lamps were subjected to a high-temperature and high-humidity energization test at 60 ° C., 90 RH%, 20 mA. The average output remaining rate after 1000 hours was 99%.

(Example 3)
The light-emitting diode of Example 3 is an example of the third embodiment, and has a configuration in which a functional substrate including a reflective layer and a metal substrate is bonded to a current diffusion layer. With reference to FIG. 15, the light-emitting diode of Example 3 will be described.

  First, a metal substrate was produced. Two substantially flat Cu plates with a thickness of 10 μm and one substantially flat Mo plate with a thickness of 75 μm are prepared, and the Mo plates are inserted between the two Cu plates and stacked. And the said board | substrate was arrange | positioned to the pressurization apparatus and the load was applied in the direction which pinches | interposes them with respect to these metal plates under high temperature. Thus, a metal substrate composed of three layers of Cu (10 μm) / Mo (75 μm) / Cu (10 μm) was produced.

The compound semiconductor layer is formed of Si-doped (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P between the buffer layer and the contact layer, and an etching stop layer having a layer thickness of 0.5 μm. It formed on the same conditions as Example 1 except the point formed.
On the surface 8b of the current spreading layer 8, Au having a thickness of 0.2 μm is laminated on AuBe having a thickness of 0.4 μm, and when viewed in plan, it has a circular shape of 20 μmφ, with an interval of 60 μm. A second electrode 57 was formed.
Next, an ITO film 52, which is a transparent conductive film, was formed by sputtering to a thickness of 0.8 μm so as to cover the second electrode 57.
Next, a film made of a silver (Ag) alloy is formed to 0.7 μm on the ITO film 52 by vapor deposition, and then a film made of nickel (Ni) / titanium (Ti) is made to 0.5 μm, gold A film made of (Au) was formed to a thickness of 1 μm to form a reflective film 53.
Next, the structure in which the ITO film 52 and the reflective film 53 are formed on the current diffusion layer 8 of the compound semiconductor layer and the metal substrate are arranged so as to face each other and are carried into a decompression apparatus, and are brought to 400 ° C. In the state heated by, they were joined with a load of 500 kg to form a joined structure.
Next, the GaAs substrate, which is a growth substrate for the compound semiconductor layer, and the buffer layer were selectively removed from the bonded structure with an ammonia-based etchant, and the etching stop layer was selectively removed with a hydrochloric acid-based etchant.
Next, using a vacuum deposition method, AuGe is deposited on the contact layer to a thickness of 0.15 μm, Ni is deposited to a thickness of 0.05 μm, and Au is further deposited to a thickness of 1 μm. A first electrode conductive film was formed by film formation. Next, by using photolithography, the electrode conductive film was patterned into a circular shape in plan view, and a first electrode 55 having a diameter of 100 μm and a thickness of 3 μm was produced.
Next, using the first electrode as a mask, the contact layer 56 was formed by etching away the portion of the contact layer except under the first electrode with an ammonia-based etchant.
The compound semiconductor layer, the reflective layer, and the eutectic metal to be cut to be separated into chips were removed, and the metal substrate was cut into squares at a pitch of 350 μm by laser dicing.

Table 7 shows the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp).
As shown in Table 7, when a current was passed between the n-type and p-type ohmic electrodes, red light having a peak wavelength of 920 nm was emitted. The forward voltage (V _F ) when a current of 20 milliamperes (mA) is passed in the forward direction is low in resistance at the junction interface between the current diffusion layer constituting the compound semiconductor layer and the functional substrate. Reflecting the good ohmic characteristics of the ohmic electrode, it was 1.2 volts. The light emission output when the forward current was 20 mA was 5.9 mW.
Twenty lamps were subjected to a high-temperature and high-humidity energization test at 60 ° C., 90 RH%, 20 mA. The average output remaining rate after 1000 hours was 100%.

(Example 4)
The light-emitting diode of Example 4 is an example of the first embodiment, and is manufactured under the same conditions as in Example 1 except that the In composition X1 of the well layer is set to 0.12 so that the emission peak wavelength is 870 nm. did.
The results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 870 nm is emitted, and the light emission output (P ₀ ) and the forward voltage (V _F ). The average output residual ratios were 6.8 mW, 1.31 V, and 100%, respectively.

(Example 5)
The light-emitting diode of Example 5 is an example of the second embodiment, and is manufactured under the same conditions as Example 2 except that the In composition X1 of the well layer is set to 0.12 so that the emission peak wavelength is 870 nm. did.
The results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 870 nm is emitted, and the light emission output (P ₀ ) and the forward voltage (V _F ). The average output residual ratio was 6.1 mW, 1.3 V, and 100%, respectively.

(Example 6)
The light-emitting diode of Example 6 is an example of the first embodiment, and is manufactured under the same conditions as Example 1 except that the In composition X1 of the well layer is set to 0.25 so that the emission peak wavelength is 960 nm. did.
The results of evaluating the characteristics of this light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 960 nm is emitted, and the light emission output (P ₀ ) and forward voltage (V _F ). The average output residual ratio was 6.5 mW, 1.2 V, and 99%, respectively.

(Example 7)
The light emitting diode of Example 7 is an example of the second embodiment, and is manufactured under the same conditions as Example 2 except that the In composition X1 of the well layer is set to 0.25 in order to set the emission peak wavelength to 960 nm. did.
The results of evaluating the characteristics of this light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 960 nm is emitted, and the light emission output (P ₀ ) and forward voltage (V _F ). The average output residual ratio was 5.3 mW, 1.2 V, and 99%, respectively.

(Example 8)
The light-emitting diode of Example 8 is an example of the first embodiment, and is manufactured under the same conditions as in Example 1 except that the In composition X1 of the well layer is set to 0.3 so that the emission peak wavelength is 985 nm. did.
The results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 985 nm is emitted, and the light emission output (P ₀ ) and forward voltage (V _F ). The average output residual ratio was 5.0 mW, 1.2 V, and 99%, respectively.

Example 9
The light-emitting diode of Example 9 is an example of the second embodiment, and is manufactured under the same conditions as Example 2 except that the In composition X1 of the well layer is set to 0.3 so that the emission peak wavelength is 985 nm. did.
The results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 985 nm is emitted, and the light emission output (P ₀ ) and forward voltage (V _F ). The average output residual ratio was 3.8 mW, 1.2 V, and 99%, respectively.

(Example 10)
The light-emitting diode of Example 10 is an example of the first embodiment, and the barrier layer is undoped and has a thickness of about 10 nm of (Al _0.1 Ga _0.9 ) _0.55 In _0.45 P. Moreover, it was produced under the same conditions as in Example 1 except that five pairs of well layers and barrier layers were alternately laminated.
The results of evaluating the characteristics of this light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 920 nm is emitted, and the light emission output (P ₀ ) and forward voltage (V _F ). The average output residual ratio was 7.0 mW, 1.24 V, and 99%, respectively.

(Comparative Example 1)
The light emitting diode of Comparative Example 1 was formed by a liquid phase epitaxial method which is a conventional technique. This is a light emitting diode having a double heterostructure light emitting portion having a light emitting layer of Al _0.01 Ga _0.99 As on a GaAs substrate.

Specifically, the light-emitting diode of Comparative Example 1 was prepared by forming an n-type (100) GaAs single crystal substrate with an n-type upper cladding layer having an interface composition of Al _0.2 Ga _0.8 As of 50 μm. 20 μm of Si-doped light-emitting layer made of Al _0.03 Ga _0.97 As, 20 μm of p-type lower cladding layer made of Al _0.1 Ga _0.9 As, transparent to the emission wavelength _{. A} p-type thick film layer made of ₂₅ Ga _0.75 As was prepared by a liquid phase epitaxial method so as to be 60 μm. After this epitaxial growth, the GaAs substrate was removed. Next, an n-type ohmic electrode having a diameter of 100 μm was formed on the surface of the n-type AlGaAs upper cladding layer. Next, p-type ohmic electrodes having a diameter of 20 μm were formed on the back surface of the p-type AlGaAs thick film layer at intervals of 80 μm and heat-treated at 420 ° C. for 5 minutes to alloy the p and n ohmic electrodes. Next, after cutting with a dicing saw at an interval of 350 μm, the crushed layer was removed by etching, and the surface was roughened for high output to produce a light emitting diode chip of Comparative Example 1.

Table 7 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 1 was mounted.
As shown in Table 7, when current was passed between the n-type and p-type ohmic electrodes, infrared light having a peak wavelength of 920 nm was emitted. The forward voltage (V _F ) when a current of 20 mA (mA) was passed in the forward direction was about 1.2 volts (V). The light emission output when the forward current was 20 mA was 2 mW. Moreover, the output of any sample of Comparative Example 1 was lower than that of the example of the present invention. Further, Table 1 shows the results of conducting a current test (20 mA power supply) for 500 hours in a high temperature and high humidity environment at a temperature of 60 ° C. and a humidity of 90%, and measuring the residual rate of light emission output. The cause of the decrease in output is thought to be that light absorption increased due to corrosion of the AlGaAs surface.
Further, as in the example, 100 lamps were subjected to a high-temperature and high-humidity energization test at 60 ° C., 90 RH%, 20 mA. The average of the remaining power after 500 hours was 14% lower than that at the start of the experiment, and was significantly lower than that of the example in which the decrease was only within 1%.

  The light-emitting diode of the present invention can be used as a light-emitting diode product that emits infrared light having an emission peak wavelength of 850 nm or more, particularly 900 nm or more with high output and high efficiency.

DESCRIPTION OF SYMBOLS 1 ... Light emitting diode 2 ... Compound semiconductor layer 3 ... Functional board | substrate 3a ... Vertical surface 3b ... Inclined surface 4 ... N-type ohmic electrode (1st electrode)
5 ... p-type ohmic electrode (second electrode)
6 ... 3rd electrode 7 ... Light emission part 8 ... Current diffusion layer 9 ... Lower clad layer (1st clad layer)
10 ... Lower guide layer
DESCRIPTION OF SYMBOLS 11 ... Active layer 12 ... Upper guide layer 13 ... Upper clad layer (2nd clad layer)
14 ... GaAs substrate 15 ... Buffer layer 16 ... Contact layer
17 ... Well layer 18 ... Barrier layer 20 ... Light emitting diode 21 ... Electrode 22 ... Transparent conductive film 23 ... Reflecting surface 25 ... Bonding electrode 30 ... Silicon substrate 31・ ・ Functional substrate α ・ ・ ・ An angle between the inclined surface and a plane parallel to the light emitting surface 50 .Metal substrate 51... Functional substrate 52 ..Transparent conductive film 53. .... First electrode 56 ... Contact layer 57 ... Second electrode

Claims (17)

Grown on GaAs substrate used as a growth substrate, the composition formula _{(In X1 Ga 1-X1)} As (0.1 ≦ X1 ≦ 0.3) consisting of a well layer and the composition formula _{(Al X2 Ga 1-X2} ) An active layer having a quantum well structure in which barrier layers made of _Y1 In _1-Y1 P (0 ≦ X2 ≦ 0.2 , 0.5 <Y1 ≦ 0.7 ) are alternately stacked, and the active layer interposed therebetween. A first guide and a second guide having a composition formula (Al _X3 Ga _1-X3 ) _Y2 In _1-Y2 P ( 0.2 ≦ X3 ≦ 0.5 , 0.4 <Y2 ≦ 0.6 ); A light emitting unit having a first clad layer and a second clad layer sandwiching the active layer via each of the first guide and the second guide;
A current spreading layer formed on the light emitting part;
A functional substrate bonded to the current spreading layer,
Said first and second cladding layer composition formula _{(Al X4 Ga 1-X4)} Y3 In 1-Y3 P (0.3 ≦ X4 ≦ 0.7, 0.4 <Y3 ≦ 0.6) consists,
After the growth of each layer, the GaAs substrate is removed,
A light emitting diode having an emission wavelength of 900 nm or more and 985 nm or less. The light emitting diode according to claim 1, wherein the functional substrate is transparent with respect to an emission wavelength. The functional substrate is a light emitting diode according to claim 1 or 2, characterized in that it consists of GaP or SiC. The side surface of the functional substrate has a vertical surface that is perpendicular to the main light extraction surface on the side close to the light emitting unit, and is inward of the main light extraction surface on the side far from the light emitting unit. the light-emitting diode according to any one of claims 1 to 3, characterized in that it has an inclined sloping surface. The light emitting diode according to claim 4 , wherein the inclined surface includes a rough surface. Grown on GaAs substrate used as a growth substrate, the composition formula _{(In X1 Ga 1-X1)} As (0.1 ≦ X1 ≦ 0.3) consisting of a well layer and the composition formula _{(Al X2 Ga 1-X2} ) An active layer having a quantum well structure in which barrier layers made of _Y1 In _1-Y1 P (0 ≦ X2 ≦ 0.2 , 0.5 <Y1 ≦ 0.7 ) are alternately stacked, and the active layer interposed therebetween. A first guide and a second guide having a composition formula (Al _X3 Ga _1-X3 ) _Y2 In _1-Y2 P ( 0.2 ≦ X3 ≦ 0.5 , 0.4 <Y2 ≦ 0.6 ); A light emitting unit having a first clad layer and a second clad layer sandwiching the active layer via each of the first guide and the second guide;
A current spreading layer formed on the light emitting part;
A functional substrate disposed opposite to the light emitting portion and including a reflective layer having a reflectance of 90% or more with respect to an emission wavelength, and a functional substrate bonded to the current diffusion layer,
Said first and second cladding layer composition formula _{(Al X4 Ga 1-X4)} Y3 In 1-Y3 P (0.3 ≦ X4 ≦ 0.7, 0.4 <Y3 ≦ 0.6) consists,
After the growth of each layer, the GaAs substrate is removed,
A light emitting diode having an emission wavelength of 900 nm or more and 985 nm or less. The light emitting diode according to claim 6 , wherein the functional substrate includes a layer made of silicon or germanium. The light emitting diode according to claim 6 , wherein the functional substrate includes a metal substrate. 9. The light emitting diode according to claim 8 , wherein the metal substrate comprises a plurality of metal layers. The current spreading layer is a light emitting diode according to any one of claims 1 to 9, characterized in that it consists of GaP or GaInP. Light-emitting diode according to any one of claims 1 to 10, wherein the thickness of the current diffusion layer is in the range of 0.5 to 20 [mu] m. The first electrode and the light emitting diode according to any one of claims 1 to 11 and the second electrode, characterized in that provided in the main light extracting surface of the light emitting diode. The light emitting diode according to claim 12 , wherein the first electrode and the second electrode are ohmic electrodes. Wherein the functional substrate, wherein the surface opposite to the main light extracting surface, the light emitting diode according to any one of claims 12 or 13, further comprising a third electrode. LED lamp, characterized in that it comprises a light emitting diode according to any one of claims 1 to 14. A light-emitting diode lamp comprising the light-emitting diode according to claim 14 , wherein the first electrode or the second electrode and the third electrode are connected to the same potential. The illuminating device which mounts the light emitting diode as described in any one of Claims 1 thru | or 14 , and / or the light emitting diode lamp as described in at least any one of Claim 15 or 16 .

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