WO2011090016A1 - Light-emitting diode, light-emitting diode lamp and lighting device - Google Patents

Light-emitting diode, light-emitting diode lamp and lighting device Download PDF

Info

Publication number
WO2011090016A1
WO2011090016A1 PCT/JP2011/050719 JP2011050719W WO2011090016A1 WO 2011090016 A1 WO2011090016 A1 WO 2011090016A1 JP 2011050719 W JP2011050719 W JP 2011050719W WO 2011090016 A1 WO2011090016 A1 WO 2011090016A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
emitting diode
light emitting
light
diode according
Prior art date
Application number
PCT/JP2011/050719
Other languages
French (fr)
Japanese (ja)
Inventor
範行 粟飯原
則善 瀬尾
典孝 村木
Original Assignee
昭和電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昭和電工株式会社 filed Critical 昭和電工株式会社
Priority to CN201180007108.8A priority Critical patent/CN102725871B/en
Publication of WO2011090016A1 publication Critical patent/WO2011090016A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Definitions

  • the present invention relates to a light emitting diode having an emission peak wavelength of 850 nm or more, particularly 900 nm or more, and a light emitting diode lamp and an illumination device using the light emitting diode.
  • Infrared light emitting diodes are widely used for infrared communication, infrared remote control devices, light sources for various sensors, night illumination, and the like.
  • a light emitting diode in which a compound semiconductor layer including an AlGaAs active layer is grown on a GaAs substrate by liquid phase epitaxy (for example, Patent Documents 1 to 3), and a GaAs substrate used as a growth substrate.
  • Patent Documents 1 to 3 liquid phase epitaxy
  • infrared communication used for transmission / reception between devices
  • infrared light for example, infrared light of 850 to 900 nm
  • infrared remote control operation communication the wavelength band in which the sensitivity of the light receiving unit is high, for example, 880 to 900 nm.
  • An infrared ray of 940 nm is used.
  • an infrared light emitting diode that can be used for both infrared communication and infrared remote control operation communication for mobile phones and other terminal devices that have both infrared communication and infrared remote control operation communication, it has an effective peak emission wavelength of 880 to 890 nm.
  • Patent Document 4 One using an AlGaAs active layer containing Ge as an impurity is known (Patent Document 4).
  • Patent Documents 5 to 7 one using an InGaAs active layer is known (Patent Documents 5 to 7).
  • JP-A-6-21507 JP 2001-274454 A Japanese Unexamined Patent Publication No. 7-38148 JP 2006-190792 A JP 2002-26377 A JP 2002-111048 A JP 2002-344013 A
  • the present invention has been made in view of the above circumstances, and an infrared light-emitting diode that emits infrared light having an emission peak wavelength of 850 nm or more, particularly 900 nm or more with high output and high efficiency, and light emission using the same.
  • An object of the present invention is to provide a diode lamp and a lighting device.
  • the present inventor has a multi-quantum well structure having a well layer made of InGaAs and a barrier layer made of AlGaInP as an active layer, and through a guide layer made of AlGaInP.
  • the active layer is sandwiched between the quaternary mixed crystal AlGaInP and the compound semiconductor layer including the active layer, the guide layer, and the cladding layer is epitaxially grown on the growth substrate, and then the compound semiconductor layer is pasted on the transparent substrate again.
  • An infrared light emitting diode that emits infrared light having an emission peak wavelength of 850 nm or more, particularly 900 nm or more with high output and high efficiency was completed by adopting a configuration in which the growth substrate was removed (bonded).
  • the present inventor adopts a well layer made of InGaAs so as to have an emission peak wavelength of 850 nm or more, particularly 900 nm or more, which is used for infrared communication or the like. Layered.
  • the barrier layer sandwiching the ternary mixed crystal well layer, and the guide layer and the cladding layer sandwiching the multiple quantum well structure including the well layer and the barrier layer also have a large band gap and are transparent to the emission wavelength.
  • the multiple quantum well structure in which the InGaAs layer is a well layer has a strained quantum well structure having a larger lattice constant than GaAs used as a growth substrate.
  • a strained quantum well structure the influence of the composition and thickness of InGaAs on the output and monochromaticity is large, and selection of an appropriate composition, thickness, and number of pairs is important.
  • the lattice irregularity due to the increase in the number of InGaAs pairs is alleviated throughout the quantum well structure, thereby improving the light emission output characteristics in the high current region. I found out.
  • the compound semiconductor layer including the active layer is attached (bonded) to the transparent substrate, and the compound semiconductor layer is grown.
  • the GaAs substrate was used as it was. However, the GaAs substrate is highly doped to increase conductivity, and absorption of light by carriers is inevitable.
  • the present invention provides the following configurations.
  • Well layer composed of composition formula (In X1 Ga 1-X1 ) As (0 ⁇ X1 ⁇ 1) and composition formula (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ⁇ X2 ⁇ 1,0)
  • An active layer having a quantum well structure in which barrier layers made of ⁇ Y1 ⁇ 1) are alternately stacked, and a composition formula (Al X3 Ga 1-X3 ) Y2 In 1-Y2 P (0 ⁇ X3 ⁇ ) sandwiching the active layer 1 and 0 ⁇ Y2 ⁇ 1), and a first cladding layer and a second guide sandwiching the active layer through the first guide and the second guide, respectively.
  • a light emitting portion having a cladding layer; a current diffusion layer formed on the light emitting portion; and a functional substrate bonded to the current diffusion layer, wherein the first and second cladding layers have a composition formula (Al X4 Ga 1-X4 ) Y3 In 1-Y3 P (0 ⁇ X4 ⁇ 1,0 ⁇ Y 3.
  • a light emitting diode comprising 3 ⁇ 1).
  • compositions X2 and Y1 of the barrier layer are 0 ⁇ X2 ⁇ 0.2 and 0.5 ⁇ Y1 ⁇ 0.7, respectively, and the compositions X3 and Y2 of the first and second guides are respectively 0.2 ⁇ X3 ⁇ 0.5, 0.4 ⁇ Y2 ⁇ 0.6, and the compositions X4 and Y3 of the first and second cladding layers are 0.3 ⁇ X4 ⁇ 0.7, 0, respectively. 4 ⁇ Y3 ⁇ 0.6, The light-emitting diode according to any one of the above items (1) to (3). (5) The light-emitting diode according to any one of (1) to (4), wherein the functional substrate is transparent to an emission wavelength.
  • the side surface of the functional substrate has a vertical surface that is substantially perpendicular to the main light extraction surface on the side close to the light emitting unit, and the main light extraction surface on the side far from the light emitting unit.
  • the light-emitting diode according to any one of (1) to (6), wherein the light-emitting diode has an inclined surface inclined inward.
  • a light emitting part having a cladding layer, a current diffusion layer formed on the light emitting part, a reflective layer disposed opposite to the light emitting part and having a reflectance of 90% or more with respect to the emission wavelength,
  • a functional substrate bonded to the current spreading layer, and the first and second Rudd layer composition formula (Al X4 Ga 1-X4) Y3 In 1-Y3 P (0 ⁇ X4 ⁇ 1,0 ⁇ Y3 ⁇ 1) light emitting diode, comprising the.
  • “bonding” further includes the case of bonding through a layer between the current diffusion layer and the functional substrate.
  • compositions X2 and Y1 of the barrier layer are 0 ⁇ X2 ⁇ 0.2 and 0.5 ⁇ Y1 ⁇ 0.7, respectively, and the compositions X3 and Y2 of the first and second guides are respectively 0.2 ⁇ X3 ⁇ 0.5, 0.4 ⁇ Y2 ⁇ 0.6, and the compositions X4 and Y3 of the first and second cladding layers are 0.3 ⁇ X4 ⁇ 0.7, 0, respectively. 4 ⁇ Y3 ⁇ 0.6, The light-emitting diode according to any one of (9) to (11) above. (13) The light-emitting diode according to any one of (9) to (12), wherein the functional substrate includes a layer made of silicon or germanium.
  • the metal substrate includes a plurality of metal layers.
  • the current diffusion layer is made of GaP or GaInP.
  • the current diffusion layer has a thickness in a range of 0.5 to 20 ⁇ m.
  • the first electrode and the second electrode are provided on the main light extraction surface side of the light-emitting diode. .
  • the term “functional substrate” means that after growing a compound semiconductor layer on a growth substrate, the growth substrate is removed and bonded to the compound semiconductor layer via a current diffusion layer to support the compound semiconductor layer.
  • the substrate including the predetermined layer is referred to as a “functional substrate”.
  • the active layer is a well layer having the composition formula (In X1 Ga 1-X1 ) As (0 ⁇ X1 ⁇ 1) and the composition formula (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ⁇ X2 ⁇ 1,0) Since it has a multi-well structure in which barrier layers made of ⁇ Y1 ⁇ 1) are alternately laminated, the monochromaticity is excellent.
  • the barrier layer, the guide layer, and the clad layer are composed of the composition formula (Al X Ga 1-X ) Y In 1-YP (0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1), it contains As that easily creates defects. Since it has no crystallinity, it contributes to high output.
  • the barrier layer, the guide layer, and the cladding layer have a composition formula (Al X Ga 1-X ) Y In 1-YP (0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1), the barrier layer, the guide layer, and the cladding layer Compared with an infrared light emitting diode whose layer is composed of a ternary mixed crystal, the Al concentration is low, and the moisture resistance is improved.
  • the active layer is a well layer having the composition formula (In X1 Ga 1-X1 ) As (0 ⁇ X1 ⁇ 1) and the composition formula (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ⁇ X2 ⁇ 1,0) Since it has a laminated structure with a barrier layer made of ⁇ Y1 ⁇ 1), it is suitable for mass production using the MOCVD method.
  • a barrier layer having a composition formula (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ⁇ X2 ⁇ 1, 0 ⁇ Y1 ⁇ 1)
  • the composition X2 and Y1 are set to satisfy 0 ⁇ X2 ⁇ 0.2 and 0.5 ⁇ Y1 ⁇ 0.7, respectively, thereby relaxing the strain of the well layer with respect to the GaAs substrate and suppressing the decrease in crystallinity. it can.
  • the functional substrate is made of GaP, SiC, silicon, or germanium, the thermal expansion coefficient is close to that of the light emitting portion, so that stress can be reduced. Moreover, since it is a material which does not corrode easily, moisture resistance improves. When both the functional substrate and the current diffusion layer are made of GaP, the bonding can be facilitated and the bonding strength can be increased.
  • the crystallinity can be improved by lattice matching with the InGaAs well layer.
  • the light-emitting diode lamp of the present invention has an emission peak wavelength of 850 nm or more, particularly 900 nm or more, and is provided with the light-emitting diode having excellent monochromaticity, high output, high efficiency, and excellent moisture resistance. Therefore, it is suitable for light sources for a wide range of applications such as sensor applications.
  • FIG. 2 is a schematic cross-sectional view taken along line A-A ′ shown in FIG. 1 of a light-emitting diode lamp using a light-emitting diode according to an embodiment of the present invention. It is a top view of the light emitting diode which is one Embodiment of this invention.
  • FIG. 4 is a schematic cross-sectional view of the light emitting diode according to the embodiment of the present invention, taken along line B-B ′ shown in FIG. 3. It is a figure for demonstrating the active layer which comprises the light emitting diode which is one Embodiment of this invention.
  • FIG. 14B is a schematic cross-sectional view taken along line C-C ′ shown in FIG. 14A. It is a cross-sectional schematic diagram of the light emitting diode which is other embodiment of this invention.
  • FIG. 1 and 2 are diagrams for explaining a light-emitting diode lamp using a light-emitting diode according to an embodiment to which the present invention is applied.
  • FIG. 1 is a plan view, and FIG. It is sectional drawing along the A 'line.
  • one or more light-emitting diodes 1 are mounted on the surface of a mount substrate 42. More specifically, an n electrode terminal 43 and a p electrode terminal 44 are provided on the surface of the mount substrate 42.
  • the n-type ohmic electrode 4 that is the first electrode of the light-emitting diode 1 and the n-electrode terminal 43 of the mount substrate 42 are connected using a gold wire 45 (wire bonding).
  • the p-type ohmic electrode 5, which is the second electrode of the light emitting diode 1, and the p-electrode terminal 44 of the mount substrate 42 are connected using a gold wire 46.
  • a third electrode 6 is provided on the surface of the light emitting diode 1 opposite to the surface on which the n-type and p-type ohmic electrodes 4 and 5 are provided.
  • the light emitting diode 1 is connected to the n electrode terminal 43 by the electrode 6 and fixed to the mount substrate 42.
  • the n-type ohmic electrode 4 and the third electrode 6 are electrically connected by the n-pole electrode terminal 43 so as to be equipotential or substantially equipotential.
  • the third electrode prevents an overcurrent from flowing in the active layer against an excessive reverse voltage, and a current flows between the third electrode and the p-type electrode, thereby preventing the active layer from being damaged.
  • a reflection structure can be added to the third electrode and the substrate interface side to achieve high output. Further, by adding eutectic metal, solder or the like to the surface side of the third electrode, a simpler assembly technique such as eutectic die bonding can be used.
  • the surface of the mount substrate 42 on which the light emitting diode 1 is mounted is sealed with a general sealing resin 47 such as silicon resin or epoxy resin.
  • FIG. 3 and 4 are diagrams for explaining the light emitting diode according to the first embodiment to which the present invention is applied.
  • FIG. 3 is a plan view
  • FIG. 4 is taken along the line BB ′ shown in FIG.
  • FIG. 5 is a cross-sectional view of a laminated structure of a well layer and a barrier layer.
  • the light emitting diode according to the first embodiment includes a well layer 17 having a composition formula (In X1 Ga 1 -X1 ) As (0 ⁇ X1 ⁇ 1) and a composition formula (Al X2 Ga 1 -X2 ) Y1 In 1 -Y1.
  • An active layer 11 having a quantum well structure in which barrier layers 18 made of P (0 ⁇ X2 ⁇ 1, 0 ⁇ Y1 ⁇ 1) are alternately stacked, and a composition formula (Al X3 Ga 1-X3 ) sandwiching the active layer 11 Via the first guide 10 and the second guide 12 made of Y2 In 1-Y2 P (0 ⁇ X3 ⁇ 1, 0 ⁇ Y2 ⁇ 1), and the first guide 10 and the second guide 12, respectively.
  • a light emitting unit 7 having a first cladding layer 9 and a second cladding layer 13 sandwiching the active layer 11, a current diffusion layer 8 formed on the light emitting unit 7, and a functional substrate bonded to the current diffusion layer 8 3 and a first clad layer 9 and a second clad layer 3 is characterized by comprising the composition formula (Al X4 Ga 1-X4) Y3 In 1-Y3 P (0 ⁇ X4 ⁇ 1,0 ⁇ Y3 ⁇ 1).
  • the light-emitting diode 1 is schematically configured to include an n-type ohmic electrode (first electrode) 4 and a p-type ohmic electrode (second electrode) 5 provided on the main light extraction surface.
  • the main light extraction surface in this embodiment is a surface of the compound semiconductor layer 2 opposite to the surface to which the functional substrate 3 is attached.
  • the compound semiconductor layer (also referred to as an epitaxial growth layer) 2 has a structure in which a pn junction type light emitting portion 7 and a current diffusion layer 8 are sequentially stacked.
  • a known functional layer can be added to the structure of the compound semiconductor layer 2 as appropriate.
  • the compound semiconductor layer 2 is preferably formed by epitaxial growth on a GaAs substrate.
  • the light emitting unit 7 includes at least a p-type lower cladding layer (first cladding layer) 9, a lower guide layer 10, an active layer 11, an upper guide layer 12, n on a current diffusion layer 8.
  • a mold upper clad layer (second clad layer) 13 is sequentially laminated. That is, the light emitting unit 7 includes a lower clad layer 9 disposed to face the lower side and the upper side of the active layer 11 in order to “confine” the carrier (carrier) and light emission that cause radiative recombination in the active layer 11.
  • a so-called double hetero (English abbreviation: DH) structure including the lower guide layer 10, the upper guide layer 12, and the upper cladding layer 13 is preferable in order to obtain high-intensity light emission.
  • the active layer 11 forms a quantum well structure in order to control the emission wavelength of the light emitting diode (LED). That is, the active layer 11 has a multilayer structure (laminated structure) of a well layer 17 and a barrier layer (also referred to as a barrier layer) 18 having a barrier layer (also referred to as a barrier layer) 18 at both ends.
  • a barrier layer also referred to as a barrier layer
  • the layer thickness of the active layer 11 is preferably in the range of 50 to 1000 nm.
  • the conductivity type of the active layer 11 is not particularly limited, and any of undoped, p-type and n-type can be selected. In order to increase the light emission efficiency, it is desirable that the crystallinity be undoped or the carrier concentration be less than 3 ⁇ 10 17 cm ⁇ 3 .
  • FIG. 6 shows the correlation between the layer thickness and the emission peak wavelength with the In composition (X1) of the well layer 17 fixed at 0.1.
  • Table 1 shows the values of the data shown in FIG. It can be seen that when the well layer is as thick as 3 nm, 5 nm, and 7 nm, the wavelength monotonously increases to 820 nm, 870 nm, and 920 nm.
  • FIG. 7 shows the correlation between the emission peak wavelength of the well layer 17 and its In composition (X1) and layer thickness.
  • FIG. 7 shows a combination of the In composition (X1) and the layer thickness of the well layer 17 in which the emission peak wavelength of the well layer 17 is a predetermined wavelength. Specifically, a combination of the In composition (X1) and the layer thickness of the well layer 17 having a configuration in which the emission peak wavelengths are 920 nm and 960 nm, respectively, is shown.
  • FIG. 7 further shows combinations of In composition (X1) and layer thicknesses at other emission peak wavelengths of 820 nm, 870 nm, 985 nm, and 995 nm. Table 2 shows the values of the data shown in FIG.
  • the corresponding layer thickness monotonously increases from 3 nm to 8 nm.
  • a combination with an emission peak wavelength of 920 nm can be easily found.
  • the In composition (X1) is 0.1 and the layer thickness is increased to 3 nm, 5 nm, 7 nm, and 8 nm, the emission peak wavelengths are correspondingly increased to 820 nm, 870 nm, 920 nm, and 960 nm.
  • the emission peak wavelength is correspondingly increased to 920 nm and 960 nm when the layer thickness is increased to 5 nm and 6 nm, and when the In composition (X1) is 0.25,
  • the emission peak wavelengths are correspondingly increased to 920 nm and 960 nm, and when the In composition (X1) is 0.3, the layer thickness is increased to 3 nm and 5 nm.
  • the emission peak wavelengths are as long as 920 nm and 985 nm.
  • the emission peak wavelengths are increased to 870 nm, 920 nm, 960 nm, and 985 nm.
  • the In composition (X1) becomes 0.35, the emission peak wavelength becomes 995 nm.
  • FIG. 7 it is shown that when a combination of the In composition (X1) with the emission peak wavelengths of 920 nm and 960 nm and the layer thickness is connected, it becomes a substantially straight line. Further, it is presumed that a line connecting a combination of the In composition (X1) having a predetermined emission peak wavelength in the wavelength band from 850 nm to 1000 nm and the layer thickness is also substantially linear. Further, it is assumed that the line connecting the combinations is located at the lower left as the emission peak wavelength is shorter, and located at the upper right as the longer the emission peak wavelength. Based on the above regularity, the In composition (X1) and the layer thickness having a desired emission peak wavelength of 850 nm or more and 1000 nm or less can be easily found.
  • FIG. 8 shows the correlation between the In composition (X1), the emission peak wavelength, and its emission output, with the well layer 17 having a thickness of 5 nm.
  • Table 3 shows the data values shown in FIG.
  • the In composition (X1) is increased to 0.12, 0.2, 0.25, 0.3, and 0.35, the emission peak wavelengths are increased to 870 nm, 920 nm, 960 nm, 985 nm, and 995 nm. More specifically, as the In composition (X1) increases from 0.12 to 0.3, the emission peak wavelength increases from 870 nm to 985 nm almost monotonically.
  • the In composition (X1) is increased from 0.3 to 0.35, the length increases from 985 nm to 995 nm, but the rate of change to long wavelengths is small.
  • the well layer 17 preferably has a composition of (In X1 Ga 1-X1 ) As (0 ⁇ X1 ⁇ 0.3, where X1 is a desired emission wavelength. Can be adjusted.
  • the emission peak wavelength is 900 nm or more, 0.1 ⁇ X1 ⁇ 0.3 is preferable, and when it is less than 900 nm, 0 ⁇ X1 ⁇ 0.1 is preferable.
  • the layer thickness of the well layer 17 is preferably in the range of 3 to 20 nm. More preferably, it is in the range of 3 to 10 nm.
  • the barrier layer 18 has a composition of (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ⁇ X2 ⁇ 1, 0 ⁇ Y1 ⁇ 1).
  • X2 is preferably a composition having a larger band gap than the well layer 17, and more preferably in the range of 0 to 0.2.
  • Y1 is preferably set to 0.5 to 0.7, more preferably in the range of 0.52 to 0.60, in order to relieve strain caused by lattice mismatch of the well layer 17.
  • the layer thickness of the barrier layer 18 is preferably equal to or thicker than the layer thickness of the well layer 17. Thereby, the luminous efficiency of the well layer 17 can be increased.
  • the light emission output is as high as 6.5 mW or more when the number of pairs is 1 to 10, but the value decreases to 5 mW with 20 pairs.
  • a high value of approximately 6.5 mW or more is maintained up to 20 pairs.
  • Table 5 shows the data values shown in FIG. This is a case where a GaAs substrate is used as the growth substrate.
  • the barrier layer is the same as that of the present invention, but the well layer is a GaAs layer made of the same material as the growth substrate (that is, when the growth substrate is not distorted). Was also shown.
  • the maximum light emission output is 7 mW
  • Y1 of the barrier layer is about 7 mW in the range of 0.52 to 0.60.
  • the light emission output is 6.5 mW at the maximum, and the range showing high output is narrower than the case of the present invention.
  • the composition range of the barrier layer exhibiting high light output and high output is wide.
  • it since it is a combination of a well layer having no strain and a barrier layer having a strain, it can be understood that as a result, the crystallinity is lowered and the light emission output characteristics are lowered.
  • FIG. 11 shows the dependence of the number of well layer and barrier layer pairs on the correlation between the forward current and the light emission output.
  • the forward current was up to 30 mA
  • the light emission output increased substantially in proportion to the increase in current in both 3 and 5 pairs.
  • the light emission output increased with increasing current while maintaining approximately proportionality with respect to 5 pairs.
  • the number of pairs in which the well layers 17 and the barrier layers 18 are alternately stacked is not particularly limited.
  • the active layer 11 preferably includes 1 to 20 well layers 17.
  • a single well layer 17 is sufficient as a suitable range for the luminous efficiency of the active layer 11.
  • the luminous efficiency is improved particularly under high current conditions. It is preferable that there are a plurality of points.
  • the lower guide layer 10 and the upper guide layer 12 are provided on the lower surface and the upper surface of the active layer 11, respectively, as shown in FIG. Specifically, the lower guide layer 10 is provided on the lower surface of the active layer 11, and the upper guide layer 12 is provided on the upper surface of the active layer 11.
  • the lower guide layer 10 and the upper guide layer 12 have a composition of (Al X3 Ga 1 -X3 ) Y2 In 1 -Y2 P (0 ⁇ X3 ⁇ 1, 0 ⁇ Y2 ⁇ 1).
  • X3 is preferably a composition having the same band gap as that of the barrier layer 18 or larger than the barrier layer 18, and more preferably in the range of 0.2 to 0.5.
  • Y2 is preferably 0.4 to 0.6.
  • X3 functions as a clad layer and is selected in a range that is transparent to the emission wavelength, and Y2 is selected as a range in which good crystal growth can be achieved by placing importance on lattice matching with the substrate because the clad layer is thick.
  • the lower guide layer 10 and the upper guide layer 12 are provided to reduce the propagation of impurities between the lower cladding layer 9 and the upper cladding layer 13 and the active layer 11, respectively. That is, in the present invention, the lower clad layer 9 and the upper clad layer 13 are doped with an impurity at a high concentration, and the diffusion of the impurity into the active layer 11 causes the performance of the light emitting diode to deteriorate.
  • the thickness of the lower guide layer 10 and the upper guide layer 12 is preferably 10 nm or more, and more preferably 20 nm to 100 nm.
  • the conductivity type of the lower guide layer 10 and the upper guide layer 12 is not particularly limited, and any of undoped, p-type, and n-type can be selected. In order to increase the light emission efficiency, it is desirable that the crystallinity be undoped or the carrier concentration be less than 3 ⁇ 10 17 cm ⁇ 3 .
  • the lower clad layer 9 and the upper clad layer 13 are provided on the lower surface of the lower guide layer 10 and the upper surface of the upper guide layer 12, respectively, as shown in FIG.
  • a semiconductor material of (Al X4 Ga 1 -X4 ) Y3 In 1-Y3 P (0 ⁇ X4 ⁇ 1, 0 ⁇ Y3 ⁇ 1) is used, and the barrier layer 15 A material having a larger band gap is preferable, and a material having a larger band gap than the lower guide layer 10 and the upper guide layer 12 is more preferable.
  • the material may have a composition in which X4 of (Al X4 Ga 1-X4 ) Y3 In 1-Y3 P (0 ⁇ X4 ⁇ 1, 0 ⁇ Y3 ⁇ 1) is 0.3 to 0.7. preferable.
  • Y3 is preferably 0.4 to 0.6.
  • X4 functions as a clad layer and is selected in a range that is transparent to the emission wavelength, and Y3 is selected as a range in which good quality crystal growth is possible from the viewpoint of lattice matching with the substrate because the clad layer is thick.
  • the lower clad layer 9 and the upper clad layer 13 are configured to have different polarities.
  • the carrier concentration and thickness of the lower clad layer 9 and the upper clad layer 13 can be in a known suitable range, and it is preferable to optimize the conditions so that the luminous efficiency of the active layer 11 is increased. Further, the warpage of the compound semiconductor layer 2 can be reduced by controlling the composition of the lower cladding layer 9 and the upper cladding layer 13.
  • the lower clad layer 9 for example, p-type (Al X4a Ga 1-X4a ) Ya In 1- YaP (0.3 ⁇ X4a ⁇ 0.7, 0.4 ⁇ Y3a) doped with Mg is used. It is desirable to use a semiconductor material composed of ⁇ 0.6).
  • the carrier concentration is preferably in the range of 2 ⁇ 10 17 to 2 ⁇ 10 18 cm ⁇ 3
  • the layer thickness is preferably in the range of 0.1 to 1 ⁇ m.
  • the carrier concentration is preferably in the range of 1 ⁇ 10 17 to 1 ⁇ 10 18 cm ⁇ 3
  • the layer thickness is preferably in the range of 0.1 to 1 ⁇ m.
  • the polarities of the lower cladding layer 9 and the upper cladding layer 13 can be selected in consideration of the element structure of the compound semiconductor layer 2.
  • a contact layer for lowering the contact resistance of the ohmic electrode a current diffusion layer for planarly diffusing the element driving current throughout the light emitting unit, and conversely
  • a known layer structure such as a current blocking layer or a current confinement layer for limiting the region through which the element driving current flows can be provided.
  • the current spreading layer 8 is provided below the light emitting unit 7.
  • the current spreading layer 8 can be made of a material that is transparent to the emission wavelength from the light emitting unit 7 (active layer 11), such as GaP or GaInP.
  • GaP the emission wavelength from the light emitting unit 7
  • the functional substrate 3 as a GaP substrate
  • bonding can be facilitated and high bonding strength can be obtained.
  • GaInP the lattice constant is made the same as that of InGaAs, which is the material of the well layer 17 on which the current diffusion layer 8 is stacked, by changing the ratio of Ga and In. There is an effect that lattice matching can be achieved.
  • the thickness of the current spreading layer 8 is preferably in the range of 0.5 to 20 ⁇ m. This is because the current diffusion is insufficient when the thickness is 0.5 ⁇ m or less, and the cost for crystal growth to the thickness increases when the thickness is 20 ⁇ m or more.
  • the functional substrate 3 is bonded to the surface of the compound semiconductor layer 2 opposite to the main light extraction surface. That is, the functional substrate 3 is bonded to the current diffusion layer 8 side constituting the compound semiconductor layer 2 as shown in FIG.
  • This functional substrate 3 is made of a material that has sufficient strength to mechanically support the light emitting portion 7, has a wide band gap, and is optically transparent to the emission wavelength from the light emitting portion 7.
  • the functional substrate 3 is a substrate having a thermal expansion coefficient close to that of the light emitting portion and excellent in moisture resistance, and is preferably made of GaP, GaInP, SiC having good thermal conductivity, and sapphire having high mechanical strength.
  • the functional substrate 3 preferably has a thickness of, for example, about 50 ⁇ m or more in order to support the light emitting unit 7 with sufficient mechanical strength. In order to facilitate the mechanical processing of the functional substrate 3 after bonding to the compound semiconductor layer 2, it is preferable that the thickness does not exceed about 300 ⁇ m.
  • the functional substrate 3 is optimally composed of an n-type GaP substrate in terms of transparency, stress, and cost with a thickness of about 50 ⁇ m or more and about 300 ⁇ m or less.
  • the side surface of the functional substrate 3 is a vertical surface 3 a that is substantially perpendicular to the main light extraction surface on the side close to the compound semiconductor layer 2, and is far from the compound semiconductor layer 2.
  • the inclined surface 3b is inclined inward with respect to the main light extraction surface.
  • the light emitted from the active layer 11 to the functional substrate 3 can be efficiently extracted to the outside.
  • part of the light emitted from the active layer 11 to the functional substrate 3 side is reflected by the vertical surface 3a and can be extracted by the inclined surface 3b.
  • the light reflected by the inclined surface 3b can be extracted by the vertical surface 3a.
  • the light extraction efficiency can be increased by the synergistic effect of the vertical surface 3a and the inclined surface 3b.
  • the angle ⁇ formed by the inclined surface 3b and the surface parallel to the light emitting surface is preferably in the range of 55 degrees to 80 degrees. By setting it as such a range, the light reflected by the bottom part of the functional board
  • the width (thickness direction) of the vertical surface 3a is preferably in the range of 30 ⁇ m to 100 ⁇ m. By setting the width of the vertical surface 3a within the above range, the light reflected at the bottom of the functional substrate 3 can be efficiently returned to the light emitting surface at the vertical surface 3a, and further emitted from the main light extraction surface. It becomes possible. For this reason, the light emission efficiency of the light emitting diode 1 can be improved.
  • the inclined surface 3b of the functional substrate 3 is preferably roughened.
  • an effect of increasing the light extraction efficiency at the inclined surface 3b can be obtained. That is, by roughening the inclined surface 3b, total reflection on the inclined surface 3b can be suppressed and light extraction efficiency can be increased.
  • the functional substrate 3 can include a reflective layer (not shown) having a reflectance of 90% or more with respect to the emission wavelength and disposed to face the light emitting unit. With this configuration, light can be efficiently extracted from the main light extraction surface.
  • the reflective layer is made of, for example, silver (Ag), aluminum (Al), gold (Au), or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective layer 23 can be 90% or more.
  • the functional substrate 3 can use a combination of eutectic metal such as AuIn, AuGe, AuSn, and the like and bonded to an inexpensive substrate such as silicon or germanium having a thermal expansion coefficient close to that of the light emitting portion.
  • AuIn has a low bonding temperature and a thermal expansion coefficient different from that of the light emitting part, but is an optimal combination for bonding the cheapest silicon substrate (silicon layer).
  • a refractory metal such as Ti, W, Pt or a transparent conductive oxide such as ITO may be inserted so that the current diffusion layer, the reflective metal and the eutectic metal do not interdiffuse. Desirable because of its stability.
  • the bonding interface between the compound semiconductor layer 2 and the functional substrate 3 may be a high resistance layer. That is, a high resistance layer (not shown) may be provided between the compound semiconductor layer 2 and the functional substrate 3. This high resistance layer exhibits a higher resistance value than that of the functional substrate 3, and when the high resistance layer is provided, the compound semiconductor layer 2 has a reverse direction from the current diffusion layer 8 side to the functional substrate 3 side. It has a function of reducing current. Moreover, although the junction structure which exhibits voltage resistance with respect to the voltage of the reverse direction applied carelessly from the functional board
  • the n-type ohmic electrode (first electrode) 4 and the p-type ohmic electrode (second electrode) 5 are low-resistance ohmic contact electrodes provided on the main light extraction surface of the light-emitting diode 1.
  • the n-type ohmic electrode 4 is provided above the upper cladding layer 11, and for example, an alloy made of AuGe, Ni alloy / Au can be used.
  • the p-type ohmic electrode 5 can use AuBe / Au or an alloy made of AuZn / Au on the exposed surface of the current diffusion layer 8.
  • the p-type ohmic electrode 5 on the current diffusion layer 8 is formed as the second electrode.
  • the effect of reducing an operating voltage is acquired.
  • the p-type ohmic electrode 5 on the current diffusion layer 8 made of p-type GaP a good ohmic contact can be obtained, so that the operating voltage can be lowered.
  • the polarity of the first electrode is n-type and the polarity of the second electrode is p-type.
  • the first electrode is p-type, current diffusion is deteriorated, resulting in a decrease in luminance.
  • the first electrode n-type current diffusion is improved, and high luminance of the light emitting diode 1 can be achieved.
  • the n-type ohmic electrode 4 and the p-type ohmic electrode 5 are arranged at diagonal positions as shown in FIG.
  • the p-type ohmic electrode 5 is most preferably surrounded by the compound semiconductor layer 2.
  • the n-type ohmic electrode 4 has a mesh such as a honeycomb or a lattice shape. With such a configuration, an effect of improving reliability can be obtained. Further, by using the lattice shape, a current can be uniformly injected into the active layer 11, and as a result, an effect of improving reliability can be obtained.
  • the n-type ohmic electrode 4 is preferably composed of a pad-shaped electrode (pad electrode) and a linear electrode (linear electrode) having a width of 10 ⁇ m or less. With such a configuration, high luminance can be achieved.
  • the opening area of the light extraction surface can be increased, and high luminance can be achieved.
  • the third electrode is formed on the back surface of the functional substrate, and in the case of a transparent substrate, the output can be further increased by reflecting the substrate.
  • the reflective metal material materials such as Au, Ag, and Al can be used.
  • eutectic metal such as AuSn and solder material on the electrode surface side, it is not necessary to use a paste in the die bonding process, which is simplified.
  • heat conduction is improved, and the heat dissipation characteristics of the light emitting diode are improved.
  • FIG. 12 is a cross-sectional view of an epi-wafer used for the light-emitting diode 1 of the present embodiment.
  • FIG. 13 is a cross-sectional view of a bonded wafer used for the light emitting diode 1 of the present embodiment.
  • the compound semiconductor layer 2 shown in FIG. 12 includes a buffer layer 15 made of GaAs on an GaAs substrate 14, an etching stop layer (not shown) provided for use in selective etching, an n-type contact layer 16 doped with Si, an n-type
  • the upper cladding layer 13, the upper guide layer 12, the active layer 11, the lower guide layer 10, the p-type lower cladding layer 9, and the current diffusion layer 8 made of Mg-doped p-type GaP are sequentially stacked.
  • the GaAs substrate 14 a commercially available single crystal substrate manufactured by a known manufacturing method can be used.
  • the surface of the GaAs substrate 14 on which the epitaxial growth is performed is desirably smooth.
  • the surface orientation of the surface of the GaAs substrate 14 is easy to epitaxially grow, and a substrate that is turned off within ⁇ 20 ° from the (100) plane and (100) that are mass-produced is desirable from the standpoint of quality stability.
  • the range of the plane orientation of the GaAs substrate 14 is more preferably 15 ° off ⁇ 5 ° from the (100) direction to the (0-1-1) direction.
  • “-” means a bar attached to the index immediately after that.
  • the dislocation density of the GaAs substrate 14 is desirably low in order to improve the crystallinity of the compound semiconductor layer 2. Specifically, for example, 10,000 pieces cm ⁇ 2 or less, preferably 1,000 pieces cm ⁇ 2 or less are suitable.
  • the GaAs substrate 14 may be n-type or p-type.
  • the carrier concentration of the GaAs substrate 14 can be appropriately selected from desired electrical conductivity and element structure.
  • the carrier concentration is preferably in the range of 1 ⁇ 10 17 to 5 ⁇ 10 18 cm ⁇ 3 .
  • the carrier concentration is preferably in the range of 2 ⁇ 10 18 to 5 ⁇ 10 19 cm ⁇ 3 .
  • the thickness of the GaAs substrate 14 has an appropriate range depending on the size of the substrate. If the thickness of the GaAs substrate 14 is thinner than an appropriate range, the compound semiconductor layer 2 may be broken during the manufacturing process. On the other hand, when the thickness of the GaAs substrate 14 is thicker than an appropriate range, the material cost increases. Therefore, when the substrate size of the GaAs substrate 14 is large, for example, when the diameter is 75 mm, a thickness of 250 to 500 ⁇ m is desirable to prevent cracking during handling. Similarly, when the diameter is 50 mm, a thickness of 200 to 400 ⁇ m is desirable, and when the diameter is 100 mm, a thickness of 350 to 600 ⁇ m is desirable.
  • the warpage of the compound semiconductor layer 2 due to the light emitting portion 7 can be reduced.
  • the temperature distribution during epitaxial growth becomes uniform, so that the in-plane wavelength distribution of the active layer 11 can be reduced.
  • the shape of the GaAs substrate 14 is not particularly limited to a circle, and there is no problem even if it is a rectangle or the like.
  • the buffer layer 15 is provided to reduce the propagation of defects between the GaAs substrate 14 and the constituent layers of the light emitting unit 7. For this reason, the buffer layer 15 is not necessarily required if the quality of the substrate and the epitaxial growth conditions are selected.
  • the buffer layer 15 is preferably made of the same material as that of the substrate to be epitaxially grown. Therefore, in the present embodiment, it is preferable to use GaAs for the buffer layer 15 as with the GaAs substrate 14.
  • the buffer layer 15 can also be a multilayer film made of a material different from that of the GaAs substrate 14 in order to reduce the propagation of defects.
  • the thickness of the buffer layer 15 is preferably 0.1 ⁇ m or more, and more preferably 0.2 ⁇ m or more.
  • the contact layer 16 (omitted in FIG. 4) is provided to reduce the contact resistance with the electrode.
  • the material of the contact layer 16 is preferably a material having a band gap larger than that of the active layer 11, and Al X Ga 1-X As, (Al X Ga 1-X ) Y In 1-YP (0 ⁇ X ⁇ 1) , 0 ⁇ Y ⁇ 1) can be preferably used.
  • the lower limit value of the carrier concentration of the contact layer 16 is preferably 5 ⁇ 10 17 cm ⁇ 3 or more and more preferably 1 ⁇ 10 18 cm ⁇ 3 or more in order to reduce the contact resistance with the electrode.
  • the upper limit value of the carrier concentration is desirably 2 ⁇ 10 19 cm ⁇ 3 or less at which the crystallinity is likely to decrease.
  • the thickness of the contact layer 16 is preferably 0.5 ⁇ m or more, and optimally 1 ⁇ m or more.
  • the upper limit value of the thickness of the contact layer 16 is not particularly limited, but is desirably 5 ⁇ m or less in order to bring the cost for epitaxial growth to an appropriate range.
  • a known growth method such as a molecular beam epitaxial method (MBE) or a low pressure metal organic chemical vapor deposition method (MOCVD method) can be applied.
  • MBE molecular beam epitaxial method
  • MOCVD method low pressure metal organic chemical vapor deposition method
  • the MOCVD method which is excellent in mass productivity.
  • the GaAs substrate 14 used for the epitaxial growth of the compound semiconductor layer 2 is preferably subjected to a pretreatment such as a cleaning process or a heat treatment before the growth to remove surface contamination or a natural oxide film.
  • the layers constituting the compound semiconductor layer 2 can be laminated by setting a GaAs substrate 14 having a diameter of 50 to 150 mm in an MOCVD apparatus and simultaneously epitaxially growing it.
  • the MOCVD apparatus a commercially available large-sized apparatus such as a self-revolving type or a high-speed rotating type can be applied.
  • examples of the group III constituent material include trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga), and trimethylindium ((CH 3 ) 3 In) can be used.
  • a Mg doping material for example, biscyclopentadienyl magnesium (bis- (C 5 H 5 ) 2 Mg) or the like can be used.
  • a Si doping material for example, disilane (Si 2 H 6 ) or the like can be used.
  • phosphine (PH 3 ), arsine (AsH 3 ), or the like can be used as a raw material for the group V constituent element.
  • each layer As the growth temperature of each layer, 720 to 770 ° C. can be applied when p-type GaP is used as the current diffusion layer 8, and 600 to 700 ° C. can be applied to the other layers. When p-type GaInP is used as the current diffusion layer 8, 600 to 700 ° C. can be applied. Furthermore, the carrier concentration, layer thickness, and temperature conditions of each layer can be selected as appropriate.
  • the compound semiconductor layer 2 produced in this way has a good surface state with few crystal defects despite having the light emitting portion 7.
  • the compound semiconductor layer 2 may be subjected to surface processing such as polishing corresponding to the element structure.
  • the compound semiconductor layer 2 and the functional substrate 3 are bonded.
  • the surface of the current diffusion layer 8 constituting the compound semiconductor layer 2 is polished and mirror-finished.
  • the functional substrate 3 to be attached to the mirror-polished surface of the current spreading layer 8 is prepared.
  • the surface of the functional substrate 3 is polished to a mirror surface before being bonded to the current diffusion layer 8.
  • the compound semiconductor layer 2 and the functional substrate 3 are carried into a general semiconductor material pasting apparatus, and electrons are collided with both surfaces which are mirror-polished in a vacuum to make the neutral (neutral) Ar beam. Irradiate.
  • bonding can join at room temperature by superimposing both surfaces in the sticking apparatus which maintained the vacuum, and applying a load (refer FIG. 13).
  • materials having the same bonding surface are more desirable from the viewpoint of stability of bonding conditions. Bonding (pasting) is optimally performed at room temperature bonding under such a vacuum, but bonding can also be performed using a eutectic metal or an adhesive.
  • an n-type ohmic electrode 4 that is a first electrode and a p-type ohmic electrode 5 that is a second electrode are formed.
  • the GaAs substrate 14 and the buffer layer 15 are selectively removed from the compound semiconductor layer 2 bonded to the functional substrate 3 with an ammonia-based etchant.
  • the n-type ohmic electrode 4 is formed on the exposed surface of the contact layer 16.
  • AuGe, Ni alloy / Pt / Au are laminated by a vacuum deposition method so as to have an arbitrary thickness, and then patterned by using a general photolithography means to form the n-type ohmic electrode 4. Form the shape.
  • the current diffusion layer 8 is exposed by selectively removing a predetermined range of the contact layer 16, the upper cladding layer 13, the upper guide layer 12, the active layer 11, the lower guide layer 10, and the p-type lower cladding layer 9.
  • the p-type ohmic electrode 5 is formed on the exposed surface of the current diffusion layer 8.
  • AuBe / Au is laminated by vacuum deposition so as to have an arbitrary thickness, and then patterned using a general photolithography means to form the shape of the p-type ohmic electrode 5.
  • the low resistance n-type ohmic electrode 4 and p-type ohmic electrode 5 can be formed, for example, by alloying by heat treatment at 400 to 500 ° C. for 5 to 20 minutes.
  • the third electrode is formed on the back surface of the functional substrate.
  • functions such as an ohmic electrode, a Schottky electrode, a reflection function, and a eutectic die bond structure can be combined and added.
  • a material such as Au, Ag, or Al is formed to reflect the light.
  • a transparent film such as silicon oxide or ITO can be inserted between the substrate and the material.
  • a known technique such as a sputtering method or a vapor deposition method can be used.
  • eutectic metal such as AuSn, lead-free solder material, etc.
  • the shape of the functional substrate 3 is processed.
  • V-shaped grooving is performed on the surface on which the third electrode 6 is not formed.
  • the inner surface of the V-shaped groove on the third electrode 6 side becomes an inclined surface 3b having an angle ⁇ formed with a surface parallel to the light emitting surface.
  • dicing is performed from the compound semiconductor layer 2 side at predetermined intervals to form chips.
  • the vertical surface 3a of the functional substrate 3 is formed by dicing at the time of chip formation.
  • the formation method of the inclined surface 3b is not particularly limited, and conventional methods such as wet etching, dry etching, scribing, and laser processing can be used in combination, but the shape controllability and productivity can be improved. Most preferably, a high dicing method is applied. By applying the dicing method, the manufacturing yield can be improved.
  • the method for forming the vertical surface 3a is not particularly limited, but it is preferably formed by laser processing, a scribe / break method or a dicing method.
  • the manufacturing cost can be reduced. That is, since it is not necessary to provide a margin for chip separation and many light emitting diodes can be manufactured, the manufacturing cost can be reduced.
  • the dicing method is excellent in cutting stability.
  • the crushed layer and dirt are removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide as necessary. In this way, the light emitting diode 1 is manufactured.
  • the compound semiconductor layer including the light-emitting portion 7 having the well layer 17 having the composition formula (In X1 Ga 1 -X1 ) As (0 ⁇ X1 ⁇ 1). 2 is provided.
  • the current diffusion layer 8 is provided on the light emitting unit 7. Since the current spreading layer 8 is transparent with respect to the emission wavelength, the light-emitting diode 1 having high output and high efficiency can be obtained without absorbing the light emitted from the light emitting unit 7.
  • the functional substrate is stable in material, has no fear of corrosion, and has excellent moisture resistance.
  • the light emitting diode 1 of the present embodiment it is possible to provide the light emitting diode 1 having a light emission wavelength of 850 nm or more, excellent monochromaticity, high output, high efficiency, and moisture resistance. Further, according to the light emitting diode 1 of the present embodiment, the high output light emitting diode 1 having a light emission efficiency of about twice or more as compared with a transparent substrate type AlGaAs light emitting diode manufactured by a conventional liquid phase epitaxial method. Can be provided. Also, high temperature and high humidity reliability was improved.
  • FIG. 14A and 14B are views for explaining a light emitting diode according to a second embodiment to which the present invention is applied.
  • FIG. 14A is a plan view
  • FIG. 14B is along the line CC ′ shown in FIG. 14A. (The guide layers 10 and 12 are not shown).
  • the light emitting diode according to the second embodiment includes a well layer 17 having a composition formula (In X1 Ga 1-X1 ) As (0 ⁇ X1 ⁇ 1), a composition formula (Al X2 Ga 1-X2 ) Y1 In 1 ⁇ A composition formula (Al X3 Ga 1-X3) sandwiching the active layer 11 and the active layer 11 having a quantum well structure in which the barrier layers 18 composed of Y1 P (0 ⁇ X2 ⁇ 1, 0 ⁇ Y1 ⁇ 1) are alternately stacked.
  • First guide layer 10 and second guide layer 12 made of Y2 In 1-Y2 P (0 ⁇ X3 ⁇ 1, 0 ⁇ Y2 ⁇ 1), and first guide layer 10 and second guide layer 12
  • the light emitting part 7 having the first clad layer 9 and the second clad layer 13 sandwiching the active layer 11 therebetween, the current diffusion layer 8 formed on the light emitting part 7, and the light emitting part 7. Reflection having a reflectance of 90% or more with respect to the emission wavelength.
  • Comprises 23 comprises a functional substrate 31 which is joined to the current diffusion layer 8, the first cladding layer 9 and the second cladding layer 13 is a composition formula (Al X4 Ga 1-X4) Y3 In 1-Y3 P; 0 ⁇ X4 ⁇ 1, 0 ⁇ Y3 ⁇ 1).
  • the light-emitting diode according to the second embodiment has a functional substrate 31 that has a reflectance of 90% or more with respect to the emission wavelength and includes the reflective layer 23 disposed to face the light-emitting portion 7. Light can be efficiently extracted from the extraction surface.
  • the functional substrate 31 includes the second electrode 21 on the lower surface 8 b of the current diffusion layer 8, and further transparent conductive so as to cover the second electrode 21.
  • a reflective structure in which a film 22 and a reflective layer 23 are laminated, and a layer (substrate) 30 made of silicon or germanium are provided.
  • the functional substrate 31 preferably includes a layer made of silicon or germanium. This is because the material is not easily corroded, so that the moisture resistance is improved.
  • the reflective layer 23 is made of, for example, silver (Ag), aluminum (Al), gold (Au), or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective layer 23 can be 90% or more.
  • a combination of eutectic metal such as AuIn, AuGe, AuSn and the like and bonded to an inexpensive substrate (layer) such as silicon or germanium can be used for the functional layer 31.
  • AuIn has a low bonding temperature and a thermal expansion coefficient different from that of the light emitting portion, but is an optimal combination for bonding the cheapest silicon substrate (silicon layer).
  • the functional substrate 31 is further inserted with a layer made of a refractory metal such as titanium (Ti), tungsten (W), or platinum (Pt) so that the current diffusion layer, the reflective layer metal, and the eutectic metal do not interdiffuse. It is also desirable from the standpoint of quality stability to have a configured configuration.
  • a refractory metal such as titanium (Ti), tungsten (W), or platinum (Pt)
  • FIG. 15 is a diagram for explaining a light emitting diode according to a third embodiment to which the present invention is applied.
  • the light emitting diode according to the third embodiment includes a well layer 17 having a composition formula (In X1 Ga 1-X1 ) As (0 ⁇ X1 ⁇ 1), a composition formula (Al X2 Ga 1-X2 ) Y1 In 1 ⁇
  • First guide layer 10 and second guide layer 12 made of Y2 In 1-Y2 P (0 ⁇ X3 ⁇ 1, 0 ⁇ Y2 ⁇ 1), and first guide layer 10 and second guide layer 12
  • the light emitting part 7 having the first clad layer 9 and the second clad layer 13 sandwiching the active layer 11 therebetween, the current diffusion layer 8 formed on the light emitting part 7, and the light emitting part 7. Reflection having a reflectance of 90% or more with respect to the emission wavelength.
  • a 53 and the metal substrate 50 comprises a functional substrate 51 which is joined to the current diffusion layer 8, the first cladding layer 9 and the second cladding layer 13 is a composition formula (Al X4 Ga 1-X4) Y3 In 1-Y3 P; 0 ⁇ X4 ⁇ 1, 0 ⁇ Y3 ⁇ 1).
  • the light-emitting diode according to the third embodiment is a characteristic configuration with respect to the light-emitting diode according to the second embodiment in that the functional substrate includes a metal substrate.
  • the metal substrate 50 has high heat dissipation, contributes to light emission of the light emitting diode with high luminance, and can extend the life of the light emitting diode. From the viewpoint of heat dissipation, the metal substrate 50 is particularly preferably made of a metal having a thermal conductivity of 130 W / m ⁇ K or more.
  • the compound semiconductor layer 2 includes an active layer 11, a first clad layer (lower clad) 9 and a second clad layer sandwiching the active layer 11 via a guide layer (not shown).
  • (Upper clad) 13 the current diffusion layer 8 below the first clad layer (lower clad) 9, and the first electrode 55 above the second clad layer (upper clad) 13 in plan view.
  • a contact layer 56 having substantially the same size.
  • the functional substrate 51 includes a second electrode 57 on the lower surface 8 b of the current diffusion layer 8, and a transparent conductive film 52 and a reflective layer 53 are laminated so as to cover the second electrode 57.
  • the joining surface 50a of the metal substrate 50 is joined to the surface 53b on the opposite side of the compound semiconductor layer 2 of the reflecting layer 53 constituting the reflecting structure.
  • the reflective layer 53 is made of, for example, a metal such as copper, silver, gold, or aluminum, or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective structure can be 90% or more.
  • the reflective layer 53 By forming the reflective layer 53, the light from the active layer 11 is reflected by the reflective layer 53 in the front direction f, and the light extraction efficiency in the front direction f can be improved. Thereby, the brightness of the light emitting diode can be further increased.
  • the reflective layer 53 preferably has a laminated structure made of Ag, a Ni / Ti barrier layer, and an Au-based eutectic metal (connecting metal) from the transparent conductive film 52 side.
  • the connecting metal is a metal that has a low electrical resistance and melts at a low temperature. By using the connecting metal, the metal substrate can be connected without applying thermal stress to the compound semiconductor layer 2.
  • an Au-based eutectic metal that is chemically stable and has a low melting point is used.
  • the Au-based eutectic metal include eutectic compositions of alloys such as AuSn, AuGe, and AuSi (Au-based eutectic metal).
  • connection metal it is preferable to add a metal such as titanium, chromium, or tungsten to the connection metal.
  • a metal such as titanium, chromium, or tungsten
  • metals such as titanium, chromium, and tungsten can function as a barrier metal, and impurities contained in the metal substrate can be prevented from diffusing and reacting on the reflective layer 53 side.
  • the transparent conductive film 52 is composed of an ITO film, an IZO film, or the like.
  • the reflective structure may be composed of only the reflective layer 53.
  • a so-called cold mirror using a difference in refractive index of a transparent material for example, a multilayer film of titanium oxide film, silicon oxide film, white alumina, AlN May be combined with the reflective layer 53.
  • the metal substrate 50 can be made of a plurality of metal layers.
  • As the configuration of the plurality of metal layers it is preferable that two types of metal layers, that is, the first metal layer 50A and the second metal layer 50B are alternately stacked as in the example shown in FIG. In particular, it is more preferable that the first metal layer 50A and the second metal layer 50B have an odd number of layers.
  • the first metal layers 50A and 50A are more than the compound semiconductor layer 3. It is preferable to use a material made of a material having a large thermal expansion coefficient. Since the thermal expansion coefficient of the metal substrate as a whole is close to the thermal expansion coefficient of the compound semiconductor layer, it is possible to suppress warping and cracking of the metal substrate when the compound semiconductor layer and the metal substrate are joined, and the light emitting diode This is because the production yield can be improved.
  • the first metal layers 50A and 50A are made of a material having a smaller thermal expansion coefficient than the compound semiconductor layer 2. It is preferable to use it. Since the thermal expansion coefficient of the metal substrate as a whole is close to the thermal expansion coefficient of the compound semiconductor layer, it is possible to suppress warping and cracking of the metal substrate when joining the compound semiconductor layer and the metal substrate, and the production yield of light emitting diodes It is because it can improve. From the above viewpoint, any of the two types of metal layers may be the first metal layer or the second metal layer.
  • a preferred example is a metal substrate composed of three layers of Cu / Mo / Cu. From the above viewpoint, the same effect can be obtained with a metal substrate composed of three layers of Mo / Cu / Mo, but the metal substrate composed of three layers of Cu / Mo / Cu is a Cu layer that has high mechanical strength and is easy to process Mo. Therefore, there is an advantage that processing such as cutting is easier than a metal substrate composed of three layers of Mo / Cu / Mo.
  • the thermal expansion coefficient of the entire metal substrate is, for example, 6.1 ppm / K for a three-layer metal substrate of Cu (30 ⁇ m) / Mo (25 ⁇ m) / Cu (30 ⁇ m), and Mo (25 ⁇ m) / Cu (70 ⁇ m). In the case of a metal substrate composed of three layers of / Mo (25 ⁇ m), it is 5.7 ppm / K.
  • the metal layer constituting the metal substrate is preferably made of a material having high thermal conductivity. This is because the heat dissipation of the metal substrate can be increased, the light emitting diode can emit light with high brightness, and the life of the light emitting diode can be extended.
  • thermo conductivity 420 W / m ⁇ K
  • alloys thereof are preferably used.
  • the metal layers are made of a material having a thermal expansion coefficient substantially equal to that of the compound semiconductor layer.
  • the material of the metal layer is preferably a material having a thermal expansion coefficient that is within ⁇ 1.5 ppm / K of the thermal expansion coefficient of the compound semiconductor layer.
  • the thermal conductivity of the entire metal substrate is, for example, 250 W / m ⁇ K for a three-layer metal substrate of Cu (30 ⁇ m) / Mo (25 ⁇ m) / Cu (30 ⁇ m), and Mo (25 ⁇ m) / Cu (70 ⁇ m) / In the case of a metal substrate composed of three layers of Mo (25 ⁇ m), it is 220 W / m ⁇ K.
  • the light-emitting diode manufactured in this example is an infrared light-emitting diode having an active layer having a quantum well structure of a well layer made of InGaAs and a barrier layer made of AlGaInP.
  • a compound semiconductor layer grown on a GaAs substrate and a functional substrate were combined to produce a light emitting diode.
  • a light-emitting diode lamp having a light-emitting diode chip mounted on a substrate was prepared for characteristic evaluation.
  • Example 1 is an example of the embodiment shown in FIG.
  • an epitaxial wafer was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of an n-type GaAs single crystal doped with Si.
  • the plane inclined by 15 ° from the (100) plane in the (0-1-1) direction was used as the growth plane, and the carrier concentration was set to 2 ⁇ 10 18 cm ⁇ 3 .
  • an n-type buffer layer made of GaAs doped with Si As the compound semiconductor layer, an n-type buffer layer made of GaAs doped with Si, an n-type contact layer made of Si-doped (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P, Si N-type upper clad layer made of (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P, doped with (Al 0.3 Ga 0.7 ) 0.5 In 0.5 P Upper guide layer, well layer / barrier layer composed of three pairs of In 0.2 Ga 0.8 As / (Al 0.1 Ga 0.9 ) 0.5 In 0.5 P, (Al 0.3 Ga 0 .7) 0.5 in 0.5 lower guide layer made of P, doped with Mg (Al 0.7 Ga 0.3) p-type lower cladding layer composed of 0.5 in 0.5 P, (Al 0.5 Ga 0.5) an intermediate layer of a thin film made of 0.5 in 0.5 P, M Using current diffusion layer made of doped p-type Ga
  • a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 76 mm and a thickness of 350 ⁇ m by using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer.
  • MOCVD apparatus metal organic chemical vapor deposition apparatus method
  • trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga) and trimethylindium ((CH 3 ) 3 In) are used as the raw material for the group III constituent element did.
  • biscyclopentadienyl magnesium bis- (C 5 H 5 ) 2 Mg
  • disilane Si 2 H 6
  • phosphine PH 3
  • arsine As the growth temperature of each layer, the current diffusion layer made of p-type GaP was grown at 750 ° C. The other layers were grown at 700 ° C.
  • the buffer layer made of GaAs has a carrier concentration of about 2 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
  • the contact layer had a carrier concentration of about 2 ⁇ 10 18 cm ⁇ 3 and a layer thickness of 4 ⁇ m.
  • the upper cladding layer had a carrier concentration of about 1 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
  • the upper guide layer was undoped and had a thickness of about 50 nm.
  • the well layer is undoped In 0.2 Ga 0.8 As with a thickness of about 5 nm, and the barrier layer is undoped (Al 0.1 Ga 0.9 ) 0.5 In 0. 5 P.
  • Three pairs of well layers and barrier layers were alternately laminated.
  • the lower guide layer was undoped and had a thickness of about 50 nm.
  • the lower cladding layer had a carrier concentration of about 8 ⁇ 10 17 cm ⁇ 3 and a layer thickness of about 0.5 ⁇ m.
  • the intermediate layer had a carrier concentration of about 8 ⁇ 10 17 cm ⁇ 3 and a layer thickness of about 50 nm.
  • the current diffusion layer made of GaP has a carrier concentration of about 3 ⁇ 10 18 cm ⁇ 3 and a layer thickness of about 10 ⁇ m.
  • the current diffusion layer was polished to a region extending from the surface to a depth of about 1 ⁇ m and mirror-finished.
  • the surface roughness (rms) of the current diffusion layer was set to 0.18 nm.
  • a functional substrate made of n-type GaP to be attached to the mirror-polished surface of the current diffusion layer was prepared.
  • a single crystal having a plane orientation of (111) added with Si so that the carrier concentration was about 2 ⁇ 10 17 cm ⁇ 3 was used for the functional substrate for sticking.
  • the functional substrate had a diameter of 76 mm and a thickness of 250 ⁇ m.
  • the surface of this functional substrate was polished to a mirror surface before being bonded to the current spreading layer, and the surface roughness (rms) was finished to 0.12 nm.
  • the functional substrate and the epitaxial wafer were carried into a general semiconductor material sticking apparatus, and the inside of the apparatus was evacuated to 3 ⁇ 10 ⁇ 5 Pa.
  • the GaAs substrate and the GaAs buffer layer were selectively removed from the bonded wafer with an ammonia-based etchant.
  • a first electrode was formed on the surface of the contact layer by vacuum deposition so that the thickness of AuGe and Ni alloy was 0.5 ⁇ m, Pt was 0.2 ⁇ m, and Au was 1 ⁇ m.
  • patterning was performed using a general photolithography means, and an n-type ohmic electrode was formed as the first electrode.
  • the surface of the light extraction surface which is the surface from which the GaAs substrate was removed, was roughened.
  • the epi layer in the region where the p-type ohmic electrode is formed as the second electrode was selectively removed to expose the current diffusion layer.
  • a p-type ohmic electrode was formed on the exposed surface of the current diffusion layer by vacuum deposition so that AuBe was 0.2 ⁇ m and Au was 1 ⁇ m.
  • heat treatment was performed at 450 ° C. for 10 minutes to form an alloy, and low resistance p-type and n-type ohmic electrodes were formed.
  • Au was formed in a thickness of 0.2 ⁇ m on the back surface of the functional substrate, and a pattern was formed in a 220 ⁇ m square.
  • the region where the third electrode is not formed from the back surface of the functional substrate is set so that the angle ⁇ of the inclined surface becomes 70 ° and the thickness of the vertical surface becomes 80 ⁇ m.
  • a letter-shaped grooving was performed.
  • a dicing saw was used to cut from the compound semiconductor layer side at 350 ⁇ m intervals to form chips. The crushing layer and dirt by dicing were removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to produce a light emitting diode of Example 1.
  • 100 light-emitting diode lamps each having the light-emitting diode chip of Example 1 manufactured as described above mounted on a mount substrate were assembled.
  • the mount is supported (mounted) by a die bonder
  • the n-type ohmic electrode of the light-emitting diode and the n-electrode terminal provided on the surface of the mount substrate are wire-bonded with a gold wire
  • the p-type ohmic electrode and the p-type electrode are connected.
  • the electrode terminal was wire bonded with a gold wire and then sealed with a general epoxy resin.
  • Table 7 shows the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp). As shown in Table 7, when current was passed between the n-type and p-type ohmic electrodes, infrared light having a peak wavelength of 920 nm was emitted.
  • the forward voltage (Vf) when a current of 20 milliamperes (mA) flows in the forward direction is the low resistance at each junction interface between the current diffusion layer constituting the compound semiconductor layer and the functional substrate and each ohmic resistance. Reflecting the good ohmic characteristics of the electrode, it was about 1.22 volts. When the forward current was 20 mA, the light emission output was 7 mW.
  • Example 2 is an example of the second embodiment shown in FIGS. 14A and 14B.
  • the light emitting diode of Example 2 is a case where a reflective layer and a functional substrate are combined. Other light emitting portions are formed in the same manner as in the first embodiment.
  • the lower guide layer 10 and the upper guide layer 12 are not shown.
  • втори ⁇ ески ⁇ ⁇ ел ⁇ ⁇ ел ⁇ ⁇ ел ⁇ ⁇ ел ⁇ ⁇ о ⁇ е ⁇ ⁇ о ⁇ е ⁇ ⁇ е ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ m a transparent conductive film was formed by a sputtering method with a thickness of 0.4 ⁇ m.
  • a layer 23 made of silver alloy / Ti / Au was formed to a thickness of 0.2 ⁇ m / 0.1 ⁇ m / 1 ⁇ m to form a reflecting surface 23.
  • a layer 32 made of Ti / Au / In was formed on the surface of a silicon substrate (functional substrate) 31 with a thickness of 0.1 ⁇ m / 0.5 ⁇ m / 0.3 ⁇ m.
  • a layer 33 made of Ti / Au was formed on the back surface of the silicon substrate 31 with a thickness of 0.1 ⁇ m / 0.5 ⁇ m.
  • the Au on the light emitting diode wafer side and the In surface on the silicon substrate side were superposed and heated at 320 ° C. and pressurized at 500 g / cm 2 to bond the functional substrate to the light emitting diode wafer.
  • the GaAs substrate is removed, an AuGe / Au ohmic electrode (first electrode) 25 having a diameter of 100 ⁇ m and a thickness of 3 ⁇ m is formed on the surface of the contact layer 16, and heat-treated at 420 ° C. for 5 minutes, p, n The ohmic electrode was alloyed.
  • the surface of the contact layer 16 was roughened.
  • the semiconductor layer, the reflective layer, and the eutectic metal that were to be cut to be separated into chips were removed, and Ti / AuSn / Au was formed to 0.3 ⁇ m / 1 ⁇ m / 0.1 ⁇ m on the back electrode of the silicon substrate. Dicing saw cut into squares at a pitch of 350 ⁇ m.
  • Table 7 shows the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp). As shown in Table 7, when current was passed between the upper and lower electrodes, infrared light having a peak wavelength of 920 nm was emitted.
  • the forward voltage (Vf) when a current of 20 milliamperes (mA) flows in the forward direction is the low resistance at each junction interface between the current diffusion layer constituting the compound semiconductor layer and the functional substrate and each ohmic resistance. Reflecting the good ohmic characteristics of the electrode, it was about 1.20 volts (V).
  • the light emission output when the forward current was 20 mA was about 6 mW.
  • Table 7 shows the results of conducting an energization test (20 mA energization) for 1000 hours in a high-temperature and high-humidity environment at a temperature of 60 ° C. and a humidity of 90%, and measuring the residual ratio of light emission output.
  • 100 lamps were subjected to a high-temperature and high-humidity energization test at 60 ° C., 90 RH%, 20 mA. The average output remaining rate after 1000 hours was 99%.
  • Example 3 The light-emitting diode of Example 3 is an example of the third embodiment, and has a configuration in which a functional substrate including a reflective layer and a metal substrate is bonded to a current diffusion layer. With reference to FIG. 15, the light-emitting diode of Example 3 will be described.
  • a metal substrate was produced. Two substantially flat Cu plates with a thickness of 10 ⁇ m and one substantially flat Mo plate with a thickness of 75 ⁇ m are prepared, and the Mo plates are inserted between the two Cu plates and stacked. And the said board
  • Compound semiconductor layer between the buffer layer and the contact layer, made of (Al 0.5 Ga 0.5) 0.5 In 0.5 P doped with Si, layer thickness 0.5 ⁇ m of the etching stop layer It formed on the same conditions as Example 1 except the point formed.
  • Au having a thickness of 0.2 ⁇ m is laminated on AuBe having a thickness of 0.4 ⁇ m, and when viewed in plan, it has a circular shape of 20 ⁇ m ⁇ , with an interval of 60 ⁇ m.
  • a second electrode 57 was formed.
  • an ITO film 52 which is a transparent conductive film, was formed by sputtering to a thickness of 0.8 ⁇ m so as to cover the second electrode 57.
  • a film made of a silver (Ag) alloy is formed to 0.7 ⁇ m on the ITO film 52 by vapor deposition, and then a film made of nickel (Ni) / titanium (Ti) is made to 0.5 ⁇ m, gold A film made of (Au) was formed to a thickness of 1 ⁇ m to form a reflective film 53.
  • the structure in which the ITO film 52 and the reflective film 53 are formed on the current diffusion layer 8 of the compound semiconductor layer and the metal substrate are arranged so as to face each other and are carried into a decompression apparatus, and are brought to 400 ° C. In the state heated by, they were joined with a load of 500 kg to form a joined structure.
  • the GaAs substrate which is a growth substrate for the compound semiconductor layer, and the buffer layer were selectively removed from the bonded structure with an ammonia-based etchant, and the etching stop layer was selectively removed with a hydrochloric acid-based etchant.
  • AuGe is deposited on the contact layer to a thickness of 0.15 ⁇ m
  • Ni is deposited to a thickness of 0.05 ⁇ m
  • Au is further deposited to a thickness of 1 ⁇ m.
  • a first electrode conductive film was formed by film formation.
  • the electrode conductive film was patterned into a circular shape in plan view, and a first electrode 55 having a diameter of 100 ⁇ m and a thickness of 3 ⁇ m was produced.
  • the contact layer 56 was formed by etching away the portion of the contact layer except under the first electrode with an ammonia-based etchant.
  • the compound semiconductor layer, the reflective layer, and the eutectic metal to be cut to be separated into chips were removed, and the metal substrate was cut into squares at a pitch of 350 ⁇ m by laser dicing.
  • Table 7 shows the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp). As shown in Table 7, when current was passed between the n-type and p-type ohmic electrodes, infrared light having a peak wavelength of 920 nm was emitted.
  • the forward voltage (V F ) when a current of 20 milliamperes (mA) is passed in the forward direction is low in resistance at the junction interface between the current diffusion layer constituting the compound semiconductor layer and the functional substrate. Reflecting the good ohmic characteristics of the ohmic electrode, it was 1.2 volts.
  • the light emission output when the forward current was 20 mA was 5.9 mW. Twenty lamps were subjected to a high-temperature and high-humidity energization test at 60 ° C., 90 RH%, 20 mA. The average output remaining rate after 1000 hours was 100%.
  • Example 4 The light-emitting diode of Example 4 is an example of the first embodiment, and is manufactured under the same conditions as in Example 1 except that the In composition X1 of the well layer is set to 0.12 so that the emission peak wavelength is 870 nm. did.
  • the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 870 nm is emitted, and the light emission output (P 0 ) and the forward voltage (V F ). The average output residual ratios were 6.8 mW, 1.31 V, and 100%, respectively.
  • Example 5 The light-emitting diode of Example 5 is an example of the second embodiment, and is manufactured under the same conditions as Example 2 except that the In composition X1 of the well layer is set to 0.12 so that the emission peak wavelength is 870 nm. did.
  • the results of evaluating the characteristics of the light emitting diode are as shown in Table 7. Infrared light having a peak wavelength of 870 nm is emitted, and the light emission output (P 0 ) and the forward voltage (V F ). The average output residual ratio was 6.1 mW, 1.3 V, and 100%, respectively.
  • Example 6 The light-emitting diode of Example 6 is an example of the first embodiment, and is manufactured under the same conditions as Example 1 except that the In composition X1 of the well layer is set to 0.25 so that the emission peak wavelength is 960 nm. did.
  • the results of evaluating the characteristics of this light emitting diode are as shown in Table 7. Infrared light having a peak wavelength of 960 nm is emitted, and the light emission output (P 0 ) and forward voltage (V F ). The average output residual ratio was 6.5 mW, 1.2 V, and 99%, respectively.
  • Example 7 The light emitting diode of Example 7 is an example of the second embodiment, and is manufactured under the same conditions as Example 2 except that the In composition X1 of the well layer is set to 0.25 in order to set the emission peak wavelength to 960 nm. did.
  • the results of evaluating the characteristics of this light emitting diode are as shown in Table 7. Infrared light having a peak wavelength of 960 nm is emitted, and the light emission output (P 0 ) and forward voltage (V F ). The average output residual ratio was 5.3 mW, 1.2 V, and 99%, respectively.
  • Example 8 The light-emitting diode of Example 8 is an example of the first embodiment, and is manufactured under the same conditions as in Example 1 except that the In composition X1 of the well layer is set to 0.3 so that the emission peak wavelength is 985 nm. did.
  • the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 985 nm is emitted, and the light emission output (P 0 ) and forward voltage (V F ). The average output residual ratio was 5.0 mW, 1.2 V, and 99%, respectively.
  • Example 9 The light-emitting diode of Example 9 is an example of the second embodiment, and is manufactured under the same conditions as Example 2 except that the In composition X1 of the well layer is set to 0.3 so that the emission peak wavelength is 985 nm. did.
  • the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 985 nm is emitted, and the light emission output (P 0 ) and forward voltage (V F ). The average output residual ratio was 3.8 mW, 1.2 V, and 99%, respectively.
  • Example 10 The light-emitting diode of Example 10 is an example of the first embodiment, and the barrier layer is undoped and has a thickness of about 10 nm of (Al 0.1 Ga 0.9 ) 0.55 In 0.45 P. Moreover, it was produced under the same conditions as in Example 1 except that five pairs of well layers and barrier layers were alternately laminated.
  • the results of evaluating the characteristics of this light emitting diode are as shown in Table 7. Infrared light having a peak wavelength of 920 nm is emitted, and the light emission output (P 0 ) and forward voltage (V F ). The average output residual ratio was 7.0 mW, 1.24 V, and 99%, respectively.
  • Comparative Example 1 The light emitting diode of Comparative Example 1 was formed by a liquid phase epitaxial method which is a conventional technique. This is a light emitting diode having a double heterostructure light emitting portion having a light emitting layer of Al 0.01 Ga 0.99 As on a GaAs substrate.
  • the light-emitting diode of Comparative Example 1 was prepared by forming an n-type (100) GaAs single crystal substrate with an n-type upper cladding layer having an interface composition of Al 0.2 Ga 0.8 As of 50 ⁇ m. 20 ⁇ m of Si-doped light-emitting layer made of Al 0.03 Ga 0.97 As, 20 ⁇ m of p-type lower cladding layer made of Al 0.1 Ga 0.9 As, transparent to the emission wavelength . A p-type thick film layer made of 25 Ga 0.75 As was prepared by a liquid phase epitaxial method so as to be 60 ⁇ m. After this epitaxial growth, the GaAs substrate was removed.
  • an n-type ohmic electrode having a diameter of 100 ⁇ m was formed on the surface of the n-type AlGaAs upper cladding layer.
  • p-type ohmic electrodes having a diameter of 20 ⁇ m were formed on the back surface of the p-type AlGaAs thick film layer at intervals of 80 ⁇ m and heat-treated at 420 ° C. for 5 minutes to alloy the p and n ohmic electrodes.
  • the crushed layer was removed by etching, and the surface was roughened for high output to produce a light emitting diode chip of Comparative Example 1.
  • Table 7 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 1 was mounted.
  • Table 7 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 1 was mounted.
  • V F forward voltage
  • V F light emission output when the forward current was 20 mA was 2 mW.
  • the output of any sample of Comparative Example 1 was lower than that of the example of the present invention.
  • Table 1 shows the results of conducting a current test (20 mA power supply) for 500 hours in a high temperature and high humidity environment at a temperature of 60 ° C. and a humidity of 90%, and measuring the residual rate of light emission output.
  • the cause of the decrease in output is thought to be that light absorption increased due to corrosion of the AlGaAs surface.
  • 100 lamps were subjected to a high-temperature and high-humidity energization test at 60 ° C., 90 RH%, 20 mA.
  • the average of the remaining power after 500 hours was 14% lower than that at the start of the experiment, and was significantly lower than that of the example in which the decrease was only within 1%.
  • the light-emitting diode of the present invention can be used as a light-emitting diode product that emits infrared light having an emission peak wavelength of 850 nm or more, particularly 900 nm or more with high output and high efficiency.
  • SYMBOLS 1 Light emitting diode 2 ... Compound semiconductor layer 3 ... Functional board
  • Light emitting diode 21 Electrode 22 ; Transparent conductive film 23 ... Reflecting surface 25 ... Bonding electrode 30 ; Silicon substrate 31 ⁇ ⁇ Functional substrate ⁇ ⁇ ⁇ ⁇ An angle between the inclined surface and a plane parallel to the light emitting surface 50 .Metal substrate 51... Functional substrate 52 ..Transparent conductive film 53. .... First electrode 56 ... Contact layer 57 ... Second electrode

Abstract

Disclosed is a light-emitting diode provided with an active layer with a quantum well structure obtained by alternately laminating a well layer having the composition (InX1Ga１－X1)As(0≦X1≦1) and a barrier layer having the composition (AlX2Ga１－X2)Y1In1-Y1P(0≦X2≦1, 0<Y1≦1); a first guide and second guide which have the following composition (AlX3Ga1-X3)Y2In1-Y2P (0≦X3≦1, 0 < Y2 ≦1), and which sandwich said active layer; a light-emitting section having a first cladding layer and a second cladding layer which sandwich the active layer, with the first guide and second guide interposed therebetween; a current diffusion layer formed on the light-emitting section; and a functional substrate bonded to the current diffusion layer. The first and second cladding layer have the following composition:(AlX4Ga1-X4)Y3In1-Y3P;0≦X4≦1, 0＜Y3≦1).

Description

発光ダイオード、発光ダイオードランプ及び照明装置Light emitting diode, light emitting diode lamp, and lighting device
　本発明は、８５０ｎｍ以上、特に９００ｎｍ以上の発光ピーク波長を有する発光ダイオードと、それを用いた発光ダイオードランプ及び照明装置に関する。
　本願は、２０１０年１月２５日に日本国に出願された特願２０１０－０１３５３０号、２０１０年８月１８日に日本国出願された特願２０１０－１８３２０５号に基づき優先権を主張し、その内容をここに援用する。 The present invention relates to a light emitting diode having an emission peak wavelength of 850 nm or more, particularly 900 nm or more, and a light emitting diode lamp and an illumination device using the light emitting diode.
This application claims priority based on Japanese Patent Application No. 2010-013530 filed in Japan on January 25, 2010 and Japanese Patent Application No. 2010-183205 filed on August 18, 2010 in Japan. The contents are incorporated herein.
　赤外発光ダイオードは、赤外線通信、赤外線リモコン装置、各種センサー用光源、夜間照明など幅広く利用されている。
かかるピーク波長近傍については、ＧａＡｓ基板にＡｌＧａＡｓ活性層を含む化合物半導体層を液相エピタキシャル法で成長させた発光ダイオードが知られている（例えば特許文献１～３）、成長基板として用いたＧａＡｓ基板を除去し、その化合物半導体層を発光波長に対して透明な成長層だけで構成した、いわゆる基板除去型発光ダイオードが、現状で最も高出力の赤外発光ダイオードである（例えば特許文献４）。
一方、機器間の送受信に用いられる赤外線通信の場合には、例えば、８５０～９００ｎｍの赤外線が用いられ、赤外線リモコン操作通信の場合には、受光部の感度が高い波長帯である、例えば８８０～９４０ｎｍの赤外線が用いられている。赤外線通信と赤外線リモコン操作通信の両機能を兼ね備えた携帯電話等の端末機器用の赤外線通信と赤外線リモコン操作通信の双方に使用できる赤外発光ダイオードとして、発光ピーク波長が８８０～８９０ｎｍの、実効的不純物としてＧｅを含むＡｌＧａＡｓ活性層を用いるものが知られている（特許文献４）。
　また、９００ｎｍ以上の発光ピーク波長を有し得る赤外発光ダイオードとして、ＩｎＧａＡｓ活性層を用いるものが知られている（特許文献５～７）。 Infrared light emitting diodes are widely used for infrared communication, infrared remote control devices, light sources for various sensors, night illumination, and the like.
In the vicinity of such a peak wavelength, a light emitting diode is known in which a compound semiconductor layer including an AlGaAs active layer is grown on a GaAs substrate by liquid phase epitaxy (for example, Patent Documents 1 to 3), and a GaAs substrate used as a growth substrate. A so-called substrate-removed light-emitting diode in which the compound semiconductor layer is composed of only a growth layer that is transparent to the emission wavelength is the highest output infrared light-emitting diode at present (for example, Patent Document 4).
On the other hand, in the case of infrared communication used for transmission / reception between devices, for example, infrared light of 850 to 900 nm is used, and in the case of infrared remote control operation communication, the wavelength band in which the sensitivity of the light receiving unit is high, for example, 880 to 900 nm. An infrared ray of 940 nm is used. As an infrared light emitting diode that can be used for both infrared communication and infrared remote control operation communication for mobile phones and other terminal devices that have both infrared communication and infrared remote control operation communication, it has an effective peak emission wavelength of 880 to 890 nm. One using an AlGaAs active layer containing Ge as an impurity is known (Patent Document 4).
In addition, as an infrared light emitting diode that can have an emission peak wavelength of 900 nm or more, one using an InGaAs active layer is known (Patent Documents 5 to 7).
特開平６－２１５０７号公報JP-A-6-21507 特開２００１－２７４４５４号公報JP 2001-274454 A 特開平７－３８１４８号公報Japanese Unexamined Patent Publication No. 7-38148 特開２００６－１９０７９２号公報JP 2006-190792 A 特開２００２－２６３７７号公報JP 2002-26377 A 特開２００２－１１１０４８号公報JP 2002-111048 A 特開２００２－３４４０１３号公報JP 2002-344013 A
　しかしながら、出願人の知る限り、８５０ｎｍ以上、特に９００ｎｍ以上の赤外発光ダイオードについて、出力を向上させるために、機能性基板をエピタキシャルウェーハに貼り付け（接合し）、成長に用いたＧａＡｓ基板を除去する所謂接合型のタイプはない。
　また、実効的不純物にＧｅを含むＡｌＧａＡｓ活性層を用いた場合、発光ピーク波長を９００ｎｍ以上にすることは困難である（特許文献４の図３）。
　また、９００ｎｍ以上の発光ピーク波長を有し得る、ＩｎＧａＡｓ活性層を用いた赤外発光ダイオードについては、更なる性能向上、省エネ、コスト面から、より発光効率の高いものの開発が望まれている。 However, as far as the applicant knows, in order to improve the output of infrared light emitting diodes of 850 nm or more, particularly 900 nm or more, a functional substrate is attached (bonded) to the epitaxial wafer and the GaAs substrate used for growth is removed. There is no so-called junction type.
Further, when an AlGaAs active layer containing Ge as an effective impurity is used, it is difficult to set the emission peak wavelength to 900 nm or more (FIG. 3 of Patent Document 4).
In addition, for an infrared light emitting diode using an InGaAs active layer that can have an emission peak wavelength of 900 nm or more, development of a higher light emitting efficiency is desired from the viewpoint of further performance improvement, energy saving, and cost.
　本発明は、上記事情を鑑みてなされたものであり、高出力・高効率で８５０ｎｍ以上、特に９００ｎｍ以上の発光ピーク波長の赤外光を発光する赤外発光ダイオードと、それを用いてなる発光ダイオードランプ及び照明装置を提供することを目的とする。 The present invention has been made in view of the above circumstances, and an infrared light-emitting diode that emits infrared light having an emission peak wavelength of 850 nm or more, particularly 900 nm or more with high output and high efficiency, and light emission using the same. An object of the present invention is to provide a diode lamp and a lighting device.
　本発明者は、上記課題を解決するために鋭意研究を重ねた結果、ＩｎＧａＡｓからなる井戸層とし、ＡｌＧａＩｎＰからなるバリア層とする多重量子井戸構造を活性層とし、ＡｌＧａＩｎＰからなるガイド層を介して活性層を挟む、クラッド層を４元混晶のＡｌＧａＩｎＰとすると共に、活性層、ガイド層及びクラッド層を含む化合物半導体層を成長基板にエピタキシャル成長させた後、化合物半導体層を透明基板に改めて貼り付け（接合して）、その成長基板を除去する構成とすることにより、高出力・高効率で８５０ｎｍ以上、特に９００ｎｍ以上の発光ピーク波長の赤外光を発光する赤外発光ダイオードを完成させた。
　まず、本発明者は、赤外線通信等に用いられる８５０ｎｍ以上、特に９００ｎｍ以上の発光ピーク波長を有するようにＩｎＧａＡｓからなる井戸層を採用し、単色性及び出力を高めるために多重量子井戸構造の活性層とした。
　また、この３元混晶の井戸層を挟むバリア層、及び前記井戸層、バリア層を含む多重量子井戸構造を挟むガイド層及びクラッド層にも、バンドギャップが大きくて発光波長に対して透明であり、かつ、欠陥を作りやすいＡｓを含まないので結晶性の良い４元混晶のＡｌＧａＩｎＰを採用した。
　さらにＩｎＧａＡｓ層を井戸層とする多重量子井戸構造は、成長基板として用いるＧａＡｓに比較し格子定数が大きくひずみ量子井戸構造となる。かかるひずみ量子井戸構造ではＩｎＧａＡｓの組成及び厚さの出力や単色性への影響も大きく、適切な組成、厚さおよびペア数の選択が重要となる。そこで、バリア層のＡｌＧａＩｎＰにＩｎＧａＡｓ井戸層とは逆のひずみを追加して、ＩｎＧａＡｓのペア数増加による格子不整を量子井戸構造全体で緩和することにより、高電流域での発光出力特性が改善されることを見出した。
　また、上記の通り、従来、ＩｎＧａＡｓ系の活性層を用いる赤外発光ダイオードにおいては、この活性層を含む化合物半導体層を透明基板に貼り付ける（接合する）タイプはなく、化合物半導体層を成長させたＧａＡｓ基板をそのまま用いていた。しかし、ＧａＡｓ基板は伝導性を高めるために高ドープしており、キャリアによる光の吸収が避けられない。そこで、キャリアによる光の吸収を回避でき、高出力・高効率が期待できる透明基板に貼り付ける（接合する）タイプを採用した。
　特に、接合型の場合、機能性基板からの応力の影響もあり、前記ひずみ量子井戸構造の最適化を含めた素子の構造設計が重要である。
　本発明者は、かかる知見に基づいてさらに研究を進めた結果、以下の構成に示す本発明を完成するに至った。 As a result of intensive research to solve the above problems, the present inventor has a multi-quantum well structure having a well layer made of InGaAs and a barrier layer made of AlGaInP as an active layer, and through a guide layer made of AlGaInP. The active layer is sandwiched between the quaternary mixed crystal AlGaInP and the compound semiconductor layer including the active layer, the guide layer, and the cladding layer is epitaxially grown on the growth substrate, and then the compound semiconductor layer is pasted on the transparent substrate again. An infrared light emitting diode that emits infrared light having an emission peak wavelength of 850 nm or more, particularly 900 nm or more with high output and high efficiency was completed by adopting a configuration in which the growth substrate was removed (bonded).
First, the present inventor adopts a well layer made of InGaAs so as to have an emission peak wavelength of 850 nm or more, particularly 900 nm or more, which is used for infrared communication or the like. Layered.
Further, the barrier layer sandwiching the ternary mixed crystal well layer, and the guide layer and the cladding layer sandwiching the multiple quantum well structure including the well layer and the barrier layer also have a large band gap and are transparent to the emission wavelength. Since it does not contain As, which is easy to make defects, quaternary mixed crystal AlGaInP having good crystallinity was adopted.
Furthermore, the multiple quantum well structure in which the InGaAs layer is a well layer has a strained quantum well structure having a larger lattice constant than GaAs used as a growth substrate. In such a strained quantum well structure, the influence of the composition and thickness of InGaAs on the output and monochromaticity is large, and selection of an appropriate composition, thickness, and number of pairs is important. Therefore, by adding a strain opposite to that of the InGaAs well layer to the AlGaInP barrier layer, the lattice irregularity due to the increase in the number of InGaAs pairs is alleviated throughout the quantum well structure, thereby improving the light emission output characteristics in the high current region. I found out.
Further, as described above, in the conventional infrared light emitting diode using an InGaAs-based active layer, there is no type in which the compound semiconductor layer including the active layer is attached (bonded) to the transparent substrate, and the compound semiconductor layer is grown. The GaAs substrate was used as it was. However, the GaAs substrate is highly doped to increase conductivity, and absorption of light by carriers is inevitable. Therefore, we adopted a type that can be affixed (bonded) to a transparent substrate that can avoid light absorption by the carrier and can be expected to have high output and high efficiency.
In particular, in the case of the junction type, there is an influence of stress from the functional substrate, and thus the element structure design including the optimization of the strain quantum well structure is important.
As a result of further research based on this knowledge, the present inventor has completed the present invention shown in the following configuration.
　本発明は、以下の構成を提供する。
（１）組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層と組成式（ＡｌＸ２Ｇａ１－Ｘ２）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ２≦１，０＜Ｙ１≦１）からなるバリア層とを交互に積層した量子井戸構造の活性層と、該活性層を挟む、組成式（ＡｌＸ３Ｇａ１－Ｘ３）Ｙ２Ｉｎ１－Ｙ２Ｐ（０≦Ｘ３≦１，０＜Ｙ２≦１）からなる第１のガイド及び第２のガイドと、該第１のガイド及び第２のガイドのそれぞれを介して前記活性層を挟む第１のクラッド層及び第２のクラッド層とを有する発光部と、前記発光部上に形成された電流拡散層と、前記電流拡散層に接合された機能性基板と、を備え、前記第１及び第２のクラッド層が組成式（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ３Ｉｎ１－Ｙ３Ｐ（０≦Ｘ４≦１，０＜Ｙ３≦１）からなることを特徴とする発光ダイオード。
（２）前記井戸層のＩｎ組成（Ｘ１）が０≦Ｘ１≦０．３であることを特徴とする前項（１）に記載の発光ダイオード。
（３）前記井戸層のＩｎ組成（Ｘ１）が０．１≦Ｘ１≦０．３であることを特徴とする前項（２）に記載の発光ダイオード。
（４）前記バリア層の組成Ｘ２及びＹ１がそれぞれ、０≦Ｘ２≦０．２，０．５＜Ｙ１≦０．７であり、前記第１及び第２のガイドの組成Ｘ３及びＹ２がそれぞれ、０．２≦Ｘ３≦０．５，０．４＜Ｙ２≦０．６であり、前記第１及び第２のクラッド層の組成Ｘ４及びＹ３がそれぞれ、０．３≦Ｘ４≦０．７，０．４＜Ｙ３≦０．６であることを特徴とする前項（１）乃至（３）のいずれか一項に記載の発光ダイオード。
（５）前記機能性基板は発光波長に対して透明であることを特徴とする前項（１）乃至（４）のいずれか一項に記載の発光ダイオード。
（６）前記機能性基板はＧａＰ又はＳｉＣからなることを特徴とする前項（１）乃至（５）のいずれか一項に記載の発光ダイオード。
（７）前記機能性基板の側面は、前記発光部に近い側においては主たる光取り出し面に対して略垂直である垂直面を有し、前記発光部に遠い側においては前記主たる光取り出し面に対して内側に傾斜した傾斜面を有することを特徴とする前項（１）乃至（６）のいずれか一項に記載の発光ダイオード。
（８）前記傾斜面は粗い面を含むことを特徴とする前項（７）に記載の発光ダイオード。
（９）組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層と組成式（ＡｌＸ２Ｇａ１－Ｘ２）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ２≦１，０＜Ｙ１≦１）からなるバリア層とを交互に積層した量子井戸構造の活性層と、該活性層を挟む、組成式（ＡｌＸ３Ｇａ１－Ｘ３）Ｙ２Ｉｎ１－Ｙ２Ｐ（０≦Ｘ３≦１，０＜Ｙ２≦１）からなる第１のガイド及び第２のガイドと、該第１のガイド及び第２のガイドのそれぞれを介して前記活性層を挟む第１のクラッド層及び第２のクラッド層とを有する発光部と、前記発光部上に形成された電流拡散層と、前記発光部に対向して配置され、発光波長に対して９０％以上の反射率を有する反射層を含み、前記電流拡散層に接合された機能性基板と、を備え、前記第１及び第２のクラッド層が組成式（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ３Ｉｎ１－Ｙ３Ｐ（０≦Ｘ４≦１，０＜Ｙ３≦１）からなることを特徴とする発光ダイオード。
　ここで、「接合」は、さらに、電流拡散層と機能性基板との間の層を介して接合する場合も含む。
（１０）前記井戸層のＩｎ組成（Ｘ１）が０≦Ｘ１≦０．３であることを特徴とする前項（９）に記載の発光ダイオード。
（１１）前記井戸層のＩｎ組成（Ｘ１）が０．１≦Ｘ１≦０．３であることを特徴とする前項（１０）に記載の発光ダイオード。
（１２）前記バリア層の組成Ｘ２及びＹ１がそれぞれ、０≦Ｘ２≦０．２，０．５＜Ｙ１≦０．７であり、前記第１及び第２のガイドの組成Ｘ３及びＹ２がそれぞれ、０．２≦Ｘ３≦０．５，０．４＜Ｙ２≦０．６であり、前記第１及び第２のクラッド層の組成Ｘ４及びＹ３がそれぞれ、０．３≦Ｘ４≦０．７，０．４＜Ｙ３≦０．６であることを特徴とする前項（９）乃至（１１）のいずれか一項に記載の発光ダイオード。
（１３）前記機能性基板はシリコンまたはゲルマニウムからなる層を含むことを特徴とする前項（９）乃至（１２）のいずれか一項に記載の発光ダイオード。
（１４）前記機能性基板は金属基板を含むことを特徴とする前項（９）乃至（１２）のいずれか一項に記載の発光ダイオード。
（１５）前記金属基板は複数の金属層からなることを特徴とする前項（１４）に記載の発光ダイオード。
（１６）前記電流拡散層はＧａＰ又はＧａＩｎＰからなることを特徴とする前項（１）乃至（１５）のいずれか一項に記載の発光ダイオード。
（１７）前記電流拡散層の厚さは０．５～２０μｍの範囲であることを特徴とする前項（１）乃至（１６）のいずれか一項に記載の発光ダイオード。
（１８）第１の電極及び第２の電極が発光ダイオードの前記主たる光取り出し面側に設けられていることを特徴とする前項（１）乃至（１７）のいずれか一項に記載の発光ダイオード。
（１９）前記第１の電極及び前記第２の電極がオーミック電極であることを特徴とする前項（１８）に記載の発光ダイオード。
（２０）前記機能性基板の、前記主たる光取り出し面側の反対側の面に、第３の電極をさらに備えることを特徴とする前項（１８）又は（１９）のいずれかに記載の発光ダイオード。
（２１）前項（１）乃至（２０）のいずれか一項に記載の発光ダイオードを備えることを特徴とする発光ダイオードランプ。
（２２）前項（２０）に記載の発光ダイオードを備え、前記第１の電極又は第２の電極と、前記第３の電極とが略同電位に接続されていることを特徴とする発光ダイオードランプ。
（２３）前項（１）乃至（２０）のいずれか一項に記載の発光ダイオード、及び／又は、前項（２１）又は（２２）の少なくともいずれかに記載の発光ダイオードランプを複数個搭載した照明装置。 The present invention provides the following configurations.
(1) Well layer composed of composition formula (In X1 Ga 1-X1 ) As (0 ≦ X1 ≦ 1) and composition formula (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ≦ X2 ≦ 1,0) An active layer having a quantum well structure in which barrier layers made of <Y1 ≦ 1) are alternately stacked, and a composition formula (Al X3 Ga 1-X3 ) Y2 In 1-Y2 P (0 ≦ X3 ≦) sandwiching the active layer 1 and 0 <Y2 ≦ 1), and a first cladding layer and a second guide sandwiching the active layer through the first guide and the second guide, respectively. A light emitting portion having a cladding layer; a current diffusion layer formed on the light emitting portion; and a functional substrate bonded to the current diffusion layer, wherein the first and second cladding layers have a composition formula (Al X4 Ga 1-X4 ) Y3 In 1-Y3 P (0 ≦ X4 ≦ 1,0 <Y 3. A light emitting diode comprising 3 ≦ 1).
(2) The light-emitting diode as described in (1) above, wherein the In composition (X1) of the well layer is 0 ≦ X1 ≦ 0.3.
(3) The light-emitting diode according to item (2), wherein the In composition (X1) of the well layer is 0.1 ≦ X1 ≦ 0.3.
(4) The compositions X2 and Y1 of the barrier layer are 0 ≦ X2 ≦ 0.2 and 0.5 <Y1 ≦ 0.7, respectively, and the compositions X3 and Y2 of the first and second guides are respectively 0.2 ≦ X3 ≦ 0.5, 0.4 <Y2 ≦ 0.6, and the compositions X4 and Y3 of the first and second cladding layers are 0.3 ≦ X4 ≦ 0.7, 0, respectively. 4 <Y3 ≦ 0.6, The light-emitting diode according to any one of the above items (1) to (3).
(5) The light-emitting diode according to any one of (1) to (4), wherein the functional substrate is transparent to an emission wavelength.
(6) The light-emitting diode according to any one of (1) to (5), wherein the functional substrate is made of GaP or SiC.
(7) The side surface of the functional substrate has a vertical surface that is substantially perpendicular to the main light extraction surface on the side close to the light emitting unit, and the main light extraction surface on the side far from the light emitting unit. The light-emitting diode according to any one of (1) to (6), wherein the light-emitting diode has an inclined surface inclined inward.
(8) The light-emitting diode according to (7), wherein the inclined surface includes a rough surface.
(9) Well layer composed of composition formula (In X1 Ga 1-X1 ) As (0 ≦ X1 ≦ 1) and composition formula (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ≦ X2 ≦ 1,0) An active layer having a quantum well structure in which barrier layers made of <Y1 ≦ 1) are alternately stacked, and a composition formula (Al X3 Ga 1-X3 ) Y2 In 1-Y2 P (0 ≦ X3 ≦) sandwiching the active layer 1 and 0 <Y2 ≦ 1), and a first cladding layer and a second guide sandwiching the active layer through the first guide and the second guide, respectively. A light emitting part having a cladding layer, a current diffusion layer formed on the light emitting part, a reflective layer disposed opposite to the light emitting part and having a reflectance of 90% or more with respect to the emission wavelength, A functional substrate bonded to the current spreading layer, and the first and second Rudd layer composition formula (Al X4 Ga 1-X4) Y3 In 1-Y3 P (0 ≦ X4 ≦ 1,0 <Y3 ≦ 1) light emitting diode, comprising the.
Here, “bonding” further includes the case of bonding through a layer between the current diffusion layer and the functional substrate.
(10) The light-emitting diode as described in (9) above, wherein the In composition (X1) of the well layer is 0 ≦ X1 ≦ 0.3.
(11) The light-emitting diode as described in (10) above, wherein an In composition (X1) of the well layer is 0.1 ≦ X1 ≦ 0.3.
(12) The compositions X2 and Y1 of the barrier layer are 0 ≦ X2 ≦ 0.2 and 0.5 <Y1 ≦ 0.7, respectively, and the compositions X3 and Y2 of the first and second guides are respectively 0.2 ≦ X3 ≦ 0.5, 0.4 <Y2 ≦ 0.6, and the compositions X4 and Y3 of the first and second cladding layers are 0.3 ≦ X4 ≦ 0.7, 0, respectively. 4 <Y3 ≦ 0.6, The light-emitting diode according to any one of (9) to (11) above.
(13) The light-emitting diode according to any one of (9) to (12), wherein the functional substrate includes a layer made of silicon or germanium.
(14) The light-emitting diode according to any one of (9) to (12), wherein the functional substrate includes a metal substrate.
(15) The light-emitting diode according to (14), wherein the metal substrate includes a plurality of metal layers.
(16) The light-emitting diode according to any one of (1) to (15), wherein the current diffusion layer is made of GaP or GaInP.
(17) The light-emitting diode according to any one of (1) to (16), wherein the current diffusion layer has a thickness in a range of 0.5 to 20 μm.
(18) The light-emitting diode according to any one of (1) to (17), wherein the first electrode and the second electrode are provided on the main light extraction surface side of the light-emitting diode. .
(19) The light-emitting diode according to (18), wherein the first electrode and the second electrode are ohmic electrodes.
(20) The light-emitting diode according to any one of (18) and (19) above, further comprising a third electrode on a surface opposite to the main light extraction surface side of the functional substrate. .
(21) A light-emitting diode lamp comprising the light-emitting diode according to any one of (1) to (20).
(22) A light-emitting diode lamp comprising the light-emitting diode according to (20), wherein the first electrode or the second electrode and the third electrode are connected to substantially the same potential. .
(23) Illumination equipped with a plurality of light emitting diodes according to any one of (1) to (20) and / or at least one of the light emitting diode lamps according to (21) or (22). apparatus.
　なお、本発明において、「機能性基板」とは、成長基板に化合物半導体層を成長させた後にその成長基板を除去し、電流拡散層を介して化合物半導体層に接合して化合物半導体層を支持する基板をいうが、電流拡散層に所定の層を形成した後に、その所定の層の上に所定の基板を接合する構成の場合は、その所定の層を含めて「機能性基板」という。 In the present invention, the term “functional substrate” means that after growing a compound semiconductor layer on a growth substrate, the growth substrate is removed and bonded to the compound semiconductor layer via a current diffusion layer to support the compound semiconductor layer. When a predetermined layer is formed on the current diffusion layer and then a predetermined substrate is bonded onto the predetermined layer, the substrate including the predetermined layer is referred to as a “functional substrate”.
　上記の構成によれば、以下の効果を得る。
　高出力・高効率で８５０ｎｍ以上、特に９００ｎｍ以上の発光ピーク波長の赤外光を発光することができる。
　活性層が組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層と組成式（ＡｌＸ２Ｇａ１－Ｘ２）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ２≦１，０＜Ｙ１≦１）からなるバリア層とを交互に積層した多重井戸構造を有する構成なので、単色性に優れている。
　機能性基板を発光波長に対して透明のものとする構成により、発光部からの発光を吸収することなく高出力・高効率を示すことができる。
　バリア層、ガイド層、クラッド層が組成式（ＡｌＸＧａ１－Ｘ）ＹＩｎ１－ＹＰ（０≦Ｘ≦１，０＜Ｙ≦１）からなる構成なので、欠陥を作りやすいＡｓを含まないため結晶性が高く、高出力に寄与する。
　バリア層、ガイド層、クラッド層が組成式（ＡｌＸＧａ１－Ｘ）ＹＩｎ１－ＹＰ（０≦Ｘ≦１，０＜Ｙ≦１）からなる構成なので、バリア層、ガイド層、クラッド層が３元混晶からなる赤外発光ダイオードに比べてと比べてＡｌ濃度が低く、耐湿性が向上する。
　活性層が組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層と組成式（ＡｌＸ２Ｇａ１－Ｘ２）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ２≦１，０＜Ｙ１≦１）からなるバリア層との積層構造を有する構成なので、ＭＯＣＶＤ法を利用して量産するのに適している。 According to said structure, the following effects are acquired.
Infrared light having an emission peak wavelength of 850 nm or more, particularly 900 nm or more can be emitted with high output and high efficiency.
The active layer is a well layer having the composition formula (In X1 Ga 1-X1 ) As (0 ≦ X1 ≦ 1) and the composition formula (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ≦ X2 ≦ 1,0) Since it has a multi-well structure in which barrier layers made of <Y1 ≦ 1) are alternately laminated, the monochromaticity is excellent.
With the configuration in which the functional substrate is transparent with respect to the emission wavelength, high output and high efficiency can be exhibited without absorbing light emitted from the light emitting portion.
Since the barrier layer, the guide layer, and the clad layer are composed of the composition formula (Al X Ga 1-X ) Y In 1-YP (0 ≦ X ≦ 1, 0 <Y ≦ 1), it contains As that easily creates defects. Since it has no crystallinity, it contributes to high output.
Since the barrier layer, the guide layer, and the cladding layer have a composition formula (Al X Ga 1-X ) Y In 1-YP (0 ≦ X ≦ 1, 0 <Y ≦ 1), the barrier layer, the guide layer, and the cladding layer Compared with an infrared light emitting diode whose layer is composed of a ternary mixed crystal, the Al concentration is low, and the moisture resistance is improved.
The active layer is a well layer having the composition formula (In X1 Ga 1-X1 ) As (0 ≦ X1 ≦ 1) and the composition formula (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ≦ X2 ≦ 1,0) Since it has a laminated structure with a barrier layer made of <Y1 ≦ 1), it is suitable for mass production using the MOCVD method.
　化合物半導体層の成長基板として用いたＧａＡｓ基板を用いた場合、組成式（ＡｌＸ２Ｇａ１－Ｘ２）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ２≦１，０＜Ｙ１≦１）からなるバリア層の組成Ｘ２及びＹ１をそれぞれ、０≦Ｘ２≦０．２，０．５＜Ｙ１≦０．７にとった構成とすることにより、ＧａＡｓ基板に対する井戸層のひずみを緩和して結晶性の低下を抑制できる。 When a GaAs substrate used as a growth substrate for a compound semiconductor layer is used, a barrier layer having a composition formula (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1) The composition X2 and Y1 are set to satisfy 0 ≦ X2 ≦ 0.2 and 0.5 <Y1 ≦ 0.7, respectively, thereby relaxing the strain of the well layer with respect to the GaAs substrate and suppressing the decrease in crystallinity. it can.
　機能性基板をＧａＰ、ＳｉＣ、シリコン、又はゲルマニウムからなる構成とすることにより、発光部と熱膨張係数が近い為、応力を低減できる。また、腐食しにくい材質である為、耐湿性が向上する。
　機能性基板と電流拡散層とをいずれもＧａＰからなる構成とすることにより、その接合が容易としかつ接合強度が大きくすることができる。 Since the functional substrate is made of GaP, SiC, silicon, or germanium, the thermal expansion coefficient is close to that of the light emitting portion, so that stress can be reduced. Moreover, since it is a material which does not corrode easily, moisture resistance improves.
When both the functional substrate and the current diffusion layer are made of GaP, the bonding can be facilitated and the bonding strength can be increased.
　電流拡散層をＧａＩｎＰからなる構成とすることにより、ＩｎＧａＡｓ井戸層と格子整合させて、結晶性を向上させることができる。 When the current diffusion layer is made of GaInP, the crystallinity can be improved by lattice matching with the InGaAs well layer.
　本発明の発光ダイオードランプは、８５０ｎｍ以上、特に９００ｎｍ以上の発光ピーク波長を有することができ、単色性に優れると共に、高出力・高効率であって耐湿性に優れた上記発光ダイオードを備えているため、センサー用途等、幅広い用途の光源に適している。 The light-emitting diode lamp of the present invention has an emission peak wavelength of 850 nm or more, particularly 900 nm or more, and is provided with the light-emitting diode having excellent monochromaticity, high output, high efficiency, and excellent moisture resistance. Therefore, it is suitable for light sources for a wide range of applications such as sensor applications.
本発明の一実施形態である発光ダイオードを用いた発光ダイオードランプの平面図である。It is a top view of the light emitting diode lamp using the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態である発光ダイオードを用いた発光ダイオードランプの、図１中に示すＡ－Ａ’線に沿った断面模式図である。FIG. 2 is a schematic cross-sectional view taken along line A-A ′ shown in FIG. 1 of a light-emitting diode lamp using a light-emitting diode according to an embodiment of the present invention. 本発明の一実施形態である発光ダイオードの平面図である。It is a top view of the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態である発光ダイオードの、図３中に示すＢ－Ｂ’線に沿った断面模式図である。FIG. 4 is a schematic cross-sectional view of the light emitting diode according to the embodiment of the present invention, taken along line B-B ′ shown in FIG. 3. 本発明の一実施形態である発光ダイオードを構成する活性層を説明するための図である。It is a figure for demonstrating the active layer which comprises the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態である発光ダイオードの井戸層の層厚と発光ピーク波長との相関を示すグラフである。It is a graph which shows the correlation with the layer thickness of the well layer of the light emitting diode which is one Embodiment of this invention, and the light emission peak wavelength. 本発明の一実施形態である発光ダイオードの井戸層のＩｎ組成（Ｘ１）及び井戸層厚と発光ピーク波長との対応を示すグラフである。It is a graph which shows the correspondence of In composition (X1) of the well layer of the light emitting diode which is one Embodiment of this invention, well layer thickness, and a light emission peak wavelength. 本発明の一実施形態である発光ダイオードの井戸層のＩｎ組成（Ｘ１）と発光ピーク波長及びその発光出力との相関を示すグラフである。It is a graph which shows the correlation with In composition (X1) of the well layer of the light emitting diode which is one Embodiment of this invention, a light emission peak wavelength, and its light emission output. 本発明の一実施形態である発光ダイオードの井戸層及びバリア層のペア数と発光出力との相関を示すグラフである。It is a graph which shows the correlation with the number of pairs of the well layer and barrier layer of the light emitting diode which is one Embodiment of this invention, and light emission output. 本発明の一実施形態である発光ダイオードのバリア層のＩｎ組成（Ｙ１）と発光出力との相関を示すグラフである。It is a graph which shows the correlation with In composition (Y1) of the barrier layer of the light emitting diode which is one Embodiment of this invention, and light emission output. 本発明の一実施形態である発光ダイオードの順方向電流と発光出力の相関に対する、井戸層及びバリア層のペア数の依存性を示すグラフである。It is a graph which shows the dependence of the number of pairs of a well layer and a barrier layer with respect to the correlation of the forward current and light emission output of the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態である発光ダイオードに用いるエピウェーハの断面模式図である。It is a cross-sectional schematic diagram of the epiwafer used for the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態である発光ダイオードに用いる接合ウェーハの断面模式図である。It is a cross-sectional schematic diagram of the bonded wafer used for the light emitting diode which is one Embodiment of this invention. 本発明の一実施形態である発光ダイオードの平面図である。It is a top view of the light emitting diode which is one Embodiment of this invention. 図１４Ａ中に示すＣ－Ｃ’線に沿った断面模式図である。FIG. 14B is a schematic cross-sectional view taken along line C-C ′ shown in FIG. 14A. 本発明の他の実施形態である発光ダイオードの断面模式図である。It is a cross-sectional schematic diagram of the light emitting diode which is other embodiment of this invention.
　以下、本発明を適用した一実施形態である発光ダイオード及びこれを用いた発光ダイオードランプについて図面を用いて詳細に説明する。なお、以下の説明で用いる図面は、特徴をわかりやすくするために、便宜上特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率などが実際と同じであるとは限らない。 Hereinafter, a light emitting diode according to an embodiment to which the present invention is applied and a light emitting diode lamp using the same will be described in detail with reference to the drawings. In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent.
＜発光ダイオードランプ＞
　図１及び図２は、本発明を適用した一実施形態である発光ダイオードを用いた発光ダイオードランプを説明するための図であり、図１は平面図、図２は図１中に示すＡ－Ａ’線に沿った断面図である。 <Light emitting diode lamp>
1 and 2 are diagrams for explaining a light-emitting diode lamp using a light-emitting diode according to an embodiment to which the present invention is applied. FIG. 1 is a plan view, and FIG. It is sectional drawing along the A 'line.
　図１及び図２に示すように、本実施形態の発光ダイオード１を用いた発光ダイオードランプ４１は、マウント基板４２の表面に１以上の発光ダイオード１が実装されている。
　より具体的には、マウント基板４２の表面には、ｎ電極端子４３とｐ電極端子４４とが設けられている。また、発光ダイオード１の第１の電極であるｎ型オーミック電極４とマウント基板４２のｎ電極端子４３とが金線４５を用いて接続されている（ワイヤボンディング）。一方、発光ダイオード１の第２の電極であるｐ型オーミック電極５とマウント基板４２のｐ電極端子４４とが金線４６を用いて接続されている。さらに、図２に示すように、発光ダイオード１のｎ型及びｐ型オーミック電極４，５が設けられた面と反対側の面には、第３の電極６が設けられており、この第３の電極６によって発光ダイオード１がｎ電極端子４３上に接続されてマウント基板４２に固定されている。ここで、ｎ型オーミック電極４と第３の電極６とは、ｎ極電極端子４３によって等電位又は略等電位となるように電気的に接続されている。第３の電極により、過大な逆電圧に対して、活性層には過電流が流れず、第３の電極とｐ型電極間に電流が流れ、活性層の破損を防止できる。第３の電極と基板界面側に、反射構造を付加し、高出力することもできる。また、第３の電極の表面側に、共晶金属、半田などを付加することにより、共晶ダイボンド等、より簡便な組み立て技術を利用可能とする。そして、マウント基板４２の発光ダイオード１が実装された表面は、シリコン樹脂やエポキシ樹脂等の一般的な封止樹脂４７によって封止されている。 As shown in FIGS. 1 and 2, in the light-emitting diode lamp 41 using the light-emitting diode 1 of the present embodiment, one or more light-emitting diodes 1 are mounted on the surface of a mount substrate 42.
More specifically, an n electrode terminal 43 and a p electrode terminal 44 are provided on the surface of the mount substrate 42. In addition, the n-type ohmic electrode 4 that is the first electrode of the light-emitting diode 1 and the n-electrode terminal 43 of the mount substrate 42 are connected using a gold wire 45 (wire bonding). On the other hand, the p-type ohmic electrode 5, which is the second electrode of the light emitting diode 1, and the p-electrode terminal 44 of the mount substrate 42 are connected using a gold wire 46. Further, as shown in FIG. 2, a third electrode 6 is provided on the surface of the light emitting diode 1 opposite to the surface on which the n-type and p- type ohmic electrodes 4 and 5 are provided. The light emitting diode 1 is connected to the n electrode terminal 43 by the electrode 6 and fixed to the mount substrate 42. Here, the n-type ohmic electrode 4 and the third electrode 6 are electrically connected by the n-pole electrode terminal 43 so as to be equipotential or substantially equipotential. The third electrode prevents an overcurrent from flowing in the active layer against an excessive reverse voltage, and a current flows between the third electrode and the p-type electrode, thereby preventing the active layer from being damaged. A reflection structure can be added to the third electrode and the substrate interface side to achieve high output. Further, by adding eutectic metal, solder or the like to the surface side of the third electrode, a simpler assembly technique such as eutectic die bonding can be used. The surface of the mount substrate 42 on which the light emitting diode 1 is mounted is sealed with a general sealing resin 47 such as silicon resin or epoxy resin.
＜発光ダイオード（第１の実施形態）＞
　図３及び図４は、本発明を適用した第１の実施形態に係る発光ダイオードを説明するための図であり、図３は平面図、図４は図３中に示すＢ－Ｂ’線に沿った断面図である。また、図５は井戸層とバリア層の積層構造の断面図である。
　第１の実施形態に係る発光ダイオードは、組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層１７と組成式（ＡｌＸ２Ｇａ１－Ｘ２）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ２≦１，０＜Ｙ１≦１）からなるバリア層１８とを交互に積層した量子井戸構造の活性層１１と、活性層１１を挟む、組成式（ＡｌＸ３Ｇａ１－Ｘ３）Ｙ２Ｉｎ１－Ｙ２Ｐ（０≦Ｘ３≦１，０＜Ｙ２≦１）からなる第１のガイド１０及び第２のガイド１２と、第１のガイド１０及び第２のガイド１２のそれぞれを介して活性層１１を挟む第１のクラッド層９及び第２のクラッド層１３を有する発光部７と、発光部７上に形成された電流拡散層８と、電流拡散層８に接合された機能性基板３と、を備え、第１のクラッド層９及び第２のクラッド層１３が組成式（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ３Ｉｎ１－Ｙ３Ｐ（０≦Ｘ４≦１，０＜Ｙ３≦１）からなることを特徴とする。
　また、発光ダイオード１は、主たる光取り出し面に設けられたｎ型オーミック電極（第１の電極）４及びｐ型オーミック電極（第２の電極）５を備えて概略構成されている。
　なお、本実施形態における主たる光取り出し面とは、化合物半導体層２において、機能性基板３を貼り付けた面の反対側の面である。 <Light Emitting Diode (First Embodiment)>
3 and 4 are diagrams for explaining the light emitting diode according to the first embodiment to which the present invention is applied. FIG. 3 is a plan view, and FIG. 4 is taken along the line BB ′ shown in FIG. FIG. FIG. 5 is a cross-sectional view of a laminated structure of a well layer and a barrier layer.
The light emitting diode according to the first embodiment includes a well layer 17 having a composition formula (In X1 Ga 1 -X1 ) As (0 ≦ X1 ≦ 1) and a composition formula (Al X2 Ga 1 -X2 ) Y1 In 1 -Y1. An active layer 11 having a quantum well structure in which barrier layers 18 made of P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1) are alternately stacked, and a composition formula (Al X3 Ga 1-X3 ) sandwiching the active layer 11 Via the first guide 10 and the second guide 12 made of Y2 In 1-Y2 P (0 ≦ X3 ≦ 1, 0 <Y2 ≦ 1), and the first guide 10 and the second guide 12, respectively. A light emitting unit 7 having a first cladding layer 9 and a second cladding layer 13 sandwiching the active layer 11, a current diffusion layer 8 formed on the light emitting unit 7, and a functional substrate bonded to the current diffusion layer 8 3 and a first clad layer 9 and a second clad layer 3 is characterized by comprising the composition formula (Al X4 Ga 1-X4) Y3 In 1-Y3 P (0 ≦ X4 ≦ 1,0 <Y3 ≦ 1).
The light-emitting diode 1 is schematically configured to include an n-type ohmic electrode (first electrode) 4 and a p-type ohmic electrode (second electrode) 5 provided on the main light extraction surface.
In addition, the main light extraction surface in this embodiment is a surface of the compound semiconductor layer 2 opposite to the surface to which the functional substrate 3 is attached.
　化合物半導体層（エピタキシャル成長層ともいう）２は、図４に示すように、ｐｎ接合型の発光部７と電流拡散層８とが順次積層された構造を有している。この化合物半導体層２の構造には、公知の機能層を適時加えることができる。例えば、オーミック（Ｏｈｍｉｃ）電極の接触抵抗を下げるためのコンタクト層、素子駆動電流を発光部の全般に平面的に拡散させるための電流拡散層、逆に素子駆動電流の通流する領域を制限するための電流阻止層や電流狭窄層など公知の層構造を設けることができる。
　なお、化合物半導体層２は、ＧａＡｓ基板上にエピタキシャル成長させて形成されたものであることが好ましい。 As shown in FIG. 4, the compound semiconductor layer (also referred to as an epitaxial growth layer) 2 has a structure in which a pn junction type light emitting portion 7 and a current diffusion layer 8 are sequentially stacked. A known functional layer can be added to the structure of the compound semiconductor layer 2 as appropriate. For example, a contact layer for reducing the contact resistance of an ohmic electrode, a current diffusion layer for planarly diffusing the element driving current over the entire light emitting portion, and conversely, limiting a region through which the element driving current flows. Therefore, a known layer structure such as a current blocking layer or a current confinement layer can be provided.
The compound semiconductor layer 2 is preferably formed by epitaxial growth on a GaAs substrate.
　発光部７は、図４に示すように、電流拡散層８上に、少なくともｐ型の下部クラッド層（第１のクラッド層）９、下部ガイド層１０、活性層１１、上部ガイド層１２、ｎ型の上部クラッド層（第２のクラッド層）１３が順次積層されて構成されている。すなわち、発光部７は、放射再結合をもたらすキャリア（担体；ｃａｒｒｉｅｒ）及び発光を活性層１１に「閉じ込める」ために、活性層１１の下側及び上側に対峙して配置した下部クラッド層９、下部ガイド（ｇｕｉｄｅ）層１０、及び上部ガイド層１２、上部クラッド層１３を含む、所謂、ダブルヘテロ（英略称：ＤＨ）構造とすることが高強度の発光を得る上で好ましい。 As shown in FIG. 4, the light emitting unit 7 includes at least a p-type lower cladding layer (first cladding layer) 9, a lower guide layer 10, an active layer 11, an upper guide layer 12, n on a current diffusion layer 8. A mold upper clad layer (second clad layer) 13 is sequentially laminated. That is, the light emitting unit 7 includes a lower clad layer 9 disposed to face the lower side and the upper side of the active layer 11 in order to “confine” the carrier (carrier) and light emission that cause radiative recombination in the active layer 11. A so-called double hetero (English abbreviation: DH) structure including the lower guide layer 10, the upper guide layer 12, and the upper cladding layer 13 is preferable in order to obtain high-intensity light emission.
　活性層１１は、図５に示すように、発光ダイオード（ＬＥＤ）の発光波長を制御するため、量子井戸構造を構成する。すなわち、活性層１１は、バリア層（障壁層ともいう）１８を両端に有する、井戸層１７とバリア層（障壁層ともいう）１８との多層構造（積層構造）である。 As shown in FIG. 5, the active layer 11 forms a quantum well structure in order to control the emission wavelength of the light emitting diode (LED). That is, the active layer 11 has a multilayer structure (laminated structure) of a well layer 17 and a barrier layer (also referred to as a barrier layer) 18 having a barrier layer (also referred to as a barrier layer) 18 at both ends.
　活性層１１の層厚は、５０～１０００ｎｍの範囲であることが好ましい。また、活性層１１の伝導型は特に限定されるものではなく、アンドープ、ｐ型及びｎ型のいずれも選択することができる。発光効率を高めるには、結晶性が良好なアンドープ又は３×１０１７ｃｍ－３未満のキャリア濃度とすることが望ましい。 The layer thickness of the active layer 11 is preferably in the range of 50 to 1000 nm. Further, the conductivity type of the active layer 11 is not particularly limited, and any of undoped, p-type and n-type can be selected. In order to increase the light emission efficiency, it is desirable that the crystallinity be undoped or the carrier concentration be less than 3 × 10 17 cm −3 .
　図６に、井戸層１７のＩｎ組成（Ｘ１）を０．１に固定して、その層厚と発光ピーク波長との相関を示す。表１に図６に示したデータの値を示す。井戸層が３ｎｍ、５ｎｍ、７ｎｍと厚くなると、波長は８２０ｎｍ、８７０ｎｍ、９２０ｎｍと単調に長くなることがわかる。 FIG. 6 shows the correlation between the layer thickness and the emission peak wavelength with the In composition (X1) of the well layer 17 fixed at 0.1. Table 1 shows the values of the data shown in FIG. It can be seen that when the well layer is as thick as 3 nm, 5 nm, and 7 nm, the wavelength monotonously increases to 820 nm, 870 nm, and 920 nm.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　図７に、井戸層１７の発光ピーク波長とそのＩｎ組成（Ｘ１）及び層厚との相関を示す。図７は、井戸層１７の発光ピーク波長を所定の波長とする、井戸層１７のＩｎ組成（Ｘ１）と層厚との組み合わせを示すものである。具体的には、発光ピーク波長がそれぞれ９２０ｎｍ、９６０ｎｍとなる構成の井戸層１７のＩｎ組成（Ｘ１）と層厚との組み合わせを示す。図７にはさらに、他の発光ピーク波長８２０ｎｍ、８７０ｎｍ、９８５ｎｍ及び９９５ｎｍのときのＩｎ組成（Ｘ１）と層厚の組み合わせも示している。表２に図７に示したデータの値を示す。 FIG. 7 shows the correlation between the emission peak wavelength of the well layer 17 and its In composition (X1) and layer thickness. FIG. 7 shows a combination of the In composition (X1) and the layer thickness of the well layer 17 in which the emission peak wavelength of the well layer 17 is a predetermined wavelength. Specifically, a combination of the In composition (X1) and the layer thickness of the well layer 17 having a configuration in which the emission peak wavelengths are 920 nm and 960 nm, respectively, is shown. FIG. 7 further shows combinations of In composition (X1) and layer thicknesses at other emission peak wavelengths of 820 nm, 870 nm, 985 nm, and 995 nm. Table 2 shows the values of the data shown in FIG.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　発光ピーク波長９２０ｎｍの場合、Ｉｎ組成（Ｘ１）が０．３から０．０５へ低下していくと、それに対応する層厚は単調に３ｎｍから８ｎｍに厚くなっているから、当業者であれば、発光ピーク波長９２０ｎｍとなる組み合わせを容易に見つけることができる。
　また、Ｉｎ組成（Ｘ１）が０．１のとき、層厚が３ｎｍ、５ｎｍ、７ｎｍ、８ｎｍと厚くなると、それに対応して発光ピーク波長は８２０ｎｍ、８７０ｎｍ、９２０ｎｍ、９６０ｎｍと長くなっている。また、Ｉｎ組成（Ｘ１）が０．２のとき、層厚が５ｎｍ、６ｎｍと厚くなるとそれに対応して発光ピーク波長は９２０ｎｍ、９６０ｎｍと長くなり、Ｉｎ組成（Ｘ１）が０．２５のとき、層厚が４ｎｍ、５ｎｍと厚くなるとそれに対応して発光ピーク波長は９２０ｎｍ、９６０ｎｍと長くなり、さらに、Ｉｎ組成（Ｘ１）が０．３のとき、層厚が３ｎｍ、５ｎｍと厚くなると、それに対応して発光ピーク波長は９２０ｎｍ、９８５ｎｍと長くなっている。
　さらにまた、層厚が５ｎｍのとき、Ｉｎ組成（Ｘ１）が０．１、０．２、０．２５、０．３と増加すると、発光ピーク波長は８７０ｎｍ、９２０ｎｍ、９６０ｎｍ、９８５ｎｍと長くなっており、Ｉｎ組成（Ｘ１）が０．３５になると、発光ピーク波長は９９５ｎｍとなる。 In the case of an emission peak wavelength of 920 nm, as the In composition (X1) decreases from 0.3 to 0.05, the corresponding layer thickness monotonously increases from 3 nm to 8 nm. A combination with an emission peak wavelength of 920 nm can be easily found.
Further, when the In composition (X1) is 0.1 and the layer thickness is increased to 3 nm, 5 nm, 7 nm, and 8 nm, the emission peak wavelengths are correspondingly increased to 820 nm, 870 nm, 920 nm, and 960 nm. Further, when the In composition (X1) is 0.2, the emission peak wavelength is correspondingly increased to 920 nm and 960 nm when the layer thickness is increased to 5 nm and 6 nm, and when the In composition (X1) is 0.25, When the layer thickness is increased to 4 nm and 5 nm, the emission peak wavelengths are correspondingly increased to 920 nm and 960 nm, and when the In composition (X1) is 0.3, the layer thickness is increased to 3 nm and 5 nm. The emission peak wavelengths are as long as 920 nm and 985 nm.
Furthermore, when the In composition (X1) increases to 0.1, 0.2, 0.25, and 0.3 when the layer thickness is 5 nm, the emission peak wavelengths are increased to 870 nm, 920 nm, 960 nm, and 985 nm. When the In composition (X1) becomes 0.35, the emission peak wavelength becomes 995 nm.
　図７において、発光ピーク波長を９２０ｎｍ及び９６０ｎｍとするＩｎ組成（Ｘ１）と層厚の組み合わせを結ぶと略直線になることが示されている。また、８５０ｎｍ以上１０００ｎｍ程度までの波長帯の所定の発光ピーク波長とするＩｎ組成（Ｘ１）と層厚の組み合わせを結ぶ線も、略直線状になると推察される。さらに、その組み合わせを結ぶ線は発光ピーク波長が短いほど左下に位置し、長いほど右上に位置するものと推察される。
　以上の規則性に基づけば、８５０ｎｍ以上１０００ｎｍ以下の所望の発光ピーク波長を有する、Ｉｎ組成（Ｘ１）と層厚を容易に見つけることができる。 In FIG. 7, it is shown that when a combination of the In composition (X1) with the emission peak wavelengths of 920 nm and 960 nm and the layer thickness is connected, it becomes a substantially straight line. Further, it is presumed that a line connecting a combination of the In composition (X1) having a predetermined emission peak wavelength in the wavelength band from 850 nm to 1000 nm and the layer thickness is also substantially linear. Further, it is assumed that the line connecting the combinations is located at the lower left as the emission peak wavelength is shorter, and located at the upper right as the longer the emission peak wavelength.
Based on the above regularity, the In composition (X1) and the layer thickness having a desired emission peak wavelength of 850 nm or more and 1000 nm or less can be easily found.
　図８に、井戸層１７の層厚を５ｎｍに固定した、Ｉｎ組成（Ｘ１）と発光ピーク波長及びその発光出力との相関を示す。表３に図８に示したデータの値を示す。
　Ｉｎ組成（Ｘ１）が０．１２、０．２、０．２５、０．３、０．３５と増加すると、発光ピーク波長は８７０ｎｍ、９２０ｎｍ、９６０ｎｍ、９８５ｎｍ、９９５ｎｍと長くなっている。より詳細には、Ｉｎ組成（Ｘ１）が０．１２から０．３へ増加していくにつれて、発光ピーク波長は略単調に８７０ｎｍから９８５ｎｍへと長くなっている。しかし、Ｉｎ組成（Ｘ１）を０．３から０．３５へと増加しても、９８５ｎｍから９９５ｎｍへと長くなるが、長波長への変化率は小さくなっている。
　また、発光ピーク波長は８７０ｎｍ（Ｘ１＝０．１２）、９２０ｎｍ（Ｘ１＝０．２）、９６０ｎｍ（Ｘ１＝０．２５）では発光出力は６．５ｍＷと高い値であり、９８５ｎｍ（Ｘ１＝０．３）でも５ｍＷと実用上十分な高い値を有するが、９９５ｎｍ（Ｘ１＝０．３５）では２ｍＷと低い値であった。 FIG. 8 shows the correlation between the In composition (X1), the emission peak wavelength, and its emission output, with the well layer 17 having a thickness of 5 nm. Table 3 shows the data values shown in FIG.
When the In composition (X1) is increased to 0.12, 0.2, 0.25, 0.3, and 0.35, the emission peak wavelengths are increased to 870 nm, 920 nm, 960 nm, 985 nm, and 995 nm. More specifically, as the In composition (X1) increases from 0.12 to 0.3, the emission peak wavelength increases from 870 nm to 985 nm almost monotonically. However, even if the In composition (X1) is increased from 0.3 to 0.35, the length increases from 985 nm to 995 nm, but the rate of change to long wavelengths is small.
The emission peak wavelength is 870 nm (X1 = 0.12), 920 nm (X1 = 0.2), and 960 nm (X1 = 0.25), and the emission output is as high as 6.5 mW, and 985 nm (X1 = 0). .3) has a practically high value of 5 mW, but was a low value of 2 mW at 995 nm (X1 = 0.35).
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
　図６～図８に基づくと、井戸層１７は、（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦０．３の組成を有していることが好ましい。上記Ｘ１は、所望の発光波長になるように調整することができる。
　発光ピーク波長を９００ｎｍ以上とする場合は０．１≦Ｘ１≦０．３であるのが好ましく、９００ｎｍ未満とする場合は、０≦Ｘ１≦０．１であるのが好ましい。 6 to 8, the well layer 17 preferably has a composition of (In X1 Ga 1-X1 ) As (0 ≦ X1 ≦ 0.3, where X1 is a desired emission wavelength. Can be adjusted.
When the emission peak wavelength is 900 nm or more, 0.1 ≦ X1 ≦ 0.3 is preferable, and when it is less than 900 nm, 0 ≦ X1 ≦ 0.1 is preferable.
　井戸層１７の層厚は、３～２０ｎｍの範囲が好適である。より好ましくは、３～１０ｎｍの範囲である。 The layer thickness of the well layer 17 is preferably in the range of 3 to 20 nm. More preferably, it is in the range of 3 to 10 nm.
　バリア層１８は、（ＡｌＸ２Ｇａ１－Ｘ２）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ２≦１，０＜Ｙ１≦１）の組成を有している。上記Ｘ２は、井戸層１７よりもバンドギャップが大きくなる組成とすることが好ましく、０～０．２の範囲がより好ましい。また、Ｙ１は、井戸層１７の格子不整合に起因するひずみを緩和する為に０．５～０．７とすることが好ましく、０．５２～０．６０の範囲がより好ましい。
　バリア層１８の層厚は、井戸層１７の層厚と等しいか又は厚いことが好ましい。これにより、井戸層１７の発光効率を高くすることができる。 The barrier layer 18 has a composition of (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1). X2 is preferably a composition having a larger band gap than the well layer 17, and more preferably in the range of 0 to 0.2. Y1 is preferably set to 0.5 to 0.7, more preferably in the range of 0.52 to 0.60, in order to relieve strain caused by lattice mismatch of the well layer 17.
The layer thickness of the barrier layer 18 is preferably equal to or thicker than the layer thickness of the well layer 17. Thereby, the luminous efficiency of the well layer 17 can be increased.
　図９に、井戸層１７の層厚を５ｎｍ、Ｉｎ組成（Ｘ１）＝０．２とし、かつ、バリア層の組成Ｘ２＝０．１、Ｙ１＝０．５５のとき（すなわち、（Ａｌ０．１Ｇａ０．９）０．５５Ｉｎ０．４５Ｐ）、井戸層及びバリア層のペア数と発光出力との相関を示す。表４に図９に示したデータの値を示す。成長基板としてＧａＡｓ基板を用いた場合である。
　尚、バリア層の効果を示すために、比較例としてバリア層にＡｌ０．３Ｇａ０．７Ａｓを用いたときを併せて示した。
　バリア層にＡｌ０．３Ｇａ０．７Ａｓを用いた比較例の場合はペア数１～１０対までは発光出力が６．５ｍＷ以上と高い値を有するが、２０対では５ｍＷと低下するのに対して、本発明の場合はペア数２０対まで略６．５ｍＷ以上の高い値を維持している。このようにペア数を多くしても高い発光出力を維持できるのは、ＧａＡｓ成長基板に対する組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層の歪みを、組成Ｘ２＝０．１、Ｙ１＝０．５５（すなわち、（Ａｌ０．１Ｇａ０．９）０．５５Ｉｎ０．４５Ｐ）のバリア層が緩和して（すなわち、バリア層が井戸層と逆方向の格子歪みが与えられている）、結晶性の低下が抑制されていることに起因する。歪み緩和の効果についてさらに図１０を用いて説明する。 In FIG. 9, when the thickness of the well layer 17 is 5 nm, the In composition (X1) = 0.2, and the barrier layer composition X2 = 0.1 and Y1 = 0.55 (that is, (Al 0. 1 Ga 0.9 ) 0.55 In 0.45 P), the correlation between the number of pairs of well layers and barrier layers and the light emission output. Table 4 shows the values of the data shown in FIG. This is a case where a GaAs substrate is used as the growth substrate.
In order to show the effect of the barrier layer, it is also shown a case of using the Al 0.3 Ga 0.7 As barrier layer as a comparative example.
In the case of the comparative example using Al 0.3 Ga 0.7 As for the barrier layer, the light emission output is as high as 6.5 mW or more when the number of pairs is 1 to 10, but the value decreases to 5 mW with 20 pairs. On the other hand, in the case of the present invention, a high value of approximately 6.5 mW or more is maintained up to 20 pairs. Thus, even if the number of pairs is increased, a high light emission output can be maintained because the strain of the well layer composed of the composition formula (In X1 Ga 1 -X1 ) As (0 ≦ X1 ≦ 1) with respect to the GaAs growth substrate X2 = 0.1, Y1 = 0.55 (i.e., (Al 0.1 Ga 0.9) 0.55 in 0.45 P) barrier layer is relaxed (i.e., the barrier layer is well layer opposite This is because the decrease in crystallinity is suppressed. The effect of strain relaxation will be further described with reference to FIG.
Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000004
　図１０は、井戸層１７の層厚を５ｎｍ、Ｉｎ組成（Ｘ１）＝０．２（発光波長９２０ｎｍ）とし、かつ、バリア層のＡｌ組成Ｘ２＝０．１で５ペアのとき、バリア層のＹ１（すなわち、（Ａｌ０．１Ｇａ０．９）ｙＩｎ１－ｙＰ）と発光出力との相関を示す。表５に図１０に示したデータの値を示す。成長基板としてＧａＡｓ基板を用いた場合である。
　バリア層の効果を示すために、比較例としてバリア層は本発明と同じだが、井戸層に成長基板と同じ材料であるＧａＡｓ層（すなわち、成長基板に対して歪みがない場合）を用いたときを併せて示した。
　本発明の場合は、発光出力の最大は７ｍＷであって、バリア層のＹ１が０．５２～０．６０の範囲で略７ｍＷを示す。これに対して、井戸層にＧａＡｓ層を用いた比較例の場合は発光出力の最大で６．５ｍＷであって、高出力を示す範囲も本発明の場合よりも狭いことがわかる。
　この結果は、本発明では、井戸層の歪みをバリア層の逆方向歪みが緩和して結晶性低下を抑制するために、発光出力は高くかつ高出力を示すバリア層の組成範囲も広いのに対して、比較例では、歪みがない井戸層と歪みを有するバリア層の組み合わせとなっているために、結果として結晶性が低下して発光出力特性が低下していると理解できる。 FIG. 10 shows that when the thickness of the well layer 17 is 5 nm, the In composition (X1) = 0.2 (emission wavelength 920 nm), and the Al composition X2 = 0.1 of the barrier layer and 5 pairs, Y1 (i.e., (Al 0.1 Ga 0.9) y in 1-y P) showing the correlation between emission output and. Table 5 shows the data values shown in FIG. This is a case where a GaAs substrate is used as the growth substrate.
In order to show the effect of the barrier layer, as a comparative example, the barrier layer is the same as that of the present invention, but the well layer is a GaAs layer made of the same material as the growth substrate (that is, when the growth substrate is not distorted). Was also shown.
In the present invention, the maximum light emission output is 7 mW, and Y1 of the barrier layer is about 7 mW in the range of 0.52 to 0.60. On the other hand, in the case of the comparative example using the GaAs layer as the well layer, the light emission output is 6.5 mW at the maximum, and the range showing high output is narrower than the case of the present invention.
As a result, in the present invention, since the strain in the well layer is relaxed by the reverse strain in the barrier layer to suppress the decrease in crystallinity, the composition range of the barrier layer exhibiting high light output and high output is wide. On the other hand, in the comparative example, since it is a combination of a well layer having no strain and a barrier layer having a strain, it can be understood that as a result, the crystallinity is lowered and the light emission output characteristics are lowered.
Figure JPOXMLDOC01-appb-T000005
Figure JPOXMLDOC01-appb-T000005
　図１１に、順方向電流と発光出力の相関に対する、井戸層及びバリア層のペア数の依存性を示す。データは井戸層１７の層厚を５ｎｍ、Ｉｎ組成（Ｘ１）＝０．２とし、かつ、バリア層の組成Ｘ２＝０．１、Ｙ１＝０．５５（すなわち、Ａｌ０．１Ｇａ０．９）０．５５Ｉｎ０．４５Ｐ）であって、ペア数が３対及び５対の場合を示している、表６に図１１に示したデータの値を示す。
　順方向電流が３０ｍＡまでは、３対及び５対のいずれも電流の増加に略比例して発光出力が増大した。しかし、５０ｍＡ、１００ｍＡでは５対について略比例を維持して電流の増加に対して発光出力が増大したが、３対については、５０ｍＡ、１００ｍＡのそれぞれで５対の場合と比べて、発光出力が２ｍＷ、９ｍＷ低かった。
　従って、大電流・高出力の発光ダイオードに対しては、３対のものより、５対のものの方が適していることがわかった。ペア数が多い方が大電流・高出力に適しているのは、成長基板に対する組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層の歪みを、組成Ｘ２＝０．１、Ｙ１＝０．５５（すなわち、（Ａｌ０．１Ｇａ０．９）０．５５Ｉｎ０．４５Ｐ）のバリア層が緩和して、結晶性の低下が抑制されていることに起因する。 FIG. 11 shows the dependence of the number of well layer and barrier layer pairs on the correlation between the forward current and the light emission output. The data shows that the thickness of the well layer 17 is 5 nm, the In composition (X1) = 0.2, and the barrier layer composition X2 = 0.1, Y1 = 0.55 (that is, Al 0.1 Ga 0.9 0.55 In 0.45 P), and the values of the data shown in FIG. 11 are shown in Table 6 showing the case where the number of pairs is 3 and 5 pairs.
When the forward current was up to 30 mA, the light emission output increased substantially in proportion to the increase in current in both 3 and 5 pairs. However, at 50 mA and 100 mA, the light emission output increased with increasing current while maintaining approximately proportionality with respect to 5 pairs. However, the light emission output with respect to 3 pairs was higher than that with 5 pairs at 50 mA and 100 mA, respectively. It was 2 mW and 9 mW lower.
Therefore, it was found that five pairs are more suitable than three pairs for high current / high output light emitting diodes. The larger number of pairs is suitable for large current and high output because the strain of the well layer composed of the composition formula (In X1 Ga 1 -X1 ) As (0 ≦ X1 ≦ 1) with respect to the growth substrate is expressed as composition X2 = The barrier layer of 0.1, Y1 = 0.55 (that is, (Al 0.1 Ga 0.9 ) 0.55 In 0.45 P) is relaxed, and the decrease in crystallinity is suppressed. to cause.
Figure JPOXMLDOC01-appb-T000006
Figure JPOXMLDOC01-appb-T000006
　井戸層１７とバリア層１８との多層構造において、井戸層１７とバリア層１８とを交互に積層する対の数は特に限定されるものではないが、図９に基づくと、１対以上２０対以下であることが好ましい。すなわち、活性層１１には、井戸層１７が１～２０層含まれていることが好ましい。ここで、図９に基づくと、活性層１１の発光効率が好適な範囲としては井戸層１７が１層で十分であるが、図１０に基づくと、特に、高電流条件下の発光効率向上の点では複数であることが好ましい。一方、井戸層１７及びバリア層１８の間には格子不整が存在する為、多くの対にすると結晶欠陥の発生の為、発光効率が低下してしまう。このため、２０対以下であることが好ましく、１０対以下であることがより好ましい。 In the multilayer structure of the well layer 17 and the barrier layer 18, the number of pairs in which the well layers 17 and the barrier layers 18 are alternately stacked is not particularly limited. However, based on FIG. The following is preferable. That is, the active layer 11 preferably includes 1 to 20 well layers 17. Here, based on FIG. 9, a single well layer 17 is sufficient as a suitable range for the luminous efficiency of the active layer 11. However, based on FIG. 10, the luminous efficiency is improved particularly under high current conditions. It is preferable that there are a plurality of points. On the other hand, since there is a lattice irregularity between the well layer 17 and the barrier layer 18, if many pairs are formed, crystal defects are generated, so that the light emission efficiency is lowered. For this reason, it is preferable that it is 20 pairs or less, and it is more preferable that it is 10 pairs or less.
　下部ガイド層１０及び上部ガイド層１２は、図４に示すように、活性層１１の下面及び上面にそれぞれ設けられている。具体的には、活性層１１の下面に下部ガイド層１０が設けられ、活性層１１の上面に上部ガイド層１２が設けられている。 The lower guide layer 10 and the upper guide layer 12 are provided on the lower surface and the upper surface of the active layer 11, respectively, as shown in FIG. Specifically, the lower guide layer 10 is provided on the lower surface of the active layer 11, and the upper guide layer 12 is provided on the upper surface of the active layer 11.
　下部ガイド層１０および上部ガイド層１２は、（ＡｌＸ３Ｇａ１－Ｘ３）Ｙ２Ｉｎ１－Ｙ２Ｐ（０≦Ｘ３≦１，０＜Ｙ２≦１）の組成を有している。上記Ｘ３は、バリア層１８とバンドギャップが等しいか又はバリア層１８よりも大きくなる組成とすることが好ましく、０．２～０．５の範囲がより好ましい。また、Ｙ２は、０．４～０．６とすることが好ましい。
　Ｘ３はクラッド層として機能し且つ発光波長に対して透明な範囲で選ばれ、Ｙ２はクラッド層が厚膜なので基板との格子整合を重視し、良質な結晶成長ができる範囲として選ばれる。 The lower guide layer 10 and the upper guide layer 12 have a composition of (Al X3 Ga 1 -X3 ) Y2 In 1 -Y2 P (0 ≦ X3 ≦ 1, 0 <Y2 ≦ 1). X3 is preferably a composition having the same band gap as that of the barrier layer 18 or larger than the barrier layer 18, and more preferably in the range of 0.2 to 0.5. Y2 is preferably 0.4 to 0.6.
X3 functions as a clad layer and is selected in a range that is transparent to the emission wavelength, and Y2 is selected as a range in which good crystal growth can be achieved by placing importance on lattice matching with the substrate because the clad layer is thick.
　下部ガイド層１０及び上部ガイド層１２はそれぞれ、下部クラッド層９及び上部クラッド層１３と活性層１１との間における不純物の伝搬を低減するために設けられている。すなわち、本発明では、下部クラッド層９及び上部クラッド層１３には高濃度に不純物がドープされており、この不純物の活性層１１への拡散は発光ダイオードの性能低下の原因となる。この不純物の拡散を有効に低減するためには、下部ガイド層１０および上部ガイド層１２の層厚は１０ｎｍ以上が好ましく、２０ｎｍ～１００ｎｍがより好ましい。 The lower guide layer 10 and the upper guide layer 12 are provided to reduce the propagation of impurities between the lower cladding layer 9 and the upper cladding layer 13 and the active layer 11, respectively. That is, in the present invention, the lower clad layer 9 and the upper clad layer 13 are doped with an impurity at a high concentration, and the diffusion of the impurity into the active layer 11 causes the performance of the light emitting diode to deteriorate. In order to effectively reduce the diffusion of impurities, the thickness of the lower guide layer 10 and the upper guide layer 12 is preferably 10 nm or more, and more preferably 20 nm to 100 nm.
　下部ガイド層１０及び上部ガイド層１２の伝導型は、特に限定されるものではなく、アンドープ、ｐ型及びｎ型のいずれも選択することができる。発光効率を高めるには、結晶性が良好なアンドープ又は３×１０１７ｃｍ－３未満のキャリア濃度とすることが望ましい。 The conductivity type of the lower guide layer 10 and the upper guide layer 12 is not particularly limited, and any of undoped, p-type, and n-type can be selected. In order to increase the light emission efficiency, it is desirable that the crystallinity be undoped or the carrier concentration be less than 3 × 10 17 cm −3 .
　下部クラッド層９及び上部クラッド層１３は、図４に示すように、下部ガイド層１０の下面及び上部ガイド層１２上面にそれぞれ設けられている。 The lower clad layer 9 and the upper clad layer 13 are provided on the lower surface of the lower guide layer 10 and the upper surface of the upper guide layer 12, respectively, as shown in FIG.
　下部クラッド層９及び上部クラッド層１３の材質としては、（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ３Ｉｎ１－Ｙ３Ｐ（０≦Ｘ４≦１，０＜Ｙ３≦１）の半導体材料を用い、バリア層１５よりもバンドギャップの大きい材質が好ましく、下部ガイド層１０及び上部ガイド層１２よりもバンドギャップが大きい材質がより好ましい。上記材質としては、（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ３Ｉｎ１－Ｙ３Ｐ（０≦Ｘ４≦１，０＜Ｙ３≦１）のＸ４が、０．３～０．７である組成を有することが好ましい。又、Ｙ３は、０．４～０．６とすることが好ましい。Ｘ４はクラッド層として機能し且つ発光波長に対して透明な範囲で選ばれ、Ｙ３はクラッド層が厚膜なので基板との格子整合の観点から良質な結晶成長ができる範囲として選ばれる。 As the material of the lower cladding layer 9 and the upper cladding layer 13, a semiconductor material of (Al X4 Ga 1 -X4 ) Y3 In 1-Y3 P (0 ≦ X4 ≦ 1, 0 <Y3 ≦ 1) is used, and the barrier layer 15 A material having a larger band gap is preferable, and a material having a larger band gap than the lower guide layer 10 and the upper guide layer 12 is more preferable. The material may have a composition in which X4 of (Al X4 Ga 1-X4 ) Y3 In 1-Y3 P (0 ≦ X4 ≦ 1, 0 <Y3 ≦ 1) is 0.3 to 0.7. preferable. Y3 is preferably 0.4 to 0.6. X4 functions as a clad layer and is selected in a range that is transparent to the emission wavelength, and Y3 is selected as a range in which good quality crystal growth is possible from the viewpoint of lattice matching with the substrate because the clad layer is thick.
　下部クラッド層９と上部クラッド層１３とは、極性が異なるように構成されている。また、下部クラッド層９及び上部クラッド層１３のキャリア濃度及び厚さは、公知の好適な範囲を用いることができ、活性層１１の発光効率が高まるように条件を最適化することが好ましい。また、下部クラッド層９及び上部クラッド層１３の組成を制御することによって、化合物半導体層２の反りを低減させることができる。 The lower clad layer 9 and the upper clad layer 13 are configured to have different polarities. The carrier concentration and thickness of the lower clad layer 9 and the upper clad layer 13 can be in a known suitable range, and it is preferable to optimize the conditions so that the luminous efficiency of the active layer 11 is increased. Further, the warpage of the compound semiconductor layer 2 can be reduced by controlling the composition of the lower cladding layer 9 and the upper cladding layer 13.
　具体的に、下部クラッド層９としては、例えば、Ｍｇをドープしたｐ型の（ＡｌＸ４aＧａ１－Ｘ４ａ）ＹａＩｎ１－ＹａＰ（０．３≦Ｘ４ａ≦０．７，０．４≦Ｙ３ａ≦０．６）からなる半導体材料を用いることが望ましい。また、キャリア濃度は２×１０１７～２×１０１８ｃｍ－３の範囲が好ましく、層厚は０．１～１μｍの範囲が好ましい。 Specifically, as the lower clad layer 9, for example, p-type (Al X4a Ga 1-X4a ) Ya In 1- YaP (0.3 ≦ X4a ≦ 0.7, 0.4 ≦ Y3a) doped with Mg is used. It is desirable to use a semiconductor material composed of ≦ 0.6). The carrier concentration is preferably in the range of 2 × 10 17 to 2 × 10 18 cm −3 , and the layer thickness is preferably in the range of 0.1 to 1 μm.
　一方、上部クラッド層１３としては、例えば、Ｓｉをドープしたｎ型の（（ＡｌＸ４ｂＧａ１－Ｘ４ｂ）ＹｂＩｎ１－ＹｂＰ（０．３≦Ｘ４ｂ≦０．７，０．４≦Ｙ３ｂ≦０．６）からなる半導体材料を用いることが望ましい。また、キャリア濃度は１×１０１７～１×１０１８ｃｍ－３の範囲が好ましく、層厚は０．１～１μｍの範囲が好ましい。
　なお、下部クラッド層９及び上部クラッド層１３の極性は、化合物半導体層２の素子構造を考慮して選択することができる。 On the other hand, as the upper clad layer 13, for example, n-type ((Al X4b Ga 1-X4b ) Yb In 1-Yb P doped with Si (0.3 ≦ X4b ≦ 0.7, 0.4 ≦ Y3b ≦) 0.6), the carrier concentration is preferably in the range of 1 × 10 17 to 1 × 10 18 cm −3 , and the layer thickness is preferably in the range of 0.1 to 1 μm.
The polarities of the lower cladding layer 9 and the upper cladding layer 13 can be selected in consideration of the element structure of the compound semiconductor layer 2.
　また、発光部７の構成層の上方には、オーミック（Ｏｈｍｉｃ）電極の接触抵抗を下げるためのコンタクト層、素子駆動電流を発光部の全般に平面的に拡散させるための電流拡散層、逆に素子駆動電流の通流する領域を制限するための電流阻止層や電流狭窄層など公知の層構造を設けることができる。 Further, above the constituent layers of the light emitting unit 7, a contact layer for lowering the contact resistance of the ohmic electrode, a current diffusion layer for planarly diffusing the element driving current throughout the light emitting unit, and conversely A known layer structure such as a current blocking layer or a current confinement layer for limiting the region through which the element driving current flows can be provided.
　電流拡散層８は、図４に示すように、発光部７の下方に設けられている。この電流拡散層８は、発光部７（活性層１１）からの発光波長に対して透明である材料、例えば、ＧａＰやＧａＩｎＰを適用することができる。
　電流拡散層８にＧａＰを適用する場合、機能性基板３をＧａＰ基板とすることにより、接合を容易にし、高い接合強度を得ることができるという効果がある。
　また、電流拡散層８にＧａＩｎＰを適用する場合、ＧａとＩｎの比率を変えることにより、電流拡散層８が積層される井戸層１７の材料であるＩｎＧａＡｓと同じ格子定数にして、井戸層１７と格子整合させることができるという効果がある。従って、所望の発光ピーク波長から選択された組成比のＩｎＧａＡｓと同じ格子定数となるように、ＧａＩｎＰの組成比を選択するのが好ましい。
　また、電流拡散層８の厚さは０．５～２０μｍの範囲であることが好ましい。０．５μｍ以下であると電流拡散が不十分であり、２０μｍ以上であるとその厚さまで結晶成長させる為のコストが増大するからである。 As shown in FIG. 4, the current spreading layer 8 is provided below the light emitting unit 7. The current spreading layer 8 can be made of a material that is transparent to the emission wavelength from the light emitting unit 7 (active layer 11), such as GaP or GaInP.
In the case of applying GaP to the current diffusion layer 8, by using the functional substrate 3 as a GaP substrate, bonding can be facilitated and high bonding strength can be obtained.
In addition, when GaInP is applied to the current diffusion layer 8, the lattice constant is made the same as that of InGaAs, which is the material of the well layer 17 on which the current diffusion layer 8 is stacked, by changing the ratio of Ga and In. There is an effect that lattice matching can be achieved. Therefore, it is preferable to select the GaInP composition ratio so that the lattice constant is the same as that of InGaAs having the composition ratio selected from the desired emission peak wavelength.
The thickness of the current spreading layer 8 is preferably in the range of 0.5 to 20 μm. This is because the current diffusion is insufficient when the thickness is 0.5 μm or less, and the cost for crystal growth to the thickness increases when the thickness is 20 μm or more.
　機能性基板３は、化合物半導体層２の主たる光取り出し面と反対側の面に接合されている。すなわち、機能性基板３は、図４に示すように、化合物半導体層２を構成する電流拡散層８側に接合されている。この機能性基板３は、発光部７を機械的に支持するのに充分な強度を有し、且つ、バンドギャップが広く、発光部７からの発光波長に対して光学的に透明である材料から構成する。
　機能性基板３は発光部と熱膨張係数が近く、耐湿性に優れた基板であり、更に熱伝導の良いＧａＰ、ＧａＩｎＰ、ＳｉＣ、また、機械強度が強いサファイアからなるのが好ましい。また、機能性基板３は、発光部７を機械的に充分な強度で支持するために、例えば約５０μｍ以上の厚みとすることが好ましい。また、化合物半導体層２へ接合した後に機能性基板３への機械的な加工を施し易くするため、約３００μｍの厚さを超えないものとすることが好ましい。機能性基板３は、約５０μｍ以上約３００μｍ以下の厚さを有する透明度、応力、コスト面からｎ型ＧａＰ基板から構成するのが最適である。 The functional substrate 3 is bonded to the surface of the compound semiconductor layer 2 opposite to the main light extraction surface. That is, the functional substrate 3 is bonded to the current diffusion layer 8 side constituting the compound semiconductor layer 2 as shown in FIG. This functional substrate 3 is made of a material that has sufficient strength to mechanically support the light emitting portion 7, has a wide band gap, and is optically transparent to the emission wavelength from the light emitting portion 7. Constitute.
The functional substrate 3 is a substrate having a thermal expansion coefficient close to that of the light emitting portion and excellent in moisture resistance, and is preferably made of GaP, GaInP, SiC having good thermal conductivity, and sapphire having high mechanical strength. The functional substrate 3 preferably has a thickness of, for example, about 50 μm or more in order to support the light emitting unit 7 with sufficient mechanical strength. In order to facilitate the mechanical processing of the functional substrate 3 after bonding to the compound semiconductor layer 2, it is preferable that the thickness does not exceed about 300 μm. The functional substrate 3 is optimally composed of an n-type GaP substrate in terms of transparency, stress, and cost with a thickness of about 50 μm or more and about 300 μm or less.
　また、図４に示すように、機能性基板３の側面は、化合物半導体層２に近い側において主たる光取り出し面に対して略垂直である垂直面３ａとされており、化合物半導体層２に遠い側において主たる光取り出し面に対して内側に傾斜した傾斜面３ｂとされている。これにより、活性層１１から機能性基板３側に放出された光を効率よく外部に取り出すことができる。また、活性層１１から機能性基板３側に放出された光のうち、一部は垂直面３ａで反射され傾斜面３ｂで取り出すことができる。一方、傾斜面３ｂで反射された光は垂直面３ａで取り出すことができる。このように、垂直面３ａと傾斜面３ｂとの相乗効果により、光の取り出し効率を高めることができる。 Further, as shown in FIG. 4, the side surface of the functional substrate 3 is a vertical surface 3 a that is substantially perpendicular to the main light extraction surface on the side close to the compound semiconductor layer 2, and is far from the compound semiconductor layer 2. On the side, the inclined surface 3b is inclined inward with respect to the main light extraction surface. Thereby, the light emitted from the active layer 11 to the functional substrate 3 can be efficiently extracted to the outside. In addition, part of the light emitted from the active layer 11 to the functional substrate 3 side is reflected by the vertical surface 3a and can be extracted by the inclined surface 3b. On the other hand, the light reflected by the inclined surface 3b can be extracted by the vertical surface 3a. Thus, the light extraction efficiency can be increased by the synergistic effect of the vertical surface 3a and the inclined surface 3b.
　また、本実施形態では、図４に示すように、傾斜面３ｂと発光面に平行な面とのなす角度αを、５５度～８０度の範囲内とすることが好ましい。このような範囲とすることで、機能性基板３の底部で反射された光を効率よく外部に取り出すことができる。
　また、垂直面３ａの幅（厚さ方向）を、３０μｍ～１００μｍの範囲内とすることが好ましい。垂直面３ａの幅を上記範囲内にすることで、機能性基板３の底部で反射された光を垂直面３ａにおいて効率よく発光面に戻すことができ、さらには、主たる光取り出し面から放出させることが可能となる。このため、発光ダイオード１の発光効率を高めることができる。 In the present embodiment, as shown in FIG. 4, the angle α formed by the inclined surface 3b and the surface parallel to the light emitting surface is preferably in the range of 55 degrees to 80 degrees. By setting it as such a range, the light reflected by the bottom part of the functional board | substrate 3 can be efficiently taken out outside.
In addition, the width (thickness direction) of the vertical surface 3a is preferably in the range of 30 μm to 100 μm. By setting the width of the vertical surface 3a within the above range, the light reflected at the bottom of the functional substrate 3 can be efficiently returned to the light emitting surface at the vertical surface 3a, and further emitted from the main light extraction surface. It becomes possible. For this reason, the light emission efficiency of the light emitting diode 1 can be improved.
　また、機能性基板３の傾斜面３ｂは、粗面化されることが好ましい。傾斜面３ｂが粗面化されることにより、この傾斜面３ｂでの光取り出し効率を上げる効果が得られる。すなわち、傾斜面３ｂを粗面化することにより、傾斜面３ｂでの全反射を抑制して、光取り出し効率を上げることができる。 In addition, the inclined surface 3b of the functional substrate 3 is preferably roughened. By roughening the inclined surface 3b, an effect of increasing the light extraction efficiency at the inclined surface 3b can be obtained. That is, by roughening the inclined surface 3b, total reflection on the inclined surface 3b can be suppressed and light extraction efficiency can be increased.
　また、機能性基板３は、発光波長に対して９０％以上の反射率を有し、前記発光部に対向して配置する反射層（図示せず）を備えることができる。この構成では、主たる光取り出し面から効率的に光を取り出すことができる。
　反射層は、例えば、銀（Ａｇ）、アルミニウム（Ａｌ）、金（Ａｕ）又はこれらの合金などにより構成される。これらの材料は光反射率が高く、反射層２３からの光反射率を９０％以上とすることができる。
　機能性基板３は、この反射層に、ＡｕＩｎ、ＡｕＧｅ、ＡｕＳｎ等の共晶金属で、発光部と熱膨張係数の近いシリコン、ゲルマニウム等の安価な基板に接合する組み合わせを用いることができる。特にＡｕＩｎは、接合温度が低く、熱膨張係数が発光部と差があるが、最も安価なシリコン基板（シリコン層）を接合するには、最適な組み合わせである。
　機能性基板３は、電流拡散層、反射金属および共晶金属が相互拡散しないよう、例えば、Ｔｉ，Ｗ、Ｐｔなどの高融点金属または、ＩＴＯなどの透明導電酸化物を挿入することも、品質の安定性から望ましい。 In addition, the functional substrate 3 can include a reflective layer (not shown) having a reflectance of 90% or more with respect to the emission wavelength and disposed to face the light emitting unit. With this configuration, light can be efficiently extracted from the main light extraction surface.
The reflective layer is made of, for example, silver (Ag), aluminum (Al), gold (Au), or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective layer 23 can be 90% or more.
The functional substrate 3 can use a combination of eutectic metal such as AuIn, AuGe, AuSn, and the like and bonded to an inexpensive substrate such as silicon or germanium having a thermal expansion coefficient close to that of the light emitting portion. In particular, AuIn has a low bonding temperature and a thermal expansion coefficient different from that of the light emitting part, but is an optimal combination for bonding the cheapest silicon substrate (silicon layer).
For the functional substrate 3, for example, a refractory metal such as Ti, W, Pt or a transparent conductive oxide such as ITO may be inserted so that the current diffusion layer, the reflective metal and the eutectic metal do not interdiffuse. Desirable because of its stability.
　化合物半導体層２と機能性基板３との接合界面は、高抵抗層とする場合がある。すなわち、化合物半導体層２と機能性基板３との間には、図示略の高抵抗層が設けられている場合がある。この高抵抗層は、機能性基板３よりも高い抵抗値を示し、高抵抗層が設けられている場合には化合物半導体層２の電流拡散層８側から機能性基板３側への逆方向の電流を低減する機能を有している。また、機能性基板３側から電流拡散層８側へと不用意に印加される逆方向の電圧に対して耐電圧性を発揮する接合構造を構成しているが、その降伏電圧は、ｐｎ接合型の発光部７の逆方向電圧より低い値となる様に構成することが好ましい。 The bonding interface between the compound semiconductor layer 2 and the functional substrate 3 may be a high resistance layer. That is, a high resistance layer (not shown) may be provided between the compound semiconductor layer 2 and the functional substrate 3. This high resistance layer exhibits a higher resistance value than that of the functional substrate 3, and when the high resistance layer is provided, the compound semiconductor layer 2 has a reverse direction from the current diffusion layer 8 side to the functional substrate 3 side. It has a function of reducing current. Moreover, although the junction structure which exhibits voltage resistance with respect to the voltage of the reverse direction applied carelessly from the functional board | substrate 3 side to the current spreading | diffusion layer side is comprised, the breakdown voltage is a pn junction. It is preferable to configure so as to have a value lower than the reverse voltage of the light emitting unit 7 of the mold.
　ｎ型オーミック電極（第１の電極）４およびｐ型オーミック電極（第２の電極）５は、発光ダイオード１の主たる光取り出し面に設けられた低抵抗のオーミック接触電極である。ここで、ｎ型オーミック電極４は、上部クラッド層１１の上方に設けられており、例えば、ＡｕＧｅ、Ｎｉ合金／Ａｕからなる合金を用いることができる。一方、ｐ型オーミック電極５は、図４に示すように、露出させた電流拡散層８の表面にＡｕＢｅ／Ａｕ、またはＡｕＺｎ／Ａｕからなる合金を用いることができる。 The n-type ohmic electrode (first electrode) 4 and the p-type ohmic electrode (second electrode) 5 are low-resistance ohmic contact electrodes provided on the main light extraction surface of the light-emitting diode 1. Here, the n-type ohmic electrode 4 is provided above the upper cladding layer 11, and for example, an alloy made of AuGe, Ni alloy / Au can be used. On the other hand, as shown in FIG. 4, the p-type ohmic electrode 5 can use AuBe / Au or an alloy made of AuZn / Au on the exposed surface of the current diffusion layer 8.
　ここで、本実施形態の発光ダイオード１では、第２の電極としてｐ型オーミック電極５を、電流拡散層８上に形成することが好ましい。このような構成とすることにより、作動電圧を下げる効果が得られる。また、ｐ型オーミック電極５をｐ型ＧａＰからなる電流拡散層８上に形成することにより、良好なオーミックコンタクトが得られるため、作動電圧を下げることができる。 Here, in the light emitting diode 1 of the present embodiment, it is preferable to form the p-type ohmic electrode 5 on the current diffusion layer 8 as the second electrode. By setting it as such a structure, the effect of reducing an operating voltage is acquired. Further, by forming the p-type ohmic electrode 5 on the current diffusion layer 8 made of p-type GaP, a good ohmic contact can be obtained, so that the operating voltage can be lowered.
　なお、本実施形態では、第１の電極の極性をｎ型とし、第２の電極の極性をｐ型とするのが好ましい。このような構成とすることにより、発光ダイオード１の高輝度化を達成することができる。一方、第１の電極をｐ型とすると、電流拡散が悪くなり、輝度の低下を招く。これに対して、第１の電極をｎ型とすることにより、電流拡散が良くなり、発光ダイオード１の高輝度化を達成することができる。 In this embodiment, it is preferable that the polarity of the first electrode is n-type and the polarity of the second electrode is p-type. By adopting such a configuration, it is possible to achieve high brightness of the light emitting diode 1. On the other hand, if the first electrode is p-type, current diffusion is deteriorated, resulting in a decrease in luminance. On the other hand, by making the first electrode n-type, current diffusion is improved, and high luminance of the light emitting diode 1 can be achieved.
　本実施形態の発光ダイオード１では、図３に示すように、ｎ型オーミック電極４とｐ型オーミック電極５とが対角の位置となるように配置することが好ましい。また、ｐ型オーミック電極５の周囲を、化合物半導体層２で囲んだ構成とすることが最も好ましい。このような構成とすることにより、作動電圧を下げる効果が得られる。また、ｐ型オーミック電極５の四方をｎ型オーミック電極４で囲むことにより、電流が四方に流れやすくなり、その結果作動電圧が低下する。 In the light emitting diode 1 of the present embodiment, it is preferable that the n-type ohmic electrode 4 and the p-type ohmic electrode 5 are arranged at diagonal positions as shown in FIG. The p-type ohmic electrode 5 is most preferably surrounded by the compound semiconductor layer 2. By setting it as such a structure, the effect of reducing an operating voltage is acquired. Further, by enclosing the four sides of the p-type ohmic electrode 5 with the n-type ohmic electrode 4, the current easily flows in the four directions, and as a result, the operating voltage decreases.
　また、本実施形態の発光ダイオード１では、図３に示すように、ｎ型オーミック電極４を、ハニカム、格子形状など網目とすることが好ましい。このような構成とすることにより、信頼性を向上させる効果が得られる。また、格子状とすることにより、活性層１１に均一に電流を注入することができ、その結果、信頼性を向上させる効果が得られる。
　なお、本実施形態の発光ダイオード１では、ｎ型オーミック電極４を、パッド形状の電極（パッド電極）と幅１０μｍ以下の線状の電極（線状電極）とで構成することが好ましい。このような構成とすることにより、高輝度化をはかることができる。さらに、線状電極の幅を狭くすることにより、光取り出し面の開口面積を上げることができ、高輝度化を達成することができる。
　第３の電極は、機能性基板の裏面に形成され、透明基板に於いては、基板側へ反射する構造にすることで、更なる高出力化ができる。反射金属材料としては、Ａｕ、Ａｇ、Ａｌなどの材料が使用できる。
　また、電極表面側を例えば、ＡｕＳｎ等の共晶金属、半田材料にすることで、ダイボンド工程で、ペーストを使用する必要がなくなり簡易化される。更に、金属で接続することで、熱伝導がよくなり、発光ダイオードの放熱特性が向上する。 Moreover, in the light emitting diode 1 of this embodiment, as shown in FIG. 3, it is preferable that the n-type ohmic electrode 4 has a mesh such as a honeycomb or a lattice shape. With such a configuration, an effect of improving reliability can be obtained. Further, by using the lattice shape, a current can be uniformly injected into the active layer 11, and as a result, an effect of improving reliability can be obtained.
In the light emitting diode 1 of this embodiment, the n-type ohmic electrode 4 is preferably composed of a pad-shaped electrode (pad electrode) and a linear electrode (linear electrode) having a width of 10 μm or less. With such a configuration, high luminance can be achieved. Furthermore, by reducing the width of the linear electrode, the opening area of the light extraction surface can be increased, and high luminance can be achieved.
The third electrode is formed on the back surface of the functional substrate, and in the case of a transparent substrate, the output can be further increased by reflecting the substrate. As the reflective metal material, materials such as Au, Ag, and Al can be used.
Further, by using eutectic metal such as AuSn and solder material on the electrode surface side, it is not necessary to use a paste in the die bonding process, which is simplified. Furthermore, by connecting with metal, heat conduction is improved, and the heat dissipation characteristics of the light emitting diode are improved.
＜発光ダイオードの製造方法＞
　次に、本実施形態の発光ダイオード１の製造方法について説明する。図１２は、本実施形態の発光ダイオード１に用いるエピウェーハの断面図である。また、図１３は、本実施形態の発光ダイオード１に用いる接合ウェーハの断面図である。 <Method for manufacturing light-emitting diode>
Next, the manufacturing method of the light emitting diode 1 of this embodiment is demonstrated. FIG. 12 is a cross-sectional view of an epi-wafer used for the light-emitting diode 1 of the present embodiment. FIG. 13 is a cross-sectional view of a bonded wafer used for the light emitting diode 1 of the present embodiment.
（化合物半導体層の形成工程）
　まず、図１２に示す、化合物半導体層２を作製する。化合物半導体層２は、ＧａＡｓ基板１４上に、ＧａＡｓからなる緩衝層１５、選択エッチングに利用するために設けられたエッチングストップ層（図示略）、Ｓｉをドープしたｎ型のコンタクト層１６、ｎ型の上部クラッド層１３、上部ガイド層１２、活性層１１、下部ガイド層１０、ｐ型の下部クラッド層９、Ｍｇドープしたｐ型ＧａＰからなる電流拡散層８を順次積層して作製する。 (Formation process of compound semiconductor layer)
First, the compound semiconductor layer 2 shown in FIG. 12 is produced. The compound semiconductor layer 2 includes a buffer layer 15 made of GaAs on an GaAs substrate 14, an etching stop layer (not shown) provided for use in selective etching, an n-type contact layer 16 doped with Si, an n-type The upper cladding layer 13, the upper guide layer 12, the active layer 11, the lower guide layer 10, the p-type lower cladding layer 9, and the current diffusion layer 8 made of Mg-doped p-type GaP are sequentially stacked.
　ＧａＡｓ基板１４は、公知の製法で作製された市販品の単結晶基板を使用することができる。ＧａＡｓ基板１４のエピタキシャル成長させる表面は、平滑であることが望ましい。ＧａＡｓ基板１４の表面の面方位は、エピタキシャル成長しやすく、量産されている（１００）面および（１００）から、±２０°以内にオフした基板が、品質の安定性の面から望ましい。さらに、ＧａＡｓ基板１４の面方位の範囲が、（１００）方向から（０－１－１）方向に１５°オフ±５°であることがより好ましい。
　尚、本明細書では、ミラー指数の表記において、“－”はその直後の指数につくバーを意味する。 As the GaAs substrate 14, a commercially available single crystal substrate manufactured by a known manufacturing method can be used. The surface of the GaAs substrate 14 on which the epitaxial growth is performed is desirably smooth. The surface orientation of the surface of the GaAs substrate 14 is easy to epitaxially grow, and a substrate that is turned off within ± 20 ° from the (100) plane and (100) that are mass-produced is desirable from the standpoint of quality stability. Furthermore, the range of the plane orientation of the GaAs substrate 14 is more preferably 15 ° off ± 5 ° from the (100) direction to the (0-1-1) direction.
In this specification, in the notation of Miller index, “-” means a bar attached to the index immediately after that.
　ＧａＡｓ基板１４の転位密度は、化合物半導体層２の結晶性を良くするために低い方が望ましい。具体的には、例えば、１０，０００個ｃｍ－２以下、望ましくは、１，０００個ｃｍ－２以下であることが好適である。 The dislocation density of the GaAs substrate 14 is desirably low in order to improve the crystallinity of the compound semiconductor layer 2. Specifically, for example, 10,000 pieces cm −2 or less, preferably 1,000 pieces cm −2 or less are suitable.
　ＧａＡｓ基板１４は、ｎ型であってもｐ型であっても良い。ＧａＡｓ基板１４のキャリア濃度は、所望の電気伝導度と素子構造から、適宜選択することができる。例えば、ＧａＡｓ基板１４がシリコンドープのｎ型である場合には、キャリア濃度が１×１０１７～５×１０１８ｃｍ－３の範囲であることが好ましい。これに対して、ＧａＡｓ基板１４が亜鉛をドープしたｐ型の場合には、キャリア濃度２×１０１８～５×１０１９ｃｍ－３の範囲であることが好ましい。 The GaAs substrate 14 may be n-type or p-type. The carrier concentration of the GaAs substrate 14 can be appropriately selected from desired electrical conductivity and element structure. For example, when the GaAs substrate 14 is a silicon-doped n-type, the carrier concentration is preferably in the range of 1 × 10 17 to 5 × 10 18 cm −3 . On the other hand, when the GaAs substrate 14 is p-type doped with zinc, the carrier concentration is preferably in the range of 2 × 10 18 to 5 × 10 19 cm −3 .
　ＧａＡｓ基板１４の厚さは、基板のサイズに応じて適切な範囲がある。ＧａＡｓ基板１４の厚さが適切な範囲よりも薄いと、化合物半導体層２の製造プロセス中に割れてしまうおそれがある。一方、ＧａＡｓ基板１４の厚さが適切な範囲よりも厚いと材料コストが増加することになる。このため、ＧａＡｓ基板１４の基板サイズが大きい場合、例えば、直径７５ｍｍの場合には、ハンドリング時の割れを防止するために２５０～５００μｍの厚さが望ましい。同様に、直径５０ｍｍの場合は、２００～４００μｍの厚さが望ましく、直径１００ｍｍの場合は、３５０～６００μｍの厚さが望ましい。 The thickness of the GaAs substrate 14 has an appropriate range depending on the size of the substrate. If the thickness of the GaAs substrate 14 is thinner than an appropriate range, the compound semiconductor layer 2 may be broken during the manufacturing process. On the other hand, when the thickness of the GaAs substrate 14 is thicker than an appropriate range, the material cost increases. Therefore, when the substrate size of the GaAs substrate 14 is large, for example, when the diameter is 75 mm, a thickness of 250 to 500 μm is desirable to prevent cracking during handling. Similarly, when the diameter is 50 mm, a thickness of 200 to 400 μm is desirable, and when the diameter is 100 mm, a thickness of 350 to 600 μm is desirable.
　このように、ＧａＡｓ基板１４の基板サイズに応じて基板の厚さを厚くすることにより、発光部７に起因する化合物半導体層２の反りを低減することができる。これにより、エピタキシャル成長中の温度分布が均一となることため、活性層１１の面内の波長分布を小さくすることができる。なお、ＧａＡｓ基板１４の形状は、特に円形に限定されず、矩形等であっても問題ない。 Thus, by increasing the thickness of the substrate according to the substrate size of the GaAs substrate 14, the warpage of the compound semiconductor layer 2 due to the light emitting portion 7 can be reduced. As a result, the temperature distribution during epitaxial growth becomes uniform, so that the in-plane wavelength distribution of the active layer 11 can be reduced. The shape of the GaAs substrate 14 is not particularly limited to a circle, and there is no problem even if it is a rectangle or the like.
　緩衝層（ｂｕｆｆｅｒ）１５は、ＧａＡｓ基板１４と発光部７の構成層との欠陥の伝搬を低減するために設けられている。このため、基板の品質やエピタキシャル成長条件を選択すれば、緩衝層１５は、必ずしも必要ではない。また、緩衝層１５の材質は、エピタキシャル成長させる基板と同じ材質とすることが好ましい。したがって、本実施形態では、緩衝層１５には、ＧａＡｓ基板１４と同じくＧａＡｓを用いることが好ましい。また、緩衝層１５には、欠陥の伝搬を低減するためにＧａＡｓ基板１４と異なる材質からなる多層膜を用いることもできる。緩衝層１５の厚さは、０．１μｍ以上とすることが好ましく、０．２μｍ以上とすることがより好ましい。 The buffer layer 15 is provided to reduce the propagation of defects between the GaAs substrate 14 and the constituent layers of the light emitting unit 7. For this reason, the buffer layer 15 is not necessarily required if the quality of the substrate and the epitaxial growth conditions are selected. The buffer layer 15 is preferably made of the same material as that of the substrate to be epitaxially grown. Therefore, in the present embodiment, it is preferable to use GaAs for the buffer layer 15 as with the GaAs substrate 14. The buffer layer 15 can also be a multilayer film made of a material different from that of the GaAs substrate 14 in order to reduce the propagation of defects. The thickness of the buffer layer 15 is preferably 0.1 μm or more, and more preferably 0.2 μm or more.
　コンタクト層１６（図４では省略）は、電極との接触抵抗を低下させるために設けられている。コンタクト層１６の材質は、活性層１１よりバンドギャップの大きい材質であることが好ましく、ＡｌＸＧａ１－ＸＡｓ、（ＡｌＸＧａ１－Ｘ）ＹＩｎ１－ＹＰ（０≦Ｘ≦１，０＜Ｙ≦１）を好適に用いることができる。また、コンタクト層１６のキャリア濃度の下限値は、電極との接触抵抗を低下させるために５×１０１７ｃｍ－３以上であることが好ましく、１×１０１８ｃｍ－３以上がより好ましい。キャリア濃度の上限値は、結晶性の低下が起こりやすくなる２×１０１９ｃｍ－３以下が望ましい。コンタクト層１６の厚さは、０．５μｍ以上が好ましく、１μｍ以上が最適である。コンタクト層１６の厚さの上限値は特に限定されてはいないが、エピタキシャル成長に係るコストを適正範囲にするため、５μｍ以下とすることが望ましい。 The contact layer 16 (omitted in FIG. 4) is provided to reduce the contact resistance with the electrode. The material of the contact layer 16 is preferably a material having a band gap larger than that of the active layer 11, and Al X Ga 1-X As, (Al X Ga 1-X ) Y In 1-YP (0 ≦ X ≦ 1) , 0 <Y ≦ 1) can be preferably used. The lower limit value of the carrier concentration of the contact layer 16 is preferably 5 × 10 17 cm −3 or more and more preferably 1 × 10 18 cm −3 or more in order to reduce the contact resistance with the electrode. The upper limit value of the carrier concentration is desirably 2 × 10 19 cm −3 or less at which the crystallinity is likely to decrease. The thickness of the contact layer 16 is preferably 0.5 μm or more, and optimally 1 μm or more. The upper limit value of the thickness of the contact layer 16 is not particularly limited, but is desirably 5 μm or less in order to bring the cost for epitaxial growth to an appropriate range.
　本実施形態では、分子線エピタキシャル法（ＭＢＥ）や減圧有機金属化学気相堆積法（ＭＯＣＶＤ法）等の公知の成長方法を適用することができる。なかでも、量産性に優れるＭＯＣＶＤ法を適用することが、最も望ましい。具体的には、化合物半導体層２のエピタキシャル成長に使用するＧａＡｓ基板１４は、成長前に洗浄工程や熱処理等の前処理を実施して、表面の汚染や自然酸化膜を除去することが望ましい。上記化合物半導体層２を構成する各層は、直径５０～１５０ｍｍのＧａＡｓ基板１４をＭＯＣＶＤ装置内にセットし、同時にエピタキシャル成長させて積層することができる。また、ＭＯＣＶＤ装置としては、自公転型、高速回転型等の市販の大型装置を適用することができる。 In this embodiment, a known growth method such as a molecular beam epitaxial method (MBE) or a low pressure metal organic chemical vapor deposition method (MOCVD method) can be applied. Among these, it is most desirable to apply the MOCVD method which is excellent in mass productivity. Specifically, the GaAs substrate 14 used for the epitaxial growth of the compound semiconductor layer 2 is preferably subjected to a pretreatment such as a cleaning process or a heat treatment before the growth to remove surface contamination or a natural oxide film. The layers constituting the compound semiconductor layer 2 can be laminated by setting a GaAs substrate 14 having a diameter of 50 to 150 mm in an MOCVD apparatus and simultaneously epitaxially growing it. As the MOCVD apparatus, a commercially available large-sized apparatus such as a self-revolving type or a high-speed rotating type can be applied.
　上記化合物半導体層２の各層をエピタキシャル成長する際、ＩＩＩ族構成元素の原料としては、例えば、トリメチルアルミニウム（（ＣＨ３）３Ａｌ）、トリメチルガリウム（（ＣＨ３）３Ｇａ）及びトリメチルインジウム（（ＣＨ３）３Ｉｎ）を用いることができる。また、Ｍｇのドーピング原料としては、例えば、ビスシクロペンタジエニルマグネシウム（ｂｉｓ－（Ｃ５Ｈ５）２Ｍｇ）等を用いることができる。また、Ｓｉのドーピング原料としては、例えば、ジシラン（Ｓｉ２Ｈ６）等を用いることができる。
　また、Ｖ族構成元素の原料としては、ホスフィン（ＰＨ３）、アルシン（ＡｓＨ３）等を用いることができる。
　また、各層の成長温度としては、電流拡散層８としてｐ型ＧａＰを用いる場合は、７２０～７７０℃を適用することができ、その他の各層では６００～７００℃を適用することができる。
　また、電流拡散層８としてｐ型ＧａＩｎＰを用いる場合は、６００～７００℃を適用することができる。
　さらに、各層のキャリア濃度及び層厚、温度条件は、適宜選択することができる。 When each layer of the compound semiconductor layer 2 is epitaxially grown, examples of the group III constituent material include trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga), and trimethylindium ((CH 3 ) 3 In) can be used. As a Mg doping material, for example, biscyclopentadienyl magnesium (bis- (C 5 H 5 ) 2 Mg) or the like can be used. Further, as a Si doping material, for example, disilane (Si 2 H 6 ) or the like can be used.
In addition, phosphine (PH 3 ), arsine (AsH 3 ), or the like can be used as a raw material for the group V constituent element.
As the growth temperature of each layer, 720 to 770 ° C. can be applied when p-type GaP is used as the current diffusion layer 8, and 600 to 700 ° C. can be applied to the other layers.
When p-type GaInP is used as the current diffusion layer 8, 600 to 700 ° C. can be applied.
Furthermore, the carrier concentration, layer thickness, and temperature conditions of each layer can be selected as appropriate.
　このようにして作製した化合物半導体層２は、発光部７を有するにもかかわらず結晶欠陥が少ない良好な表面状態が得られる。また、化合物半導体層２は、素子構造に対応して研磨などの表面加工を施しても良い。 The compound semiconductor layer 2 produced in this way has a good surface state with few crystal defects despite having the light emitting portion 7. The compound semiconductor layer 2 may be subjected to surface processing such as polishing corresponding to the element structure.
（機能性基板の接合工程）
　次に、化合物半導体層２と機能性基板３とを接合する。
　化合物半導体層２と機能性基板３との接合は、まず、化合物半導体層２を構成する電流拡散層８の表面を研磨して、鏡面加工する。次に、この電流拡散層８の鏡面研磨した表面に貼付する機能性基板３を用意する。なお、この機能性基板３の表面は、電流拡散層８に接合させる以前に鏡面に研磨する。次に、一般の半導体材料貼付装置に、化合物半導体層２と機能性基板３とを搬入し、真空中で鏡面研磨した双方の表面に電子を衝突させて中性（ニュートラル）化したＡｒビームを照射する。その後、真空を維持した貼付装置内で双方の表面を重ね合わせて荷重をかけることで、室温で接合することができる（図１３参照）。接合に関しては、接合条件の安定性から、接合面が同じ材質がより望ましい。
　接合（貼り付け）はこのような真空下での常温接合が最適であるが、共晶金属、接着剤を用いて接合することもできる。 (Functional substrate bonding process)
Next, the compound semiconductor layer 2 and the functional substrate 3 are bonded.
In joining the compound semiconductor layer 2 and the functional substrate 3, first, the surface of the current diffusion layer 8 constituting the compound semiconductor layer 2 is polished and mirror-finished. Next, the functional substrate 3 to be attached to the mirror-polished surface of the current spreading layer 8 is prepared. The surface of the functional substrate 3 is polished to a mirror surface before being bonded to the current diffusion layer 8. Next, the compound semiconductor layer 2 and the functional substrate 3 are carried into a general semiconductor material pasting apparatus, and electrons are collided with both surfaces which are mirror-polished in a vacuum to make the neutral (neutral) Ar beam. Irradiate. Then, it can join at room temperature by superimposing both surfaces in the sticking apparatus which maintained the vacuum, and applying a load (refer FIG. 13). With respect to bonding, materials having the same bonding surface are more desirable from the viewpoint of stability of bonding conditions.
Bonding (pasting) is optimally performed at room temperature bonding under such a vacuum, but bonding can also be performed using a eutectic metal or an adhesive.
（第１及び第２の電極の形成工程）
　次に、第１の電極であるｎ型オーミック電極４及び第２の電極であるｐ型オーミック電極５を形成する。
　ｎ型オーミック電極４及びｐ型オーミック電極５の形成は、まず、機能性基板３と接合した化合物半導体層２から、ＧａＡｓ基板１４及び緩衝層１５をアンモニア系エッチャントによって選択的に除去する。次に、露出したコンタクト層１６の表面にｎ型オーミック電極４を形成する。具体的には、例えば、ＡｕＧｅ、Ｎｉ合金／Ｐｔ／Ａｕを任意の厚さとなるように真空蒸着法により積層した後、一般的なフォトリソグラフィー手段を利用してパターニングを行ってｎ型オーミック電極４の形状を形成する。 (First and second electrode forming steps)
Next, an n-type ohmic electrode 4 that is a first electrode and a p-type ohmic electrode 5 that is a second electrode are formed.
In forming the n-type ohmic electrode 4 and the p-type ohmic electrode 5, first, the GaAs substrate 14 and the buffer layer 15 are selectively removed from the compound semiconductor layer 2 bonded to the functional substrate 3 with an ammonia-based etchant. Next, the n-type ohmic electrode 4 is formed on the exposed surface of the contact layer 16. Specifically, for example, AuGe, Ni alloy / Pt / Au are laminated by a vacuum deposition method so as to have an arbitrary thickness, and then patterned by using a general photolithography means to form the n-type ohmic electrode 4. Form the shape.
　次に、コンタクト層１６、上部クラッド層１３、上部ガイド層１２、活性層１１、下部ガイド層１０、ｐ型の下部クラッド層９の所定範囲について選択的に除去して電流拡散層８を露出させ、この露出した電流拡散層８の表面にｐ型オーミック電極５を形成する。具体的には、例えば、ＡｕＢｅ／Ａｕを任意の厚さとなるように真空蒸着法により積層した後、一般的なフォトリソグラフィー手段を利用してパターニングを行ってｐ型オーミック電極５の形状を形成する。その後、例えば４００～５００℃、５～２０分間の条件で熱処理を行って合金化することにより、低抵抗のｎ型オーミック電極４及びｐ型オーミック電極５を形成することができる。 Next, the current diffusion layer 8 is exposed by selectively removing a predetermined range of the contact layer 16, the upper cladding layer 13, the upper guide layer 12, the active layer 11, the lower guide layer 10, and the p-type lower cladding layer 9. Then, the p-type ohmic electrode 5 is formed on the exposed surface of the current diffusion layer 8. Specifically, for example, AuBe / Au is laminated by vacuum deposition so as to have an arbitrary thickness, and then patterned using a general photolithography means to form the shape of the p-type ohmic electrode 5. . Thereafter, the low resistance n-type ohmic electrode 4 and p-type ohmic electrode 5 can be formed, for example, by alloying by heat treatment at 400 to 500 ° C. for 5 to 20 minutes.
（第３の電極の形成工程）
　　第３の電極は、機能性基板の裏面に形成される。素子の構造により、オーミック電極、ショットキー電極、反射機能、共晶ダイボンド構造などの機能を組み合わせ付加できる。透明基板に於いては、Ａｕ、Ａｇ、Ａｌなどの材料を形成し、反射する構造にする。基板と前記材料の間に、例えば、酸化ケイ素、ＩＴＯなどの透明膜を挿入できる。形成方法は、スパッタ法、蒸着法など公知の技術を利用できる。
　また、電極表面側を例えば、ＡｕＳｎ等の共晶金属、鉛フリー半田材料などにすることで、ダイボンド工程で、ペーストを使用する必要がなくなり簡易化される。形成方法は、スパッタ法、蒸着法、めっき、印刷など公知の技術を利用できる。
　金属で接続することで、熱伝導がよくなり、発光ダイオードの放熱特性が向上する。
前記の2つの機能を組み合わせる場合は、金属が拡散しないようにバリア金属、酸化物を挿入することも好適な方法である。これらは、素子構造、基板材料により、最適なものを選択できる。 (Third electrode forming step)
The third electrode is formed on the back surface of the functional substrate. Depending on the structure of the element, functions such as an ohmic electrode, a Schottky electrode, a reflection function, and a eutectic die bond structure can be combined and added. In the transparent substrate, a material such as Au, Ag, or Al is formed to reflect the light. For example, a transparent film such as silicon oxide or ITO can be inserted between the substrate and the material. As a forming method, a known technique such as a sputtering method or a vapor deposition method can be used.
Further, by using eutectic metal such as AuSn, lead-free solder material, etc. on the electrode surface side, it is not necessary to use paste in the die-bonding process, thereby simplifying. As a forming method, known techniques such as sputtering, vapor deposition, plating, and printing can be used.
By connecting with metal, heat conduction is improved and heat dissipation characteristics of the light emitting diode are improved.
In the case of combining the above two functions, it is also preferable to insert a barrier metal and an oxide so that the metal does not diffuse. These can be selected optimally depending on the element structure and the substrate material.
（機能性基板の加工工程）
　次に、機能性基板３の形状を加工する。
　機能性基板３の加工は、まず、第３の電極６を形成していない表面にＶ字状の溝入れを行う。この際、Ｖ字状の溝の第３の電極６側の内側面が発光面に平行な面とのなす角度αを有する傾斜面３ｂとなる。次に、化合物半導体層２側から所定の間隔でダイシングを行ってチップ化する。なお、チップ化の際のダイシングによって機能性基板３の垂直面３ａが形成される。 (Functional substrate processing process)
Next, the shape of the functional substrate 3 is processed.
In processing the functional substrate 3, first, V-shaped grooving is performed on the surface on which the third electrode 6 is not formed. At this time, the inner surface of the V-shaped groove on the third electrode 6 side becomes an inclined surface 3b having an angle α formed with a surface parallel to the light emitting surface. Next, dicing is performed from the compound semiconductor layer 2 side at predetermined intervals to form chips. In addition, the vertical surface 3a of the functional substrate 3 is formed by dicing at the time of chip formation.
　傾斜面３ｂの形成方法は、特に限定されるものではなく、ウェットエッチング、ドライエッチング、スクライブ法、レーザー加工などの従来からの方法を組み合わせて用いることができるが、形状の制御性及び生産性の高いダイシング法を適用することが最も好ましい。ダイシング法を適用することにより、製造歩留まりを向上することができる。 The formation method of the inclined surface 3b is not particularly limited, and conventional methods such as wet etching, dry etching, scribing, and laser processing can be used in combination, but the shape controllability and productivity can be improved. Most preferably, a high dicing method is applied. By applying the dicing method, the manufacturing yield can be improved.
　また、垂直面３ａの形成方法は、特に限定されるものではないが、レーザー加工、スクライブ・ブレーク法又はダイシング法で形成するのが好ましい。
　レーザー加工、スクライブ・ブレーク法を採用することにより、製造コストを低下させることができる。すなわち、チップ分離の際に切りしろを設ける必要なく、数多くの発光ダイオードが製造できるため製造コストを下げることができる。
　一方、ダイシング法は、切断の安定性に優れている。 The method for forming the vertical surface 3a is not particularly limited, but it is preferably formed by laser processing, a scribe / break method or a dicing method.
By employing the laser processing and the scribe / break method, the manufacturing cost can be reduced. That is, since it is not necessary to provide a margin for chip separation and many light emitting diodes can be manufactured, the manufacturing cost can be reduced.
On the other hand, the dicing method is excellent in cutting stability.
　最後に、破砕層及び汚れを必要に応じて硫酸・過酸化水素混合液等でエッチング除去する。このようにして発光ダイオード１を製造する。 Finally, the crushed layer and dirt are removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide as necessary. In this way, the light emitting diode 1 is manufactured.
　以上説明したように、本実施形態の発光ダイオード１によれば、組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層１７を有する発光部７を含む化合物半導体層２を備えている。 As described above, according to the light-emitting diode 1 of this embodiment, the compound semiconductor layer including the light-emitting portion 7 having the well layer 17 having the composition formula (In X1 Ga 1 -X1 ) As (0 ≦ X1 ≦ 1). 2 is provided.
　また、本実施形態の発光ダイオード１では、発光部７上に電流拡散層８が設けられている。この電流拡散層８は、発光波長に対して透明であるため、発光部７からの発光を吸収することなく高出力・高効率の発光ダイオード１とすることができる。機能性基板は、材質的に安定で、腐食の心配がなく耐湿性に優れている。 Further, in the light emitting diode 1 of the present embodiment, the current diffusion layer 8 is provided on the light emitting unit 7. Since the current spreading layer 8 is transparent with respect to the emission wavelength, the light-emitting diode 1 having high output and high efficiency can be obtained without absorbing the light emitted from the light emitting unit 7. The functional substrate is stable in material, has no fear of corrosion, and has excellent moisture resistance.
　したがって、本実施形態の発光ダイオード１によれば、８５０ｎｍ以上の発光波長を有し、単色性に優れると共に、高出力・高効率であって耐湿性の発光ダイオード１を提供することができる。また、本実施形態の発光ダイオード１によれば、従来の液相エピタキシャル法で作製した透明基板型ＡｌＧaＡｓ系の発光ダイオードと比較して、約２倍以上の発光効率を有する高出力発光ダイオード１を提供することができる。また、高温高湿信頼性も向上した。 Therefore, according to the light emitting diode 1 of the present embodiment, it is possible to provide the light emitting diode 1 having a light emission wavelength of 850 nm or more, excellent monochromaticity, high output, high efficiency, and moisture resistance. Further, according to the light emitting diode 1 of the present embodiment, the high output light emitting diode 1 having a light emission efficiency of about twice or more as compared with a transparent substrate type AlGaAs light emitting diode manufactured by a conventional liquid phase epitaxial method. Can be provided. Also, high temperature and high humidity reliability was improved.
＜発光ダイオード（第２の実施形態）＞
　図１４Ａ及びＢは、本発明を適用した第２の実施形態に係る発光ダイオードを説明するための図であり、図１４Ａは平面図、図１４Ｂは図１４Ａ中に示すＣ－Ｃ’線に沿った断面図である（ガイド層１０及び１２は図示省略）。
　第２の実施形態に係る発光ダイオードは、組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層１７と、組成式（ＡｌＸ２Ｇａ１－Ｘ２）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ２≦１，０＜Ｙ１≦１）からなるバリア層１８とを交互に積層した量子井戸構造の活性層１１と、活性層１１を挟む、組成式（ＡｌＸ３Ｇａ１－Ｘ３）Ｙ２Ｉｎ１－Ｙ２Ｐ（０≦Ｘ３≦１，０＜Ｙ２≦１）からなる第１のガイド層１０及び第２のガイド層１２と、第１のガイド層１０及び第２のガイド層１２のそれぞれを介して活性層１１を挟む第１のクラッド層９及び第２のクラッド層１３とを有する発光部７と、発光部７上に形成された電流拡散層８と、発光部７に対向して配置され、発光波長に対して９０％以上の反射率を有する反射層２３を含み、電流拡散層８に接合された機能性基板３１と、を備え、第１のクラッド層９及び第２のクラッド層１３が組成式（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ３Ｉｎ１－Ｙ３Ｐ；０≦Ｘ４≦１，０＜Ｙ３≦１）からなることを特徴とする。 <Light Emitting Diode (Second Embodiment)>
14A and 14B are views for explaining a light emitting diode according to a second embodiment to which the present invention is applied. FIG. 14A is a plan view, and FIG. 14B is along the line CC ′ shown in FIG. 14A. (The guide layers 10 and 12 are not shown).
The light emitting diode according to the second embodiment includes a well layer 17 having a composition formula (In X1 Ga 1-X1 ) As (0 ≦ X1 ≦ 1), a composition formula (Al X2 Ga 1-X2 ) Y1 In 1 − A composition formula (Al X3 Ga 1-X3) sandwiching the active layer 11 and the active layer 11 having a quantum well structure in which the barrier layers 18 composed of Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1) are alternately stacked. ) First guide layer 10 and second guide layer 12 made of Y2 In 1-Y2 P (0 ≦ X3 ≦ 1, 0 <Y2 ≦ 1), and first guide layer 10 and second guide layer 12 The light emitting part 7 having the first clad layer 9 and the second clad layer 13 sandwiching the active layer 11 therebetween, the current diffusion layer 8 formed on the light emitting part 7, and the light emitting part 7. Reflection having a reflectance of 90% or more with respect to the emission wavelength. Comprises 23, comprises a functional substrate 31 which is joined to the current diffusion layer 8, the first cladding layer 9 and the second cladding layer 13 is a composition formula (Al X4 Ga 1-X4) Y3 In 1-Y3 P; 0 ≦ X4 ≦ 1, 0 <Y3 ≦ 1).
　第２の実施形態に係る発光ダイオードでは、発光波長に対して９０％以上の反射率を有し、発光部７に対向して配置する反射層２３を含む機能性基板３１を有するので、主たる光取り出し面から効率的に光を取り出すことができる。
　図１４Ａ及び図１４Ｂに示した例では、機能性基板３１は、電流拡散層８の下側の面８ｂに、第２の電極２１を備え、さらにその第２の電極２１を覆うように透明導電膜２２と反射層２３とが積層されてなる反射構造体と、シリコン又はゲルマニウムからなる層(基板)３０を備えている。 The light-emitting diode according to the second embodiment has a functional substrate 31 that has a reflectance of 90% or more with respect to the emission wavelength and includes the reflective layer 23 disposed to face the light-emitting portion 7. Light can be efficiently extracted from the extraction surface.
In the example shown in FIGS. 14A and 14B, the functional substrate 31 includes the second electrode 21 on the lower surface 8 b of the current diffusion layer 8, and further transparent conductive so as to cover the second electrode 21. A reflective structure in which a film 22 and a reflective layer 23 are laminated, and a layer (substrate) 30 made of silicon or germanium are provided.
　第２の実施形態に係る発光ダイオードにおいては、機能性基板３１はシリコンまたはゲルマニウムからなる層を含むのが好ましい。腐食しにくい材質である為、耐湿性が向上するからである。 In the light emitting diode according to the second embodiment, the functional substrate 31 preferably includes a layer made of silicon or germanium. This is because the material is not easily corroded, so that the moisture resistance is improved.
　反射層２３は例えば、銀（Ａｇ）、アルミニウム（Ａｌ）、金（Ａｕ）又はこれらの合金などにより構成される。これらの材料は光反射率が高く、反射層２３からの光反射率を９０％以上とすることができる。
　機能性基板３１は、この反射層２３に、ＡｕＩｎ、ＡｕＧｅ、ＡｕＳｎ等の共晶金属で、シリコン、ゲルマニウム等の安価な基板（層）に接合する組み合わせを用いることができる。特にＡｕＩｎは、接合温度が低く、熱膨張係数が発光部と差があるが、最も安価なシリコン基板（シリコン層）を接合するには最適な組み合わせである。
　機能性基板３１はさらに、電流拡散層、反射層金属および共晶金属が相互拡散しないよう、例えば、チタン（Ｔｉ）、タングステン（Ｗ）、白金（Ｐｔ）などの高融点金属からなる層を挿入された構成とすることも品質の安定性から望ましい。 The reflective layer 23 is made of, for example, silver (Ag), aluminum (Al), gold (Au), or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective layer 23 can be 90% or more.
In the functional substrate 31, a combination of eutectic metal such as AuIn, AuGe, AuSn and the like and bonded to an inexpensive substrate (layer) such as silicon or germanium can be used for the functional layer 31. In particular, AuIn has a low bonding temperature and a thermal expansion coefficient different from that of the light emitting portion, but is an optimal combination for bonding the cheapest silicon substrate (silicon layer).
The functional substrate 31 is further inserted with a layer made of a refractory metal such as titanium (Ti), tungsten (W), or platinum (Pt) so that the current diffusion layer, the reflective layer metal, and the eutectic metal do not interdiffuse. It is also desirable from the standpoint of quality stability to have a configured configuration.
＜発光ダイオード（第３の実施形態）＞
　図１５は、本発明を適用した第３の実施形態に係る発光ダイオードを説明するための図である。
　第３の実施形態に係る発光ダイオードは、組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層１７と、組成式（ＡｌＸ２Ｇａ１－Ｘ２）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ２≦１，０＜Ｙ１≦１）からなるバリア層１８とを交互に積層した量子井戸構造の活性層１１と、活性層１１を挟む、組成式（ＡｌＸ３Ｇａ１－Ｘ３）Ｙ２Ｉｎ１－Ｙ２Ｐ（０≦Ｘ３≦１，０＜Ｙ２≦１）からなる第１のガイド層１０及び第２のガイド層１２と、第１のガイド層１０及び第２のガイド層１２のそれぞれを介して活性層１１を挟む第１のクラッド層９及び第２のクラッド層１３とを有する発光部７と、発光部７上に形成された電流拡散層８と、発光部７に対向して配置され、発光波長に対して９０％以上の反射率を有する反射層５３と金属基板５０とを含み、電流拡散層８に接合された機能性基板５１と、を備え、第１のクラッド層９及び第２のクラッド層１３が組成式（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ３Ｉｎ１－Ｙ３Ｐ；０≦Ｘ４≦１，０＜Ｙ３≦１）からなることを特徴とする。 <Light Emitting Diode (Third Embodiment)>
FIG. 15 is a diagram for explaining a light emitting diode according to a third embodiment to which the present invention is applied.
The light emitting diode according to the third embodiment includes a well layer 17 having a composition formula (In X1 Ga 1-X1 ) As (0 ≦ X1 ≦ 1), a composition formula (Al X2 Ga 1-X2 ) Y1 In 1 − A composition formula (Al X3 Ga 1-X3) sandwiching the active layer 11 and the active layer 11 having a quantum well structure in which the barrier layers 18 composed of Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1) are alternately stacked. ) First guide layer 10 and second guide layer 12 made of Y2 In 1-Y2 P (0 ≦ X3 ≦ 1, 0 <Y2 ≦ 1), and first guide layer 10 and second guide layer 12 The light emitting part 7 having the first clad layer 9 and the second clad layer 13 sandwiching the active layer 11 therebetween, the current diffusion layer 8 formed on the light emitting part 7, and the light emitting part 7. Reflection having a reflectance of 90% or more with respect to the emission wavelength. And a 53 and the metal substrate 50 comprises a functional substrate 51 which is joined to the current diffusion layer 8, the first cladding layer 9 and the second cladding layer 13 is a composition formula (Al X4 Ga 1-X4) Y3 In 1-Y3 P; 0 ≦ X4 ≦ 1, 0 <Y3 ≦ 1).
　第３の実施形態に係る発光ダイオードでは、機能性基板が金属基板を含む点が第２の実施形態に係る発光ダイオードに対して特徴的な構成である。
　金属基板５０は放熱性が高く、発光ダイオードを高輝度で発光するのに寄与すると共に、発光ダイオードの寿命を長寿命とすることができる。
　放熱性の観点からは、金属基板５０は熱伝導率が１３０Ｗ／ｍ・Ｋ以上の金属からなるのが特に好ましい。熱伝導率が１３０Ｗ／ｍ・Ｋ以上の金属としては、例えば、モリブデン（１３８Ｗ／ｍ・Ｋ）やタングステン（１７４Ｗ／ｍ・Ｋ）、銀（熱伝導率＝４２０Ｗ／ｍ・Ｋ）、銅（熱伝導率＝３９８Ｗ／ｍ・Ｋ）、金（熱伝導率＝３２０Ｗ／ｍ・Ｋ）、アルミニウム（熱伝導率＝２３６Ｗ／ｍ・Ｋ）がある。 The light-emitting diode according to the third embodiment is a characteristic configuration with respect to the light-emitting diode according to the second embodiment in that the functional substrate includes a metal substrate.
The metal substrate 50 has high heat dissipation, contributes to light emission of the light emitting diode with high luminance, and can extend the life of the light emitting diode.
From the viewpoint of heat dissipation, the metal substrate 50 is particularly preferably made of a metal having a thermal conductivity of 130 W / m · K or more. Examples of metals having a thermal conductivity of 130 W / m · K or more include molybdenum (138 W / m · K), tungsten (174 W / m · K), silver (thermal conductivity = 420 W / m · K), copper ( There are thermal conductivity = 398 W / m · K), gold (thermal conductivity = 320 W / m · K), and aluminum (thermal conductivity = 236 W / m · K).
　図１５に示すように、化合物半導体層２は、活性層１１と、ガイド層（図示せず）を介してその活性層１１を挟む第１のクラッド層（下部クラッド）９及び第２のクラッド層（上部クラッド）１３と、第１のクラッド層（下部クラッド）９の下側に電流拡散層８と、第２のクラッド層（上部クラッド）１３の上側に第１の電極５５と平面視してほぼ同じサイズのコンタクト層５６とを有する。
　機能性基板５１は、電流拡散層８の下側の面８ｂに、第２の電極５７を備え、さらにその第２の電極５７を覆うように透明導電膜５２と反射層５３とが積層されてなる反射構造体と、金属基板５０とからなり、反射構造体を構成する反射層５３の化合物半導体層２と反対側の面５３ｂに、金属基板５０の接合面５０ａが接合されている。 As shown in FIG. 15, the compound semiconductor layer 2 includes an active layer 11, a first clad layer (lower clad) 9 and a second clad layer sandwiching the active layer 11 via a guide layer (not shown). (Upper clad) 13, the current diffusion layer 8 below the first clad layer (lower clad) 9, and the first electrode 55 above the second clad layer (upper clad) 13 in plan view. A contact layer 56 having substantially the same size.
The functional substrate 51 includes a second electrode 57 on the lower surface 8 b of the current diffusion layer 8, and a transparent conductive film 52 and a reflective layer 53 are laminated so as to cover the second electrode 57. The joining surface 50a of the metal substrate 50 is joined to the surface 53b on the opposite side of the compound semiconductor layer 2 of the reflecting layer 53 constituting the reflecting structure.
　反射層５３は例えば、銅、銀、金、アルミニウムなどの金属又はこれらの合金などにより構成される。これらの材料は光反射率が高く、反射構造体からの光反射率を９０％以上とすることができる。反射層５３を形成することにより、活性層１１からの光を反射層５３で正面方向ｆへ反射させて、正面方向ｆでの光取り出し効率を向上させることができる。これにより、発光ダイオードをより高輝度化できる。 The reflective layer 53 is made of, for example, a metal such as copper, silver, gold, or aluminum, or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective structure can be 90% or more. By forming the reflective layer 53, the light from the active layer 11 is reflected by the reflective layer 53 in the front direction f, and the light extraction efficiency in the front direction f can be improved. Thereby, the brightness of the light emitting diode can be further increased.
　反射層５３は、透明導電膜５２側からＡｇ、Ｎｉ／Ｔｉバリア層、Ａｕ系の共晶金属（接続用金属）からなる積層構造が好ましい。
　上記接続用金属は、電気抵抗が低く、低温で溶融する金属である。上記接続用金属を用いることにより、化合物半導体層２に熱ストレスを与えることなく、金属基板を接続することができる。
　接続用金属としては、化学的に安定で、融点の低いＡｕ系の共晶金属などを用いられる。上記Ａｕ系の共晶金属としては、例えば、ＡｕＳｎ、ＡｕＧｅ、ＡｕＳｉなどの合金の共晶組成（Ａｕ系の共晶金属）を挙げることができる。
　また、接続用金属には、チタン、クロム、タングステンなどの金属を添加することが好ましい。これにより、チタン、クロム、タングステンなどの金属がバリア金属として機能して、金属基板に含まれる不純物などが反射層５３側に拡散して、反応することを抑制できる。 The reflective layer 53 preferably has a laminated structure made of Ag, a Ni / Ti barrier layer, and an Au-based eutectic metal (connecting metal) from the transparent conductive film 52 side.
The connecting metal is a metal that has a low electrical resistance and melts at a low temperature. By using the connecting metal, the metal substrate can be connected without applying thermal stress to the compound semiconductor layer 2.
As the connection metal, an Au-based eutectic metal that is chemically stable and has a low melting point is used. Examples of the Au-based eutectic metal include eutectic compositions of alloys such as AuSn, AuGe, and AuSi (Au-based eutectic metal).
Further, it is preferable to add a metal such as titanium, chromium, or tungsten to the connection metal. Thereby, metals such as titanium, chromium, and tungsten can function as a barrier metal, and impurities contained in the metal substrate can be prevented from diffusing and reacting on the reflective layer 53 side.
　透明導電膜５２は、ＩＴＯ膜、ＩＺＯ膜などにより構成されている。なお、反射構造体は、反射層５３だけで構成してもよい。
　また、透明導電膜５２の代わりに、または、透明導電膜５２とともに、透明な材料の屈折率差を利用したいわゆるコールドミラー、例えば、酸化チタン膜、酸化ケイ素膜の多層膜や白色のアルミナ、ＡｌＮを用いて、反射層５３に組み合わせてもよい。 The transparent conductive film 52 is composed of an ITO film, an IZO film, or the like. Note that the reflective structure may be composed of only the reflective layer 53.
Further, instead of the transparent conductive film 52 or together with the transparent conductive film 52, a so-called cold mirror using a difference in refractive index of a transparent material, for example, a multilayer film of titanium oxide film, silicon oxide film, white alumina, AlN May be combined with the reflective layer 53.
　金属基板５０は複数の金属層からなるものを用いることができる。
　複数の金属層の構成としては図１５で示した例のように、２種類の金属層すなわち、第１の金属層５０Ａと第２の金属層５０Ｂとが交互に積層されてなるものが好ましい。
　特に、第１の金属層５０Ａと第２の金属層５０Ｂの層数は合わせて奇数とすることがより好ましい。 The metal substrate 50 can be made of a plurality of metal layers.
As the configuration of the plurality of metal layers, it is preferable that two types of metal layers, that is, the first metal layer 50A and the second metal layer 50B are alternately stacked as in the example shown in FIG.
In particular, it is more preferable that the first metal layer 50A and the second metal layer 50B have an odd number of layers.
　この場合、金属基板の反りや割れの観点から、第２の金属層５０Ｂとして化合物半導体層２より熱膨張係数が小さい材料を用いるときは、第１の金属層５０Ａ、５０Ａを化合物半導体層３より熱膨張係数が大きい材料からなるものを用いるのが好ましい。金属基板全体としての熱膨張係数が化合物半導体層の熱膨張係数に近いものとなるため、化合物半導体層と金属基板とを接合する際の金属基板の反りや割れを抑制することができ、発光ダイオードの製造歩留まりを向上させることができるからである。同様に、第２の金属層５０Ｂとして化合物半導体層２より熱膨張係数が大きい材料を用いるときは、第１の金属層５０Ａ、５０Ａを化合物半導体層２より熱膨張係数が小さい材料からなるものを用いるのが好ましい。金属基板全体としての熱膨張係数が化合物半導体層の熱膨張係数に近いものとなるため、化合物半導体層と金属基板とを接合する際の金属基板の反りや割れを抑制でき、発光ダイオードの製造歩留まりを向上できるからである。
　以上の観点からは、２種類の金属層はいずれが第１の金属層でも第２の金属層でも構わない。 In this case, from the viewpoint of warping and cracking of the metal substrate, when a material having a smaller thermal expansion coefficient than the compound semiconductor layer 2 is used as the second metal layer 50B, the first metal layers 50A and 50A are more than the compound semiconductor layer 3. It is preferable to use a material made of a material having a large thermal expansion coefficient. Since the thermal expansion coefficient of the metal substrate as a whole is close to the thermal expansion coefficient of the compound semiconductor layer, it is possible to suppress warping and cracking of the metal substrate when the compound semiconductor layer and the metal substrate are joined, and the light emitting diode This is because the production yield can be improved. Similarly, when a material having a larger thermal expansion coefficient than the compound semiconductor layer 2 is used as the second metal layer 50B, the first metal layers 50A and 50A are made of a material having a smaller thermal expansion coefficient than the compound semiconductor layer 2. It is preferable to use it. Since the thermal expansion coefficient of the metal substrate as a whole is close to the thermal expansion coefficient of the compound semiconductor layer, it is possible to suppress warping and cracking of the metal substrate when joining the compound semiconductor layer and the metal substrate, and the production yield of light emitting diodes It is because it can improve.
From the above viewpoint, any of the two types of metal layers may be the first metal layer or the second metal layer.
　２種類の金属層としては、例えば、銀（熱膨張係数＝１８．９ｐｐｍ／Ｋ）、銅（熱膨張係数＝１６．５ｐｐｍ／Ｋ）、金（熱膨張係数＝１４．２ｐｐｍ／Ｋ）、アルミニウム（熱膨張係数＝２３．１ｐｐｍ／Ｋ）、ニッケル（熱膨張係数＝１３．４ｐｐｍ／Ｋ）およびこれらの合金のいずれかからなる金属層と、モリブデン（熱膨張係数＝５．１ｐｐｍ／Ｋ）、タングステン（熱膨張係数＝４．３ｐｐｍ／Ｋ）、クロム（熱膨張係数＝４．９ｐｐｍ／Ｋ）およびこれらの合金のいずれかからなる金属層との組み合わせを用いることができる。
　好適な例としては、Ｃｕ／Ｍｏ／Ｃｕの３層からなる金属基板があげられる。上記の観点ではＭｏ／Ｃｕ／Ｍｏの３層からなる金属基板でも同様な効果が得られるが、Ｃｕ／Ｍｏ／Ｃｕの３層からなる金属基板は、機械的強度が高いＭｏを加工しやすいＣｕで挟んだ構成なので、Ｍｏ／Ｃｕ／Ｍｏの３層からなる金属基板よりも切断等の加工が容易であるという利点がある。 Examples of the two metal layers include silver (thermal expansion coefficient = 18.9 ppm / K), copper (thermal expansion coefficient = 16.5 ppm / K), gold (thermal expansion coefficient = 14.2 ppm / K), and aluminum. (Thermal expansion coefficient = 23.1 ppm / K), nickel (thermal expansion coefficient = 13.4 ppm / K) and a metal layer made of any of these alloys, molybdenum (thermal expansion coefficient = 5.1 ppm / K), Combinations of tungsten (thermal expansion coefficient = 4.3 ppm / K), chromium (thermal expansion coefficient = 4.9 ppm / K), and a metal layer made of any of these alloys can be used.
A preferred example is a metal substrate composed of three layers of Cu / Mo / Cu. From the above viewpoint, the same effect can be obtained with a metal substrate composed of three layers of Mo / Cu / Mo, but the metal substrate composed of three layers of Cu / Mo / Cu is a Cu layer that has high mechanical strength and is easy to process Mo. Therefore, there is an advantage that processing such as cutting is easier than a metal substrate composed of three layers of Mo / Cu / Mo.
　金属基板全体としての熱膨張係数は例えば、Ｃｕ（３０μｍ）／Ｍｏ（２５μｍ）／Ｃｕ（３０μｍ）の３層からなる金属基板では６．１ｐｐｍ／Ｋであり、Ｍｏ（２５μｍ）／Ｃｕ（７０μｍ）／Ｍｏ（２５μｍ）の３層からなる金属基板では５．７ｐｐｍ／Ｋとなる。 The thermal expansion coefficient of the entire metal substrate is, for example, 6.1 ppm / K for a three-layer metal substrate of Cu (30 μm) / Mo (25 μm) / Cu (30 μm), and Mo (25 μm) / Cu (70 μm). In the case of a metal substrate composed of three layers of / Mo (25 μm), it is 5.7 ppm / K.
　また、放熱の観点からは、金属基板を構成する金属層は熱伝導率が高い材料からなるのが好ましい。これにより、金属基板の放熱性を高くして、発光ダイオードを高輝度で発光させることができるとともに、発光ダイオードの寿命を長寿命とすることができるからである。
　例えば、銀（熱伝導率＝４２０Ｗ／ｍ・Ｋ）、銅（熱伝導率＝３９８Ｗ／ｍ・Ｋ）、金（熱伝導率＝３２０Ｗ／ｍ・Ｋ）、アルミニウム（熱伝導率＝２３６Ｗ／ｍ・Ｋ）、モリブデン（熱伝導率＝１３８Ｗ／ｍ・Ｋ）、タングステン（熱伝導率＝１７４Ｗ／ｍ・Ｋ）およびこれらの合金などを用いることが好ましい。 From the viewpoint of heat dissipation, the metal layer constituting the metal substrate is preferably made of a material having high thermal conductivity. This is because the heat dissipation of the metal substrate can be increased, the light emitting diode can emit light with high brightness, and the life of the light emitting diode can be extended.
For example, silver (thermal conductivity = 420 W / m · K), copper (thermal conductivity = 398 W / m · K), gold (thermal conductivity = 320 W / m · K), aluminum (thermal conductivity = 236 W / m) · K), molybdenum (thermal conductivity = 138 W / m · K), tungsten (thermal conductivity = 174 W / m · K), and alloys thereof are preferably used.
　それらの金属層の熱膨張係数が化合物半導体層の熱膨張係数と略等しい材料からなるのがさらに好ましい。特に、金属層の材料が、化合物半導体層の熱膨張係数の±１．５ｐｐｍ／Ｋ以内である熱膨張係数を有する材料であるのが好ましい。これにより、金属基板と化合物半導体層との接合時の発光部への熱によるストレスを小さくすることができ、金属基板を化合物半導体層と接続させたときの熱による金属基板の割れを抑制することができ、発光ダイオードの製造歩留まりを向上させることができる。
　金属基板全体としての熱伝導率は例えば、Ｃｕ（３０μｍ）／Ｍｏ（２５μｍ）／Ｃｕ（３０μｍ）の３層からなる金属基板では２５０Ｗ／ｍ・Ｋとなり、Ｍｏ（２５μｍ）／Ｃｕ（７０μｍ）／Ｍｏ（２５μｍ）の３層からなる金属基板では２２０Ｗ／ｍ・Ｋとなる。 More preferably, the metal layers are made of a material having a thermal expansion coefficient substantially equal to that of the compound semiconductor layer. In particular, the material of the metal layer is preferably a material having a thermal expansion coefficient that is within ± 1.5 ppm / K of the thermal expansion coefficient of the compound semiconductor layer. As a result, it is possible to reduce stress due to heat applied to the light emitting portion when the metal substrate and the compound semiconductor layer are joined, and to suppress cracking of the metal substrate due to heat when the metal substrate is connected to the compound semiconductor layer. The manufacturing yield of the light emitting diode can be improved.
The thermal conductivity of the entire metal substrate is, for example, 250 W / m · K for a three-layer metal substrate of Cu (30 μm) / Mo (25 μm) / Cu (30 μm), and Mo (25 μm) / Cu (70 μm) / In the case of a metal substrate composed of three layers of Mo (25 μm), it is 220 W / m · K.
　以下、本発明の効果を、実施例を用いて具体的に説明する。なお、本発明はこれらの実施例に限定されるものではない。 Hereinafter, the effects of the present invention will be described in detail with reference to examples. The present invention is not limited to these examples.
　本実施例では、本発明に係る発光ダイオードを作製した例を具体的に説明する。また、本実施例で作製した発光ダイオードは、ＩｎＧａＡｓからなる井戸層とＡｌＧａＩｎＰからなるバリア層との量子井戸構造からなる活性層を有する赤外発光ダイオードである。本実施例では、ＧａＡｓ基板上に成長させた化合物半導体層と機能性基板とを結合させて発光ダイオードを作製した。そして、特性評価のために発光ダイオードチップを基板上に実装した発光ダイオードランプを作製した。 In this example, an example in which a light emitting diode according to the present invention is manufactured will be specifically described. The light-emitting diode manufactured in this example is an infrared light-emitting diode having an active layer having a quantum well structure of a well layer made of InGaAs and a barrier layer made of AlGaInP. In this example, a compound semiconductor layer grown on a GaAs substrate and a functional substrate were combined to produce a light emitting diode. Then, a light-emitting diode lamp having a light-emitting diode chip mounted on a substrate was prepared for characteristic evaluation.
（実施例１）
　実施例１は図４に示した実施形態の実施例である。
　実施例１の発光ダイオードは、まず、Ｓｉをドープしたｎ型のＧａＡｓ単結晶からなるＧａＡｓ基板上に、化合物半導体層を順次積層してエピタキシャルウェーハを作製した。
ＧａＡｓ基板は、（１００）面から（０－１－１）方向に１５°傾けた面を成長面とし、キャリア濃度を２×１０１８ｃｍ－３とした。化合物半導体層としては、ＳｉをドープしたＧａＡｓからなるｎ型の緩衝層、Ｓｉをドープした（Ａｌ０．７Ｇａ０．３）０．５Ｉｎ０．５Ｐからなるｎ型のコンタクト層、Ｓｉをドープした（Ａｌ０．７Ｇａ０．３）０．５Ｉｎ０．５Ｐからなるｎ型の上部クラッド層、（Ａｌ０．３　Ｇａ０．７　）０．５　Ｉｎ０．５　Ｐからなる上部ガイド層、Ｉｎ０．２　Ｇａ０．８　Ａｓ／（Ａｌ０．１Ｇａ０．９　）０．５　Ｉｎ０．５Ｐの３対からなる井戸層／バリア層、（Ａｌ０．３　Ｇａ０．７）０．５　Ｉｎ０．５Ｐからなる下部ガイド層、Ｍｇをドープした（Ａｌ０．７Ｇａ０．３）０．５Ｉｎ０．５Ｐからなるｐ型の下部クラッド層、（Ａｌ０．５Ｇａ０．５）０．５Ｉｎ０．５Ｐからなる薄膜の中間層、Ｍｇドープしたｐ型ＧａＰからなる電流拡散層を用いた。 Example 1
Example 1 is an example of the embodiment shown in FIG.
In the light emitting diode of Example 1, first, an epitaxial wafer was fabricated by sequentially laminating compound semiconductor layers on a GaAs substrate made of an n-type GaAs single crystal doped with Si.
In the GaAs substrate, the plane inclined by 15 ° from the (100) plane in the (0-1-1) direction was used as the growth plane, and the carrier concentration was set to 2 × 10 18 cm −3 . As the compound semiconductor layer, an n-type buffer layer made of GaAs doped with Si, an n-type contact layer made of Si-doped (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P, Si N-type upper clad layer made of (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P, doped with (Al 0.3 Ga 0.7 ) 0.5 In 0.5 P Upper guide layer, well layer / barrier layer composed of three pairs of In 0.2 Ga 0.8 As / (Al 0.1 Ga 0.9 ) 0.5 In 0.5 P, (Al 0.3 Ga 0 .7) 0.5 in 0.5 lower guide layer made of P, doped with Mg (Al 0.7 Ga 0.3) p-type lower cladding layer composed of 0.5 in 0.5 P, (Al 0.5 Ga 0.5) an intermediate layer of a thin film made of 0.5 in 0.5 P, M Using current diffusion layer made of doped p-type GaP.
　本実施例では、減圧有機金属化学気相堆積装置法（ＭＯＣＶＤ装置）を用い、直径７６ｍｍ、厚さ３５０μｍのＧａＡｓ基板に化合物半導体層をエピタキシャル成長させて、エピタキシャルウェーハを形成した。エピタキシャル成長層を成長させる際、ＩＩＩ族構成元素の原料としては、トリメチルアルミニウム（（ＣＨ３）３Ａｌ）、トリメチルガリウム（（ＣＨ３）３Ｇａ）及びトリメチルインジウム（（ＣＨ３）３Ｉｎ）を使用した。また、Ｍｇのドーピング原料としては、ビスシクロペンタジエニルマグネシウム（ｂｉｓ－（Ｃ５Ｈ５）２Ｍｇ）を使用した。また、Ｓｉのドーピング原料としては、ジシラン（Ｓｉ２Ｈ６）を使用した。また、Ｖ族構成元素の原料としては、ホスフィン（ＰＨ３）、アルシン（ＡｓＨ３）を使用した。また、各層の成長温度としては、ｐ型ＧａＰからなる電流拡散層は、７５０℃で成長させた。その他の各層では７００℃で成長させた。 In this example, a compound semiconductor layer was epitaxially grown on a GaAs substrate having a diameter of 76 mm and a thickness of 350 μm by using a low pressure metal organic chemical vapor deposition apparatus method (MOCVD apparatus) to form an epitaxial wafer. When growing an epitaxial growth layer, trimethylaluminum ((CH 3 ) 3 Al), trimethylgallium ((CH 3 ) 3 Ga) and trimethylindium ((CH 3 ) 3 In) are used as the raw material for the group III constituent element did. Further, biscyclopentadienyl magnesium (bis- (C 5 H 5 ) 2 Mg) was used as a Mg doping material. Further, disilane (Si 2 H 6 ) was used as a Si doping material. Further, phosphine (PH 3 ) and arsine (AsH 3 ) were used as raw materials for the group V constituent elements. As the growth temperature of each layer, the current diffusion layer made of p-type GaP was grown at 750 ° C. The other layers were grown at 700 ° C.
　ＧａＡｓからなる緩衝層は、キャリア濃度を約２×１０１８ｃｍ－３、層厚を約０．５μｍとした。コンタクト層は、キャリア濃度を約２×１０１８ｃｍ－３、層厚を４μｍとした。上部クラッド層は、キャリア濃度を約１×１０１８ｃｍ－３、層厚を約０．５μｍとした。上部ガイド層は、アンドープで層厚を約５０ｎｍとした。井戸層は、アンドープで層厚が約５ｎｍのＩｎ０．２　Ｇａ０．８　Ａｓとし、バリア層はアンドープで層厚が約１０ｎｍの（Ａｌ０．１Ｇａ０．９　）０．５　Ｉｎ０．５Ｐとした。また、井戸層とバリア層とを交互に３対積層した。下部ガイド層は、アンドープで層厚を約５０ｎｍとした。下部クラッド層は、キャリア濃度を約８×１０１７ｃｍ－３、層厚を約０．５μｍとした。中間層は、キャリア濃度を約８×１０１７ｃｍ－３、層厚を約５０ｎｍとした。
　ＧａＰからなる電流拡散層は、キャリア濃度を約３×１０１８ｃｍ－３、層厚を約１０μｍとした。 The buffer layer made of GaAs has a carrier concentration of about 2 × 10 18 cm −3 and a layer thickness of about 0.5 μm. The contact layer had a carrier concentration of about 2 × 10 18 cm −3 and a layer thickness of 4 μm. The upper cladding layer had a carrier concentration of about 1 × 10 18 cm −3 and a layer thickness of about 0.5 μm. The upper guide layer was undoped and had a thickness of about 50 nm. The well layer is undoped In 0.2 Ga 0.8 As with a thickness of about 5 nm, and the barrier layer is undoped (Al 0.1 Ga 0.9 ) 0.5 In 0. 5 P. Three pairs of well layers and barrier layers were alternately laminated. The lower guide layer was undoped and had a thickness of about 50 nm. The lower cladding layer had a carrier concentration of about 8 × 10 17 cm −3 and a layer thickness of about 0.5 μm. The intermediate layer had a carrier concentration of about 8 × 10 17 cm −3 and a layer thickness of about 50 nm.
The current diffusion layer made of GaP has a carrier concentration of about 3 × 10 18 cm −3 and a layer thickness of about 10 μm.
　次に、電流拡散層を表面から約１μｍの深さに至る領域まで研磨して、鏡面加工した。
この鏡面加工によって、電流拡散層の表面の粗さ（ｒｍｓ）を０．１８ｎｍとした。
　一方、上記の電流拡散層の鏡面研磨した表面に貼付するｎ型ＧａＰからなる機能性基板を用意した。この貼付用の機能性基板には、キャリア濃度が約２×１０１７ｃｍ－３となるようにＳｉを添加し、面方位を（１１１）とした単結晶を用いた。また、機能性基板の直径は７６ｍｍで、厚さは２５０μｍであった。この機能性基板の表面は、電流拡散層に接合させる以前に鏡面に研磨し、表面の粗さ（ｒｍｓ）を０．１２ｎｍに仕上げた。 Next, the current diffusion layer was polished to a region extending from the surface to a depth of about 1 μm and mirror-finished.
By this mirror finishing, the surface roughness (rms) of the current diffusion layer was set to 0.18 nm.
On the other hand, a functional substrate made of n-type GaP to be attached to the mirror-polished surface of the current diffusion layer was prepared. A single crystal having a plane orientation of (111) added with Si so that the carrier concentration was about 2 × 10 17 cm −3 was used for the functional substrate for sticking. The functional substrate had a diameter of 76 mm and a thickness of 250 μm. The surface of this functional substrate was polished to a mirror surface before being bonded to the current spreading layer, and the surface roughness (rms) was finished to 0.12 nm.
　次に、一般の半導体材料貼付装置に、上記の機能性基板及びエピタキシャルウェーハを搬入し、３×１０－５Ｐａとなるまで装置内を真空に排気した。 Next, the functional substrate and the epitaxial wafer were carried into a general semiconductor material sticking apparatus, and the inside of the apparatus was evacuated to 3 × 10 −5 Pa.
　次に、機能性基板、及び電流拡散層の双方の表面に、電子を衝突させて中性（ニュートラル）化したＡｒビームを３分間に亘り照射した。その後、真空に維持した貼付装置内で、機能性基板及び電流拡散層の表面を重ね合わせ、各々の表面での圧力が５０ｇ／ｃｍ２となる様に荷重を掛け、双方を室温で接合した。このようにして接合ウェーハを形成した。 Next, the surface of both the functional substrate and the current spreading layer was irradiated with an Ar beam neutralized by colliding electrons for 3 minutes. Thereafter, the surfaces of the functional substrate and the current diffusion layer were superposed in a sticking apparatus maintained in vacuum, a load was applied so that the pressure on each surface was 50 g / cm 2, and both were bonded at room temperature. In this way, a bonded wafer was formed.
　次に、上記接合ウェーハから、ＧａＡｓ基板およびＧａＡｓ緩衝層をアンモニア系エッチャントにより選択的に除去した。次に、コンタクト層の表面に第１の電極として、ＡｕＧｅ、Ｎｉ合金を厚さが０．５μｍ、Ｐｔを０．２μｍ、Ａｕを１μｍとなるように真空蒸着法によって成膜した。その後、一般的なフォトリソグラフィー手段を利用してパターニングを施し、第１の電極としてｎ型オーミック電極を形成した。次に、ＧａＡｓ基板を除去した面である光取り出し面の表面に粗面化処理を施した。 Next, the GaAs substrate and the GaAs buffer layer were selectively removed from the bonded wafer with an ammonia-based etchant. Next, a first electrode was formed on the surface of the contact layer by vacuum deposition so that the thickness of AuGe and Ni alloy was 0.5 μm, Pt was 0.2 μm, and Au was 1 μm. Then, patterning was performed using a general photolithography means, and an n-type ohmic electrode was formed as the first electrode. Next, the surface of the light extraction surface, which is the surface from which the GaAs substrate was removed, was roughened.
　次に、第２の電極としてｐ型オーミック電極を形成する領域のエピ層を選択的に除去し、電流拡散層を露出させた。この露出した電流拡散層の表面に、ＡｕＢｅを０．２μｍ、Ａｕを１μｍとなるように真空蒸着法でｐ形オーミック電極を形成した。その後、４５０℃で１０分間熱処理を行って合金化し、低抵抗のｐ型およびｎ型オーミック電極を形成した。更に、機能性基板の裏面にＡｕを厚さ０．２μｍ形成し、２２０μｍの正方形にパターンを形成した。 Next, the epi layer in the region where the p-type ohmic electrode is formed as the second electrode was selectively removed to expose the current diffusion layer. A p-type ohmic electrode was formed on the exposed surface of the current diffusion layer by vacuum deposition so that AuBe was 0.2 μm and Au was 1 μm. Thereafter, heat treatment was performed at 450 ° C. for 10 minutes to form an alloy, and low resistance p-type and n-type ohmic electrodes were formed. Furthermore, Au was formed in a thickness of 0.2 μm on the back surface of the functional substrate, and a pattern was formed in a 220 μm square.
　次に、ダイシングソーを用いて、機能性基板の裏面から、第３の電極を形成していない領域を傾斜面の角度αが７０°となると共に垂直面の厚さが８０μｍとなるようにＶ字状の溝入れを行った。次に、化合物半導体層側からダイシングソーを用い３５０μｍ間隔で切断し、チップ化した。ダイシングによる破砕層および汚れを硫酸・過酸化水素混合液でエッチング除去して、実施例１の発光ダイオードを作製した。 Next, using a dicing saw, the region where the third electrode is not formed from the back surface of the functional substrate is set so that the angle α of the inclined surface becomes 70 ° and the thickness of the vertical surface becomes 80 μm. A letter-shaped grooving was performed. Next, a dicing saw was used to cut from the compound semiconductor layer side at 350 μm intervals to form chips. The crushing layer and dirt by dicing were removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to produce a light emitting diode of Example 1.
　上記の様にして作製した実施例１の発光ダイオードチップを、マウント基板上に実装した発光ダイオードランプを１００個組み立てた。この発光ダイオードランプは、マウントは、ダイボンダーで支持（マウント）し、発光ダイオードのｎ型オーミック電極とマウント基板の表面に設けたｎ電極端子とを金線でワイヤボンディングし、ｐ型オーミック電極とｐ電極端子とを金線でワイヤボンディングした後、一般的なエポキシ樹脂で封止して作製した。 100 light-emitting diode lamps each having the light-emitting diode chip of Example 1 manufactured as described above mounted on a mount substrate were assembled. In this light-emitting diode lamp, the mount is supported (mounted) by a die bonder, the n-type ohmic electrode of the light-emitting diode and the n-electrode terminal provided on the surface of the mount substrate are wire-bonded with a gold wire, and the p-type ohmic electrode and the p-type electrode are connected. The electrode terminal was wire bonded with a gold wire and then sealed with a general epoxy resin.
　この発光ダイオード（発光ダイオードランプ）の特性を評価した結果を表７に示す。
表７に示すように、ｎ型及びｐ型オーミック電極間に電流を流したところ、ピーク波長９２０ｎｍとする赤外光が出射された。順方向に２０ミリアンペア（ｍＡ）の電流を通流した際の順方向電圧（Ｖｆ）は、化合物半導体層を構成する電流拡散層と機能性基板との接合界面での抵抗の低さ及び各オーミック電極の良好なオーミック特性を反映し、約１．２２ボルトとなった。順方向電流を２０ｍＡとした際の発光出力は、７ｍＷであった　更に、温度６０℃、湿度９０％の高温高湿環境下で、通電試験（２０ｍＡ通電）を１０００時間実施し、発光出力の残存率を測定した結果を表７に示す。
　このランプ１００個を、６０℃、９０ＲＨ％，２０ｍＡで高温高湿通電試験を実施した。１０００時間後の出力残存率の平均は１００％であった。 Table 7 shows the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp).
As shown in Table 7, when current was passed between the n-type and p-type ohmic electrodes, infrared light having a peak wavelength of 920 nm was emitted. The forward voltage (Vf) when a current of 20 milliamperes (mA) flows in the forward direction is the low resistance at each junction interface between the current diffusion layer constituting the compound semiconductor layer and the functional substrate and each ohmic resistance. Reflecting the good ohmic characteristics of the electrode, it was about 1.22 volts. When the forward current was 20 mA, the light emission output was 7 mW. Furthermore, in a high temperature and high humidity environment with a temperature of 60 ° C. and a humidity of 90%, an energization test (20 mA energization) was conducted for 1000 hours, and the light emission output remained. Table 7 shows the result of measuring the rate.
The 100 lamps were subjected to a high-temperature and high-humidity energization test at 60 ° C., 90 RH%, 20 mA. The average output remaining rate after 1000 hours was 100%.
Figure JPOXMLDOC01-appb-T000007
Figure JPOXMLDOC01-appb-T000007
（実施例２）
　実施例２は図１４Ａ及びＢに示した第２の実施形態の実施例である。
　実施例２の発光ダイオードは、反射層と機能性基板とを組み合わせ場合である。その他の発光部の形成は、実施例１と同じである。尚、下部ガイド層１０及び上部ガイド層１２は図示省略している。 (Example 2)
Example 2 is an example of the second embodiment shown in FIGS. 14A and 14B.
The light emitting diode of Example 2 is a case where a reflective layer and a functional substrate are combined. Other light emitting portions are formed in the same manner as in the first embodiment. The lower guide layer 10 and the upper guide layer 12 are not shown.
　電流拡散層８の表面に、ＡｕＢｅ／Ａｕ合金を厚さ０．２μｍで２０μｍφのドットでなる電極（第２の電極）２１を、光取り出し面の端から５０μｍになるように等間隔で８個配置した。
　次に、透明導電膜であるＩＴＯ膜２２を０．４μｍの厚さでスパッタ法により形成した。更に、銀合金／Ｔｉ／Ａｕでなる層２３を０．２μｍ／０．１μｍ／１μｍの厚さで形成し、反射面２３とした。 On the surface of the current spreading layer 8, eight electrodes (second electrodes) 21 made of 20 μmφ dots of AuBe / Au alloy with a thickness of 0.2 μm are arranged at equal intervals so as to be 50 μm from the end of the light extraction surface. Arranged.
Next, an ITO film 22 which is a transparent conductive film was formed by a sputtering method with a thickness of 0.4 μm. Further, a layer 23 made of silver alloy / Ti / Au was formed to a thickness of 0.2 μm / 0.1 μm / 1 μm to form a reflecting surface 23.
　一方、シリコン基板（機能性基板）３１の表面に、Ｔｉ／Ａｕ／Ｉｎでなる層３２を０．１μｍ／０．５μｍ／０．３μｍの厚さで形成した。シリコン基板３１の裏面に、Ｔｉ／Ａｕでなる層３３を０．１μｍ／０．５μｍの厚さで形成した。前記発光ダイオードウェーハ側のＡｕとシリコン基板側のＩｎ表面とを重ね合わせ、３２０℃で加熱・５００ｇ／ｃｍ２で加圧し、機能性基板を発光ダイオードウェーハに接合した。 On the other hand, a layer 32 made of Ti / Au / In was formed on the surface of a silicon substrate (functional substrate) 31 with a thickness of 0.1 μm / 0.5 μm / 0.3 μm. A layer 33 made of Ti / Au was formed on the back surface of the silicon substrate 31 with a thickness of 0.1 μm / 0.5 μm. The Au on the light emitting diode wafer side and the In surface on the silicon substrate side were superposed and heated at 320 ° C. and pressurized at 500 g / cm 2 to bond the functional substrate to the light emitting diode wafer.
　ＧａＡｓ基板を除去し、コンタクト層１６の表面に、ＡｕＧｅ／Ａｕでなる直径１００μｍで厚さ３μｍのオーミック電極（第１の電極）２５を形成し、４２０℃で、５分間熱処理し、ｐ、ｎオーミック電極を合金化処理した。 The GaAs substrate is removed, an AuGe / Au ohmic electrode (first electrode) 25 having a diameter of 100 μm and a thickness of 3 μm is formed on the surface of the contact layer 16, and heat-treated at 420 ° C. for 5 minutes, p, n The ohmic electrode was alloyed.
　次に、コンタクト層１６の表面を粗面化処理した。
チップに分離する為の切断予定部分の半導体層と反射層、共晶金属を除去し、シリコン基板の裏面電極の上にＴｉ／ＡｕＳn／Ａｕを０．３μｍ／１μｍ／０．１μｍを形成した。ダイシングソーで、３５０μｍピッチで正方形に切断した。　 Next, the surface of the contact layer 16 was roughened.
The semiconductor layer, the reflective layer, and the eutectic metal that were to be cut to be separated into chips were removed, and Ti / AuSn / Au was formed to 0.3 μm / 1 μm / 0.1 μm on the back electrode of the silicon substrate. Dicing saw cut into squares at a pitch of 350 μm.
　この発光ダイオード（発光ダイオードランプ）の特性を評価した結果を表７に示す。
　表７に示すように、上面及び下面の電極間に電流を流したところ、ピーク波長９２０ｎｍとする赤外光が出射された。順方向に２０ミリアンペア（ｍＡ）の電流を通流した際の順方向電圧（Ｖｆ）は、化合物半導体層を構成する電流拡散層と機能性基板との接合界面での抵抗の低さ及び各オーミック電極の良好なオーミック特性を反映し、約１．２０ボルト（Ｖ）となった。順方向電流を２０ｍＡとした際の発光出力は、約６ｍＷであった。更に、温度６０℃、湿度９０％の高温高湿環境下で、通電試験（２０ｍＡ通電）を１０００時間実施し、発光出力の残存率を測定した結果を表７に示す。
　実施例１と同様に、このランプ１００個を、６０℃、９０ＲＨ％，２０ｍＡで高温高湿通電試験を実施した。１０００時間後の出力残存率の平均は９９％であった。 Table 7 shows the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp).
As shown in Table 7, when current was passed between the upper and lower electrodes, infrared light having a peak wavelength of 920 nm was emitted. The forward voltage (Vf) when a current of 20 milliamperes (mA) flows in the forward direction is the low resistance at each junction interface between the current diffusion layer constituting the compound semiconductor layer and the functional substrate and each ohmic resistance. Reflecting the good ohmic characteristics of the electrode, it was about 1.20 volts (V). The light emission output when the forward current was 20 mA was about 6 mW. Furthermore, Table 7 shows the results of conducting an energization test (20 mA energization) for 1000 hours in a high-temperature and high-humidity environment at a temperature of 60 ° C. and a humidity of 90%, and measuring the residual ratio of light emission output.
Similarly to Example 1, 100 lamps were subjected to a high-temperature and high-humidity energization test at 60 ° C., 90 RH%, 20 mA. The average output remaining rate after 1000 hours was 99%.
（実施例３）
　実施例３の発光ダイオードは第３の実施形態の実施例であり、電流拡散層に、反射層と金属基板とを含む機能性基板を接合した構成である。図１５を参照して、実施例３の発光ダイオードを説明する。 (Example 3)
The light-emitting diode of Example 3 is an example of the third embodiment, and has a configuration in which a functional substrate including a reflective layer and a metal substrate is bonded to a current diffusion layer. With reference to FIG. 15, the light-emitting diode of Example 3 will be described.
　まず、金属基板を作製した。２枚の略平板状で厚さ１０μｍのＣｕ板と、１枚の略平板状の厚さ７５μｍのＭｏ板とを用意し、２枚のＣｕ板の間にＭｏ板を挿入してこれらを重ねて配置し、加圧装置に前記基板を配置して、高温下でそれら金属板に対してそれらを挟む方向に荷重をかけた。これにより、Ｃｕ（１０μｍ）／Ｍｏ（７５μｍ）／Ｃｕ（１０μｍ）の３層からなる金属基板を作製した。 First, a metal substrate was produced. Two substantially flat Cu plates with a thickness of 10 μm and one substantially flat Mo plate with a thickness of 75 μm are prepared, and the Mo plates are inserted between the two Cu plates and stacked. And the said board | substrate was arrange | positioned to the pressurization apparatus, and the load was applied in the direction which pinches | interposes them with respect to these metal plates under high temperature. Thus, a metal substrate composed of three layers of Cu (10 μm) / Mo (75 μm) / Cu (10 μm) was produced.
　化合物半導体層は、緩衝層とコンタクト層との間に、Ｓｉドープの（Ａｌ０．５Ｇａ０．５）０．５Ｉｎ０．５Ｐからなり、層厚が０．５μｍのエッチングストップ層を形成した点を除いて、実施例１の条件と同じ条件で形成した。
　電流拡散層８の面８ｂ上に、０．４μｍの厚さのＡｕＢｅ上に０．２μｍの厚さのＡｕが積層されてなり、平面視したときに２０μｍφの円形状であり、６０μｍの間隔で第２の電極５７を形成した。
　次に、透明導電膜であるＩＴＯ膜５２を、第２の電極５７を覆うように、０．８μｍの厚さでスパッタ法により形成した。
　次に、ＩＴＯ膜５２上に、蒸着法を用いて、銀（Ａｇ）合金からなる膜を０．７μｍ成膜した後、ニッケル（Ｎｉ）／チタン（Ｔｉ）からなる膜を０．５μｍ、金（Ａｕ）からなる膜を１μｍ成膜して、反射膜５３を形成した。
　次に、化合物半導体層の電流拡散層８上にＩＴＯ膜５２及び反射膜５３を形成した構造体と、金属基板とを対向して重ね合わせるように配置して減圧装置内に搬入し、４００℃で加熱した状態で、５００ｋｇ重の荷重でそれらを接合して接合構造体を形成した。
　次に、接合構造体から、化合物半導体層の成長基板であるＧａＡｓ基板と緩衝層とをアンモニア系エッチャントにより選択的に除去し、さらに、エッチングストップ層を塩酸系エッチャントにより選択的に除去した。
　次に、真空蒸着法を用いて、コンタクト層上に、ＡｕＧｅを０．１５μｍの厚さで成膜した後、Ｎｉを０．０５μｍの厚さで成膜し、さらにＡｕを１μｍの厚さで成膜して、第１の電極用導電膜を形成した。次に、フォトリソグラフィーを用いて、電極用導電膜を平面視円形状にパターニングして、直径１００μｍで厚さ３μｍの第１の電極５５を作製した。
　次に、第１の電極をマスクとして、アンモニア系エッチャントにより、コンタクト層のうち、第１の電極の下以外の部分をエッチングで除去してコンタクト層５６を形成した。
　チップに分離する為の切断予定部分の化合物半導体層と反射層、共晶金属を除去し、金属基板をレーザーダイシングにより、３５０μｍピッチで正方形に切断した。 Compound semiconductor layer, between the buffer layer and the contact layer, made of (Al 0.5 Ga 0.5) 0.5 In 0.5 P doped with Si, layer thickness 0.5μm of the etching stop layer It formed on the same conditions as Example 1 except the point formed.
On the surface 8b of the current spreading layer 8, Au having a thickness of 0.2 μm is laminated on AuBe having a thickness of 0.4 μm, and when viewed in plan, it has a circular shape of 20 μmφ, with an interval of 60 μm. A second electrode 57 was formed.
Next, an ITO film 52, which is a transparent conductive film, was formed by sputtering to a thickness of 0.8 μm so as to cover the second electrode 57.
Next, a film made of a silver (Ag) alloy is formed to 0.7 μm on the ITO film 52 by vapor deposition, and then a film made of nickel (Ni) / titanium (Ti) is made to 0.5 μm, gold A film made of (Au) was formed to a thickness of 1 μm to form a reflective film 53.
Next, the structure in which the ITO film 52 and the reflective film 53 are formed on the current diffusion layer 8 of the compound semiconductor layer and the metal substrate are arranged so as to face each other and are carried into a decompression apparatus, and are brought to 400 ° C. In the state heated by, they were joined with a load of 500 kg to form a joined structure.
Next, the GaAs substrate, which is a growth substrate for the compound semiconductor layer, and the buffer layer were selectively removed from the bonded structure with an ammonia-based etchant, and the etching stop layer was selectively removed with a hydrochloric acid-based etchant.
Next, using a vacuum deposition method, AuGe is deposited on the contact layer to a thickness of 0.15 μm, Ni is deposited to a thickness of 0.05 μm, and Au is further deposited to a thickness of 1 μm. A first electrode conductive film was formed by film formation. Next, by using photolithography, the electrode conductive film was patterned into a circular shape in plan view, and a first electrode 55 having a diameter of 100 μm and a thickness of 3 μm was produced.
Next, using the first electrode as a mask, the contact layer 56 was formed by etching away the portion of the contact layer except under the first electrode with an ammonia-based etchant.
The compound semiconductor layer, the reflective layer, and the eutectic metal to be cut to be separated into chips were removed, and the metal substrate was cut into squares at a pitch of 350 μm by laser dicing.
　この発光ダイオード（発光ダイオードランプ）の特性を評価した結果を表７に示す。
　表７に示すように、ｎ型及びｐ型オーミック電極間に電流を流したところ、ピーク波長９２０ｎｍとする赤外光が出射された。順方向に２０ミリアンペア（ｍＡ）の電流を通流した際の順方向電圧（ＶＦ）は、化合物半導体層を構成する電流拡散層と機能性基板との接合界面での抵抗の低さ及び各オーミック電極の良好なオーミック特性を反映し、１．２ボルトとなった。順方向電流を２０ｍＡとした際の発光出力は、５．９ｍＷであった。
　このランプ２０個を、６０℃、９０ＲＨ％，２０ｍＡで高温高湿通電試験を実施した。
１０００時間後の、出力残存率の平均は、１００％であった。 Table 7 shows the results of evaluating the characteristics of the light emitting diode (light emitting diode lamp).
As shown in Table 7, when current was passed between the n-type and p-type ohmic electrodes, infrared light having a peak wavelength of 920 nm was emitted. The forward voltage (V F ) when a current of 20 milliamperes (mA) is passed in the forward direction is low in resistance at the junction interface between the current diffusion layer constituting the compound semiconductor layer and the functional substrate. Reflecting the good ohmic characteristics of the ohmic electrode, it was 1.2 volts. The light emission output when the forward current was 20 mA was 5.9 mW.
Twenty lamps were subjected to a high-temperature and high-humidity energization test at 60 ° C., 90 RH%, 20 mA.
The average output remaining rate after 1000 hours was 100%.
（実施例４）
　実施例４の発光ダイオードは第１の実施形態の実施例であり、発光ピーク波長を８７０ｎｍにするべく井戸層のＩｎ組成Ｘ１＝０．１２にしたこと以外は、実施例１と同じ条件で作製した。
　この発光ダイオード（発光ダイオードランプ）の特性を評価した結果は表７に示した通りであり、ピーク波長８７０ｎｍとする赤外光が出射され、発光出力（Ｐ０）、順方向電圧（ＶＦ）、出力残存率の平均はそれぞれ、６．８ｍＷ、１．３１Ｖ、１００％であった。 Example 4
The light-emitting diode of Example 4 is an example of the first embodiment, and is manufactured under the same conditions as in Example 1 except that the In composition X1 of the well layer is set to 0.12 so that the emission peak wavelength is 870 nm. did.
The results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 870 nm is emitted, and the light emission output (P 0 ) and the forward voltage (V F ). The average output residual ratios were 6.8 mW, 1.31 V, and 100%, respectively.
（実施例５）
　実施例５の発光ダイオードは第２の実施形態の実施例であり、発光ピーク波長を８７０ｎｍにするべく井戸層のＩｎ組成Ｘ１＝０．１２にしたこと以外は、実施例２と同じ条件で作製した。
　この発光ダイオード（発光ダイオードランプ）の特性を評価した結果は表７に示した通りであり、ピーク波長８７０ｎｍとする赤外光が出射され、発光出力（Ｐ０）、順方向電圧（ＶＦ）、出力残存率の平均はそれぞれ、６．１ｍＷ、１．３Ｖ、１００％であった。 (Example 5)
The light-emitting diode of Example 5 is an example of the second embodiment, and is manufactured under the same conditions as Example 2 except that the In composition X1 of the well layer is set to 0.12 so that the emission peak wavelength is 870 nm. did.
The results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 870 nm is emitted, and the light emission output (P 0 ) and the forward voltage (V F ). The average output residual ratio was 6.1 mW, 1.3 V, and 100%, respectively.
（実施例６）
　実施例６の発光ダイオードは第１の実施形態の実施例であり、発光ピーク波長を９６０ｎｍにするべく井戸層のＩｎ組成Ｘ１＝０．２５にしたこと以外は、実施例１と同じ条件で作製した。
　この発光ダイオード（発光ダイオードランプ）の特性を評価した結果は表７に示した通りであり、ピーク波長９６０ｎｍとする赤外光が出射され、発光出力（Ｐ０）、順方向電圧（ＶＦ）、出力残存率の平均はそれぞれ、６．５ｍＷ、１．２Ｖ、９９％であった。 (Example 6)
The light-emitting diode of Example 6 is an example of the first embodiment, and is manufactured under the same conditions as Example 1 except that the In composition X1 of the well layer is set to 0.25 so that the emission peak wavelength is 960 nm. did.
The results of evaluating the characteristics of this light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 960 nm is emitted, and the light emission output (P 0 ) and forward voltage (V F ). The average output residual ratio was 6.5 mW, 1.2 V, and 99%, respectively.
（実施例７）
　実施例７の発光ダイオードは第２の実施形態の実施例であり、発光ピーク波長を９６０ｎｍにするべく井戸層のＩｎ組成Ｘ１＝０．２５にしたこと以外は、実施例２と同じ条件で作製した。
　この発光ダイオード（発光ダイオードランプ）の特性を評価した結果は表７に示した通りであり、ピーク波長９６０ｎｍとする赤外光が出射され、発光出力（Ｐ０）、順方向電圧（ＶＦ）、出力残存率の平均はそれぞれ、５．３ｍＷ、１．２Ｖ、９９％であった。 (Example 7)
The light emitting diode of Example 7 is an example of the second embodiment, and is manufactured under the same conditions as Example 2 except that the In composition X1 of the well layer is set to 0.25 in order to set the emission peak wavelength to 960 nm. did.
The results of evaluating the characteristics of this light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 960 nm is emitted, and the light emission output (P 0 ) and forward voltage (V F ). The average output residual ratio was 5.3 mW, 1.2 V, and 99%, respectively.
（実施例８）
　実施例８の発光ダイオードは第１の実施形態の実施例であり、発光ピーク波長を９８５ｎｍにするべく井戸層のＩｎ組成Ｘ１＝０．３にしたこと以外は、実施例１と同じ条件で作製した。
　この発光ダイオード（発光ダイオードランプ）の特性を評価した結果は表７に示した通りであり、ピーク波長９８５ｎｍとする赤外光が出射され、発光出力（Ｐ０）、順方向電圧（ＶＦ）、出力残存率の平均はそれぞれ、５．０ｍＷ、１．２Ｖ、９９％であった。 (Example 8)
The light-emitting diode of Example 8 is an example of the first embodiment, and is manufactured under the same conditions as in Example 1 except that the In composition X1 of the well layer is set to 0.3 so that the emission peak wavelength is 985 nm. did.
The results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 985 nm is emitted, and the light emission output (P 0 ) and forward voltage (V F ). The average output residual ratio was 5.0 mW, 1.2 V, and 99%, respectively.
（実施例９）
　実施例９の発光ダイオードは第２の実施形態の実施例であり、発光ピーク波長を９８５ｎｍにするべく井戸層のＩｎ組成Ｘ１＝０．３にしたこと以外は、実施例２と同じ条件で作製した。
　この発光ダイオード（発光ダイオードランプ）の特性を評価した結果は表７に示した通りであり、ピーク波長９８５ｎｍとする赤外光が出射され、発光出力（Ｐ０）、順方向電圧（ＶＦ）、出力残存率の平均はそれぞれ、３．８ｍＷ、１．２Ｖ、９９％であった。 Example 9
The light-emitting diode of Example 9 is an example of the second embodiment, and is manufactured under the same conditions as Example 2 except that the In composition X1 of the well layer is set to 0.3 so that the emission peak wavelength is 985 nm. did.
The results of evaluating the characteristics of the light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 985 nm is emitted, and the light emission output (P 0 ) and forward voltage (V F ). The average output residual ratio was 3.8 mW, 1.2 V, and 99%, respectively.
（実施例１０）
　実施例１０の発光ダイオードは第１の実施形態の実施例であり、バリア層をアンドープで層厚が約１０ｎｍの（Ａｌ０．１Ｇａ０．９　）０．５５　Ｉｎ０．４５Ｐとしたこと、また、井戸層とバリア層とを交互に５対積層したこと以外は、実施例１と同じ条件で作製した。
　この発光ダイオード（発光ダイオードランプ）の特性を評価した結果は表７に示した通りであり、ピーク波長９２０ｎｍとする赤外光が出射され、発光出力（Ｐ０）、順方向電圧（ＶＦ）、出力残存率の平均はそれぞれ、７．０ｍＷ、１．２４Ｖ、９９％であった。 (Example 10)
The light-emitting diode of Example 10 is an example of the first embodiment, and the barrier layer is undoped and has a thickness of about 10 nm of (Al 0.1 Ga 0.9 ) 0.55 In 0.45 P. Moreover, it was produced under the same conditions as in Example 1 except that five pairs of well layers and barrier layers were alternately laminated.
The results of evaluating the characteristics of this light emitting diode (light emitting diode lamp) are as shown in Table 7. Infrared light having a peak wavelength of 920 nm is emitted, and the light emission output (P 0 ) and forward voltage (V F ). The average output residual ratio was 7.0 mW, 1.24 V, and 99%, respectively.
（比較例１）
　比較例１の発光ダイオードは、従来技術である液相エピタキシャル法で形成した。ＧａＡｓ基板にＡｌ０．０１Ｇａ０．９９Ａｓを発光層とするダブルヘテロ構造の発光部を有する発光ダイオードに変更したものである。 (Comparative Example 1)
The light emitting diode of Comparative Example 1 was formed by a liquid phase epitaxial method which is a conventional technique. This is a light emitting diode having a double heterostructure light emitting portion having a light emitting layer of Al 0.01 Ga 0.99 As on a GaAs substrate.
　比較例１の発光ダイオードの作製は、具体的には、ｎ型の（１００）面のＧａＡｓ単結晶基板に、界面の組成をＡｌ０．２Ｇａ０．８Ａｓのｎ型上部クラッド層を５０μｍ、Ａｌ０．０３Ｇａ０．９７ＡｓからなるＳｉドープの発光層を２０μｍ、Ａｌ０．１Ｇａ０．９Ａｓからなるｐ型の下部クラッド層を２０μｍ、発光波長に対して透明なＡｌ０．２５Ｇａ０．７５Ａｓからなるｐ型の厚膜層を６０μｍとなるように液相エピタキシャル方法によって作製した。このエピタキシャル成長後にＧａＡｓ基板を除去した。次に、ｎ型ＡｌＧａＡｓ上部クラッド層の表面に直径１００μｍのｎ型オーミック電極を形成した。
次に、ｐ型ＡｌＧａＡｓ厚膜層の裏面に直径２０μｍのｐ型オーミック電極を８０μｍ間隔に形成し、４２０℃で、５分間熱処理し、ｐ、ｎオーミック電極を合金化処理した。次に、ダイシングソーにより３５０μｍ間隔で切断した後、破砕層をエッチング除去し、高出力化の為、表面を粗面化処理して比較例１の発光ダイオードチップを作製した。 Specifically, the light-emitting diode of Comparative Example 1 was prepared by forming an n-type (100) GaAs single crystal substrate with an n-type upper cladding layer having an interface composition of Al 0.2 Ga 0.8 As of 50 μm. 20 μm of Si-doped light-emitting layer made of Al 0.03 Ga 0.97 As, 20 μm of p-type lower cladding layer made of Al 0.1 Ga 0.9 As, transparent to the emission wavelength . A p-type thick film layer made of 25 Ga 0.75 As was prepared by a liquid phase epitaxial method so as to be 60 μm. After this epitaxial growth, the GaAs substrate was removed. Next, an n-type ohmic electrode having a diameter of 100 μm was formed on the surface of the n-type AlGaAs upper cladding layer.
Next, p-type ohmic electrodes having a diameter of 20 μm were formed on the back surface of the p-type AlGaAs thick film layer at intervals of 80 μm and heat-treated at 420 ° C. for 5 minutes to alloy the p and n ohmic electrodes. Next, after cutting with a dicing saw at an interval of 350 μm, the crushed layer was removed by etching, and the surface was roughened for high output to produce a light emitting diode chip of Comparative Example 1.
　比較例１の発光ダイオードを実装した発光ダイオードランプの特性を評価した結果を表７に示す。
　表７に示すように、ｎ型及びｐ型オーミック電極間に電流を流したところ、ピーク波長を９２０ｎｍとする赤外光が出射された。また、順方向に２０ミリアンペア（ｍＡ）の電流を通流した際の順方向電圧（ＶＦ）は、約１．２ボルト（Ｖ）となった。また、順方向電流を２０ｍＡとした際の発光出力は、２ｍＷであった。また、比較例１のいずれのサンプルについても、本発明の実施例に比べて出力が低かった。更に、温度６０℃、湿度９０％の高温高湿環境下で、通電試験（２０ｍＡ通電）を５００時間実施し、発光出力の残存率を測定した結果を表１に示す。出力低下の原因は、ＡｌＧａＡｓ表面の腐食により、光の吸収が増加した為と考えられる。
　また、実施例と同様に、このランプ１００個を、６０℃、９０ＲＨ％，２０ｍＡで高温高湿通電試験を実施した。５００時間後の出力残存率の平均は実験開始時に比べて１４％も低下し、１％以内の低下に過ぎなかった実施例に比べて大きく低下した。 Table 7 shows the results of evaluating the characteristics of the light-emitting diode lamp on which the light-emitting diode of Comparative Example 1 was mounted.
As shown in Table 7, when current was passed between the n-type and p-type ohmic electrodes, infrared light having a peak wavelength of 920 nm was emitted. The forward voltage (V F ) when a current of 20 mA (mA) was passed in the forward direction was about 1.2 volts (V). The light emission output when the forward current was 20 mA was 2 mW. Moreover, the output of any sample of Comparative Example 1 was lower than that of the example of the present invention. Further, Table 1 shows the results of conducting a current test (20 mA power supply) for 500 hours in a high temperature and high humidity environment at a temperature of 60 ° C. and a humidity of 90%, and measuring the residual rate of light emission output. The cause of the decrease in output is thought to be that light absorption increased due to corrosion of the AlGaAs surface.
Further, as in the example, 100 lamps were subjected to a high-temperature and high-humidity energization test at 60 ° C., 90 RH%, 20 mA. The average of the remaining power after 500 hours was 14% lower than that at the start of the experiment, and was significantly lower than that of the example in which the decrease was only within 1%.
　本発明の発光ダイオードは高出力・高効率で８５０ｎｍ以上、特に９００ｎｍ以上の発光ピーク波長の赤外光を発光する発光ダイオード製品として利用できる。 The light-emitting diode of the present invention can be used as a light-emitting diode product that emits infrared light having an emission peak wavelength of 850 nm or more, particularly 900 nm or more with high output and high efficiency.
　１・・・発光ダイオード
　２・・・化合物半導体層
　３・・・機能性基板
　３ａ・・・垂直面
　３ｂ・・・傾斜面
　４・・・ｎ型オーミック電極（第１の電極）
　５・・・ｐ型オーミック電極（第２の電極）
　６・・・第３の電極
　７・・・発光部
　８・・・電流拡散層
　９・・・下部クラッド層（第１のクラッド層）
　１０・・・下部ガイド層　
　１１・・・活性層
　１２・・・上部ガイド層
　１３・・・上部クラッド層（第２のクラッド層）
　１４・・・ＧａＡｓ基板
　１５・・・緩衝層
　１６・・・コンタクト層　
　１７・・・井戸層
　１８・・・バリア層
　２０・・・発光ダイオード
　２１・・・電極
　２２・・・透明導電膜
　２３・・・反射面
　２５・・・ボンディング電極
　３０・・・シリコン基板
　３１・・・機能性基板
　α・・・傾斜面と発光面に平行な面とのなす角度
　５０・・・金属基板
　５１・・・機能性基板
　５２・・・透明導電膜
　５３・・・反射層
　５５・・・第１の電極
　５６・・・コンタクト層
　５７・・・第２の電極 DESCRIPTION OF SYMBOLS 1 ... Light emitting diode 2 ... Compound semiconductor layer 3 ... Functional board | substrate 3a ... Vertical surface 3b ... Inclined surface 4 ... N-type ohmic electrode (1st electrode)
5 ... p-type ohmic electrode (second electrode)
6 ... 3rd electrode 7 ... Light emission part 8 ... Current diffusion layer 9 ... Lower clad layer (1st clad layer)
10 ... Lower guide layer
DESCRIPTION OF SYMBOLS 11 ... Active layer 12 ... Upper guide layer 13 ... Upper clad layer (2nd clad layer)
14 ... GaAs substrate 15 ... Buffer layer 16 ... Contact layer
17 ... Well layer 18 ... Barrier layer 20 ... Light emitting diode 21 ... Electrode 22 ... Transparent conductive film 23 ... Reflecting surface 25 ... Bonding electrode 30 ... Silicon substrate 31・ ・ Functional substrate α ・ ・ ・ An angle between the inclined surface and a plane parallel to the light emitting surface 50 .Metal substrate 51... Functional substrate 52 ..Transparent conductive film 53. .... First electrode 56 ... Contact layer 57 ... Second electrode

Claims (23)

  1. 　組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層と組成式（ＡｌＸ２Ｇａ１－Ｘ２）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ２≦１，０＜Ｙ１≦１）からなるバリア層とを交互に積層した量子井戸構造の活性層と、該活性層を挟む、組成式（ＡｌＸ３Ｇａ１－Ｘ３）Ｙ２Ｉｎ１－Ｙ２Ｐ（０≦Ｘ３≦１，０＜Ｙ２≦１）からなる第１のガイド及び第２のガイドと、該第１のガイド及び第２のガイドのそれぞれを介して前記活性層を挟む第１のクラッド層及び第２のクラッド層とを有する発光部と、
    　前記発光部上に形成された電流拡散層と、
    　前記電流拡散層に接合された機能性基板と、を備え、
    　前記第１及び第２のクラッド層が組成式（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ３Ｉｎ１－Ｙ３Ｐ（０≦Ｘ４≦１，０＜Ｙ３≦１）からなることを特徴とする発光ダイオード。     A well layer having a composition formula (In X1 Ga 1-X1 ) As (0 ≦ X1 ≦ 1) and a composition formula (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1) An active layer having a quantum well structure in which barrier layers made of 1) are alternately stacked, and a composition formula (Al X3 Ga 1-X3 ) Y2 In 1-Y2 P (0 ≦ X3 ≦ 1,0) sandwiching the active layer A first guide and a second guide made of <Y2 ≦ 1), and a first clad layer and a second clad layer sandwiching the active layer through the first guide and the second guide, respectively. A light emitting unit having
    A current spreading layer formed on the light emitting part;
    A functional substrate bonded to the current spreading layer,
    The light emitting diode according to claim 1, wherein the first and second cladding layers are composed of a composition formula (Al X4 Ga 1 -X4 ) Y3 In 1 -Y3 P (0≤X4≤1, 0 <Y3≤1).
  2. 　前記井戸層のＩｎ組成（Ｘ１）が０≦Ｘ１≦０．３であることを特徴とする請求項１に記載の発光ダイオード。 2. The light emitting diode according to claim 1, wherein the In composition (X1) of the well layer is 0 ≦ X1 ≦ 0.3.
  3. 　前記井戸層のＩｎ組成（Ｘ１）が０．１≦Ｘ１≦０．３であることを特徴とする請求項２に記載の発光ダイオード。 3. The light emitting diode according to claim 2, wherein an In composition (X1) of the well layer is 0.1 ≦ X1 ≦ 0.3.
  4. 　前記バリア層の組成Ｘ２及びＹ１がそれぞれ、０≦Ｘ２≦０．２，０．５＜Ｙ１≦０．７であり、前記第１及び第２のガイドの組成Ｘ３及びＹ２がそれぞれ、０．２≦Ｘ３≦０．５，０．４＜Ｙ２≦０．６であり、前記第１及び第２のクラッド層の組成Ｘ４及びＹ３がそれぞれ、０．３≦Ｘ４≦０．７，０．４＜Ｙ３≦０．６であることを特徴とする請求項１に記載の発光ダイオード。 The compositions X2 and Y1 of the barrier layer are 0 ≦ X2 ≦ 0.2 and 0.5 <Y1 ≦ 0.7, respectively, and the compositions X3 and Y2 of the first and second guides are 0.2, respectively. ≦ X3 ≦ 0.5, 0.4 <Y2 ≦ 0.6, and the compositions X4 and Y3 of the first and second cladding layers are 0.3 ≦ X4 ≦ 0.7 and 0.4 <, respectively. 2. The light emitting diode according to claim 1, wherein Y3 ≦ 0.6.
  5. 　前記機能性基板は発光波長に対して透明であることを特徴とする請求項１に記載の発光ダイオード。 2. The light emitting diode according to claim 1, wherein the functional substrate is transparent with respect to an emission wavelength.
  6. 　前記機能性基板はＧａＰ又はＳｉＣからなることを特徴とする請求項１に記載の発光ダイオード。 The light emitting diode according to claim 1, wherein the functional substrate is made of GaP or SiC.
  7. 　前記機能性基板の側面は、前記発光部に近い側においては主たる光取り出し面に対して略垂直である垂直面を有し、前記発光部に遠い側においては前記主たる光取り出し面に対して内側に傾斜した傾斜面を有することを特徴とする請求項１に記載の発光ダイオード。 The side surface of the functional substrate has a vertical surface that is substantially perpendicular to the main light extraction surface on the side close to the light emitting unit, and is inside the main light extraction surface on the side far from the light emitting unit. The light emitting diode according to claim 1, wherein the light emitting diode has an inclined surface.
  8. 　前記傾斜面は粗い面を含むことを特徴とする請求項７に記載の発光ダイオード。 The light emitting diode according to claim 7, wherein the inclined surface includes a rough surface.
  9. 　組成式（ＩｎＸ１Ｇａ１－Ｘ１）Ａｓ（０≦Ｘ１≦１）からなる井戸層と組成式（ＡｌＸ２Ｇａ１－Ｘ２）Ｙ１Ｉｎ１－Ｙ１Ｐ（０≦Ｘ２≦１，０＜Ｙ１≦１）からなるバリア層とを交互に積層した量子井戸構造の活性層と、該活性層を挟む、組成式（ＡｌＸ３Ｇａ１－Ｘ３）Ｙ２Ｉｎ１－Ｙ２Ｐ（０≦Ｘ３≦１，０＜Ｙ２≦１）からなる第１のガイド及び第２のガイドと、該第１のガイド及び第２のガイドのそれぞれを介して前記活性層を挟む第１のクラッド層及び第２のクラッド層とを有する発光部と、
    　前記発光部上に形成された電流拡散層と、
    　前記発光部に対向して配置され、発光波長に対して９０％以上の反射率を有する反射層を含み、前記電流拡散層に接合された機能性基板と、を備え、
    　前記第１及び第２のクラッド層が組成式（ＡｌＸ４Ｇａ１－Ｘ４）Ｙ３Ｉｎ１－Ｙ３Ｐ（０≦Ｘ４≦１，０＜Ｙ３≦１）からなることを特徴とする発光ダイオード。     A well layer having a composition formula (In X1 Ga 1-X1 ) As (0 ≦ X1 ≦ 1) and a composition formula (Al X2 Ga 1-X2 ) Y1 In 1-Y1 P (0 ≦ X2 ≦ 1, 0 <Y1 ≦ 1) An active layer having a quantum well structure in which barrier layers made of 1) are alternately stacked, and a composition formula (Al X3 Ga 1-X3 ) Y2 In 1-Y2 P (0 ≦ X3 ≦ 1,0) sandwiching the active layer A first guide and a second guide made of <Y2 ≦ 1), and a first clad layer and a second clad layer sandwiching the active layer through the first guide and the second guide, respectively. A light emitting unit having
    A current spreading layer formed on the light emitting part;
    A functional substrate disposed opposite to the light emitting portion and including a reflective layer having a reflectance of 90% or more with respect to an emission wavelength, and a functional substrate bonded to the current diffusion layer,
    The light emitting diode according to claim 1, wherein the first and second cladding layers are composed of a composition formula (Al X4 Ga 1 -X4 ) Y3 In 1 -Y3 P (0≤X4≤1, 0 <Y3≤1).
  10. 　前記井戸層のＩｎ組成（Ｘ１）が０≦Ｘ１≦０．３であることを特徴とする請求項９に記載の発光ダイオード。 10. The light emitting diode according to claim 9, wherein an In composition (X1) of the well layer is 0 ≦ X1 ≦ 0.3.
  11. 　前記井戸層のＩｎ組成（Ｘ１）が０．１≦Ｘ１≦０．３であることを特徴とする請求項１０に記載の発光ダイオード。 11. The light emitting diode according to claim 10, wherein the In composition (X1) of the well layer is 0.1 ≦ X1 ≦ 0.3.
  12. 　前記バリア層の組成Ｘ２及びＹ１がそれぞれ、０≦Ｘ２≦０．２，０．５＜Ｙ１≦０．７であり、前記第１及び第２のガイドの組成Ｘ３及びＹ２がそれぞれ、０．２≦Ｘ３≦０．５，０．４＜Ｙ２≦０．６であり、前記第１及び第２のクラッド層の組成Ｘ４及びＹ３がそれぞれ、０．３≦Ｘ４≦０．７，０．４＜Ｙ３≦０．６であることを特徴とする請求項９乃至１１のいずれか一項に記載の発光ダイオード。 The compositions X2 and Y1 of the barrier layer are 0 ≦ X2 ≦ 0.2 and 0.5 <Y1 ≦ 0.7, respectively, and the compositions X3 and Y2 of the first and second guides are 0.2, respectively. ≦ X3 ≦ 0.5, 0.4 <Y2 ≦ 0.6, and the compositions X4 and Y3 of the first and second cladding layers are 0.3 ≦ X4 ≦ 0.7 and 0.4 <, respectively. The light emitting diode according to claim 9, wherein Y3 ≦ 0.6.
  13. 　前記機能性基板はシリコンまたはゲルマニウムからなる層を含むことを特徴とする請求項９に記載の発光ダイオード。 The light emitting diode according to claim 9, wherein the functional substrate includes a layer made of silicon or germanium.
  14. 　前記機能性基板は金属基板を含むことを特徴とする請求項９に記載の発光ダイオード。 The light emitting diode according to claim 9, wherein the functional substrate includes a metal substrate.
  15. 　前記金属基板は複数の金属層からなることを特徴とする請求項１４に記載の発光ダイオード。 15. The light emitting diode according to claim 14, wherein the metal substrate comprises a plurality of metal layers.
  16. 　前記電流拡散層はＧａＰ又はＧａＩｎＰからなることを特徴とする請求項１又は９に記載の発光ダイオード。 The light-emitting diode according to claim 1 or 9, wherein the current diffusion layer is made of GaP or GaInP.
  17. 前記電流拡散層の厚さは０．５～２０μｍの範囲であることを特徴とする請求項１又は９に記載の発光ダイオード。 10. The light emitting diode according to claim 1, wherein a thickness of the current diffusion layer is in a range of 0.5 to 20 μm.
  18. 第１の電極及び第２の電極が発光ダイオードの前記主たる光取り出し面側に設けられていることを特徴とする請求項１又は９に記載の発光ダイオード。 The light emitting diode according to claim 1, wherein the first electrode and the second electrode are provided on the main light extraction surface side of the light emitting diode.
  19. 　前記第１の電極及び前記第２の電極がオーミック電極であることを特徴とする請求項１８に記載の発光ダイオード。 The light emitting diode according to claim 18, wherein the first electrode and the second electrode are ohmic electrodes.
  20. 　前記機能性基板の、前記主たる光取り出し面側の反対側の面に、第３の電極をさらに備えることを特徴とする請求項１８に記載の発光ダイオード。 The light emitting diode according to claim 18, further comprising a third electrode on a surface of the functional substrate opposite to the main light extraction surface.
  21. 　請求項１乃至２０のいずれか一項に記載の発光ダイオードを備えることを特徴とする発光ダイオードランプ。 A light-emitting diode lamp comprising the light-emitting diode according to any one of claims 1 to 20.
  22. 　請求項２０に記載の発光ダイオードを備え、前記第１の電極又は第２の電極と、前記第３の電極とが略同電位に接続されていることを特徴とする発光ダイオードランプ。 21. A light-emitting diode lamp comprising the light-emitting diode according to claim 20, wherein the first electrode or the second electrode and the third electrode are connected to substantially the same potential.
  23. 　請求項１乃至２０のいずれか一項に記載の発光ダイオード、及び／又は、請求項２１又は２２の少なくともいずれかに記載の発光ダイオードランプを複数個搭載した照明装置。 An illumination device equipped with a plurality of the light emitting diodes according to any one of claims 1 to 20 and / or at least one of the light emitting diode lamps according to claim 21 or 22.
PCT/JP2011/050719 2010-01-25 2011-01-18 Light-emitting diode, light-emitting diode lamp and lighting device WO2011090016A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201180007108.8A CN102725871B (en) 2010-01-25 2011-01-18 Light-emitting diode, LED light lamp and lighting device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2010013530 2010-01-25
JP2010-013530 2010-01-25
JP2010-183205 2010-08-18
JP2010183205A JP5557648B2 (en) 2010-01-25 2010-08-18 Light emitting diode, light emitting diode lamp, and lighting device

Publications (1)

Publication Number Publication Date
WO2011090016A1 true WO2011090016A1 (en) 2011-07-28

Family

ID=44306819

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/050719 WO2011090016A1 (en) 2010-01-25 2011-01-18 Light-emitting diode, light-emitting diode lamp and lighting device

Country Status (4)

Country Link
JP (1) JP5557648B2 (en)
CN (1) CN102725871B (en)
TW (1) TWI446580B (en)
WO (1) WO2011090016A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012119585A (en) 2010-12-02 2012-06-21 Showa Denko Kk Light-emitting diode, light-emitting diode lamp and luminaire
CN111819702B (en) 2019-11-26 2024-04-09 天津三安光电有限公司 Infrared light-emitting diode
JP7455267B1 (en) 2022-10-28 2024-03-25 Ｄｏｗａエレクトロニクス株式会社 Ultraviolet light emitting device and its manufacturing method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207508A (en) * 2002-12-25 2004-07-22 Shin Etsu Handotai Co Ltd Light emitting element and its manufacturing method thereof
JP2006066518A (en) * 2004-08-25 2006-03-09 Sharp Corp Semiconductor light-emitting element and method of manufacturing the same
JP2007157838A (en) * 2005-12-01 2007-06-21 Matsushita Electric Ind Co Ltd Semiconductor laser element
JP2007194536A (en) * 2006-01-23 2007-08-02 Showa Denko Kk Light emitting diode and manufacturing method thereof
WO2008151255A1 (en) * 2007-06-05 2008-12-11 Semi-Photonics Co., Ltd. Method for handling a semiconductor wafer assembly
JP2010016353A (en) * 2008-06-03 2010-01-21 Sumitomo Electric Ind Ltd AlxGa(1-x)As SUBSTRATE, EPITAXIAL WAFER FOR INFRARED LED, INFRARED LED, METHOD OF MANUFACTURING AlxGa(1-x)As SUBSTRATE, METHOD OF MANUFACTURING EPITAXIAL WAFER FOR INFRARED LED, AND METHOD OF MANUFACTURING INFRARED LED

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3982940B2 (en) * 1999-03-26 2007-09-26 三井化学株式会社 Method for manufacturing optical semiconductor element
US6900467B2 (en) * 2001-05-21 2005-05-31 Stanley Electric Co., Ltd. Semiconductor light emitting device having quantum well layer sandwiched between carrier confinement layers

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207508A (en) * 2002-12-25 2004-07-22 Shin Etsu Handotai Co Ltd Light emitting element and its manufacturing method thereof
JP2006066518A (en) * 2004-08-25 2006-03-09 Sharp Corp Semiconductor light-emitting element and method of manufacturing the same
JP2007157838A (en) * 2005-12-01 2007-06-21 Matsushita Electric Ind Co Ltd Semiconductor laser element
JP2007194536A (en) * 2006-01-23 2007-08-02 Showa Denko Kk Light emitting diode and manufacturing method thereof
WO2008151255A1 (en) * 2007-06-05 2008-12-11 Semi-Photonics Co., Ltd. Method for handling a semiconductor wafer assembly
JP2010016353A (en) * 2008-06-03 2010-01-21 Sumitomo Electric Ind Ltd AlxGa(1-x)As SUBSTRATE, EPITAXIAL WAFER FOR INFRARED LED, INFRARED LED, METHOD OF MANUFACTURING AlxGa(1-x)As SUBSTRATE, METHOD OF MANUFACTURING EPITAXIAL WAFER FOR INFRARED LED, AND METHOD OF MANUFACTURING INFRARED LED

Also Published As

Publication number Publication date
TWI446580B (en) 2014-07-21
JP5557648B2 (en) 2014-07-23
CN102725871B (en) 2016-03-09
CN102725871A (en) 2012-10-10
JP2011171694A (en) 2011-09-01
TW201214753A (en) 2012-04-01

Similar Documents

Publication Publication Date Title
WO2012073993A1 (en) Light-emitting diode, light-emitting diode lamp, and illumination device
EP2400571A1 (en) Light-emitting diode, light-emitting diode lamp, and method for producing light-emitting diode
WO2010103752A1 (en) Light emitting diode, light emitting diode lamp and illuminating device
WO2011034080A1 (en) Light emitting diode, light emitting diode lamp and lighting device
JP5557649B2 (en) Light emitting diode, light emitting diode lamp, and lighting device
JP2012109436A (en) Light-emitting diode
WO2012023558A1 (en) Light-emitting diode and light-emitting diode lamp
JP5586371B2 (en) Light emitting diode, light emitting diode lamp, and lighting device
JP5586372B2 (en) Light emitting diode, light emitting diode lamp, and lighting device
JP6101303B2 (en) Light emitting diode, light emitting diode lamp, and lighting device
JP5557648B2 (en) Light emitting diode, light emitting diode lamp, and lighting device
JP5538006B2 (en) Light emitting diode
JP5801542B2 (en) Light emitting diode and light emitting diode lamp
JP5876897B2 (en) Light emitting diode, light emitting diode lamp, and lighting device
JP2012129249A (en) Light-emitting diode, light-emitting diode lamp, and method for manufacturing light-emitting diode
JP2014168101A (en) Light emitting diode, light emitting diode lamp, and lighting device
JP2014158057A (en) Light-emitting diode, light-emitting diode lamp, and illuminating device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201180007108.8

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11734622

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11734622

Country of ref document: EP

Kind code of ref document: A1