JP5191766B2 - デコーダ回路 - Google Patents

デコーダ回路 Download PDF

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Publication number
JP5191766B2
JP5191766B2 JP2008075351A JP2008075351A JP5191766B2 JP 5191766 B2 JP5191766 B2 JP 5191766B2 JP 2008075351 A JP2008075351 A JP 2008075351A JP 2008075351 A JP2008075351 A JP 2008075351A JP 5191766 B2 JP5191766 B2 JP 5191766B2
Authority
JP
Japan
Prior art keywords
voltage
power supply
load current
node
supply voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008075351A
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English (en)
Japanese (ja)
Other versions
JP2009230805A (ja
JP2009230805A5 (enExample
Inventor
光弘 友枝
誠 棟安
昌宏 細田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2008075351A priority Critical patent/JP5191766B2/ja
Priority to US12/361,755 priority patent/US7795922B2/en
Publication of JP2009230805A publication Critical patent/JP2009230805A/ja
Priority to US12/845,290 priority patent/US7969200B2/en
Priority to US13/106,573 priority patent/US8242808B2/en
Publication of JP2009230805A5 publication Critical patent/JP2009230805A5/ja
Application granted granted Critical
Publication of JP5191766B2 publication Critical patent/JP5191766B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Read Only Memory (AREA)
JP2008075351A 2008-03-24 2008-03-24 デコーダ回路 Expired - Fee Related JP5191766B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2008075351A JP5191766B2 (ja) 2008-03-24 2008-03-24 デコーダ回路
US12/361,755 US7795922B2 (en) 2008-03-24 2009-01-29 Decoder circuit
US12/845,290 US7969200B2 (en) 2008-03-24 2010-07-28 Decoder circuit
US13/106,573 US8242808B2 (en) 2008-03-24 2011-05-12 Decoder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008075351A JP5191766B2 (ja) 2008-03-24 2008-03-24 デコーダ回路

Publications (3)

Publication Number Publication Date
JP2009230805A JP2009230805A (ja) 2009-10-08
JP2009230805A5 JP2009230805A5 (enExample) 2012-09-13
JP5191766B2 true JP5191766B2 (ja) 2013-05-08

Family

ID=41088249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008075351A Expired - Fee Related JP5191766B2 (ja) 2008-03-24 2008-03-24 デコーダ回路

Country Status (2)

Country Link
US (3) US7795922B2 (enExample)
JP (1) JP5191766B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8692333B2 (en) * 2010-08-12 2014-04-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device for word line driver with efficient routing of conductor for decreased gate resistance
US20120162121A1 (en) 2010-12-22 2012-06-28 Shih Chang Chang Slew rate and shunting control separation
US9319036B2 (en) 2011-05-20 2016-04-19 Apple Inc. Gate signal adjustment circuit
US8837252B2 (en) 2012-05-31 2014-09-16 Atmel Corporation Memory decoder circuit
US9407245B2 (en) * 2014-06-30 2016-08-02 Intel IP Corporation System for digitally controlled edge interpolator linearization
JP6963480B2 (ja) * 2017-12-01 2021-11-10 ルネサスエレクトロニクス株式会社 半導体装置
US11443820B2 (en) 2018-01-23 2022-09-13 Microchip Technology Incorporated Memory device, memory address decoder, system, and related method for memory attack detection
JP7065007B2 (ja) * 2018-10-01 2022-05-11 ルネサスエレクトロニクス株式会社 半導体装置
US20230393978A1 (en) * 2022-06-02 2023-12-07 Intel Corporation Half latch level shifting circuit for non-volatile memory architectures

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62175999A (ja) * 1986-01-29 1987-08-01 Toshiba Corp 不揮発性半導体記憶装置
JPH0632230B2 (ja) * 1987-03-31 1994-04-27 株式会社東芝 半導体不揮発性記憶装置
US5668485A (en) * 1992-05-21 1997-09-16 Texas Instruments Incorporated Row decoder with level translator
US5696721A (en) * 1995-05-05 1997-12-09 Texas Instruments Incorporated Dynamic random access memory having row decoder with level translator for driving a word line voltage above and below an operating supply voltage range
US5781497A (en) * 1996-08-02 1998-07-14 Alliance Semiconductor Corp. Random access memory word line select circuit having rapid dynamic deselect
WO1999065036A1 (en) * 1998-06-12 1999-12-16 Macronix International Co., Ltd. Channel fn program/erase recovery scheme
JP2001102915A (ja) * 1999-09-29 2001-04-13 Sony Corp レベルシフト回路及びそれを用いた信号線駆動回路
JP3463027B2 (ja) 2000-08-25 2003-11-05 株式会社東芝 不揮発性半導体メモリ
WO2008082995A1 (en) * 2006-12-31 2008-07-10 Sandisk 3D Llc Reversible polarity decoder circuit and related methods

Also Published As

Publication number Publication date
JP2009230805A (ja) 2009-10-08
US20110216620A1 (en) 2011-09-08
US20090237114A1 (en) 2009-09-24
US20100301902A1 (en) 2010-12-02
US7969200B2 (en) 2011-06-28
US7795922B2 (en) 2010-09-14
US8242808B2 (en) 2012-08-14

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