JP5152432B2 - 絶縁性基板、金属張積層板、プリント配線板、及び半導体装置 - Google Patents

絶縁性基板、金属張積層板、プリント配線板、及び半導体装置 Download PDF

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Publication number
JP5152432B2
JP5152432B2 JP2012191864A JP2012191864A JP5152432B2 JP 5152432 B2 JP5152432 B2 JP 5152432B2 JP 2012191864 A JP2012191864 A JP 2012191864A JP 2012191864 A JP2012191864 A JP 2012191864A JP 5152432 B2 JP5152432 B2 JP 5152432B2
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Japan
Prior art keywords
layer
fiber base
resin
insulating substrate
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2012191864A
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English (en)
Japanese (ja)
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JP2012231195A (ja
Inventor
偉師 小野塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP2012191864A priority Critical patent/JP5152432B2/ja
Publication of JP2012231195A publication Critical patent/JP2012231195A/ja
Application granted granted Critical
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Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2012191864A 2010-11-18 2012-08-31 絶縁性基板、金属張積層板、プリント配線板、及び半導体装置 Expired - Fee Related JP5152432B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012191864A JP5152432B2 (ja) 2010-11-18 2012-08-31 絶縁性基板、金属張積層板、プリント配線板、及び半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010258172 2010-11-18
JP2010258172 2010-11-18
JP2012191864A JP5152432B2 (ja) 2010-11-18 2012-08-31 絶縁性基板、金属張積層板、プリント配線板、及び半導体装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2011209540A Division JP5115645B2 (ja) 2010-11-18 2011-09-26 絶縁性基板、金属張積層板、プリント配線板、及び半導体装置

Publications (2)

Publication Number Publication Date
JP2012231195A JP2012231195A (ja) 2012-11-22
JP5152432B2 true JP5152432B2 (ja) 2013-02-27

Family

ID=47432428

Family Applications (2)

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JP2012191864A Expired - Fee Related JP5152432B2 (ja) 2010-11-18 2012-08-31 絶縁性基板、金属張積層板、プリント配線板、及び半導体装置
JP2012191863A Expired - Fee Related JP5821811B2 (ja) 2010-11-18 2012-08-31 絶縁性基板、金属張積層板、プリント配線板、及び半導体装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2012191863A Expired - Fee Related JP5821811B2 (ja) 2010-11-18 2012-08-31 絶縁性基板、金属張積層板、プリント配線板、及び半導体装置

Country Status (1)

Country Link
JP (2) JP5152432B2 (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102494332B1 (ko) * 2015-07-15 2023-02-02 삼성전기주식회사 전자소자 패키지
KR101916379B1 (ko) * 2016-01-22 2018-11-08 한솔테크닉스(주) 커브드형 회로기판
WO2025154213A1 (ja) * 2024-01-17 2025-07-24 株式会社レゾナック 半導体パッケージを製造する方法、半導体パッケージ用基板材料、及び半導体パッケージ用基板材料を製造する方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3168870B2 (ja) * 1995-04-26 2001-05-21 松下電工株式会社 多層積層板の製造方法
JP2001177244A (ja) * 1999-12-17 2001-06-29 Hitachi Chem Co Ltd 多層板の製造方法
JP2002134918A (ja) * 2000-10-26 2002-05-10 Matsushita Electric Works Ltd 多層プリント配線板の製造方法
JP3499837B2 (ja) * 2001-03-13 2004-02-23 住友ベークライト株式会社 プリプレグの製造方法
MY148173A (en) * 2006-04-28 2013-03-15 Sumitomo Bakelite Co Solder resist material, wiring board using the solder resist material, and semiconductor package
WO2008056500A1 (fr) * 2006-11-10 2008-05-15 Nec Corporation Substrat à circuit multicouche
WO2008093579A1 (ja) * 2007-01-29 2008-08-07 Sumitomo Bakelite Company Limited 積層体、基板の製造方法、基板および半導体装置

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Publication number Publication date
JP5821811B2 (ja) 2015-11-24
JP2013016835A (ja) 2013-01-24
JP2012231195A (ja) 2012-11-22

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