JP5143350B2 - Nonvolatile memory cell structure having charge trapping film and manufacturing method thereof - Google Patents

Description

  The present invention relates to a nonvolatile memory device and a manufacturing method thereof, and more particularly, to a nonvolatile memory device having a charge trap film and a manufacturing method thereof.

  Recently, non-volatile memory elements are generally used in electronic devices, particularly portable electronic devices that use a battery as a power source. Such a non-volatile memory device maintains stored data even when power supply is interrupted, thus eliminating the need for a refresh operation that consumes power to maintain the stored data.

  Referring to FIG. 1, in an existing SONOS type nonvolatile memory cell structure, a charge trap structure 110 is formed on a silicon substrate 102, and the drain region 104 and the source region 106 are separated from each other by a pre-calculated distance. To be formed. The charge trapping structure 110 has a stacked structure, in which a tunneling film 112 formed of a first silicon film, a charge trapping film 114 formed of silicon nitride, and a shielding formed of silicon oxide. A film 116 is sequentially stacked on the silicon substrate 102. The control gate electrode 120 formed of a polysilicon film is formed on the charge trap structure 110.

  To perform a program or read operation, a positive bias voltage is applied to the gate electrode 120, and the source region 106 and the drain region 104 are grounded. The voltage applied to the gate electrode 120 and the source region 106 causes a vertical electric field and a horizontal electric field from the drain region 104 to the source region 106 along the channel region. Due to this electric field, electrons are pushed from the drain region 104 and accelerated to the source region 106. The electrons gain energy while passing through the channel region, and some of the electrons move to a thermal state, thereby obtaining enough energy to jump over the potential barrier of the tunneling layer 112 and move to the charge trapping film 114. it can.

  Such a phenomenon occurs most frequently in the vicinity of the drain region 106 because electrons can obtain the largest energy in that region. Once electrons in the thermal state move to the charge trapping film 114, the electrons are trapped in the charge trapping film and stored there, and the threshold voltage of the memory element increases.

  In order to perform the erase operation, a voltage different from the voltage used when the program operation or the memory element is read is required.

  For example, a positive bias voltage is applied to the source region 106 and a negative bias voltage is applied to the gate electrode 120. The drain region 104 is fluid. In such a state, electrons stored in the charge trapping film 114 move to the source region 106, and holes in the source region 106 move to the charge trapping film 114. The electrons stored in the charge trapping film 114 are removed or eliminated by the holes, so that the data in the memory cell is erased.

  In the existing SONOS type memory device, a certain amount of electrons previously trapped in the overlap region of the gate electrode and the source region or in the gate electrode and the drain region are still trapped after the erase operation is performed. May remain in the membrane.

  The potential barrier between the channel region and the source / drain region is increased by electrons remaining after the erase operation. As the potential barrier increases, the subthreshold voltage gradient of the nonvolatile memory device is reduced. Such a phenomenon is mentioned in Non-Patent Document 1.

When such a phenomenon occurs, the device characteristics are degraded by the threshold voltage difference between the programmed state and the erased state of the device.
US Pat. No. 6,335,554 “Characterization of Channel Hot Electrons Injection by The Sub Threshold, Slope of NROMTM Device” by Eli Lusky et al. , IEEE Electron Device Letters, Vol. 22, no. 11, November 2001

  The technical problem of the present invention is to provide a nonvolatile memory cell structure having a charge trapping film capable of maintaining the threshold voltage of an element during a program operation and the threshold voltage of an element during an erase operation at an appropriate and constant level, and a method for manufacturing the same. There is to offer.

  The technical problem of the present invention is not limited to the technical problem mentioned above, and still other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

  In order to achieve the above technical problem, the present invention relates to a nonvolatile memory device in which at least one edge of a charge trapping film is recessed and a method of forming such a device. In such a system, the threshold voltage of the element during the program operation and the threshold voltage of the element during the erase operation are maintained at appropriate and constant levels. As a result, the characteristics of the element are improved.

  In one aspect, the present invention provides a non-volatile memory device. The device includes a semiconductor substrate, a source-drain region, and a charge trapping structure on the substrate between the source region and the drain region, provided in a space-isolated position in the upper layer portion of the substrate. And a gate electrode on the charge trapping structure, and there is a recess in the charge trapping structure between at least one of the gate electrode, the source region, and the drain region.

  In one embodiment, the gate electrode overlaps with a portion of the source region and a portion of the drain region.

  In another embodiment, the source region and the drain region include a high concentration impurity region and a low concentration impurity region, respectively, and the low concentration impurity region of the source region and the drain region corresponds to the corresponding high concentration impurity along the upper layer portion of the substrate. Extending from the region, the gate electrode overlaps a part of the low concentration impurity region of the source region and the drain region.

  In other embodiments, the lightly doped source and drain regions are self-aligned to the source and drain sides of the gate electrode when initially formed.

  In another embodiment, the low-concentration impurity source and drain regions are extended under the source side and drain side of the gate electrode, respectively, through a diffusion process.

  In other embodiments, sidewall spacers are provided on the source and drain sides of the gate electrode, and the heavily doped source and drain regions are self-aligned outside the sidewall spacers when initially formed.

  In other embodiments, the source and drain regions are self-aligned to the source and drain sides of the gate electrode, respectively, when initially formed.

  In another embodiment, the source and drain regions are extended below the source and drain sides of the gate electrode, respectively, through a diffusion process.

  In other embodiments, at least one inner edge of the source and drain regions is substantially aligned with the outer edge of the charge trapping structure.

  In other embodiments, the recess is on the side of the source region of the charge trapping structure.

  In other embodiments, the recess is on both sides of the source region side and drain region side of the charge trapping structure.

  In other embodiments, the recess further comprises a dielectric material.

  In another embodiment, the charge trapping structure includes a first dielectric film, a second dielectric film overlying the first dielectric film, and a third dielectric film overlying the second dielectric film. .

  In another embodiment, the first dielectric film comprises a material selected from the group consisting of silicon oxide and silicon oxynitride, and the second dielectric film comprises silicon nitride, silicon oxynitride, and high dielectric The third dielectric layer includes a material selected from the group consisting of a dielectric material (a high-k dielectric material), and the third dielectric layer includes silicon oxide.

  In other embodiments, the recess is formed in the second dielectric film.

  In another embodiment, the charge trapping structure includes a first dielectric film, a quantum dot array on the first dielectric film, and a quantum dot structure including a second dielectric film on the quantum dot array. Including.

  In another embodiment, the first dielectric film includes a material selected from the group consisting of silicon oxide and silicon oxynitride, and the quantum dot array is a group consisting of polysilicon quantum dots and silicon nitride quantum dots. And the second dielectric film includes silicon oxide.

  In another embodiment, the charge trap structure extends from the source region to an intermediate region between the source region and the drain region, and the gate dielectric film on the substrate extends from the charge trap structure in the intermediate region to the drain region. And the gate electrode is on the charge trapping structure and the gate dielectric film.

  In other embodiments, the charge trapping structure includes a first charge trapping structure, the gate electrode includes a first auxiliary gate electrode, and the main gate dielectric on the substrate between the source region and the drain region. A first charge trapping structure on a substrate between the film, a main gate dielectric film on the main gate dielectric film, a source region and the main gate electrode, and a first charge trap structure, A first auxiliary gate electrode in which a first recess exists in the first charge trapping structure between the auxiliary gate electrode and a part of the source region, and between the drain region and the main gate electrode A second charge trapping structure on the substrate and a second charge trapping structure on the second charge trapping structure and in the second charge trapping structure between the second auxiliary gate electrode and a portion of the drain region. Second auxiliary gate electrode with a recess , Further comprising a.

  In another aspect, the present invention relates to a semiconductor substrate, a source region and a drain region provided in a spatially separated manner in an upper layer portion of the substrate, and a main gate dielectric film on the substrate between the source region and the drain region. , A main gate electrode on the main gate dielectric film, a first charge trap structure on the substrate between the source region and the main gate electrode, and a first charge trap structure, A first auxiliary gate electrode having a first recess in a first charge trapping structure between the auxiliary gate electrode and a portion of the source region; and a substrate between the drain region and the main gate electrode. A second charge trapping structure on the second charge trapping structure and on a portion between the second auxiliary gate electrode and the drain region that is on the second charge trapping structure A second auxiliary game with a second recess in it And the electrode, to a nonvolatile memory device comprising a.

  In another embodiment, the first and second auxiliary gate electrodes are formed on the first charge trap structure and the second charge trap structure on the drain side surface and the source side surface of the first gate electrode, respectively. Conductive sidewall spacers.

  In other embodiments, the source and drain regions are self-aligned with the first and second auxiliary gate electrodes when initially formed.

  In other embodiments, the first and second charge trapping structures include a first dielectric film, a second dielectric film on the first dielectric film, and a third dielectric film on the second dielectric film, respectively. And a dielectric film.

  In another embodiment, the first dielectric film includes any one material selected from the group consisting of silicon oxide and silicon oxynitride, and the second dielectric film includes silicon nitride, silicon oxynitride. And the third dielectric layer includes silicon oxide. The third dielectric layer includes any one selected from the group consisting of a material and a high dielectric constant material.

  In other embodiments, first and second recesses are formed in the second dielectric film of the first and second charge trapping structures, respectively.

  In another embodiment, each of the first and second charge trapping structures includes a first dielectric film, a quantum dot array on the first dielectric film, and a second dielectric film on the quantum dot array. Including a quantum dot structure.

  In another embodiment, the first dielectric film includes any one material selected from the group consisting of silicon oxide and silicon oxynitride, and the quantum dot array includes polysilicon quantum dots and silicon nitride quantum dots. The second dielectric film includes silicon oxide and includes any one type of quantum dots selected from the group consisting of the above.

  In another embodiment, the source and drain regions include a high-concentration impurity region and a low-concentration impurity region, respectively, and the low-concentration impurity regions of the source region and the drain region are separated from the corresponding high-concentration impurity regions along the upper layer portion of the substrate. The first and second auxiliary gate electrodes are extended from each other and overlap with a part of the low concentration impurity region of the source region and the drain region.

  In other embodiments, the lightly doped source and drain regions are self-aligned with the source and drain sides of the main gate electrode when initially formed.

  In another embodiment, the low concentration impurity source and drain regions are extended under the source and drain of the main gate electrode, respectively, by a diffusion process.

  In other embodiments, a dielectric material is present in the first and second recesses.

  In another aspect, the present invention provides a charge trapping structure on a semiconductor substrate, providing a gate electrode on the charge trapping structure, and selectively etching at least one exposed outer edge of the charge trapping structure. And forming a source region and a drain region in the semiconductor substrate by forming at least one recess between the semiconductor substrate and the gate electrode, and using the gate electrode as an ion implantation mask. It relates to a method of forming.

  In another embodiment, the step of providing a charge trapping structure and the step of providing a gate electrode include providing a charge trap film on a semiconductor substrate, providing a gate electrode film on the charge trap film, A non-volatile memory device including forming a gate electrode and a charge trapping structure by patterning the charge trapping film is formed.

  In another embodiment, the step of providing the charge trapping structure and the step of providing the gate electrode include providing a charge trapping film on the semiconductor substrate and patterning the charge trapping film between the source region and the drain region. Forming a charge trap structure extending on a substrate between an intermediate region and a source region, and providing a gate dielectric film on the substrate extending from the charge trap film in the intermediate region to the drain region; Providing a gate electrode film on the film and on the gate dielectric film, and patterning the gate electrode film and the gate dielectric film to form a gate electrode and a charge trapping structure.

  In other embodiments, the source and drain regions are formed following selective etching of the charge trapping structure.

  In other embodiments, the source and drain regions are formed prior to selectively etching the charge trapping structure.

  In other embodiments, the method further includes diffusing the source and drain regions to overlap the gate structure with the source and drain regions.

  In other embodiments, at least one inner edge of the source and drain regions is diffused until it is substantially aligned with the outer edge of the charge trapping structure.

  In another embodiment, the recess is formed by selectively etching the side surface of the source region of the charge trapping structure.

  In another embodiment, the method includes a gate extending through the sidewall of the drain side of the gate to the drain region to prevent the drain region side of the charge trapping structure from being etched prior to selective etching. The method further includes applying a photoresist pattern on a portion of the drain side surface.

  In another embodiment, a recess is formed by selectively etching both side surfaces of the source region and the drain region of the charge trapping structure.

  In another embodiment, forming a source region and a drain region includes forming a low concentration impurity source region and a low concentration impurity drain region in a semiconductor substrate using a gate electrode as a first ion implantation mask, Forming a high concentration impurity source region and a high concentration impurity drain region in the semiconductor substrate using the side wall spacer as a second ion implantation mask.

  In another embodiment, the method further includes diffusing the low concentration impurity region and the low concentration impurity drain region such that the gate structure overlaps the low concentration impurity source region and the low concentration impurity drain region.

  In another embodiment, providing a charge trapping structure provides a first dielectric film, a second dielectric film on the first dielectric film, and a third on the second dielectric film. Providing a dielectric film.

  In another embodiment, the first dielectric film includes a material selected from the group consisting of silicon oxide and silicon oxynitride, and the second dielectric film is silicon nitride, silicon oxynitride, and a high dielectric constant. The third dielectric film includes silicon oxide and includes a material selected from the group consisting of materials.

  In another embodiment, selective etching is performed to obtain a recess formed in the second dielectric film.

  In other embodiments, providing a charge trapping structure provides a first dielectric film, provides a quantum dot array on the first dielectric film, and provides a second dielectric film on the quantum dot array. Including providing.

  In another embodiment, the first dielectric film comprises a material selected from the group consisting of silicon oxide and silicon oxynitride, and the quantum dot array consists of polysilicon quantum dots and silicon nitride quantum dots. One type of quantum dots selected from the group is formed, and the second dielectric film includes silicon oxide.

  In other embodiments, the method further includes providing a dielectric material in the recess.

  In another aspect, the present invention provides a main gate dielectric film on a semiconductor substrate, a main gate electrode on the main gate dielectric film, and a charge trap structure on the semiconductor substrate and on the main gate electrode. Providing first and second auxiliary gate electrodes on first and second sidewalls of the main gate electrode on the main gate dielectric and selectively etching at least one exposed outer edge of the charge trapping structure; A first recess is formed between the semiconductor substrate and the first auxiliary gate electrode, and the source region is formed in the semiconductor substrate using the main gate electrode and the first and second auxiliary gate electrodes as an ion implantation mask. And a drain region, and a method for forming a non-volatile memory device.

  In one embodiment, the selective etching further forms a second recess between the semiconductor substrate and the second auxiliary gate electrode.

  In another embodiment, providing the first and second auxiliary gate electrodes forms first and second sidewall spacers of conductive material on the charge trapping structures on the sidewalls of the main gate electrode; The first and second sidewall spacers include first and second auxiliary gate electrodes, respectively, and a source region in the semiconductor substrate using the main gate electrode and the first and second sidewall spacers as an ion implantation mask. And forming a drain region.

  In another embodiment, providing a charge trapping structure provides a first dielectric film, a second dielectric film on the first dielectric film, and a third on the second dielectric film. Providing a dielectric film, wherein the first dielectric film comprises a material selected from the group consisting of silicon oxide and silicon oxynitride, and the second dielectric film is silicon nitride, silicon oxynitride And a material selected from the group consisting of a high dielectric constant material, and the third dielectric film includes silicon oxide.

  In other embodiments, the selective etching obtains a recess formed in the second dielectric film.

  In other embodiments, providing a charge trapping structure provides a first dielectric film, provides a quantum dot array on the first dielectric film, and provides a second dielectric film on the quantum dot array. And the first dielectric film comprises a material selected from the group consisting of silicon oxide and silicon oxynitride, and the quantum dot array is selected from the group consisting of polysilicon quantum dots and silicon nitride quantum dots And the second dielectric film includes silicon oxide.

  In other embodiments, the method further includes providing a dielectric material in the recess.

  In another embodiment, providing the source and drain regions prior to providing the first and second auxiliary gate electrodes in the semiconductor substrate using the main gate electrode as the first ion implantation mask. After the low concentration impurity source region and the low concentration impurity drain region are formed and the first and second auxiliary gate electrodes are provided, the main gate electrode and the first and second electrodes are used as the second ion implantation mask. Forming a high concentration impurity source region and a high concentration impurity drain region in the semiconductor.

  In another embodiment, the method further includes diffusing the lightly doped source and drain regions and the heavily doped source and drain regions in an inward direction to extend from one another.

  Specific matters of the other embodiments are included in the detailed description and the drawings.

  As described above, according to the nonvolatile memory cell structure having the charge trap film and the manufacturing method thereof according to the present invention, the threshold voltage of the device during the program operation and the threshold voltage of the device during the erase operation are at appropriate and constant levels. Maintained at. As a result, the characteristics of the element are improved.

  Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms. The present embodiment is intended to complete the disclosure of the present invention, and to those skilled in the art. The present invention is provided to fully inform the scope of the invention, and the present invention should be determined based on the description of the claims. Note that the same reference numerals denote the same components throughout the specification.

  In the accompanying drawings, the thickness of the membrane is exaggerated for clarity. Also, when referring to one film being formed on another film or substrate, this means that one film can be formed on another film or substrate, or a third film or added. It means that a film can be provided between one film and another film or substrate. Similar reference characters refer to similar elements throughout the specification.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 is a cross-sectional view illustrating a non-volatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed according to the present invention. The element includes a substrate 310, such as a semiconductor substrate. The source region and the drain region are provided on the opposite side of the channel region 381 of the element in the substrate 310. The source region includes a high concentration impurity region 391 and a low concentration impurity region 371. The drain region includes a high concentration impurity region 392 and a low concentration impurity region 372. The charge trapping film 320 is on the substrate 310 between the source and drain regions of the device. The charge trap structure 320 includes a tunneling film 325 formed of a dielectric film, a charge trap film 330 on the tunneling film, and a shielding film 335 formed of a dielectric film on the charge trap film 330. In one embodiment, the charge trapping film 330 includes an oxide-nitride-oxide (ONO) film. In other embodiments, the charge trapping film 330 includes a quantum dot structure. The gate electrode 350 is on the charge trapping structure 320, and the gate insulating film 360 is on the structure. There is a sidewall spacer 380 formed of a dielectric material on the source and drain sidewalls of the gate 350.

  In the present invention, the charge trap film 330 of the charge trap structure 320 is recessed under one or both sides of the gate 350. In the embodiment provided in FIG. 2, the charge trap film 330 is recessed below both sides of the source and drain sides of the gate 350. In one embodiment having a recess on one side of gate 350, the recess is provided on the source side of gate 350. Preferably, the recess is sufficiently deep so that the charge trapping film 330 does not overlap the source / drain regions 371 and 372. In the embodiment provided in FIG. 2, the recesses are formed so that the source side surface and the drain side surface of the charge trapping film 330 can be aligned with the inner edges of the low concentration impurity source region 371 and the low concentration impurity drain region 372. Formed on both sides of the side. In one embodiment, the gate length of the gate 350 is 0.2 μm, and the gate 350 overlaps the source region 371 by about 10 nm. In this embodiment, an appropriate recess depth is about 20 nm to 40 nm. The advantages of such an arrangement will be described later.

  FIG. 3A is a cross-sectional view illustrating a non-volatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed in a program operation process according to the present invention. FIG. 3B is a diagram showing the direction of an electric field that appears during a program operation in the device of FIG. 3A.

  As shown in FIG. 3A, during the program operation, a positive bias voltage is applied to the gate electrode g in a range of about 3.0V to 5.0V, for example, and a positive voltage is applied in a range of about 3.5V to 5.5V, for example. The bias voltage is applied to the source electrode s, and the ground electrode is applied to the drain electrode d. During the programming operation, thermionic electrons are trapped in the charge trapping film 330 and stored there. In this way, the threshold voltage of the memory cell 100 is increased. Referring to FIG. 3B, during the program operation, the gate electric field Eg is directed vertically downward, and the source / drain electric field Esd is directed from the source to the drain direction. During such operation, thermionic electrons tend to move to the overlap region A of the device, where the gate 350 is the low edge at the edge of the charge trapping film 330 closest to the source regions 371,391. It overlaps with the concentration impurity source region 371. The recess provided in the charge trapping film 330 minimizes the amount of thermal electrons trapped in the A region of the charge trapping film.

  FIG. 4A is a cross-sectional view illustrating a non-volatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed in an erase operation process according to the present invention. FIG. 4B is a drawing showing the direction of the electric field that appears during the erase operation in the device of FIG. 4A.

  As shown in FIG. 4A, during the erase operation, a negative bias voltage in the range of about -4.5V to -6.5V, for example, is applied to the gate electrode g, for example, in the range of about 4.5V to 6.5V. The positive bias voltage is applied to the source electrode s, and the ground electrode is applied to the drain electrode d. During such an erasing operation, the holes h move to the charge trapping film 330. Accordingly, the electrons stored in the charge trapping film are removed by holes or disappear. In this manner, the memory cell data is erased. Referring to FIG. 4B, during the erase operation, the gate electric field Eg is directed vertically upward, and the source / drain electric field Esd is directed from the source to the drain direction. Due to the presence of the recess in the region A, the electrons stored in the charge trap film 330 during the erasing process are annihilated and do not remain on the source side surface of the charge trap film 330 by the recess.

  5A to 5F are cross-sectional views illustrating a first process of forming a non-volatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a source and a drain according to the present invention. FIG. Referring to FIG. 5A, a first dielectric film 325a as a tunneling film, a second dielectric film 330a as a charge trapping film, and a third dielectric film 335a as a shielding film are sequentially provided on the substrate 310. In an exemplary embodiment, the first dielectric layer 325a may be formed to have a thickness of about 30 to 50 mm, for example, by an RT (Rapid Thermal) process, a CVD (Chemical Vapor Deposition) process, a furnace process, or other suitable deposition or growth process. It includes silicon oxide or silicon oxynitride formed to a certain thickness. The second dielectric film 330a may be formed of silicon nitride, silicon oxynitride, having a thickness of about 30 to 100 mm using CVD, LPCVD (Low-Pressure CVD), or other suitable deposition or growth process. Or a high dielectric constant material or a combination thereof. The third dielectric film 335a includes silicon oxide formed to a thickness of about 50 to 150 mm by, for example, CVD, LPCVD, or other suitable deposition or growth process. A conductive material film 350a suitable for forming a gate electrode is then deposited on the resulting structure. In one embodiment, the conductive material film 350a includes a polysilicon material, a metal material, or a combination thereof. The uppermost portion of the conductive material film 350a can be selectively processed to form a polysilicon-silicide film implanted with positive impurities. The conductive material film 350a can be applied to a depth of about 80 to 2000 mm using, for example, CVD or LPCVD.

  Referring to FIG. 5B, the resulting structure is sequentially patterned using a standard photolithography technique to form a gate electrode 350b, a shielding film 335b, a charge trapping film 330b, and a tunneling film 325b.

Referring to FIG. 5C, a selective etching process is performed on the obtained structure to selectively etch the outer portion of the charge trapping film 330b. In one embodiment, when the charge trapping film 330c includes silicon nitride or silicon oxynitride, a wet etching solution including phosphoric oxide (H ₃ PO ₄ ) is suitable for increasing the etching ratio. Following the etching of the charge trapping film 330c, a recess is formed at the edge of the charge trapping film 330c, and the tunneling film 325b and the shielding film 335b remain with almost the same width as the gate electrode 350b.

  Referring to FIG. 5D, ion implantation is performed on the obtained structure to form low concentration impurity source / drain regions 371 and 372 of the source / drain region of the device. The obtained low-concentration impurity source / drain regions 371 and 372 are self-aligned with the gate electrode 350b. The self-aligned low-concentration impurity source / drain region can be formed following selective etching of the charge trapping film 330c, or optionally can be formed prior to selective etching of the charge trapping film 330c. A gate insulating film 360 is then formed on the resulting structure. In one embodiment, the gate insulating layer 360 includes silicon oxide formed to a thickness of about 50 to 100 inches, for example, by CVD, LPCVD, or other suitable deposition or growth process. The recessed region of the charge trapping film 330c is filled with the gate insulating film 360 applied partially or entirely.

  Referring to FIG. 5E, sidewall spacers 380 are formed on the sidewalls on both sides of the source and drain of the gate electrode 350b. In one embodiment, a silicon nitride film is provided on the resulting structure, but is formed to a thickness of 500 to 700 inches, for example, by CVD or other suitable deposition or growth process. Thereafter, an etch back process is performed according to a conventional technique to form the sidewall spacer 380.

  Referring to FIG. 5F, ion implantation is performed on the resulting structure to form high concentration impurity source / drain regions 391 and 392 of the source / drain region of the device. The resulting high concentration impurity source / drain regions 391, 392 are self-aligned with the sidewall spacers 380. In order to further diffuse the low-concentration impurity source / drain regions 371 and 372 into the channel region, a diffusion process is performed on the obtained structure using, for example, an RT process at a temperature of about 1000 ° C. or higher for several seconds. Thus, the gate electrode 350b overlaps with the low concentration impurity source / drain regions 371 and 372.

  As a result of the first manufacturing process of the nonvolatile memory element, the element of FIG. 2 is formed. The resulting device 100 of FIG. 2 has a recessed charge trapping film. As described above, the recess minimizes the amount of electrons trapped in the charge trapping film on the overlapping region of the gate electrode 350b and the low-concentration impurity source region 371. This stabilizes the transistor threshold voltage during the programming and erasing process, and makes the operation more reliable. For example, the recess can prevent misreading of data information stored in the charge trapping film despite frequent SONOS memory device accesses and numerous repetitive program and erase operations.

  6A-6B are diagrams illustrating a second process of forming a memory device having a SONOS type charge trap structure in accordance with the present invention, wherein the charge trap structure is on one of the gate source and drain sides. Only, for example, only on the source side of the gate is recessed. As shown in FIG. 6A, the second step is a photoresist pattern 510c to prevent the charge trap film 530c on the drain side from being selectively etched during the selective etching stage of the charge trap film 530c. Is applied to the drain side of the structure, but is substantially the same as the first step except that the charge trapping film 530c is selectively etched to form a recess in the manner mentioned above. is there. Following the selective etching of charge trap film 530c, the steps shown in FIGS. 5D-5F are performed to have charge trap film 530c with a recess formed only on the source side of charge trap film 530c. The structure shown in is obtained. The embodiment of FIG. 6 is particularly applicable when there is an asymmetry between the source and drain of the transistor, for example when the source and drain are asymmetric in impurity implantation concentration and profile. For applications where recesses in the charge trapping film on both sides of the source and drain are allowed, the fabrication method according to the embodiment of FIGS. 5A-5F is preferred, but such a process is an additional step shown in FIG. 6A. This is because an unnecessary masking step is unnecessary.

7A to 7G are cross-sectional views illustrating a third process for forming a nonvolatile memory device having a charge trap structure in a quantum dot array according to the present invention. Recessed on both sides of the gate source and drain sides as it is on the source sides. Referring to FIG. 7A, a first dielectric film 625a as a tunneling film, a quantum dot array 630a as a charge trapping film, and a second dielectric film 635a as a shielding film are sequentially provided on the substrate 310. In an exemplary embodiment, the first dielectric layer 625a may be a silicon oxide formed to a thickness of about 30 to 50 mm by, for example, an RT process, a CVD process, a furnace process, or other suitable deposition or growth process, or Contains silicon oxynitride. Quantum dot array 630a, in one embodiment, the use of a mixture of about 500 ° C. dichlorosilane with to 700 ° C. range temperature LPCVD or other suitable deposition process (dichlorosilane) and hydrogen gas _{(H 2)} 1 including a polysilicon quantum dot array applied to the upper surface of one dielectric film 625a. In another embodiment, the quantum dot array 630a includes a silicon nitride quantum dot array formed by nitriding the polysilicon quantum dot array described above. In one optional step, quantum dots are oxidized to reduce their diameter. The second dielectric film 635a includes silicon oxide formed to a thickness of about 50 to 150 mm by, for example, CVD, LPCVD, or other suitable deposition or growth process. A conductive material film 350a suitable for forming a gate electrode is then deposited on the resulting structure. In one embodiment, the conductive material film 350a includes a polysilicon material, a metal material, or a combination thereof. The uppermost portion of the conductive material film 350a can be arbitrarily processed to obtain a polysilicon-silicide film into which positive impurities are implanted. The conductive material film 350a is applied to a thickness of about 80 to 2000 mm using, for example, a CVD or LPCVD process.

  Referring to FIG. 7B, the resulting structure is sequentially patterned using standard photolithography techniques to form a gate electrode 350b, a shielding film 635b, a quantum dot array 630b, and a tunneling film 625b.

  Referring to FIG. 7C, a selective etching process is performed on the obtained structure to selectively etch an outer portion of the charge trap structure 620 including the charge trap film 630b in the quantum dot array form. In one embodiment, when the tunneling film 625b and the shielding film 635b include silicon oxide or silicon oxynitride, a wet etchant including hydrogen fluoride (HF) is suitable for increasing the etching ratio. After etching the charge trapping structure 620, a recess is formed at the edge of the charge trapping structure 620 including the charge trapping film 630c, the tunneling film 625c, and the shielding film 635c.

  Referring to FIG. 7D, ion implantation is performed on the resulting structure to form low concentration impurity source / drain regions 371 and 372 of the source / drain region of the device. The resulting low concentration impurity source / drain regions 371, 372 are self-aligned with the gate electrode 350b. The self-aligned low-concentration impurity source / drain region can be formed following selective etching of the charge trapping film 630c, or optionally can be formed prior to selective etching of the charge trapping film 630c. A gate insulating film 360 is then formed on the resulting structure. In one embodiment, the gate insulating layer 360 includes silicon oxide formed to a thickness of about 50-100 cm, for example, by CVD, LPCVD, or other suitable deposition or growth process. The recess region of the charge trap structure 620 is filled with a gate insulating film 360 that is applied partially or entirely.

  Referring to FIG. 7E, sidewall spacers 380 are formed on both sides of the source and drain of gate electrode 350b. In one embodiment, the silicon nitride film is formed on a structure obtained to a thickness on the order of about 500 to 700 inches, for example, by CVD or other suitable deposition or growth process. Thereafter, an etch back process is performed according to a conventional technique to form the sidewall spacer 380.

  Referring to FIG. 7F, ion implantation is performed on the resulting structure to form high concentration impurity source / drain regions 391, 392 of the source / drain region of the device. The resulting high concentration impurity source / drain regions 391, 392 are self-aligned with the sidewall spacers 380.

  Referring to FIG. 7G, to further diffuse the low concentration impurity source / drain region into the channel region, diffuse over the resulting structure using, for example, an RT process at a temperature of about 1000 ° C. or higher for several seconds. By performing the process, the gate electrode 350 b overlaps with the low concentration impurity source / drain regions 371 and 372. In one embodiment, the lightly doped source / drain regions 371, 372 are extended so that their inner edges are approximately aligned with the recessed edges of the charge trap structure 620. Such alignment ensures the annihilation of electrons trapped by hole transfer during the erase operation. The smaller recess can allow the charge trapping structure 620 to overlap the low concentration impurity source / drain regions 371, 372, reducing the possibility of complete annihilation of electrons during the erase operation. The recess formed deeper can lead to the removal of a substantial portion of the charge trap structure 620 that requires hole annihilation.

  As a result of the third manufacturing process of the non-volatile memory device, the resulting device 600 has a recessed charge trapping film, providing the advantages mentioned above.

  8A and 8B are cross-sectional views illustrating a fourth process for forming a non-volatile memory device having a quantum dot array-like charge trap structure according to the present invention. Recessed only on one of the source and drain sides of the gate, as is the case on the source side. FIGS. 8A and 8B are diagrams illustrating a fourth step of forming a memory device having a SONOS type charge trapping structure, where the charge trapping structure is formed only on one of the gate source and drain side surfaces, for example, Recessed only on the source side of the gate as in the invention. The fourth step is a photoresist pattern 710 to prevent the charge trapping structure 720 from being selectively etched during the selective etching stage of the charge trapping structure 720, as shown in FIG. 8A. Is applied, but is substantially the same as the third step except that the charge trapping structure 720 is selectively etched to form a recess in the manner referred to above. Following the selective etching of the charge trapping structure 720, the steps shown in FIGS. 7D-7G are performed to form a charge trapping structure 720 with a recess formed only on the source side of the charge trapping structure 720. The structure shown in FIG. 8B is obtained. The embodiment of FIG. 8A is particularly applicable when there is an asymmetry between the source and drain of the transistor, such as when the source and drain are asymmetric in impurity implantation concentration and profile. For applications where recesses in the charge trapping film on both sides of the source and drain are acceptable, the fabrication method according to the embodiment of FIGS. 7A-7G is preferred, but such a process is the additional step shown in FIG. 8A. This is because the masking step is unnecessary.

  9A to 9D illustrate a fifth step of forming a non-volatile memory device having a localized SONOS type charge trap structure with a recessed charge trap film on one side of the source and drain sides according to the present invention. It is sectional drawing which showed. Referring to FIG. 9A, a first dielectric film 825a as a tunneling film, a second dielectric film 830a as a charge trapping film, and a third dielectric film as a shielding film, for example, by a method corresponding to the embodiment mentioned above. 835a is sequentially provided on the substrate 310.

  Referring to FIG. 9B, the resulting structure is patterned using standard photolithography techniques to form a shielding film 835b, a charge trapping film 830b, and a tunneling film 825b.

  Referring to FIG. 9C, the fourth dielectric film for forming the coupling film 840 is formed to a thickness of about 50 to 100 mm by, for example, CVD, LPCVD, or other suitable deposition or growth process. Provided on structures obtained with silicon oxide. A conductive material film suitable for forming a gate electrode is then deposited on the resulting structure, and the conductive material film and the fourth dielectric film are patterned using an existing photolithography process. A gate electrode 850 is formed on the coupling film 840 on the charge trap structure 820 and 310. In one embodiment, the conductive material film 850 includes a polysilicon material, a metal material, or a combination thereof. The uppermost portion of the conductive material film 850 can be arbitrarily processed to form a polysilicon-silicide film into which positive impurities are implanted. The conductive material film is applied to a thickness of about 80 to 2000 mm using, for example, a CVD or LPCVD process.

Referring to FIG. 9D, a selective etching process is performed on the obtained structure to selectively etch the exposed outer portion of the charge trap film 830b. In one embodiment, when the charge trapping film 830b includes silicon nitride or silicon oxynitride, a wet etching solution including phosphoric acid oxide (H ₃ PO ₄ ) is suitable for increasing the etching ratio. As shown, a recess is formed at the exposed edge of the charge trapping film 830c following etching of the charge trapping film 830c.

  Ion implantation is performed on the resulting structure to form low concentration impurity source / drain regions 871, 872 of the source / drain regions of the device. The resulting low concentration impurity source / drain regions 871, 872 are self-aligned with the gate electrode 850. The self-aligned low-concentration impurity source / drain region can be formed following selective etching of the charge trapping film 830c, or optionally can be formed prior to selective etching of the charge trapping film 830c. A gate insulating film 360 is then formed on the resulting structure. In one embodiment, the gate insulating layer 360 includes silicon oxide formed to a thickness of about 50 to 100 inches, for example, by CVD, LPCVD, or other suitable deposition or growth process. The recessed region of the charge trapping film 830c is filled with the gate insulating film 360 applied partially or entirely.

  The sidewall spacers 380 are formed on the sidewalls on both sides of the source and drain of the gate electrode 850. In one embodiment, a silicon nitride film is provided on the resulting structure at a thickness of about 500 to 700 inches, for example, by CVD or other suitable deposition or growth process. Thereafter, an etch back process is performed according to a conventional technique to form the sidewall spacer 380.

  Next, ion implantation is performed on the obtained structure to form high-concentration impurity source / drain regions 891 and 892 of the source / drain region of the device. The resulting high concentration impurity source / drain regions 891, 892 are self-aligned with the sidewall spacers 380. In order to further diffuse the low-concentration impurity source / drain regions 871 and 872 into the channel region, a diffusion process is performed on the resulting structure using, for example, an RT process at a temperature of about 1000 ° C. or higher for several seconds. As a result, the gate electrode 850 overlaps with the low concentration impurity source / drain regions 871 and 872.

  As a result of the fifth manufacturing process of the non-volatile memory device, the device 800 has a recessed charge trapping film, providing the advantages mentioned above.

  10A to 10D are cross-sectional views illustrating a sixth process for forming a nonvolatile memory device having a charge trap structure localized in a quantum dot array according to the present invention. The charge trap film is recessed on one side of the gate source and drain side as in the case of on the side. Referring to FIG. 10A, a first dielectric film 925a as a tunneling film, a quantum dot array 930a as a charge trapping film, and a second dielectric film 935a as a shielding film, for example, in a manner corresponding to the embodiment mentioned above. Provided on the substrate 310.

  Referring to FIG. 10B, the resulting structure is patterned using standard photolithography techniques to form a shielding film 935b, a charge trapping film 930b, and a tunneling film 925b.

  Referring to FIG. 10C, a third dielectric film for forming the coupling film 840 is provided on the resulting structure, but is reduced by, for example, CVD, LPCVD, or other suitable deposition or growth process. It includes silicon oxide formed to a thickness of about 50 to 100 mm. A suitable conductive film for forming the gate electrode is then deposited on the resulting structure, and the conductive material film and the fourth dielectric film are patterned using a conventional photolithography process to form the substrate 310 and the charge. A gate electrode 850 is formed on the coupling film 840 on the trap film 920. In one embodiment, the conductive material film 850 includes a polysilicon material, a metal material, or a combination thereof. The uppermost portion of the conductive material film 850 can be arbitrarily processed to form a polysilicon-silicide film into which positive impurities are implanted. The conductive material film is applied to a thickness of about 80 to 2000 mm using, for example, a CVD or LPCVD process.

  Referring to FIG. 10D, a selective etching process is performed on the resulting structure to selectively etch the exposed exterior of the charge trapping structure 920. In one embodiment, when the tunneling film 925c and the shielding film 935c include silicon oxide or silicon oxynitride, a wet etching solution including hydrogen fluoride is suitable for increasing the etching ratio. Following etching of the charge trapping structure 920, a recess is formed at the exposed edge of the charge trapping structure 920.

  Ion implantation is performed on the resulting structure to form low concentration impurity source / drain regions 871, 872 of the source / drain regions of the device. The resulting low concentration impurity source / drain regions 871, 872 are self-aligned with the gate electrode 850. The self-aligned low-concentration impurity source / drain region can be formed following selective etching of the charge trapping film 930c, or optionally can be formed prior to selective etching of the charge trapping film 930c. A gate insulating film 360 is then formed on the resulting structure. In one embodiment, the gate insulating layer 360 includes silicon oxide formed to a thickness of about 50 to 100 inches, for example, by CVD, LPCVD, or other suitable deposition or growth process. The recessed region of the charge trap structure 920 is filled with a partially or fully applied gate insulating layer 360.

  The sidewall spacers 380 are formed on the sidewalls on both sides of the source and drain of the gate electrode 850. In one embodiment, the silicon nitride film is provided on a structure obtained to a thickness of 500 to 700 inches, for example, by CVD or other suitable deposition or growth process. Thereafter, an etch back process is performed according to a conventional technique to form the sidewall spacer 380.

  Ion implantation is performed on the obtained structure to form high-concentration impurity source / drain regions 891 and 892 in the source / drain regions of the device. The resulting high concentration impurity source / drain regions 891, 892 are self-aligned with the sidewall spacers 380. In order to further diffuse the low-concentration impurity source / drain regions 871 and 872 into the channel region, a diffusion process is performed on the resulting structure using, for example, an RT process at a temperature of about 1000 ° C. or higher for several seconds. As a result, the gate electrode 850 overlaps with the low concentration impurity source / drain regions 871 and 872. In one embodiment, the lightly doped source / drain regions 871 and 872 are extended so that the inner edge of the lightly doped region 871 is approximately aligned with the recessed edge of the charge trap structure 920.

  As a result of the sixth manufacturing process of the non-volatile memory device, the resulting device 900 has a recessed charge trapping film, providing the advantages mentioned above.

  11A to 11F are cross-sectional views illustrating a seventh step of forming a halo type nonvolatile memory device having a SONOS type charge trap structure according to the present invention, on both sides of a source and a drain. The charge trapping film is recessed.

  Referring to FIG. 11A, a gate insulating film is formed on the substrate. In one embodiment, the gate insulating layer includes silicon oxide formed to a thickness of about 50-100 cm, for example, by CVD, LPCVD, or other suitable deposition or growth process. A conductive material film suitable for forming a gate electrode on the gate insulating film is provided. In one embodiment, the conductive material film includes a polysilicon material, a silicon-germanium-based material, a germanium-based material, or a combination thereof. The uppermost portion of the conductive material film can be arbitrarily treated to form a polysilicon-silicide film implanted with positive impurities. The conductive material film is applied to a thickness of about 80 to 2000 mm using, for example, a CVD or LPCVD process. The gate insulating film and the conductive material film are patterned using a conventional photolithography process to form a gate insulating film 1015 and a main gate electrode 1018.

  Ion implantation is performed on the obtained structure to form low-concentration impurity source / drain regions 1071 and 1072 in the source / drain regions of the device. The obtained low-concentration impurity source / drain regions 1071 and 1072 are self-aligned with the main gate electrode 1018. In order to further diffuse the low-concentration impurity source / drain regions 1071 and 1072 to the inside of the channel region, a diffusion process is performed on the obtained structure using, for example, an RT process at a temperature of about 1000 ° C. or higher for several seconds. As a result, the main gate electrode 1018 overlaps with the low-concentration impurity source / drain regions 1071 and 1072.

  Referring to FIG. 11B, the first dielectric film 1025a as the tunneling film, the second dielectric film 1030a as the charge trapping film, and the third dielectric film 1035a as the shielding film, for example, as described above with reference to FIG. 5A. It is sequentially provided on the main gate electrode 1018 and the substrate 310 in a manner corresponding to the embodiment. Referring to FIG. 11C, conductive sidewall spacers 1050 are formed on both side walls of the source and drain of the main gate electrode 1018. In one embodiment, a conductive material film comprising, for example, a polysilicon material, a silicon-germanium-based material, a germanium-based material, or a combination thereof is formed, for example, by CVD to form a conductive spacer. , Provided by a LPCVD or other suitable deposition or growth process on a structure obtained to a thickness on the order of about 500-700 mm. Thereafter, an etch back process is performed according to a conventional technique to form a conductive side wall spacer 1050, which provides a function of a side gate electrode of the device.

  Referring to FIG. 11D, exposed portions of the first, second, and third dielectric films 1025a, 1030a, and 1035a are etched to form a tunneling film 1025b and a charge trapping film 1030b on each side surface of the main gate electrode 1018. Then, a shielding film 1035b is formed.

Referring to FIG. 11E, a selective etching process is performed on the obtained structure to selectively etch the exposed outside of the charge trapping film 1030b. In one embodiment, when the charge trapping film includes silicon nitride or silicon oxynitride, a wet etchant including phosphoric oxide (H ₃ PO ₄ ) is suitable for increasing the etching ratio. Following the etching of the charge trapping film 1030c, a recess is formed at the edge of the charge trapping film 1030c.

  Referring to FIG. 11F, ion implantation is performed on the structure obtained to form the high concentration impurity source / drain regions 1091 and 1092 of the device. The resulting high concentration impurity source / drain regions 1091, 1092 are self-aligned with the side gate electrode 1050. Ion implantation to form the high concentration impurity source / drain regions 1091 and 1092 can be formed subsequent to the selective etching of the charge trapping film 1030c, or optionally before the selective etching of the charge trapping film 1030c. In order to further diffuse the low-concentration impurity source / drain regions 1071, 1072 and the high-concentration impurity regions 1091, 1092 to the inside of the channel region, it was obtained using, for example, an RT process at a temperature of about 1000 ° C. or higher for several seconds. By performing a diffusion process on the structure, the gate electrode 1050 is overlapped with the high concentration impurity source / drain regions 1091 and 1092.

  As a result of the seventh step for fabricating the non-volatile memory device, the resulting halo type device 1000 has a recessed charge trapping film, providing the advantages mentioned above.

  12A to 12F are cross-sectional views illustrating an eighth step of forming a halo type non-volatile memory device having a charge trap structure in the form of a quantum dot array according to the present invention. Recessed on both sides of the drain.

  Referring to FIG. 12A, a gate insulating film is formed on the substrate. In one embodiment, the gate insulating layer includes silicon oxide formed to a thickness of about 50-100 cm, for example, by CVD, LPCVD, or other suitable deposition or growth process. A conductive material film suitable for forming a gate electrode on the gate insulating film is provided. In one embodiment, the conductive material film includes a polysilicon material, a silicon-germanium-based material, a germanium-based material, or a combination thereof. The conductive material film is applied to a thickness of about 80 to 2000 mm using, for example, a CVD or LPCVD process. The gate insulating film and the conductive material film are patterned using a conventional photolithography technique to form a gate dielectric film 1015 and a main gate electrode 1018.

  In order to form the low concentration impurity source / drain regions 1071 and 1072 in the source / drain region of the device, ion implantation is performed on the obtained structure. The low concentration impurity drain / source regions 1071 and 1072 are self-aligned with the main gate electrode 1018.

  Referring to FIG. 12B, the first dielectric film 1125a, which is a tunneling film, a charge trap film in the form of a quantum dot array 1130a, and a third film, which is a shielding film, are added to the method described above with reference to FIG. 7A, for example. A dielectric film 1135 a is provided on the main gate electrode 1018 and the substrate 310.

  Referring to FIG. 12C, conductive sidewall spacers 1050 are formed on both sides of the source and drain sidewalls of main gate electrode 1018. In one embodiment for forming a conductive spacer, a conductive material film including, for example, polysilicon, a silicon-germanium-based material, a germanium-based material, or a combination thereof may be, for example, CVD or other. Is provided on a structure obtained to a thickness of about 500 to 700 mm. Thereafter, an etch-back process is performed by conventional techniques to form sidewall spacers 1050, which provide the function of the side gate electrodes of the device.

  Referring to FIG. 12D, exposed portions of the first dielectric film 1125a, the quantum dot array 1130a, and the second dielectric film 1135a are etched to form a tunneling film 1125b and a charge trap on each side surface of the main gate electrode 1018. A charge trap structure 1120 including a film 1130b and a shielding film 1135b is formed.

  Referring to FIG. 12E, a selective etching process is performed on the resulting structure, for example by the process mentioned above in conjunction with FIG. 7C, so that the exposed exterior of the charge trapping structure 1120 is selectively etched. The Following etching of the charge trapping structure 1120, a recess is formed at the edge of the charge trapping structure 1120.

  Referring to FIG. 12F, ion implantation is performed on the obtained structure to form high concentration impurity source / drain regions 1091 and 1092 of the device. The resulting high concentration impurity source / drain regions 1091 and 1092 are self-aligned with the side gate electrode 1050. Self-aligned heavily doped source / drain regions 1091 and 1092 can be formed following selective etching of the charge trapping structure 1120, or optionally prior to selective etching of the charge trapping structure 1120. In order to further diffuse the low-concentration impurity source / drain regions 1071 and 1072 and / or the high-concentration impurity source / drain structures 1091 and 1092 into the channel region, an RT process is performed for several seconds at a temperature of about 1000 ° C. or higher, for example. The side gate electrode 1050 is overlapped with the high-concentration impurity source / drain regions 1091 and 1092 by performing a diffusion process on the obtained structure. As a result of the eighth step for the manufacture of the non-volatile memory device, the resulting device 1100 has a recessed charge trapping film, providing the advantages mentioned above.

  The preferred embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art will recognize other specific forms without changing the technical idea and essential features of the present invention. It can be understood that it can be implemented. Accordingly, the preferred embodiments described above are to be understood as illustrative and not restrictive.

  The nonvolatile memory device and the manufacturing method thereof of the present invention can be applied to memory devices of various electronic devices.

1 is a cross-sectional view illustrating a conventional nonvolatile memory device having a SONOS type charge trapping structure. 1 is a cross-sectional view illustrating a nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film according to the present invention is recessed; FIG. 1 is a cross-sectional view illustrating a nonvolatile memory device having a SONOS type charge trap structure with a recessed charge trap film in a program operation process according to the present invention; 3B is a diagram illustrating the direction of an electric field that appears during a program operation in the device of FIG. 3A. FIG. 3 is a cross-sectional view illustrating a nonvolatile memory device having a SONOS type charge trap structure with a recessed charge trap film in an erase operation process according to the present invention. 4B is a diagram showing the direction of an electric field appearing during an erase operation in the device of FIG. 4A. 4 is a cross-sectional view illustrating a first process of forming a nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a gate source and a drain according to the present invention. FIG. 4 is a cross-sectional view illustrating a first process of forming a nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a gate source and a drain according to the present invention. FIG. 4 is a cross-sectional view illustrating a first process of forming a nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a gate source and a drain according to the present invention. FIG. 4 is a cross-sectional view illustrating a first process of forming a nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a gate source and a drain according to the present invention. FIG. 4 is a cross-sectional view illustrating a first process of forming a nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a gate source and a drain according to the present invention. FIG. 4 is a cross-sectional view illustrating a first process of forming a nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a gate source and a drain according to the present invention. FIG. 4 is a cross-sectional view illustrating a second process of forming a non-volatile memory device having a SONOS type charge trap structure in which a charge trapping film is recessed at any one of a gate source and a drain side according to the present invention. It is. 4 is a cross-sectional view illustrating a second process of forming a non-volatile memory device having a SONOS type charge trap structure in which a charge trapping film is recessed at any one of a gate source and a drain side according to the present invention. It is. In accordance with the present invention, the charge trapping film is recessed on both sides of the gate source and drain to show a third step of forming a non-volatile memory device having a charge trapping structure in the form of a quantum dot array. FIG. In accordance with the present invention, the charge trapping film is recessed on both sides of the gate source and drain to show a third step of forming a non-volatile memory device having a charge trapping structure in the form of a quantum dot array. FIG. In accordance with the present invention, the charge trapping film is recessed on both sides of the gate source and drain to show a third step of forming a non-volatile memory device having a charge trapping structure in the form of a quantum dot array. FIG. In accordance with the present invention, the charge trapping film is recessed on both sides of the gate source and drain to show a third step of forming a non-volatile memory device having a charge trapping structure in the form of a quantum dot array. FIG. In accordance with the present invention, the charge trapping film is recessed on both sides of the gate source and drain to show a third step of forming a non-volatile memory device having a charge trapping structure in the form of a quantum dot array. FIG. In accordance with the present invention, the charge trapping film is recessed on both sides of the gate source and drain to show a third step of forming a non-volatile memory device having a charge trapping structure in the form of a quantum dot array. FIG. In accordance with the present invention, the charge trapping film is recessed on both sides of the gate source and drain to show a third step of forming a non-volatile memory device having a charge trapping structure in the form of a quantum dot array. FIG. According to the present invention, the charge trapping film is recessed at any one of the gate source and drain side surfaces to form a nonvolatile memory device having a charge trapping structure in the form of a quantum dot array. It is sectional drawing which showed. According to the present invention, the charge trapping film is recessed at any one of the gate source and drain side surfaces to form a nonvolatile memory device having a charge trapping structure in the form of a quantum dot array. It is sectional drawing which showed. In accordance with the present invention, the charge trapping film comprises a fifth step of forming a non-volatile memory device having a localized SONOS type charge trap structure recessed at one of the gate source and drain sides. It is sectional drawing shown. According to the present invention, the charge trapping film includes a fifth step of forming a non-volatile memory device having a localized SONOS type charge trap structure recessed in one of the gate source and drain side surfaces. It is sectional drawing shown. According to the present invention, the charge trapping film includes a fifth step of forming a non-volatile memory device having a localized SONOS type charge trap structure recessed in one of the gate source and drain side surfaces. It is sectional drawing shown. According to the present invention, the charge trapping film includes a fifth step of forming a non-volatile memory device having a localized SONOS type charge trap structure recessed in one of the gate source and drain side surfaces. It is sectional drawing shown. In accordance with the present invention, a sixth step of forming a non-volatile memory device having a localized charge trap structure in the form of a quantum dot array, wherein the charge trap film is recessed at one of the source and drain side surfaces. It is sectional drawing shown. In accordance with the present invention, a sixth step of forming a non-volatile memory device having a localized charge trap structure in the form of a quantum dot array, wherein the charge trap film is recessed in one of the source and drain side surfaces. It is sectional drawing shown. In accordance with the present invention, a sixth step of forming a non-volatile memory device having a localized charge trap structure in the form of a quantum dot array, wherein the charge trap film is recessed in one of the source and drain side surfaces. It is sectional drawing shown. In accordance with the present invention, a sixth step of forming a non-volatile memory device having a localized charge trap structure in the form of a quantum dot array, wherein the charge trap film is recessed in one of the source and drain side surfaces. It is sectional drawing shown. FIG. 10 is a cross-sectional view illustrating a seventh step of forming a halo type nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a source and a drain according to the present invention; FIG. 10 is a cross-sectional view illustrating a seventh step of forming a halo type nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a source and a drain according to the present invention; FIG. 10 is a cross-sectional view illustrating a seventh step of forming a halo type nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a source and a drain according to the present invention; FIG. 10 is a cross-sectional view illustrating a seventh step of forming a halo type nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a source and a drain according to the present invention; FIG. 10 is a cross-sectional view illustrating a seventh step of forming a halo type nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a source and a drain according to the present invention; FIG. 10 is a cross-sectional view illustrating a seventh step of forming a halo type nonvolatile memory device having a SONOS type charge trap structure in which a charge trap film is recessed on both sides of a source and a drain according to the present invention; 8 is a cross-sectional view illustrating an eighth step of forming a halo type nonvolatile memory device having a charge trap structure in the form of a quantum dot array in which a charge trap film is recessed on both sides of a source and a drain according to the present invention. It is. 8 is a cross-sectional view illustrating an eighth step of forming a halo type nonvolatile memory device having a charge trap structure in the form of a quantum dot array in which a charge trap film is recessed on both sides of a source and a drain according to the present invention. It is. 8 is a cross-sectional view illustrating an eighth step of forming a halo type nonvolatile memory device having a charge trap structure in the form of a quantum dot array in which a charge trap film is recessed on both sides of a source and a drain according to the present invention. It is. 8 is a cross-sectional view illustrating an eighth step of forming a halo type nonvolatile memory device having a charge trap structure in the form of a quantum dot array in which a charge trap film is recessed on both sides of a source and a drain according to the present invention. It is. 8 is a cross-sectional view illustrating an eighth step of forming a halo type nonvolatile memory device having a charge trap structure in the form of a quantum dot array in which a charge trap film is recessed on both sides of a source and a drain according to the present invention. It is. 8 is a cross-sectional view illustrating an eighth step of forming a halo type nonvolatile memory device having a charge trap structure in the form of a quantum dot array in which a charge trap film is recessed on both sides of a source and a drain according to the present invention. It is.

Explanation of symbols

100, 500, 600, 700, 800, 900, 1000, 1100 Non-volatile memory element 102, 310 Substrate 320, 520, 620, 720, 820, 920, 1020, 1120 Charge trap structure 325 Tunneling layer 330 Charge trap layer 335 Shielding layer 350 Gate electrode 360 Insulating film 371 Low concentration impurity region 380 Spacer 392 High concentration impurity region 510 Photoresist pattern

Claims (14)

A semiconductor substrate;
A source region and a drain region that are provided in space in the upper layer portion of the substrate;
A charge trap structure on the substrate between the source region and the drain region, and a gate electrode on the charge trap structure,
The charge trapping structure, the semiconductor substrate and is formed between the gate electrode and the first dielectric film as a tunneling film laminated in the thickness direction of the semiconductor substrate, as electric load trap film Including a second dielectric film and a third dielectric film as a shielding film ;
A recess selectively exists in the second dielectric film of the charge trapping structure between at least one of the gate electrode and the source region and the drain region ;
The edge of the second dielectric film, the nonvolatile memory element characterized that you have aligned with the edge of the source region and the drain region where the recess exists.   The non-volatile memory device of claim 1, wherein at least one inner edge of the source and drain regions is substantially aligned with an outer edge of the charge trapping structure.   The nonvolatile memory device of claim 1, wherein the recess is on a side surface of the source region of the charge trapping structure.   The nonvolatile memory device of claim 1, wherein the recess is on both sides of a source region side surface and a drain region side surface of the charge trapping structure.   The nonvolatile memory device of claim 1, further comprising a dielectric material in the recess. The charge trapping structure includes the first dielectric film including a material selected from the group consisting of silicon oxide and silicon oxynitride;
A second dielectric film formed on the first dielectric film and including a material selected from the group consisting of silicon nitride, silicon oxynitride, and a high dielectric constant material; and the second dielectric film. The nonvolatile memory device according to claim 1, further comprising: the third dielectric film including silicon oxide. The first dielectric film, wherein the charge trapping structure includes a material selected from the group consisting of silicon oxide and silicon oxynitride;
A quantum dot array formed on the first dielectric film and including a quantum dot of a type selected from the group consisting of polysilicon quantum dots and silicon nitride quantum dots; and a silicon oxide on the quantum dot array. Including the second dielectric film;
The nonvolatile memory device according to claim 1, comprising: The charge trapping structure extends from the source region to an intermediate region between the source region and the drain region,
A gate dielectric on the substrate extending from the charge trapping structure in the intermediate region to the drain region;
The nonvolatile memory device of claim 1, wherein the gate electrode is on the charge trapping structure and the gate dielectric film. The charge trapping structure includes a first charge trapping structure;
The gate electrode includes a first auxiliary gate electrode;
A main gate dielectric on the substrate between the source region and the drain region;
A main gate electrode on the main gate dielectric film;
The first charge trapping structure on the substrate between the source region and the main gate electrode;
The first recess is present in the first charge trapping structure on the first charge trapping structure and between the first auxiliary gate electrode and a portion of the source region. 1 auxiliary gate electrode;
A second charge trapping structure on the substrate between the drain region and the main gate electrode, and on the second charge trapping structure, wherein the second auxiliary gate electrode and the drain region A second auxiliary gate electrode having a second recess in the second charge trapping structure between a portion thereof;
The nonvolatile memory device according to claim 1, further comprising: A semiconductor substrate;
A source region and a drain region provided in space on the upper layer portion of the substrate,
A main gate dielectric overlying the substrate between the source region and the drain region;
A main gate electrode on the main gate dielectric film;
A first charge trapping structure on the substrate between the source region and the main gate electrode;
A first auxiliary gate electrode present on the first charge trapping structure, wherein the first charge trapping structure is located between the first auxiliary gate electrode and a part of the source region; The first auxiliary gate electrode in which a first recess is present;
A second charge trap structure on the substrate between the drain region and the main gate electrode; and a second auxiliary gate electrode present on the second charge trap structure, The second auxiliary gate electrode having a second recess in the second charge trapping structure between the two auxiliary gate electrodes and a portion of the drain region;
Including
The first and second charge trapping structures are formed between the semiconductor substrate and the main gate electrode, and are a first dielectric film as a tunneling film stacked in the thickness direction of the semiconductor substrate , comprises a third dielectric film as a second dielectric layer, and the shielding film as conductive load trap film,
The first and second recesses are selectively formed in the second dielectric film of the first and second charge trapping structures, respectively ;
Wherein said edge of the second dielectric film of the first and second charge trapping structure, characterized that you have aligned with the edge of the source region and the drain region and the first and second recesses are present A non-volatile memory element.   The first and second auxiliary gate electrodes are formed on the first charge trap structure and the second charge trap structure on the drain side surface and the source side surface of the first gate electrode, respectively. The nonvolatile memory device of claim 10, further comprising a sidewall spacer. The first and second charge trapping structures include the first dielectric film including a material selected from the group consisting of silicon oxide and silicon oxynitride;
A second dielectric film formed on the first dielectric film and including a material selected from the group consisting of silicon nitride, silicon oxynitride, and a high dielectric constant material; and the second dielectric film. The non-volatile memory device according to claim 10, further comprising: the third dielectric film formed of a silicon oxide containing silicon oxide. The first and second charge trapping structures include the first dielectric film including a material selected from the group consisting of silicon oxide and silicon oxynitride;
A quantum dot array formed on the first dielectric film and including a quantum dot of a type selected from the group consisting of polysilicon quantum dots and silicon nitride quantum dots; and silicon formed on the quantum dot array The nonvolatile memory element according to claim 10, further comprising: the second dielectric film containing an oxide.   The nonvolatile memory device of claim 10, further comprising a dielectric material in the first and second recesses.

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