CN100555662C - Non-volatile memory cell structure and manufacture method thereof with electric charge capture layer - Google Patents
Non-volatile memory cell structure and manufacture method thereof with electric charge capture layer Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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Abstract
The invention discloses a kind of in non-volatile memory device and manufacture method thereof.In described device, at least one edge of electric charge capture layer is recessed into.Like this, the threshold voltage of device during the programming operation and during erase operation the threshold voltage of device remain on suitable and stable level.As a result, improved device property.
Description
Technical field
The present invention relates to a kind of non-volatile memory cell structure and manufacture method thereof, particularly a kind of non-volatile memory cell structure and manufacture method thereof with electric charge capture layer.
Background technology
Non-volatile memory device particularly relies in the portable electronic system of battery power source very universal in current electronic system.Even this non-volatile memory device also can keep information when the system power source stops, therefore do not need the power consumption complement operation to keep the data of storing.
With reference to Fig. 1, in conventional SONOS type non-volatile memory cell structure, charge trapping structure 110 is formed on drain region 104 and source region 106 with on the preset distance silicon base 102 separated from one another.Charge trapping structure 110 has stacked structure, in this structure, and the tunnel layer 112 that forms by first silicon oxide layer, the electric charge capture layer 114 that forms by silicon nitride layer and stack gradually on the surface of silicon base 102 by the barrier layer 116 that second silicon oxide layer forms.The control grid 120 that is formed by polysilicon layer is formed on the charge trapping structure 110.
In order to programme or write operation, positive bias voltage is applied to grid 120 and source region 106, and drain region 104 ground connection.The voltage that is applied to grid 120 and source region 106 cause vertical electric field and along channel region from the drain region 104 to the source region horizontal component of electric field of 106 directions.Because described electric field, electronics 104 is pushed open and 106 is quickened towards the source region from the drain region.When channel region moves, electronics increases energy, and some electronics enter hot state, so they can obtain enough energy and cross the potential barrier of tunnel layer 112 and enter electric charge capture layer 114.This phenomenon is in the close source region the most normal generation in 106 places, because obtain the energy of maximum at this regional electronic energy.Enter electric charge capture layer 114 in case be in the electronics of hot state, the electronics that is in hot state is captured and is stored in this place in electric charge capture layer 114, increased the threshold voltage of memory cell like this.
In order to carry out erase operation, need with the different voltage of voltage that is used in programming or reading cells.For example, positive bias voltage is applied to source region 106, and negative bias voltage is applied to grid 120.Float in drain region 104.In this case, be stored in electronics in the electric charge capture layer 114 and 106 move, and the hole migration in the source region 106 is to electric charge capture layer 114 towards the source region.The electronics that is stored in the electric charge capture layer 114 is eliminated or is offset by the hole, has wiped the data on the memory cell like this.
In conventional SONOS memory device, after finishing erase operation, the certain amount of electrons that before had been trapped in the overlapping region in grid and source region or grid and drain region still can be retained in the electric charge capture layer.
Potential barrier between channel region and the source/drain region can increase owing to the electric charge that keeps after the erase operation.Along with the increase of potential barrier, voltage gradient reduces under the thresholding of non-volatile memory device.This phenomenon is at IEEEElectron Device Letters, Vol.22, and No.11, people's such as Eli Lusky article " adopts NROM on the November 2001
TMCharacteristic (the Characterization of Channel Hot Electron Injection by the Subthreshold SlopeofNROM that the channel hot electron of gradient injects under the thresholding of device
TMDevice) " describe in.
When this phenomenon takes place, because the reduction of the threshold voltage difference of the programming state of device and erase status causes device property to reduce.
Summary of the invention
The present invention relates to a kind of non-volatile memory device and form the method for this device, wherein at least one limit of electric charge capture layer is recessed.Like this, in programming operation the threshold voltage of this device and in erase operation the threshold voltage of this device remain on proper level.As a result, improved device property.
According to an aspect, the present invention proposes a kind of non-volatile memory device.Described device comprises: the semiconductor-based end; In source region on disconnected position and the drain region that this base upper portion is divided; Suprabasil charge trapping structure between source region and drain region; With the grid on charge trapping structure, wherein be recessed in the charge trapping structure that is between the part one of at least of grid and source region and drain region.
In one embodiment, overlap a part of source region and a part of drain region of grid.
In another embodiment, each all comprises heavily doped region and light doping section source region and drain region, and extend towards each other on the top of the light doping section in source region and drain region from corresponding heavily doped region along substrate, and the part of the light doping section in grid overlapping source region and drain region.In another embodiment, lightly doped source region and drain region are self aligned with the source side and the drain side of grid in first formation.In another embodiment, extend below by diffusion process in the source side and the drain side of grid respectively in lightly doped source region and drain region.In another embodiment, sidewall spacer body (sidewall spacer) is arranged on the source side and the drain side of grid, and wherein heavily doped source region and drain region are self aligned with the outside of sidewall spacer body when first formation.
In another embodiment, source region and drain region are self aligned with the source side and the drain electrode example of grid respectively when first formation.In another embodiment, extend below by diffusion process in the source side and the drain side of grid respectively in source region and drain region.In another embodiment, at least one inward flange of source region and drain region is aimed at the outward flange of charge trapping structure basically.
In another embodiment, be recessed in the source side of charge trapping structure.In another embodiment, be recessed in the source region side and the drain region side of charge trapping structure.
In another embodiment, during dielectric substance is arranged on and is recessed into.
In another embodiment, charge trapping structure comprise first dielectric, at second dielectric on first dielectric and the 3rd dielectric on second dielectric.In another embodiment, first dielectric comprises the material that is selected from silica and silicon oxynitride (silicon oxynitride); Wherein second dielectric comprises the material that is selected from silicon nitride, silicon oxynitride and high-k dielectric, and wherein the 3rd dielectric comprises silica.In another embodiment, recessed being formed in second dielectric.
In another embodiment, charge trapping structure comprises quantum-dot structure, second dielectric that described quantum-dot structure comprises first dielectric, the quantum dot array on first dielectric and lists at quantum dot array.In another embodiment, first dielectric comprises the material that is selected from silica and silicon oxynitride; Wherein quantum dot array comprises the quantum dot of the type that is selected from polysilicon quantum dot and silicon nitride quantum dot, and wherein second dielectric comprises silica.
In another embodiment, charge trapping structure extends from the source region to the mesozone between source region and drain region, also be included in the gate-dielectric that the charge trapping structure from the mesozone in the substrate extends to the drain region, wherein grid is positioned on the charge trapping structure and on gate-dielectric.
In another embodiment, charge trapping structure comprise first charge trapping structure and wherein grid comprise first auxiliary grid (auxiliary gate electrode), and also comprise: the suprabasil main grid utmost point dielectric between source region and drain region; The main grid utmost point on main grid utmost point dielectric; Suprabasil first charge trapping structure between the source region and the main grid utmost point; First auxiliary grid on first charge trapping structure is wherein in first first charge trapping structure that is recessed between first auxiliary grid and a part of source region; Second charge trapping structure is in the substrate between the drain region and the main grid utmost point; And second auxiliary grid is on second charge trapping structure, wherein in second second charge trapping structure that is recessed between second auxiliary grid and a part of drain region.
On the other hand, the present invention relates to a kind of non-volatile memory device, described device comprises: the semiconductor-based end; The source region of the disconnected position in the top at the semiconductor-based end and drain region; Suprabasil main grid utmost point dielectric between source region and drain region; The main grid utmost point on main grid utmost point dielectric; Suprabasil first charge trapping structure between the source region and the main grid utmost point; With first auxiliary grid on first charge trapping structure, wherein in first first charge trapping structure that is recessed between first auxiliary grid and a part of source region; Second charge trapping structure is in the substrate between the drain region and the main grid utmost point; And second auxiliary grid is positioned on second charge trapping structure, wherein in second second charge trapping structure that is recessed between second auxiliary grid and a part of drain region.
In one embodiment, first and second auxiliary grids comprise and are formed on drain side and first charge trapping structure of source side and the side direction spacer body of the conduction on second charge trapping structure that lays respectively at the main grid utmost point.In another embodiment, source region and drain region are when first formation and the outward flange autoregistration of first and second auxiliary grids.In another embodiment, first and second charge trapping structures each all comprise first dielectric, at second dielectric on first dielectric and the 3rd dielectric on second dielectric.In another embodiment, first dielectric comprises the material that is selected from silica and silicon oxynitride; Wherein second dielectric comprises the material that is selected from silicon nitride, silicon oxynitride and high-k dielectric, and wherein the 3rd dielectric comprises silica.In another embodiment, first and second recessed being respectively formed in second dielectric of first and second charge trapping structures.
In another embodiment, each all comprises quantum-dot structure first and second charge trapping structures, and described quantum-dot structure comprises first dielectric, the quantum dot array on first dielectric and second dielectric that lists at quantum dot array.In another embodiment, first dielectric comprises the material that is selected from silica and silicon oxynitride; Wherein quantum dot array comprises the quantum dot of the type that is selected from polysilicon quantum dot and silicon nitride quantum dot, and wherein second dielectric comprises silica.
In another embodiment, source region and drain region each all comprise heavily doped region and light doping section; Extend towards each other on the top of the light doping section in source region and drain region from corresponding heavily doped region along substrate, and the part of the light doping section in first and second auxiliary grids each all overlap respectively source region and drain region.In another embodiment, lightly doped source region and drain region are self aligned with the source side and the drain side of the main grid utmost point when first formation.In another embodiment, extend below by diffusion process in the source side and the drain side of the main grid utmost point respectively in lightly doped source region and drain region.
In another embodiment, dielectric substance is arranged in first and second recessed.
On the other hand, the present invention relates to a kind of method that forms non-volatile memory device, described method comprises: on the semiconductor-based end charge trapping structure is set; Grid is set on charge trapping structure; Optionally etching charge is captured the outward flange of at least one exposure of structure to form being recessed between the semiconductor-based end and grid; And use grid in the semiconductor-based end, to form source region and drain region as the ion injecting mask.
In one embodiment, charge trapping structure and grid is set comprises is set: on the semiconductor-based end, electric charge capture layer is set; Grid layer is set on electric charge capture layer; And composition grid layer and electric charge capture layer are to form grid structure and charge trapping structure.
In another embodiment, charge trapping structure and grid is set comprises is set: on the semiconductor-based end, electric charge capture layer is set; This electric charge capture layer of composition is to be formed on the charge trapping structure that extends in the substrate between source region and the mesozone, and the mesozone is between source region and drain region; The gate-dielectric that extend in electric charge capture course drain region from the mesozone is set in substrate; On the electric charge capture layer He on the gate-dielectric grid layer is being set; And composition grid layer and gate-dielectric are to form grid and charge trapping structure.
In another embodiment, after capturing structure, the selection etching charge forms source region and drain region.In another embodiment, before capturing structure, the selection etching charge forms source region and drain region.
In another embodiment, this method comprises that also diffusion source region and drain region make grid structure overlapping source region and drain region.In another embodiment, the inward flange that spreads up to source region and drain region at least one is aimed at the outward flange of charge trapping structure basically.
In another embodiment, the source region side of selecting to be etched in charge trapping structure forms recessed.
In another embodiment, this method also comprises, before selecting etching on the drain side part of the grid that extends to the drain region across the drain side sidewall of grid the painting photoresist pattern, with the etching of the drain region side that prevents charge trapping structure.
In another embodiment, source region side and the drain region side of selecting to be etched in charge trapping structure all forms recessed.
In another embodiment, forming source region and drain region comprises: use grid to form light dope source region and lightly doped drain as the first ion injecting mask in the semiconductor-based end; On the sidewall of grid, form the side direction spacer body; In the semiconductor-based end, form heavy doping source region and heavy doping drain region with employing side direction spacer body as the second ion injecting mask.In another embodiment, this method comprises that also diffusion light dope source region and lightly doped drain make grid structure overlapping light dope source region and lightly doped drain.
In another embodiment, charge trapping structure being set comprises: first dielectric layer is set; Second dielectric layer is set on first dielectric layer; With the 3rd dielectric layer is set on second dielectric layer.In another embodiment, first dielectric layer comprises the material that is selected from silica and silicon oxynitride; Wherein second dielectric layer comprises the material that is selected from silicon nitride, silicon oxynitride and high-k dielectric, and wherein the 3rd dielectric layer comprises silica.In another embodiment, selective etch causes being formed on being recessed in second dielectric layer.
In another embodiment, charge trapping structure being set comprises: first dielectric layer is set; On first dielectric layer, quantum dot array is set; And list at quantum dot array second dielectric layer is set.In another embodiment, first dielectric layer comprises the material that is selected from silica and silicon oxynitride; Wherein quantum dot array comprises the quantum dot of the type that is selected from polysilicon quantum dot and silicon nitride quantum dot, and wherein second dielectric layer comprises silica.
In another embodiment, this method is provided with dielectric substance in also being included in and being recessed into.
On the other hand, the present invention relates to a kind of method that forms non-volatile memory device, described comprising: main grid utmost point dielectric is set on the semiconductor-based end; On main grid utmost point dielectric, the main grid utmost point is set; Main grid extremely go up and the semiconductor-based end on charge trapping structure is set; At first and second sidewalls that are positioned at the main grid utmost point on the main grid utmost point dielectric first and second auxiliary grids are set; The outward flange of selecting etching charge to capture at least one exposure of structure is recessed into to form first between the semiconductor-based end and first auxiliary grid; And use the main grid utmost point and first and second auxiliary grid source region and drain region to be set in the semiconductor-based end as the ion injecting mask.
In one embodiment, it is recessed to select etching also to be formed on second between the semiconductor-based end and second auxiliary grid.
In another embodiment, first and second auxiliary grids are set to be comprised: form the first and second side direction spacer bodies of electric conducting material on the charge trapping structure on the sidewall that is positioned at the main grid utmost point, the first and second side direction spacer bodies comprise first and second auxiliary grids respectively; And use the main grid utmost point and first and second side direction spacer body in the semiconductor-based end, to form source region and drain region as the ion injecting mask.
In another embodiment, charge trapping structure being set comprises: first dielectric layer is set; Second dielectric layer is set on first dielectric layer; With the 3rd dielectric layer is set on second dielectric layer.In another embodiment, first dielectric layer comprises the material that is selected from silica and silicon oxynitride; Wherein second dielectric layer comprises the material that is selected from silicon nitride, silicon oxynitride and high-k dielectric, and wherein the 3rd dielectric layer comprises silica.In another embodiment, select etching to cause recessed being formed in second dielectric.
In another embodiment, charge trapping structure being set comprises: first dielectric layer is set; On first dielectric layer, quantum dot array is set; And list at quantum dot array and to form second dielectric layer.In another embodiment, first dielectric layer comprises the material that is selected from silica and silicon oxynitride; Wherein quantum dot array comprises the quantum dot of the type that is selected from polysilicon quantum dot and silicon nitride quantum dot, and wherein second dielectric layer comprises silica.
In another embodiment, this method is provided with dielectric substance in also being included in and being recessed into.
In another embodiment, the source region is set and the drain region comprises: before first and second auxiliary grids are set, use the main grid utmost point in the semiconductor-based end, to form light dope source region and lightly doped drain as the first ion injecting mask; After first and second auxiliary grids are set, use the main grid utmost point and first and second auxiliary grid in the semiconductor-based end, to form heavy doping source region and heavy doping drain region as the second ion injecting mask.
In another embodiment, this method also comprises diffusion light dope source region and drain region and heavy doping source region and drain region, to extend described district toward each other at interior side direction.
Description of drawings
In conjunction with the drawings to the more specifically description of the preferred embodiments of the present invention, above and other purpose of the present invention, feature and advantage will be more obvious, and in the accompanying drawings, identical Reference numeral is represented identical part in the whole text.Accompanying drawing is not necessarily pro rata, and emphasis is for principle of the present invention is shown.
Fig. 1 is the sectional view with conventional non-volatile memory device of SONOS type charge trapping structure;
Fig. 2 is the sectional view according to the non-volatile memory device of the SONOS type charge trapping structure with recessed electric charge capture layer of the present invention;
Fig. 3 A is the sectional view that the non-volatile memory device with SONOS type charge trapping structure of recessed electric charge capture layer according to the present invention carries out programming operation, and Fig. 3 B is the schematic diagram of electric field orientation during the device of Fig. 3 A carries out programming operation;
Fig. 4 A is the sectional view that the non-volatile memory device with SONOS type charge trapping structure of recessed electric charge capture layer according to the present invention carries out erase operation, and Fig. 4 B is the schematic diagram of electric field orientation during the device of Fig. 4 A carries out erase operation;
Fig. 5 A-5F is the sectional view of first technology of the non-volatile memory device of the SONOS type charge trapping structure that all has recessed electric charge capture layer in the source side and the drain side of grid formed according to the present invention;
Fig. 6 A-6B be formed according to the present invention at grid source side and the sectional view of second technology of the non-volatile memory device of one of drain side SONOS type charge trapping structure with recessed electric charge capture layer;
Fig. 7 A-7G is the sectional view of the 3rd technology of the non-volatile memory device of the quantum dot array type charge trapping structure that all has recessed electric charge capture layer in the source side and the drain side of grid formed according to the present invention;
Fig. 8 A-8B be formed according to the present invention at grid source side and the sectional view of the 4th technology of the non-volatile memory device of one of drain side quantum dot array type charge trapping structure with recessed electric charge capture layer;
Fig. 9 A-9D be formed according to the present invention at grid source side and the sectional view of the 5th technology of the non-volatile memory device of one of drain side local SONOS type charge trapping structure with recessed electric charge capture layer;
Figure 10 A-10D be formed according to the present invention at grid source side and the sectional view of the 6th technology of the non-volatile memory device of one of drain side quantum dot array type local charge trapping structure with recessed electric charge capture layer;
Figure 11 A-11F is the sectional view of the 7th technology of the dizzy type non-volatile memory device of the SONOS type charge trapping structure that all has recessed electric charge capture layer in the source side and the drain side of grid formed according to the present invention;
Figure 12 A-12F is the sectional view of the 8th technology of the dizzy type non-volatile memory device of the quantum dot array type charge trapping structure that all has recessed electric charge capture layer in the source side and the drain side of grid formed according to the present invention.
Embodiment
The present invention is more specifically described below with reference to accompanying drawings, the preferred embodiments of the present invention shown in the drawings.Yet the present invention can be with multi-form enforcement, and should not be construed as the embodiment that is confined to propose herein.In the accompanying drawings, amplified the thickness of layer in order to know.In addition, when layer be described to be formed on another layer is gone up or substrate on the time, mean that this layer can be formed in another layer or the substrate, perhaps can have the 3rd layer or extra play to be inserted between this layer and another layer or the substrate.Identical in the whole text Reference numeral is represented components identical.
Fig. 2 is the sectional view according to the non-volatile memory device of the SONOS type charge trapping structure with recessed electric charge capture layer of the present invention.This device comprises substrate 310, for example semiconductor-based end.Source region and drain region are arranged in the substrate 310, the opposite side of the channel region 381 of device.The source region comprises heavy doping source region 391 and light dope source region 371.The drain region comprises heavy doping drain region 392 and lightly doped drain 372.Charge trapping structure 320 is on the source region and the substrate between the drain region 310 of device.Charge trapping structure 320 comprises the tunnel layer 325 that formed by dielectric layer, on electric charge capture layer on the tunnel layer 325 330 and the barrier layer 335 that on electric charge capture layer 330, forms by dielectric layer.In an one exemplary embodiment, electric charge capture layer 330 comprises oxide-nitride thing-oxide (ONO) layer.In another one exemplary embodiment, electric charge capture layer 330 comprises quantum-dot structure.Grid 350 is positioned on the charge trapping structure 320, and gate insulator 360 is positioned on this composite structure.The side direction spacer body 380 that is formed by dielectric substance is arranged on the source electrode and drain electrode sidewall of grid 350.
In the present invention, an example or the both sides of the electric charge capture layer 330 of charge trapping structure 320 under grid 350 are recessed.In the embodiment of Fig. 2, electric charge capture layer 330 is all recessed below the source side of grid 350 and drain side.Side at grid 350 has in the recessed example, this recessed source side that is arranged on grid 350.Preferably, this recessed electric charge capture layer 330 source/drain region 371,372 that do not overlap that enough makes deeply.In the example of Fig. 2, this is recessed to be formed on source side and drain side makes the source side edge of electric charge capture layer 330 and drain side edge aim at the inside edge of light dope source region 371 and lightly doped drain 372 up to a degree of depth.In an example, the grid length of grid 350 is 0.2 μ m, and grid 350 and source region 371 have the overlapping of 10nm approximately.In this example, the suitable recessed degree of depth is about 20-40nm.The advantage of this structure is discussed below.
Fig. 3 A is the sectional view that the non-volatile memory device with SONOS type charge trapping structure of recessed electric charge capture layer according to the present invention carries out programming operation, and Fig. 3 B is the schematic diagram of electric field orientation during the device of Fig. 3 A carries out programming operation.
As shown in Figure 3A, during programming operation, for example the positive bias voltage in about 3.0 to 5.0 volt range is applied to grid g, and for example the positive bias voltage in about 3.5-5.5 volt range is applied to source electrode s, and earthed voltage is applied to drain electrode d.During programming operation, the electronics e that is in hot state is captured in the electric charge capture layer 330, and is stored in this place.Like this, the threshold voltage of memory cell 100 increases.With reference to Fig. 3 B, during programming operation, grid electric field Eg is along downward vertical direction orientation, and source/electric leakage Esd is orientated to leaking direction along the source.In this operating period, the electronics that is in hot state tends to move to the crossover region A of device, and grid 350 overlaps in the edge and the light dope source region 371 in electric charge capture layer 330 the most close source regions 371,391 there.Be arranged on the recessed thermionic quantity that will minimize among the regional A that is trapped in electric charge capture layer in the electric charge capture layer 330.
Fig. 4 A is the sectional view that the non-volatile memory device with SONOS type charge trapping structure of recessed electric charge capture layer according to the present invention carries out erase operation, and Fig. 4 B is the schematic diagram of electric field orientation during the device of Fig. 4 A carries out erase operation.
Shown in Fig. 4 A, during erase operation, for example the negative bias voltage in about-4.5 to-6.5 volt range is applied to grid g, and for example the positive bias voltage in about 4.5 to 6.5 volt range is applied to source electrode s, and earthed voltage is applied to drain electrode d.During erase operation, hole h is moved to electric charge capture layer 330.Therefore, the electronics that is stored in the electric charge capture layer is eliminated or is offset by the hole.Like this, memory cell data is wiped free of.With reference to Fig. 4 B, during erase operation, grid electric field Eg is along downward vertical direction orientation, and source/electric leakage Esd is orientated to leaking direction along the source.Because recessed existence in regional A, the electronics that is stored in the electric charge capture layer 330 is cancelled in erase process, and because recessed former thereby be not retained in the source side of electric charge capture layer 330.
Fig. 5 A-5F is the sectional view of first technology of the non-volatile memory device of the SONOS type charge trapping structure that all has recessed electric charge capture layer in the source side and the drain side of grid formed according to the present invention.With reference to Fig. 5 A, be used for the first dielectric 325a of tunnel layer, the 3rd dielectric 335a that is used for the second dielectric 330a of electric charge capture layer and is used for the barrier layer and be successively set on substrate 310.In one embodiment, the first dielectric layer 325a comprises the degree of depth that formed by for example rapid thermal treatment (RTP), chemical vapor deposition (CVD), stove system technology (furnace process) or other suitable deposits or growth technique silica or the silicon oxy-nitride material about 30 to 50 dusts.The second dielectric layer 330a comprises silicon nitride, silicon oxynitride or high-k dielectric layer or its combination of the degree of depth of use CVD, low pressure chemical vapor deposition (LPCVD) or other suitable deposits or growth technique formation about 30 to 100 dusts.The 3rd dielectric layer 335a comprises the degree of depth that formed by for example CVD, LPCVD or other suitable deposits or the growth technique silica material about 50 to 150 dusts.Then deposit is suitable for forming the conductive material layer 350a of grid on this composite structure.In one embodiment, conductive material layer 350a comprises polycrystalline silicon material, metal material or its combination.Can optionally the top of conductive material layer 350a be handled to form the policide layer that positivity is mixed.Conductive material layer 350a for example adopts CVD or LPCVD to form about 80 to 2000 angstroms depths.
With reference to Fig. 5 B, then use this composite structure of standard photoetching composition technology composition to form grid 350b, barrier layer 335b, electric charge capture layer 330b and tunnel layer 325b.
With reference to Fig. 5 C, on this composite structure, select etching, this selection etching causes the selection etching of electric charge capture layer 330b outside.In one embodiment, comprise at electric charge capture layer 330C under the situation of silicon nitride or silicon oxynitride, comprise phosphoric acid (phosphoric oxide, H
3PO
4) wet etchant be applicable to and increase etched selectivity.After the etching of electric charge capture layer 330c, form recessedly at the edge of electric charge capture layer 330c, and tunnel layer 325b and barrier layer 335b keep the approximately width identical with grid 350b.
With reference to Fig. 5 D, on this composite structure, carry out ion and inject, to form the lightly-doped source/drain region 371,372 of device source/drain regions.Lightly-doped source/the drain region 371,372 of gained and grid 350b autoregistration.Self aligned lightly-doped source/drain region can form after the selection etching of electric charge capture layer 330c, perhaps can selectively form before the selection etching of electric charge capture layer 330c.Then gate insulator 360 is formed on this composite structure.In one embodiment, gate insulator 360 comprises the silica material of about 50 to 100 angstroms depths that formed by for example CVD, LPCVD or other suitable deposits or growth technique.The gate insulator 360 that the recessed district of electric charge capture layer 330c is applied in is partially or even wholly filled.
With reference to Fig. 5 E, side direction spacer body 380 is formed on the source electrode and drain electrode sidewall of grid 350b.In one embodiment, silicon nitride layer is arranged on this composite structure by for example CVD or other suitable deposits or growth technique, and the degree of depth is about 500 to 700 dusts.Eat-back (etch-back) technology to form side direction spacer body 380 according to routine techniques then.
With reference to Fig. 5 F, on this composite structure, carry out ion and inject, with the heavy-doped source/drain region 391,392 in source/drain region of forming device.Gained heavy-doped source/drain region 391,392 and 380 autoregistrations of side direction spacer body.For example using the RTP that under about 1000 ℃ or higher temperature, continues several seconds to carry out diffusion technology on this composite structure,, make grid 350b overlapping lightly-doped source/drain region 371,372 so that lightly-doped source/drain region 371,372 is further inwardly diffused into channel region.
Be used to make the result of first technology of non-volatile memory device, formed the device of above-mentioned Fig. 2.The obtained device 100 of Fig. 2 has recessed electric charge capture layer.As mentioned above, the quantity of the electronics that also therefore can behind erase operation, keep in the recessed electric charge capture layer that has minimized on the crossover region that is captured on grid 350b and light dope source region 371.Like this, therefore stablize the transistorized threshold voltage that is used to programme with erase operation, caused more reliable operation.For example, recessed can prevent to be stored in misreading of data message in the electric charge capture layer, even under frequent SONOS memory device access and a large amount of and the programming and erase operation that repeat.
Fig. 6 A-6B be formed according to the present invention at grid source side and the sectional view of second technology of the non-volatile memory device of the source side of one of drain side, for example grid SONOS type charge trapping structure with recessed electric charge capture layer.Second technology is identical with first technology basically; except in the selection etching step of electric charge capture layer 530c; the drain side that photoresist pattern 510 is applied to structure with the drain side of protection electric charge capture layer 530c not by the selectivity etching; thereby the source side of electric charge capture layer 530c is formed in the above described manner by the selectivity etching and is recessed into simultaneously, as shown in Figure 6A.After selecting etching charge capture layer 530c, carry out in the step shown in above-mentioned Fig. 5 D-5F, to form the structure that only has the recessed electric charge capture layer 530c of formation shown in Fig. 6 B in the source side of layer 530c.The embodiment of Fig. 6 is specially adapted to exist in transistorized source electrode and drain electrode the doping content situation different with profile of asymmetric for example source electrode and drain electrode.When allowing all to form when recessed, preferably according to the manufacture method of the embodiment of Fig. 5 A-5F, because this technology does not require the extra masks shown in Fig. 6 A in the source electrode of electric charge capture layer and drain electrode.
Fig. 7 A-7G is the sectional view of the 3rd technology of the non-volatile memory device of the quantum dot array type charge trapping structure that all has recessed electric charge capture layer in the source side and the drain side of grid formed according to the present invention.With reference to Fig. 7 A, be used for the first dielectric layer 625a of tunnel layer, the second dielectric layer 635a that is used for the quantum dot array 630a of electric charge capture layer and is used for the barrier layer and be successively set on substrate 310.In one embodiment, the first dielectric layer 625a comprises that the degree of depth that for example forms by rapid thermal treatment (RTP), chemical vapor deposition (CVD), stove system technology or other suitable deposits or growth technique is about the silica or the silicon oxy-nitride material of 30 to 50 dusts.In one embodiment, quantum dot array 630a comprises LPCVD or other suitable dichlorosilane that depositing technics applied (dichlorsilane DCS) and the hydrogen (H of employing under about 500 ℃ to 700 ℃ temperature ranges
2) mixture and be applied to the polysilicon quantum dot array of the upper surface of first dielectric layer 625.In another one exemplary embodiment, quantum dot array 630a comprises the silicon nitride quantum dot array that the nitrogenize by above-mentioned polysilicon quantum dot array forms.In selectable technology, quantum dot is oxidized, is used to reduce its diameter separately.The second dielectric layer 635a comprises that the degree of depth that is formed by for example CVD, LPCVD or other suitable deposits or growth technique is about the silica material of 50 to 150 dusts.The conductive material layer 350a that then is fit to the formation grid is deposited on this composite structure.In one embodiment, conductive material layer 350a comprises polycrystalline silicon material, metal material or its combination.Can optionally the top of conductive material layer 350a be handled to form the policide layer that positivity is mixed.Conductive material layer 350a for example adopts CVD or LPCVD to be applied for about 80 to 2000 angstroms depths.
With reference to Fig. 7 B, adopt standard photoetching composition technology successively this composite structure of composition to form grid 350b, barrier layer 635b, quantum dot array 630b and tunnel layer 625b.
With reference to Fig. 7 C, on this composite structure, select etch process, it causes comprising the selection etching of outer part of charge trapping structure 620 of the electric charge capture layer 630b of quantum dot array type.In one embodiment, comprise under the situation of silica or silicon oxynitride that suitable employing comprises that the wet etchant of HF is to improve etching selectivity at tunnel layer 625b and barrier layer 635b.After the etching of charge trapping structure 620, form recessed at the edge of the charge trapping structure 620 that comprises electric charge capture layer 630c, tunnel layer 625b and barrier layer 635b.
With reference to Fig. 7 D, on this composite structure, carry out ion and inject, with the lightly-doped source/drain region 371,372 in source/drain region of forming device.Lightly-doped source/the drain region 371,372 of gained and grid 350b autoregistration.Self aligned lightly-doped source/drain region can form after the selection etching of electric charge capture layer 630c, perhaps as selecting, can form before the selection etching of electric charge capture layer 630c.Then on this composite structure, form gate insulator 360.In one embodiment, gate insulator 360 comprises that the degree of depth by for example CVD, LPCVD or other suitable deposits or growth technique formation is about the silica material of 50 to 100 dusts.The gate insulator 360 that the recessed district of charge trapping structure 620 is applied in is partially or even wholly filled.
With reference to Fig. 7 E, side direction spacer body 380 is formed on source electrode and the drain side of grid 350b.In one embodiment, silicon nitride layer is arranged on this composite structure by for example CVD or other suitable deposits or growth technique, and the degree of depth is about 500 to 700 dusts.Carry out etch-back technics to form side direction spacer body 380 according to routine techniques then.
With reference to Fig. 7 F, on this composite structure, carry out ion implantation technology, to form the heavy-doped source/drain region 391,392 of device source/drain regions.Heavy-doped source/the drain region 391,392 of gained and 380 autoregistrations of side direction spacer body.
With reference to Fig. 7 G, on this composite structure, carry out diffusion technology, the RTP that for example adopts about 1000 ℃ or higher temperature to continue several seconds down, with further inwardly the lightly doped source/drain region 371,372 of diffusion make grid 350b overlapping lightly-doped source/drain region 371,372 to channel region.In one embodiment, lightly-doped source/drain region 371,372 is extended and is made their the recessed edge rough alignment of inward flange and charge trapping structure 620.This aligning has guaranteed that the electronics of capturing offset by hole migration in erase operation.The part of littler recessed permission charge trapping structure 620 and lightly-doped source/drain region 371,372 overlap, and it may reduce the possibility that electronics is offset fully in erase operation.Darker recessed meeting causes the elimination of the valuable part of the required charge trapping structure 620 that the hole offsets.
The 3rd technology that is used to make non-volatile memory device causes obtained device 600 to have provides the recessed electric charge capture layer of above-mentioned advantage.
Fig. 8 A-8B be formed according to the present invention at grid source side and the sectional view of the 4th technology of the non-volatile memory device of the source side of one of drain side, for example grid quantum dot array type charge trapping structure with recessed electric charge capture layer.The 4th technology is identical with the 3rd technology basically; except in the selection etching step of charge trapping structure 720; photoresist pattern 710 is applied to the drain side of structure; the not selected etching of drain side with protection charge trapping structure 720; the source side of charge trapping structure 720 is etched with as above to form by selectivity and is recessed into simultaneously, shown in Fig. 8 A.After the selective etch of charge trapping structure 720, carry out the step shown in Fig. 7 D-7G to cause the structure shown in Fig. 8 B, this structure has the recessed charge trapping structure 720 that only is formed on structure 720 source side.The embodiment of Fig. 8 A is specially adapted to exist in transistorized source electrode and drain electrode the doping content situation different with profile of asymmetric for example source electrode and drain electrode.When allowing all to form when recessed, preferably according to the manufacture method of the embodiment of Fig. 7 A-7G, because this technology does not require the extra masks shown in Fig. 8 A in the source electrode of electric charge capture layer and drain electrode.
Fig. 9 A-9D be formed according to the present invention at grid source side and the sectional view of the 5th technology of the non-volatile memory device of one of drain side local SONOS type charge trapping structure with recessed electric charge capture layer.With reference to Fig. 9 A, be used for the first dielectric 825a of tunnel layer, the 3rd dielectric layer 835a that is used for the second dielectric 830a of electric charge capture layer and is used for the barrier layer and be successively set on substrate 310 in for example mode corresponding to the foregoing description.
With reference to Fig. 9 B, use this composite structure of standard photoetching composition technology composition to form barrier layer 835b, electric charge capture layer 830b and tunnel layer 825b.
With reference to Fig. 9 C, the 4th dielectric layer that is used to form coupling layer 840 is arranged on this composite structure, for example comprises silica material, forms about 50 to 100 dusts by for example CVD, LPCVD or other suitable deposits or growth technique.The conductive material layer that then is suitable for forming grid is deposited on this composite structure, and conductive material layer and the 4th dielectric layer pass through conventional photoetching composition process quilt composition, thereby are being positioned at formation grid 850 on the coupling layer 840 that reaches in the substrate 310 on the charge trapping structure 820.In one embodiment, conductive material layer 850 comprises polycrystalline silicon material, metal material or its combination.Can optionally the top of conductive material layer 850 be handled to form the policide layer that positivity is mixed.For example adopt CVD or LPCVD to apply the conductive material layer that the degree of depth is about 80 to 2000 dusts.
With reference to Fig. 9 D, on this composite structure, select etch process, this technology causes the selection etching of electric charge capture layer 830b exposed exterior.In one embodiment, comprise at electric charge capture layer 830b under the situation of silicon nitride or silicon oxynitride, comprise phosphoric acid (H
3PO
4) wet etchant be applicable to the raising etching selectivity.After the etching of electric charge capture layer 830c, form in the exposed edge of electric charge capture layer 830c recessed, as shown.
On this composite structure, carry out ion and inject, with the lightly-doped source/drain region 871,872 in source/drain region of forming device.Lightly-doped source/the drain region 871,872 of gained and grid 850 autoregistrations.Self aligned lightly-doped source/drain region can form after the selection etching of electric charge capture layer 830c, perhaps as selecting, can form before the selection etching of electric charge capture layer 830c.Then gate insulator 360 is formed on this composite structure.In one embodiment, gate insulator 360 comprises that the degree of depth by for example CVD, LPCVD or other suitable deposits or growth technique formation is about the silica material of 50 to 100 dusts.The gate insulator 360 that the recessed district of electric charge capture layer 830c is applied in is partially or even wholly filled.
Side direction spacer body 380 is formed on the source electrode and the drain side of grid 850.In one embodiment, silicon nitride layer is arranged on this composite structure by for example CVD or other suitable deposits or growth technique, and the degree of depth is about 500 to 700 dusts.Eat-back to form side direction spacer body 380 according to routine techniques then.
On this composite structure, carry out ion then and inject, to form the heavy-doped source/drain region 891,892 of device source/drain regions.Heavy-doped source/the drain region 891,892 of gained and 380 autoregistrations of side direction spacer body.The RTP that adopts for example about 1000 ℃ or higher temperature to continue several seconds down carries out diffusion technology on this composite structure, with further inwardly diffusion lightly-doped source/drain region 871,872 make grid 850 overlapping lightly-doped source/drain regions 871,872 to channel region.
The 5th technology that is used to make non-volatile memory device causes obtained device 800 to have provides the recessed electric charge capture layer of above-mentioned advantage.
Figure 10 A-10D is source side and one of the drain side at grid formed according to the present invention, for example has the sectional view of the 6th technology of non-volatile memory device of the quantum dot array type local charge trapping structure of recessed electric charge capture layer in the source side of grid.With reference to Figure 10 A, be used for the first dielectric 925a of tunnel layer, the second dielectric 935a that is used for the quantum dot array 930a of electric charge capture layer and is used for the barrier layer and be successively set on substrate 310 in mode corresponding to the foregoing description.
With reference to Figure 10 B, use this composite structure of standard photoetching composition technology composition to form barrier layer 935b, electric charge capture layer 930b and tunnel layer 925b.
With reference to Figure 10 C, the 3rd dielectric layer that is used to form coupling layer 840 is arranged on this composite structure, for example comprises silica material, forms about 50 to 100 dusts by for example CVD, LPCVD or other suitable deposits or growth technique.The conductive material layer that then is suitable for forming grid is deposited on this composite structure, and conductive material layer and the 4th dielectric layer pass through conventional photoetching composition process quilt composition, thereby are being positioned at formation grid 850 on the coupling layer 840 that reaches in the substrate 310 on the charge trapping structure 920.In one embodiment, conductive material layer 850 comprises polycrystalline silicon material, metal material or its combination.Can optionally the top of conductive material layer 850 be handled to form the policide layer that positivity is mixed.For example adopt CVD or LPCVD to apply the conductive material layer that the degree of depth is about 80 to 2000 dusts.
With reference to Figure 10 D, on this composite structure, select etch process, this technology causes the selection etching of electric charge capture layer 920 exposed exterior.In one embodiment, comprise under the situation of silicon nitride or silicon oxynitride, comprise that the wet etchant of hydrogen fluoride (HF) is applicable to the raising etching selectivity at tunnel layer 925c and barrier layer 935c.After charge trapping structure 920 is etched, form recessed in the exposed edge of charge trapping structure 920.
On this composite structure, carry out ion and inject, with the lightly-doped source/drain region 871,872 in source/drain region of forming device.Lightly-doped source/the drain region 871,872 of gained and grid 850 autoregistrations.Self aligned lightly-doped source/drain region can form after the selection etching of electric charge capture layer 930c, perhaps as selecting, can form before the selection etching of electric charge capture layer 930c.Then gate insulator 360 is formed on this composite structure.In one embodiment, gate insulator 360 comprises that the degree of depth by for example CVD, LPCVD or other suitable deposits or growth technique formation is about the silica material of 50 to 100 dusts.The gate insulator 360 that the recessed district of charge trapping structure 920 is applied in is partially or even wholly filled.
Side direction spacer body 380 is formed on the source electrode and the drain side of grid 850.In one embodiment, silicon nitride layer is arranged on this composite structure by for example CVD or other suitable deposits or growth technique, and the degree of depth is about 500 to 700 dusts.Eat-back to form side direction spacer body 380 according to routine techniques then.
On this composite structure, carry out ion then and inject, to form the heavy-doped source/drain region 891,892 of device source/drain regions.Heavy-doped source/the drain region 891,892 of gained and 380 autoregistrations of side direction spacer body.The RTP that adopts for example about 1000 ℃ or higher temperature to continue several seconds down carries out diffusion technology on this composite structure, with further inwardly diffusion lightly-doped source/drain region 871,872 make grid 850 overlapping lightly-doped source/drain regions 871,872 to channel region.In one embodiment, lightly doped source/drain region 871,872 extensions make lightly doped source region 871 aim at the recessed edge of charge trapping structure 920 basically.
The 6th technology that is used to make non-volatile memory device causes obtained device 900 to have provides the recessed electric charge capture layer of above-mentioned advantage.
Figure 11 A-11F is the sectional view of the 7th technology of the dizzy type non-volatile memory device of the SONOS type charge trapping structure that all has recessed electric charge capture layer in the source side and the drain side of grid formed according to the present invention.
With reference to Figure 11 A, gate insulator is formed in the substrate.In one embodiment, gate insulator comprises the silica material that forms about 50 to 100 angstroms depths by for example CVD, LPCVD or other suitable deposits or growth technique.The conductive material layer that is suitable for forming grid is arranged on the gate insulator.In one embodiment, conductive material layer comprises polycrystalline silicon material, SiGe sill, Ge sill or its combination.Can optionally the top of conductive material layer be handled to form positivity doped polycrystalline silicon-silicide layer.Conductive material layer for example adopts CVD or LPCVD to be embodied as about 80 to 2000 angstroms depths.Use conventional photoetching composition technology composition gate insulator and conductive material layer to form the gate dielectric layer 1015 and the main grid utmost point 1018.
On this composite structure, carry out ion and inject, with the lightly-doped source/ drain region 1071,1072 in source/drain region of forming device.Gained lightly-doped source/ drain region 1071,1072 and 1018 autoregistrations of the main grid utmost point.The RTP that uses for example about 1000 ℃ or higher temperature to continue several seconds on this composite structure carries out diffusion technology, so that lightly-doped source/ drain region 1071,1072 is further inwardly diffused into channel region, make the main grid utmost point 1018 overlapping lightly-doped source/ drain regions 1071,1072.
With reference to Figure 11 B, be used for the first dielectric 1025a of tunnel layer, the 3rd dielectric layer 1035a that is used for the second dielectric 1030a of electric charge capture layer and is used for the barrier layer and be successively set on the main grid utmost point 1018 and substrate 310 with aforesaid way shown in Fig. 5 A.
With reference to Figure 11 C, lateral conductive spacer body 1050 is formed on the source electrode and the drain side of the main grid utmost point 1018.In an embodiment who is used to form the conduction spacer body, the conductive material layer that for example comprises polycrystalline silicon material, SiGe sill, Ge sill or its combination is arranged on this composite structure by for example CVD or other suitable deposits or growth technique, and the degree of depth is about 500 to 700 dusts.Eat-back to form lateral conductive spacer body 1050 according to routine techniques then, it provides the function of side grid for device.
With reference to Figure 11 D, first, second expose portion with the 3rd dielectric layer 1025a, 1030a and 1035a is etched to form tunnel layer 1025b, electric charge capture layer 1030b and barrier layer 1035b with each side at the main grid utmost point 1018.
With reference to Figure 11 E, on this composite structure, select etch process, this technology causes the selection etching of electric charge capture layer 1030b exposed exterior.In one embodiment, comprise at electric charge capture layer 1030b under the situation of silicon nitride or silicon oxynitride, comprise phosphoric acid (H
3PO
4) wet etchant be applicable to the raising etching selectivity.After the etching of electric charge capture layer 1030c, form recessed in the exposed edge of electric charge capture layer 1030c.
With reference to Figure 11 F, on this composite structure, carry out ion and inject, to form the heavy-doped source/ drain region 1091,1092 of device source/drain regions.Heavy-doped source/the drain region 1091,1092 of gained and 1050 autoregistrations of side grid.The ion that is used to form heavy-doped source/ drain region 1091,1092 injects and can carry out after the selection etching of electric charge capture layer 1030c, perhaps as selecting, can carry out before the selection etching of electric charge capture layer 1030c.The RTP that adopts for example about 1000 ℃ or higher temperature to continue several seconds down carries out diffusion technology on this composite structure, to channel region, make side grid 1050 overlapping heavy-doped source/ drain regions 1091,1092 with further inwardly diffusion lightly-doped source/ drain region 1071,1072 and heavy-doped source/ drain region 1091,1092.
The 7th technology that is used to make non-volatile memory device causes the dizzy type device 1000 of gained to have the recessed electric charge capture layer that above-mentioned advantage is provided.
Figure 12 A-12F is the sectional view of the 8th technology of the dizzy type non-volatile memory device of the quantum dot array type charge trapping structure that all has recessed electric charge capture layer in the source side and the drain side of grid formed according to the present invention.
With reference to Figure 12 A, gate insulator is formed in the substrate.In one embodiment, gate insulator comprises the silica material that forms about 50 to 100 angstroms depths by for example CVD, LPCVD or other suitable deposits or growth technique.The conductive material layer that is suitable for forming grid is arranged on the gate insulator.In one embodiment, conductive material layer comprises polycrystalline silicon material, SiGe sill, Ge sill or its combination.Can optionally the top of conductive material layer be handled to form positivity doped polycrystalline silicon-silicide layer.Conductive material layer for example adopts CVD or LPCVD to be embodied as about 80 to 2000 angstroms depths.Use conventional photoetching composition technology composition gate insulator and conductive material layer to form the gate dielectric layer 1015 and the main grid utmost point 1018.
On this composite structure, carry out ion and inject, with the lightly-doped source/ drain region 1071,1072 in source/drain region of forming device.Gained lightly-doped source/ drain region 1071,1072 and 1018 autoregistrations of the main grid utmost point.
With reference to Figure 12 B, be used for the electric charge capture layer 1130a of the first dielectric 1125a, quantum dot array type of tunnel layer and the 3rd dielectric layer 1135a that is used for the barrier layer and be successively set on the main grid utmost point 1018 and substrate 310 in for example mode shown in above-mentioned Fig. 7 A.
With reference to Figure 12 C, lateral conductive spacer body 1050 is formed on the source electrode and the drain side of the main grid utmost point 1018.In an embodiment who is used to form the conduction spacer body, the conductive material layer that for example comprises polycrystalline silicon material, SiGe sill, Ge sill or its combination is arranged on this composite structure by for example CVD or other suitable deposits or growth technique, and the degree of depth is about 500 to 700 dusts.Eat-back to form lateral conductive spacer body 1050 according to routine techniques then, it provides the function of side grid for device.
With reference to Figure 12 D, the expose portion of the first dielectric layer 1125a, quantum dot array 1130a and the second dielectric layer 1135a is etched to form the charge trapping structure 1120 that comprises tunnel layer 1125b, electric charge capture layer 1130b and barrier layer 1135b with each side at the main grid utmost point 1018.
With reference to Figure 12 E, according to the described technology of Fig. 7 C, on this composite structure, select etch process, this technology causes the selection etching of charge trapping structure 1120 exposed exterior.After the etching of charge trapping structure 1120, form recessed in the exposed edge of charge trapping structure 1120.
With reference to Figure 12 F, on this composite structure, carry out ion and inject, to form the heavy-doped source/ drain region 1091,1092 of device source/drain regions.Heavy-doped source/the drain region 1091,1092 of gained and 1050 autoregistrations of side grid.Self aligned heavy-doped source/ drain region 1091,1092 can be carried out after the selection etching of charge trapping structure 1120, perhaps as selecting, can carry out before the selection etching of charge trapping structure 1120.The RTP that adopts for example about 1000 ℃ or higher temperature to continue several seconds down carries out diffusion technology on this composite structure, to channel region, make side grid 1050 overlapping heavy-doped source/ drain regions 1091,1092 with further inwardly diffusion lightly-doped source/ drain region 1071,1072 and/or heavy-doped source/drain region 1091,1092.The 8th technology that is used to make non-volatile memory device causes obtained device 1100 to have provides the recessed electric charge capture layer of above-mentioned advantage.
Though specifically illustrated the present invention and be described with reference to its preferred embodiment, but it should be appreciated by those skilled in the art, can in the scope that does not break away from spirit of the present invention defined by the claims and category, can carry out the variation of various forms and details the present invention.
Claims (50)
1, a kind of non-volatile memory device comprises:
The semiconductor-based end;
Source region and drain region, the position that separates on the top of described substrate;
Charge trapping structure is in the substrate between described source region and the drain region and comprise electric charge capture layer; With
Grid, on described charge trapping structure, wherein, be recessed in the described electric charge capture layer of the described charge trapping structure between the part one of at least of described grid and described source region and described drain region, wherein have recessed electric charge capture layer and between the lightly doped drain in the light dope source region in this source region and this drain region, extend continuously.
2, non-volatile memory device as claimed in claim 1, wherein, described grid overlap a part of described source region and a part of described drain region.
3, non-volatile memory device as claimed in claim 1, wherein, described source region comprises heavy doping source region and light dope source region, described drain region comprises heavy doping drain region and lightly doped drain, described light dope source region and lightly doped drain extend along the top of substrate towards each other from corresponding heavy doping source region and heavy doping drain region, and wherein, the described grid part of described light dope source region and lightly doped drain that overlaps.
4, non-volatile memory device as claimed in claim 3, wherein, described light dope source region and lightly doped drain are when first formation and the source side and the drain side autoregistration of described grid.
5, non-volatile memory device as claimed in claim 4, wherein, described light dope source region and lightly doped drain extend below by diffusion process in the source side and the drain side of described grid respectively.
6, non-volatile memory device as claimed in claim 3 also is included in the sidewall spacer body of the source side and the drain side of grid, and wherein heavy doping source region and heavy doping drain region are when first formation and the outside autoregistration of sidewall spacer body.
7, non-volatile memory device as claimed in claim 1, wherein, described source region and drain region when first formation respectively with the source side and the drain side autoregistration of grid.
8, non-volatile memory device as claimed in claim 7, wherein, extend below by diffusion process in the source side and the drain side of grid respectively in described source region and drain region.
9, as right source region 8 described non-volatile memory devices, wherein, the internal edge of at least one is aimed at the external margin of described charge trapping structure basically in described source region and the drain region.
10, non-volatile memory device as claimed in claim 1, wherein, the female is positioned at the source region side of electric charge capture layer.
11, non-volatile memory device as claimed in claim 1, wherein, the female is positioned at the source region side and the drain region side of described electric charge capture layer.
12, non-volatile memory device as claimed in claim 1 also is included in the dielectric substance in the female.
13, non-volatile memory device as claimed in claim 1, wherein, described charge trapping structure comprises first dielectric under the described electric charge capture layer and the 3rd dielectric on the described electric charge capture layer.
14, non-volatile memory device as claimed in claim 13, wherein, described first dielectric comprises the material that is selected from silica and silicon oxynitride; Wherein, described electric charge capture layer comprises the material that is selected from silicon nitride, silicon oxynitride and high-k dielectric, and wherein, described the 3rd dielectric comprises silica.
15, non-volatile memory device as claimed in claim 1, wherein, described electric charge capture layer is a quantum dot array.
16, non-volatile memory device as claimed in claim 15, wherein, described quantum dot array comprises the quantum dot that is selected from polysilicon quantum dot and silicon nitride quantum dot.
17, non-volatile memory device as claimed in claim 1, wherein, described charge trapping structure extends from the source region to the mesozone between source region and drain region, also be included in the gate-dielectric that the charge trapping structure from described mesozone extends to described drain region in the described substrate, wherein, described grid is positioned on the described charge trapping structure and on described gate-dielectric.
18, non-volatile memory device as claimed in claim 1, wherein, described charge trapping structure comprises that first charge trapping structure and wherein said grid comprise first auxiliary grid, also comprise:
Main grid utmost point dielectric is in the substrate between described source region and the drain region;
The main grid utmost point is on described main grid utmost point dielectric;
First charge trapping structure is in the substrate between the described source region and the main grid utmost point;
First auxiliary grid, on described first charge trapping structure, wherein, in first described first charge trapping structure that is recessed between described first auxiliary grid and a part of described source region;
Second charge trapping structure is in the substrate between the described drain region and the main grid utmost point; With
Second auxiliary grid, on described second charge trapping structure, wherein, in second described second charge trapping structure that is recessed between described second auxiliary grid and a part of described drain region.
19, a kind of non-volatile memory device comprises:
The semiconductor-based end;
Source region and drain region, the disconnected position in the top at the described semiconductor-based end;
Main grid utmost point dielectric is in the substrate between described source region and the drain region;
The main grid utmost point is on described main grid utmost point dielectric;
First charge trapping structure is in the substrate between the described source region and the main grid utmost point;
First auxiliary grid, on described first charge trapping structure, wherein, in first first charge trapping structure that is recessed between described first auxiliary grid and a part of described source region;
Second charge trapping structure is in the substrate between the described drain region and the main grid utmost point; With
Second auxiliary grid, on described second charge trapping structure, wherein, in second described second charge trapping structure that is recessed between described second auxiliary grid and a part of described drain region.
20, non-volatile memory device as claimed in claim 19, wherein, described first and second auxiliary grids comprise the side direction spacer body of conduction, and described spacer body is formed on described first charge trapping structure and described second charge trapping structure of the drain side that lays respectively at the main grid utmost point and source side.
21, non-volatile memory device as claimed in claim 19, wherein, described first and second charge trapping structures each all comprise first dielectric, at second dielectric on described first dielectric and the 3rd dielectric on described second dielectric.
22, non-volatile memory device as claimed in claim 21, wherein, described first dielectric comprises the material that is selected from silica and silicon oxynitride; Wherein, described second dielectric comprises the material that is selected from silicon nitride, silicon oxynitride and high-k dielectric, and wherein, described the 3rd dielectric comprises silica.
23, non-volatile memory device as claimed in claim 21, wherein, described first and second recessed being respectively formed in second dielectric of described first and second charge trapping structures.
24, non-volatile memory device as claimed in claim 19, wherein, each all comprises quantum-dot structure described first and second charge trapping structures, and described quantum-dot structure comprises first dielectric, the quantum dot array on described first dielectric and second dielectric that lists at described quantum dot array.
25, non-volatile memory device as claimed in claim 24, wherein, described first dielectric comprises the material that is selected from silica and silicon oxynitride; Wherein, described quantum dot array comprises the quantum dot that is selected from polysilicon quantum dot and silicon nitride quantum dot, and wherein, described second dielectric comprises silica.
26, non-volatile memory device as claimed in claim 19 also is included in first and second the dielectric substances in recessed.
27, a kind of method that forms non-volatile memory device comprises:
On the semiconductor-based end charge trapping structure is set, described charge trapping structure comprises electric charge capture layer;
On described charge trapping structure, grid is set;
Optionally the outward flange of at least one exposure of the described electric charge capture layer of etching is to form at least one being recessed between the described semiconductor-based end and described grid; And
Use described grid to form source region and drain region as the ion injecting mask in the described semiconductor-based end, wherein this electric charge capture layer does not extend to this source region and drain region.
28, method as claimed in claim 27 wherein, is provided with charge trapping structure and grid is set, and comprising:
On the described semiconductor-based end, electric charge capture layer is set;
On described electric charge capture layer, grid layer is set; And
Described grid layer of composition and electric charge capture layer are to form described grid structure and described charge trapping structure.
29, method as claimed in claim 27 wherein, is provided with charge trapping structure and grid is set, and comprising:
On the described semiconductor-based end, electric charge capture layer is set;
The described electric charge capture layer of composition is to be formed on the charge trapping structure that extends in the substrate between described source region and the mesozone, and described mesozone is between source region and drain region;
The gate-dielectric that extend in the described drain region of electric charge capture course from described mesozone is set in described substrate;
On the described electric charge capture layer He on the described gate-dielectric grid layer is being set; And
Described grid layer of composition and described gate-dielectric are to form described grid and described charge trapping structure.
30, method as claimed in claim 27 wherein, forms source region and drain region after the selection etching charge is captured structure.
31, method as claimed in claim 27 wherein, formed source region and drain region before the selection etching charge is captured structure.
32, method as claimed in claim 27 comprises that also diffusion described source region and described drain region make described grid structure overlap described source region and described drain region.
33, method as claimed in claim 32, wherein, the inward flange that spreads up to described source region and drain region at least one is aimed at the outward flange of described charge trapping structure basically.
34, method as claimed in claim 27, wherein, the source region side of selecting to be etched in described electric charge capture layer forms recessed.
35, method as claimed in claim 34, also comprise, before selecting etching, on the leakage side part of the described grid that extends to described drain region across the leakage side sidewall of described grid, applying the photoresist pattern, with the etching of the drain region side that prevents charge trapping structure.
36, method as claimed in claim 27, wherein, source region side and the drain region side selecting to be etched in electric charge capture layer all form recessed.
37, method as claimed in claim 27 wherein, forms described source region and drain region and comprises:
Use described grid in the described semiconductor-based end, to form light dope source region and lightly doped drain as the first ion injecting mask;
On the sidewall of described grid, form the side direction spacer body; With
Adopt described side direction spacer body in the described semiconductor-based end, to form heavy doping source region and heavy doping drain region as the second ion injecting mask.
38, method as claimed in claim 37 comprises that also diffusion described light dope source region and described lightly doped drain make described grid structure overlap described light dope source region and described lightly doped drain.
39, method as claimed in claim 27 wherein, is provided with described charge trapping structure and comprises: first dielectric layer is set; On described first dielectric layer, described electric charge capture layer is set; With the 3rd dielectric layer is set on described electric charge capture layer.
40, method as claimed in claim 39, wherein, described first dielectric layer comprises the material that is selected from silica and silicon oxynitride; Wherein, described electric charge capture layer comprises the material that is selected from silicon nitride, silicon oxynitride and high-k dielectric, and wherein, described the 3rd dielectric layer comprises silica.
41, method as claimed in claim 27 wherein, is provided with described charge trapping structure and comprises: first dielectric layer is set; On described first dielectric layer, quantum dot array is set; And list at described quantum dot array second dielectric layer is set.
42, method as claimed in claim 41, wherein, described first dielectric layer comprises the material that is selected from silica and silicon oxynitride; Wherein, described quantum dot array comprises the quantum dot of polysilicon quantum dot and silicon nitride quantum dot, and wherein, described second dielectric layer comprises silica.
43, method as claimed in claim 27 also is included in dielectric substance is set in the female.
44, a kind of method that forms non-volatile memory device comprises:
Main grid utmost point dielectric was set on the semiconductor-based end;
On described main grid utmost point dielectric, the main grid utmost point is set;
Described main grid extremely go up and the described semiconductor-based end on charge trapping structure is set;
At first and second sidewalls that are positioned at the main grid utmost point on the described main grid utmost point dielectric first and second auxiliary grids are set;
Select the outward flange of at least one exposure of the described charge trapping structure of etching to be recessed between the described semiconductor-based end and described first auxiliary grid, to form first; And
Use the described main grid utmost point and described first and second auxiliary grid in the described semiconductor-based end, source region and drain region to be set as the ion injecting mask.
45, method as claimed in claim 44 wherein, is selected etching also to form second between the described semiconductor-based end and described second auxiliary grid and is recessed into.
46, method as claimed in claim 44 wherein, is provided with described first and second auxiliary grids and comprises:
Form the first and second side direction spacer bodies of electric conducting material on the charge trapping structure on the sidewall of the described main grid utmost point, the described first and second side direction spacer bodies comprise first and second auxiliary grids respectively; And
Use the described main grid utmost point and described first and second side direction spacer body in the described semiconductor-based end, to form described source region and described drain region as the ion injecting mask.
47, method as claimed in claim 44 wherein, is provided with described charge trapping structure and comprises:
First dielectric layer is set; On described first dielectric layer, electric charge capture layer is set; With the 3rd dielectric layer is set on described electric charge capture layer, wherein, described first dielectric layer comprises the material that is selected from silica and silicon oxynitride; Wherein, described electric charge capture layer comprises the material that is selected from silicon nitride, silicon oxynitride and high-k dielectric, and wherein, described the 3rd dielectric layer comprises silica.
48, method as claimed in claim 47 wherein, selects etching to cause the female to be formed in the described electric charge capture layer.
49, method as claimed in claim 44 wherein, is provided with described charge trapping structure and comprises: first dielectric layer is set; On described first dielectric layer, quantum dot array is set; And list at described quantum dot array and to form second dielectric layer, wherein, described first dielectric layer comprises the material of selecting from the group that comprises silica and silicon oxynitride; Wherein, described quantum dot array comprises the quantum dot that is selected from polysilicon quantum dot and silicon nitride quantum dot, and wherein, described second dielectric layer comprises silica.
50, method as claimed in claim 44 also is included in dielectric substance is set in the female.
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| US62081104P | 2004-10-21 | 2004-10-21 | |
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| KR1267/05 | 2005-01-06 | ||
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| US7405441B2 (en) | 2005-03-11 | 2008-07-29 | Infineon Technology Ag | Semiconductor memory |
| KR100855557B1 (en) * | 2006-10-12 | 2008-09-01 | 삼성전자주식회사 | Non-volatile memory device and method of fabricating the same |
| KR100827705B1 (en) * | 2006-10-23 | 2008-05-07 | 삼성전자주식회사 | on volatic memory device and method manufacturing the same |
| KR100827450B1 (en) | 2007-05-18 | 2008-05-07 | 삼성전자주식회사 | Non-volatile memory device and method of fabricating the same |
| KR100810519B1 (en) * | 2007-05-23 | 2008-03-07 | 한국과학기술원 | Non-volatile memory cell using mechanical switch and array thereof |
| KR101033222B1 (en) | 2007-06-29 | 2011-05-06 | 주식회사 하이닉스반도체 | Method of fabricating the non-volatile memory device having charge trapping layer |
| KR100941619B1 (en) * | 2008-02-04 | 2010-02-11 | 경북대학교 산학협력단 | High-performance NAND flash memory cell string and cell device and switching device |
| US7829929B2 (en) | 2008-02-19 | 2010-11-09 | Samsung Electronics Co., Ltd. | Non-volatile memory device and non-volatile semiconductor integrated circuit device, including the same |
| CN106653761A (en) * | 2009-04-10 | 2017-05-10 | 赛普拉斯半导体公司 | Oxide-nitride-oxide stack comprising multi-layer oxynitride layer |
| KR101115756B1 (en) * | 2011-09-23 | 2012-03-06 | 권의필 | Highly integrated programmable non-volatile memory and the manufacturing method thereof |
| CN110364215B (en) * | 2019-07-16 | 2021-05-25 | 武汉新芯集成电路制造有限公司 | Flash memory HTOL test method |
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| US6639271B1 (en) | 2001-12-20 | 2003-10-28 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
| KR100475087B1 (en) * | 2002-08-19 | 2005-03-10 | 삼성전자주식회사 | Method for fabricating non-volatile memory device having local SONOS structure |
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