CN106653761A - Oxide-nitride-oxide stack comprising multi-layer oxynitride layer - Google Patents
Oxide-nitride-oxide stack comprising multi-layer oxynitride layer Download PDFInfo
- Publication number
- CN106653761A CN106653761A CN201610911402.6A CN201610911402A CN106653761A CN 106653761 A CN106653761 A CN 106653761A CN 201610911402 A CN201610911402 A CN 201610911402A CN 106653761 A CN106653761 A CN 106653761A
- Authority
- CN
- China
- Prior art keywords
- layer
- oxynitride layer
- oxide
- oxynitride
- oxygen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims abstract description 90
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 53
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 43
- 239000001301 oxygen Substances 0.000 claims abstract description 43
- 238000003860 storage Methods 0.000 claims abstract description 39
- 239000000203 mixture Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 239000000126 substance Substances 0.000 claims abstract description 7
- 239000007789 gas Substances 0.000 claims description 36
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 32
- 229910000069 nitrogen hydride Inorganic materials 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 27
- 238000005229 chemical vapour deposition Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 17
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 11
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 9
- 230000008859 change Effects 0.000 claims description 7
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 239000002800 charge carrier Substances 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 239000001272 nitrous oxide Substances 0.000 claims 8
- 206010011906 Death Diseases 0.000 claims 4
- 238000001556 precipitation Methods 0.000 claims 3
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 claims 2
- 125000003636 chemical group Chemical group 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 42
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 21
- 230000015572 biosynthetic process Effects 0.000 abstract description 16
- 238000000151 deposition Methods 0.000 description 13
- 230000014759 maintenance of location Effects 0.000 description 11
- 230000008021 deposition Effects 0.000 description 10
- 230000015654 memory Effects 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000002156 mixing Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 230000036962 time dependent Effects 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 239000005046 Chlorosilane Substances 0.000 description 2
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical group [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 206010058490 Hyperoxia Diseases 0.000 description 2
- 206010021143 Hypoxia Diseases 0.000 description 2
- OLBVUFHMDRJKTK-UHFFFAOYSA-N [N].[O] Chemical compound [N].[O] OLBVUFHMDRJKTK-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052805 deuterium Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- LZDSILRDTDCIQT-UHFFFAOYSA-N dinitrogen trioxide Chemical compound [O-][N+](=O)N=O LZDSILRDTDCIQT-UHFFFAOYSA-N 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000000222 hyperoxic effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- -1 -tert-butyl amino silane Chemical compound 0.000 description 1
- 206010002660 Anoxia Diseases 0.000 description 1
- 241000976983 Anoxia Species 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 241001062009 Indigofera Species 0.000 description 1
- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 description 1
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ILRRQNADMUWWFW-UHFFFAOYSA-K aluminium phosphate Chemical compound O1[Al]2OP1(=O)O2 ILRRQNADMUWWFW-UHFFFAOYSA-K 0.000 description 1
- 230000007953 anoxia Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000007954 hypoxia Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Abstract
The invention relates to an oxide-nitride-oxide stack comprising a multi-layer oxynitride layer, and discloses a semiconductor device of the oxide-nitride-oxide (ONO) stack comprising a multi-layer charge storage layer and a formation method of the semiconductor device. In general, the method relates to the following steps of (i) forming a first oxide layer of an ONO structure; (ii) forming the multi-layer charge storage layer containing nitrides on the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on the multi-layer charge storage layer. Preferably, the charge storage layer comprises at least two silicon oxynitride layers containing different chemical composition ratios of oxygen, nitrogen and/or silicon. More preferably, the ONO structure is one part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is an SONOS storage transistor.
Description
The application is Application No. 200910134374.1, and the applying date is on April 10th, 2009, entitled " containing many
The divisional application of the application of the oxidenitride oxide storehouse of layer oxynitride layer ".
Technical field
The present invention relates to semiconductor fabrication process, more particularly to the oxygen of the nitride-oxide containing improvement or oxynitride layer
Compound-Nitride Oxide storehouse and forming method thereof.
Background technology
Nonvolatile semiconductor memory such as splitting bar flash memories, are usually used storehouse floating gate type field effect transistor
Pipe.In such a transistor, by being biased to control gate, the body area ground connection of the substrate that memory element is formed thereon is made,
Electronics is injected into will be programmed that in the floating boom of memory element.
One oxidenitride oxide (ONO) storehouse is used as silicon-oxide-nitride-oxide-silicon
(SONOS) charge storage layer of transistor, or the isolation being used as between the floating boom of splitting bar flash memories and control gate
Layer.
Fig. 1 is the intermediate structure sectional view of semiconductor device 100.Semiconductor device 100 includes one comprising by tradition side
The SONOS grid storehouse or structure 102 of the conventional ONO stack 104 that method is formed on the surface 106 of silicon substrate 108.Additionally, generally half
Conductor device 100 also includes one or more diffusion zones 110, such as source and drain areas, alignment grid storehouse and by channel region 112 every
From.Briefly, SONOS grid storehouse 102 includes a polycrystalline silicon grid layer for being formed on ONO storehouses 104 and being attached thereto
114.ONO storehouses 104 separate polycrystalline silicon grid layer 114 with silicon substrate 108 or electrical isolation.ONO storehouses 104 generally include one
Suboxides layer 116, and as the nitride or oxynitride layer 118 of the charge storage layer of device 100, and be covered in nitride or
Top high-temperature oxide (HTO) layer 120 on oxynitride layer.
The problem that traditional SONOS structures 102 and forming method thereof are present is the number of nitride or oxynitride layer 118
It is poor according to retentivity, which has limited the life cycle of semiconductor device 100, and the drain current limit of nitride or oxynitride layer
Its application at several aspects.
Another problem that traditional SONOS structures 102 and forming method thereof are present is the chemical dose of oxynitride layer 118
Than both uneven or not optimization thickness.Especially oxynitride layer 118 is usually formed or is deposited on and mixed using single technique
The one step of gas and technique for fixing condition, in order to provide a conforming layer, it has high nitrogen, the relevant layers of elevated oxygen level
Thickness.However, due to the function influence nitrogen of top and bottom, oxygen and silicone content result, it can change whole routine oxynitride
Layer 118.It is due to closing process gas after deposition that top effect causes.Particularly, the silicon containing process gas, such as silane, typical case
Closing first result in the top of the oxynitride layer 118 containing hyperoxia and/or nitrogen and low silicon.Likewise, bottom effect causes
Process gas is introduced when being due to Preliminary deposition.Particularly, the deposition of oxynitride layer 118 generally occurs in an annealing steps
Afterwards, result in ammonia (NH3) concentration higher even up to peak and produces the high nitrogen of the low silicon of hypoxia in the depositing operation incipient stage
Oxynitride layer bottom.Bottom effect is also due to surface nucleation phenomenon, the silicon and oxygen and lining in initial process mixed gas
The silicon preferential reaction of basal surface, the silicon and oxygen in initial process mixed gas does not have any tribute to the formation of oxynitride layer
Offer.Therefore, the memorizer 100 containing ONO storehouses 104 electric charge storage characteristic curve, especially programmed and erased speed and
Data retention, there is snob effect.
Thus generate and, as the demand of the semiconductor device of the ONO storehouses of accumulation layer, be somebody's turn to do half to oxynitride layer
Conductor device can improve programmed and erased speed and data retention.Also generate to the ONO structure storehouse containing oxynitride layer
The further demand of formation process or method, the technique or method can improve oxynitride stoichiometric proportion.
The content of the invention
The present invention will be to provide a kind of oxynitriding containing multilamellar there is provided the method for solving these or other technical problems
The semiconductor device of the oxidenitride oxide storehouse of nitride layer, it can improve programmed and erased speed and data keep
Property.For this purpose, the present invention also provides the forming method of above-mentioned semiconductor device.
To solve above-mentioned technical problem, the present invention provides a kind of forming method of charge storage layer in semiconductor device, should
Method comprises the steps:
A persilicic nitride is deposited on substrate;And
Oxidation persilicic nitride forms the few oxynitride layer of oxygen first of Silicon-rich.
The method further includes step:At least one of which extra play is formed in the first oxynitride layer surface to form one
Individual plurality of charge storage layers.
The step of formation at least one of which extra play, includes the step of forming the second oxynitride layer.
Oxygen in first oxynitride layer and the second oxynitride layer, nitrogen and/or silicon have different chemical composition ratios.
The step of the second oxynitride layer of the formation, form second under the conditions of the few oxygen oxynitride layer of Silicon-rich including being formed
The step of oxynitride layer.
First oxynitride layer is formed by chemical vapor deposition method, and its process gas for adopting is included
SiH2Cl2/NH3Mixture and N2O/NH3Mixture, both ratios are 8:1, second oxynitride layer passes through chemical vapor deposition
Product technique is formed, and its process gas includes N2O/NH3Mixture and SiH2C 2/NH3Mixture, its blending ratio is 5: 1.
The step of the first oxynitride layer of the formation and the second oxynitride layer, is by changing N2O/NH3And SiH2Cl2/
NH3Mixing ratio in succession in same CVD instruments operate.
The temperature that at least one of which in first oxynitride layer and the second oxynitride layer is formed is at least 780 DEG C.
The present invention also provides a kind of formation side of the semiconductor device including an oxidenitride oxide structure
Method, the method comprises the steps:
Form the first oxide skin(coating) of ONO structure;
The plurality of charge storage layers containing nitride is formed on the first oxide skin(coating);And
The second oxide skin(coating) of ONO structure is formed on plurality of charge storage layers surface.
The plurality of charge storage layers includes at least two silicon oxynitride layers.
Oxygen at least two oxynitride layer, nitrogen and/or silicon have different chemical composition ratios.
At least two oxynitride layer includes a top oxynitride layer and a bottom oxynitride layer, wherein
Top oxynitride layer is formed as Silicon-rich, and few oxygen oxynitride layer, bottom oxynitride layer is formed as Silicon-rich oxygen-rich oxy-nitride
Layer.
The top oxynitride layer is rich nitrogen oxynitride layer.
The step of the first oxide skin(coating) of the formation, includes the step of forming the first oxide skin(coating) by steam annealing, wherein
The thickness ratio of suitable top oxynitride layer and bottom oxynitride layer is selected, is to form tunnel oxidation using steam annealing
The formation of multilayered memory layer after layer provides facility.
The process gas composition that formation top oxynitride layer is used includes SiH2Cl2/NH3Mixed gas and N2O/
NH3Mixed gas, its mixed proportion about 5:1, the process gas composition that formation top oxynitride layer is used is comprising N2O/NH3It is mixed
Close gas and SiH2Cl2/NH3Mixed gas, its mixed proportion is 8:1.
The temperature that at least two oxynitride layer is formed is at least 780 DEG C.
Additionally, the present invention also provides a kind of semiconductor device of oxycompound-nitride-oxide configuration, the oxidation
Thing-nitride-oxide configuration includes the multilayered memory layer between the first oxide layer and the second oxide layer, wherein multilayered memory layer
Comprising at least two silicon oxynitride layers.
Oxygen at least two oxynitride layer, nitrogen and/or silicon have different chemical composition ratios.
The oxygen, nitrogen and silicon form at least two oxynitride layers so as to which in operation temperature, at least 125 DEG C are issued in advance
The data retention of setting.
At least two oxynitride layer includes a top oxynitride layer and a bottom oxynitride layer, wherein
The thickness ratio of top oxynitride layer and bottom oxynitride layer is 1-5.
Compared with prior art, the beneficial effects of the present invention is:I () can improve and for oxynitride layer be divided into multilamellar simultaneously
Every layer of oxygen of adjustment, nitrogen, and the data retention of the memory device of silicon;(ii) can not be improved premised on sacrifice data retention
The speed of memory device;(iii) according to embodiments of the present invention 125 DEG C are at least about in temperature using the memory device of ONO structure
When, data retention and speed can be met or exceeded;And (iv) provide the big task programming erasing cycle be 100,000 times or
It is more.
Description of the drawings
The present invention will be by detailed description below, in conjunction with the accompanying drawings and embodiments discussing these or some of the present invention
Other the characteristics of or advantage.Wherein:
Fig. 1 (prior art) is containing oxidenitride oxide (ONO) storehouse according to traditional method formation
The sectional structure chart of the intermediate structure of memory device.
Fig. 2 is of the semiconductor device of an ONO structure comprising plurality of charge storage layers in the embodiment of the present invention
The sectional structure chart for dividing.
Fig. 3 is the flow chart of the forming method of the ONO structure comprising plurality of charge storage layers in the embodiment of the present invention.
Fig. 4 is the memory device using the accumulation layer for being formed according to embodiments of the present invention and the storage for using conventional store layer
The curve chart that the data retention that device is compared is improved.
Specific embodiment
Oxidenitride oxide (ONO) structure of the paper of the present invention comprising plurality of charge storage layers and its system
Make method.ONO structure and its manufacture method are particularly suited for the formation of memory device accumulation layer, such as silicon-oxide-nitride-
Oxide-silicon (SONOS) memory transistor.
In following description, by the detailed substantial amounts of detail of elaboration, so as to fully be fully understood by the present invention.
In the case of without these details, those skilled in the art can also implement the present invention.In other cases, known knot
Structure and technology, are not described in or show in the accompanying drawings, in order to avoid unnecessary dark solution is produced to the present invention.
With reference to " embodiment " of description of the invention, the specific function for describing in a related embodiment, structure, material are referred to
Expect, or feature is included at least one embodiment of the present invention.Therefore, the present invention different places occur phrase "
In one embodiment " it is not necessarily referring in the same embodiment of the present invention.Additionally, specific function, structure, material, or
Feature may in an appropriate manner combine in other one or more embodiments.
Briefly, the method is related to form the plurality of charge storage layers comprising plurality of oxynitrides layers, such as oxynitriding
Thing silicon layer (Si2N2O), there are the oxygen of variable concentrations, nitrogen and/or silicon.Generally, oxynitride layer is formed in and nitrogen in traditional ONO structure
Compound or oxynitride layer are compared under higher temperature conditionss, and the different process gas mixture of per layer of employing and/or
Formed under different flow rate ratios.Preferably, oxynitride layer includes at least one top oxynitride layer and bottom oxygen nitrogen
Compound layer.It is further preferred that the stoichiometric proportion composition of each layer is adjusted or is chosen to bottom or lower end oxynitride and has
The high silicon concentration of hyperoxia, top oxynitride layer has high-silicon high nitrogen low oxygen concentration to produce persilicic nitride or oxynitride.Silicon-rich
With the charge loss that oxygen-enriched bottom oxynitride layer reduces storage, do not damage device speed or programmed and erased voltage just
Beginning difference (life cycle incipient stage).Silicon-rich and anoxia top oxynitride layer increased program voltage and the wiping of memory device
Except the difference of voltage, thus device speed is enhanced, improve data retention, extend the operation life cycle of device.
Optionally, the thickness ratio of top oxynitride layer and bottom oxynitride layer can be selected, is to be moved back using steam
Oxynitride layer being formed after fire the first oxide skin(coating) of formation on the first oxide skin(coating) of ONO structure, facility is provided.
According to various embodiments of the invention, ONO structure and its manufacture method will be described in detail, details refer to figure
2-4。
Fig. 2 is the semiconductor storage unit 200 of an ONO structure comprising plurality of charge storage layers in the embodiment of the present invention
A part sectional structure chart.According to Fig. 2, memory device 200 includes a SONOS grid storehouse 202, the SONOS grid storehouses
202 include an ONO structure 204 being formed on the silicon surface 206 of substrate or silicon substrate 208.Additionally, SONOS type devices
Part 200 further includes one or more diffusion zones 210, such as source drain region, the alignment grid storehouse of source drain region 210
202 and separated by channel region 212.Generally, SONOS grid storehouse 202 includes polysilicon (poly) gate layer 214, its formation
In ONO structure 204 and part silicon layer or the top of substrate 208 and it is attached thereto.ONO structure 204 is by polysilicon gate 214 and substrate
208 separate or electrical isolation.ONO structure 204 generally includes a thin relatively low oxide layer or tunnel oxide 216, and it will
Grid storehouse 202 and channel region 212, top or barrier oxide layer 218, and the plurality of charge storage layers comprising nitride multilayer thing
Separate or electrical isolation.Preferably, as mentioned above and shown in Fig. 2, plurality of charge storage layers includes at least two oxynitrides
Layer, including top oxynitride layer 220A and bottom oxynitride layer 220B.
In general, substrate 208 potentially includes any of silicon semiconductor material includes silicon, SiGe, SOI or indigo plant
Gem silicon substrate.In addition, substrate 208 potentially includes the silicon layer being formed in not siliceous semiconductor base material, such as GaAs,
Germanium, gallium nitride, or aluminum phosphate.Preferably substrate 208 is a doped or non-doped silicon substrate.
The relatively low oxide layer of ONO structure 204 or tunneling oxide layer 216 generally include the silicon dioxide of a relative thin
(SiO2) layer its thickness is aboutPreferably approximatelyTunneling oxide layer 216 can be in any suitable manner
Formed or deposited, for example, be thermally generated or deposited by chemical vapor deposition (CVD).In a preferred embodiment, tunnel
Oxide layer is formed by steam annealing or grown.Generally, the technique includes wet oxidation method, and wherein substrate 208 is placed on heavy
Product or process cavity, heating makes temperature from about 700 DEG C to about 850 DEG C, and is exposed in wet method gas phase, is the predetermined time cycle
The tunnel oxidation layer 216 completed on the basis of desired thickness is selected.The exemplary process time is of about 5 to 20 minutes.Can be big
Oxidation technology is carried out in gas or at lower pressures.
As described above, plurality of charge storage layers generally includes at least two oxynitride layers, it has a different silicon, oxygen and
Nitrogen is constituted, and gross thickness is aboutPreferably aboutIn a preferred embodiment, oxynitriding
Nitride layer is formed or is deposited in low pressure CVD processes, using silicon source, such as silane (SiH4), chlorosilane (SiH3Cl), Silicon chloride.
(SiCl4), or dual-tert-butyl amino silane (BTBAS), nitrogen source, such as N2, NH3, N2O or nitrogen trioxide (NO3), and it is oxygenous
Body, such as O2Or N2O.Selectively, hydrogen may be replaced with deuterium, including for example, with ammonia, deuterated (ND3) substitute NH3。
Deuterium is substituted into hydrogen to be conducive to being passivated the Si keys that silicon-oxide interface hangs, thus increases NBTI (the back bias voltage temperature of SONOS type devices
Degree unstability) life-span.
For example, a bottom or lower end oxynitride layer 220B are deposited on tunnel oxide 216, by placing lining
Bottom 208 is in deposition chamber and introduces process gas including N2O, NH3And DCS, and chamber pressure is kept in about 5-500mT, and keep
Underlayer temperature, preferably at least at about 780 DEG C, lasts about 2.5-20 minutes at about 700 DEG C -850 DEG C.In a further enforcement
In example, process gas includes the first mixed gas N2O and NH3, its mixing ratio is about 8: 1-1: 8, the second mixed gas SiH2Cl2
And NH (DCS)3, its mixing ratio about 1: 7-7: 1, the flow-rate ratio about 5-200 standard cubic centimeters per minutes (sccm) of introducing.It is reported that
The oxynitride layer for generating in this case or depositing produces the oxygen-enriched bottom oxynitride layer 220B of Silicon-rich, after reducing programming
With the charge loss rate after erasing, its major embodiment little voltage drift in retained mode.
One top oxynitride layer 220A is deposited on low side oxynitride layer 220B, and by CVD techniques work is adopted
Skill gas includes N2O, NH3And DCS, and chamber pressure is kept in about 5-500mT, and underlayer temperature is kept at about 700 DEG C -850
DEG C, preferably at least at about 780 DEG C, last about 2.5-20 minutes.In one further embodiment, process gas includes first
Mixed gas N2O and NH3, its mixing ratio is about 8: 1-1: 8, the second mixed gas DCS and NH3, its mixing ratio about 1: 7-7: 1 draws
The flow-rate ratio for entering is about 5-20 standard cubic centimeters per minutes (sccm).It is reported that the oxynitriding for being formed in this case or being deposited
Nitride layer produces Silicon-rich and the few oxygen top oxynitride layer 220A of rich nitrogen, which raises speed and increased the programming electricity of memory device
The initial difference of pressure and erasing voltage, and do not affect the electric charge of the memory device of the ONO structure 204 for using the embodiment of the present invention
Turnover rate, so as to extend the operation life cycle of device.
Preferably, oxynitride layer 220A in top is subsequently deposited at the same instrument to form bottom oxynitride layer 220B
In, and do not break the vacuum environment of deposition chamber completely.It is further preferred that top oxynitride layer 220A does not have completely when depositing
Have and change the temperature that substrate 208 is heated when bottom oxynitride layer 220B is deposited.In one embodiment, top oxynitride
Layer 220A sequential depositions, and the followed by deposition of bottom oxynitride layer 220B, and by reducing N2O/NH3Mixed gas for
DCS/NH3The flow rate ratio of mixed gas forms the few oxygen bottom oxygen nitrogen of Silicon-rich richness nitrogen come the mixed gas flow rate required for reaching
Compound layer 220A.
In certain embodiments, another oxide or oxide layer (not shown) are formed in substrate zones of different
After ONO structure 204 is formed, or vapor-phase oxidation is used in the devices.In this embodiment, top oxynitride layer 220A and
The top oxide layer 218 of ONO structure 204 good steam annealing during vapor-phase oxidation.Particularly steam annealing improves
The quality of top oxide layer 218, reduces and is formed in the top layer of top oxide layer top oxynitride layer adjacent and below
Trap near the top layer of 220A, thus reduction or substantially elimination can form the electric field of top oxide layer, and this will cause electricity
The data or electric charge of the backflow of charge carrier and converse impact charge storage layer keep.
It is reported that, the suitable thickness of bottom oxynitride layer 220B is aboutBottom and top oxynitride layer
Thickness ratio about 1: 6-6: 1, preferably at least about 1: 4.
The top oxide layer 218 of ONO structure 204 includes a relative thickness aboutSiO2Layer, it is best
BeTop oxide layer 218 can be formed or deposited by any suitable method, and for example, heat energy is generated or CVD is heavy
Product.In a preferred embodiment, top oxide layer 218 is by CVD process high-temperatures oxidation (HTO) deposition.Generally, deposit
Technique includes exposure substrate 208 in silicon source, such as silane, chlorosilane, or dichlorosilane, and oxygen-containing gas, such as O2Or N2O, deposition
The air pressure of cavity is about 50mT-1000mT, and the persistent period is about 10-120 minutes, keeps underlayer temperature to be about 650 DEG C -850 DEG C.
Preferably top oxide layer 218 is deposited on to form oxynitride layer 220A then, in the same instrument of 220B.More
Preferably oxynitride layer 220A, 220B and top oxide layer 218 are formed or are deposited on and generate the same of tunneling oxide layer 216
In instrument.Suitable instrument includes, for example, the ONO AVP of California AVIZA technology companys production.
According to embodiments of the present invention, the method for forming or manufacturing ONO storehouses refers to the flow chart of Fig. 3.
According to Fig. 3, the method from the beginning of the first oxide layer of ONO structure is formed, such as tunneling oxide layer, first oxidation
Layer is formed in (step 300) on the silicon-containing layer of substrate surface.Then, the ground floor of the multilamellar electric charge storage layer of nitrogenate is formed
In the first oxidation layer surface (step 302).As described above, this ground floor or bottom oxynitride layer can pass through CVD techniques
Formed or deposited, it uses process gas to include N2O/NH3And DCS/NH3Mixed gas, its mixed proportion or flow rate adjustment are suitable
Conjunction forms Silicon-rich oxygen-rich oxynitride layer.The second layer of multilamellar electric charge storage layer is subsequently formed at the first layer surface (step 304).
The second layer contains the stoichiometric proportion composition of the oxygen different with ground floor, nitrogen and/or silicon.Especially, as described above, second or top
Oxynitride layer can be formed or deposited by CVD techniques, and it uses process gas to include N2O/NH3And DCS/NH3Gaseous mixture
Body, its mixed proportion or flow rate adjustment are to suitably form the few oxygen top oxynitride layer of Silicon-rich.Finally, the second oxygen of ONO structure
Change the second layer surface (step 306) that layer is formed in multilamellar electric charge storage layer.As described above, the top or barrier oxide layer can be with
Formed by any suitable means or deposited, it is preferred that using CVD process deposits.In one embodiment, top or
Dioxide layer is in HTO CVD technique high temperature oxide depositions.In addition, top or barrier oxide layer can be generated by heat energy,
But fortunately in this embodiment, the thickness of oxynitride must adjust or increase to a part of top oxynitriding
Thing can effectively be consumed or aoxidized during heat energy generates barrier oxide layer.
Selectively, this method may further include that the silicon-containing layer to be formed or be deposited in the second oxidation layer surface comes
Form SONOS storehouses or structure (step 308).Silicon-containing layer can be, such as polysilicon layer, and it is by CVD process deposits come shape
Into SONOS transistors or the control gate of device.
The data of the memory device of the memory device and conventional store layer of the accumulation layer formed according to present example example are protected
Holding property relatively refers to Fig. 4.Especially, Fig. 4 illustrates traditional ONO structure and the ONO structure containing plurality of oxynitrides layers is generated
Electronics EPROM (EEPROM) device lifetime programming (VTP) and erasing (VTE) during device
Threshold voltage change.To collect data two devices elimination run 100K time all at 85 DEG C of this figure.
According to Fig. 4, icon or line 402 illustrate using traditional ONO structure of single oxynitride layer EEPROM at any time
Between the VTP that changes, and do not have to be updated after initial write operation-programming or erasing and store.Actual data point on line 402 is empty
Heart circle shows that remaining line represents the VTP of reckonings of the EEPROM under specific EOL.Figure or line 404 show traditional ONO structure
The time dependent VTE of lower EEPROM.The actual data point of line 404 shows that remaining line represents that EEPROM is specified with filled circles
The VTE of the reckoning under EOL.Generally, EEPROM differences of VTE and VTP under EOL are at least 0.5V, could recognize and sense volume
The difference of journey and erase status.As can be seen here, the difference of the VTE and VTP of the EEPROM under traditional ONO structure is about 0.35V, special
EOL is determined for 20 years.Therefore, the EEPROM of a traditional ONO structure is compared with the EEPROM under above-mentioned condition and be have lost at least 17
The operating time in year.
By contrast, over time, using containing plurality of oxynitrides layers ONO structure EEPROM in VTP and
The change online 406 and 408 of VTE respectively obtains statement, it is shown that the difference of VTE and VTP is at least 1.96V under specific EOL.
Therefore, the specific operation life that 20 years can be reached and exceeded using the EEPROM of ONO structure according to embodiments of the present invention.Especially
It is, figure or line 406 illustrate the time dependent VTP of EEPROM according to embodiments of the present invention using ONO structure.Online
Actual data point on 406 is represented that remaining line shows the VTP of the deduction of specific EOL by hollow square.Figure or line 408 are explained
Understand the VTE of time dependent EEPROM, the actual data point on online 408 is represented that remaining line shows by closed square
Go out a kind of VTE of the deduction to EOL.
Although shown above and statement only two-layer oxynitride layer, e.g., top layer and bottom, the present invention does not limit to
In this, plurality of charge storage layers can include any quantity, n-layer oxynitride layer, one layer of any of which or all of have not
With the oxygen that stoichiometric proportion is constituted, nitrogen and/or silicon.Particularly plurality of charge storage layers has and reaches 5 layers of oxynitride layer, every layer of Jing
Test is made up of different stoichiometric proportions.However, due to those skilled in the art preferably as far as possible using fewer
Accomplishing the result wanted, reduction forms the necessary processing step of device to layer, so as to improve simpler sound automation process.
Additionally, it is better using fewer layer, high yield is also generated, because less level is relatively easy to control the stoichiometry of constituent
Than and density.
More fortunately, although being expressed as the SONOS storehouses in the SONOS memorizeies of part, the ONO of the present invention
Structures and methods are not limited thereto, and ONO structure can be used in any semiconductor technology or any need to store electric charge or medium
The device of layer or storehouse, including for example, in a splitting bar flash memories, a TaNOS storehouse, a 1T (transistor)
SONOS units, a 2T SONOS unit, a 3T SONOS unit, a local 2-bit unit, and a multilamellar programming
Or unit, all it is not above the scope of the invention.
According to embodiments of the present invention, ONO structure and its advantage of formation, surmount existing or traditional method including (i)
Can improve by oxynitride layer be divided into multilamellar and adjust every layer of oxygen, nitrogen, and silicon memory device data retention;(ii) energy
The enough speed that memory device is not improved premised on sacrifice data retention.(iii) ONO structure is used according to embodiments of the present invention
Memory device when temperature is at least about 125 DEG C, data retention and speed can be met or exceeded;And (iv) provides big
The task programming erasing cycle is 100,000 times or more.
Although the present invention describes architectural feature and/or method and technology in detail, it is to be appreciated that defined in the present invention
Accessory claim be not necessarily limited to described specific features or technical scheme.These specific features and technical scheme should be by
Understanding is the specific embodiment as the claims in the present invention.Illustrate as far as possible, and not limit the present invention.
Claims (17)
1. a kind of forming method of semiconductor device, including:
Plurality of charge storage layers is formed, is included on substrate and is deposited the first oxygen-enriched oxynitride layer, and in first oxygen
Second oxynitride layer of the few oxygen of Direct precipitation and Silicon-rich on nitride layer, wherein the chemical group of first oxynitride layer
Into oxygen of the ratio comprising selected high concentration, the oxygen of the selected high concentration is captured on second oxynitriding by serving as
The barrier between electric charge and the substrate in nitride layer is increasing the holding performance of the plurality of charge storage layers;
Second oxynitride layer described in steam annealing is reducing the quantity of the trap being formed near its top layer;And
Directly barrier oxide layer is formed on second oxynitride layer, wherein form the barrier oxide layer moving back including steam
The fire barrier oxide layer is reducing the backflow of the electric charge carrier by the barrier oxide layer.
2. method according to claim 1, wherein the increasedd holding performance of the plurality of charge storage layers will compiled
The end-of-life (EOL) of the semiconductor device under the specified difference between journey voltage and erasing voltage increases at least about 20
Year.
3. method according to claim 1, wherein first oxynitride layer passes through chemical vapor deposition (CVD) technique
Formed, the process gas that it is adopted includes dichlorosilane (SiH2Cl2)/ammonia (NH3) mixture and nitrous oxide (N2O)/NH3
Mixture, both ratios are for about 8: 1, and wherein described second oxynitride layer is formed by CVD techniques, its technique for adopting
Gas includes N2O/NH3Mixture and SiH2Cl2/NH3Mixture, its mixed proportion is for about 5: 1.
4. method according to claim 3, wherein forming first oxynitride layer and second oxynitride layer
By changing N2O/NH3And SiH2Cl2/NH3The mixed proportion of mixture is operated in same CVD instruments in succession.
5. method according to claim 1, wherein first oxynitride layer passes through chemical vapor deposition (CVD) technique
Formed, the process gas that it is adopted includes dichlorosilane (SiH2Cl2)/deuterated ammonia (ND3) mixture and nitrous oxide
(N2O)/ND3Mixture, both ratios are for about 8: 1, and wherein described second oxynitride layer is formed by CVD techniques, and it is adopted
Process gas includes N2O/ND3Mixture and SiH2Cl2/ND3Mixture, its mixed proportion is for about 5: 1.
6. method according to claim 5, wherein forming first oxynitride layer and second oxynitride layer
By changing N2O/ND3And SiH2Cl2/ND3The mixed proportion of mixture is operated in same CVD instruments in succession.
7. method according to claim 1, wherein the thickness of second oxynitride layer is than first oxynitride
The thickness of layer is big 1 to 5 times.
8. a kind of method, including:
Tunnel oxide is formed using low-pressure oxidized on the silicon-containing layer of substrate;And
Plurality of charge storage layers is formed on the tunnel oxide, forming the plurality of charge storage layers includes:
The first oxygen-enriched oxynitride layer is deposited on the tunnel oxide;And
The second oxynitride layer of the few oxygen of Direct precipitation and Silicon-rich on first oxynitride layer,
Oxygen of the chemical composition ratio of wherein described first oxynitride layer comprising selected high concentration, the selected high concentration
Oxygen increase described by serving as the barrier between the electric charge and the substrate that are captured in second oxynitride layer
The holding performance of plurality of charge storage layers.
9. method according to claim 8, wherein form the tunnel oxide including under low pressure and about 700
DEG C at a temperature of about 850 DEG C, in the oxidation of chemical vapor deposition (CVD) stove mesolow.
10. method according to claim 9, has about wherein forming the tunnel oxide and including being formedTo aboutThickness described in tunnel oxide.
11. methods according to claim 8, the second oxynitride layer described in further steam annealing is formed at it to reduce
The quantity of the trap near top layer.
12. methods according to claim 8, wherein the increasedd holding performance of the plurality of charge storage layers will be in electricity
The end-of-life (EOL) of the semiconductor device under specified difference between pressure programmed and erased voltage increases at least about 20
Year.
13. methods according to claim 8, also including directly on second oxynitride layer forming barrier oxidation
Layer.
14. methods according to claim 13, wherein form the barrier oxide layer to include stopping oxygen described in steam annealing
Change layer to reduce the backflow of the electric charge carrier by the barrier oxide layer.
A kind of 15. methods, including:
Tunnel oxide is formed using low-pressure oxidized on the silicon-containing layer of substrate;
Plurality of charge storage layers is formed on the tunnel oxide, forming the plurality of charge storage layers includes:
The first oxygen-enriched oxynitride layer is deposited on the tunnel oxide;
The second oxynitride layer of the few oxygen of Direct precipitation and Silicon-rich, second oxynitriding on first oxynitride layer
Nitride layer has the chemical composition ratio of first oxynitride layer, and the oxygen that it includes high concentration is captured on described to serve as
Barrier between the electric charge of two oxynitride layers and the substrate;And
Second oxynitride layer described in steam annealing is reducing the quantity of the trap being formed near its top layer;And
Directly form barrier oxide layer on second oxynitride layer.
16. methods according to claim 15, wherein form the barrier oxide layer to include stopping oxygen described in steam annealing
Change layer to reduce the backflow of the electric charge carrier by the barrier oxide layer.
17. methods according to claim 15, wherein form the tunnel oxide including under low pressure and about
At a temperature of 700 DEG C to about 850 DEG C, formed in chemical vapor deposition (CVD) stove and had aboutTo aboutThickness
The tunnel oxide.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610911402.6A CN106653761A (en) | 2009-04-10 | 2009-04-10 | Oxide-nitride-oxide stack comprising multi-layer oxynitride layer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200910134374.1A CN101859702B (en) | 2009-04-10 | 2009-04-10 | Oxidenitride oxide storehouse containing plurality of oxynitrides layers |
CN201610911402.6A CN106653761A (en) | 2009-04-10 | 2009-04-10 | Oxide-nitride-oxide stack comprising multi-layer oxynitride layer |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910134374.1A Division CN101859702B (en) | 2009-04-10 | 2009-04-10 | Oxidenitride oxide storehouse containing plurality of oxynitrides layers |
Publications (1)
Publication Number | Publication Date |
---|---|
CN106653761A true CN106653761A (en) | 2017-05-10 |
Family
ID=42945510
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910134374.1A Active CN101859702B (en) | 2009-04-10 | 2009-04-10 | Oxidenitride oxide storehouse containing plurality of oxynitrides layers |
CN201610911402.6A Pending CN106653761A (en) | 2009-04-10 | 2009-04-10 | Oxide-nitride-oxide stack comprising multi-layer oxynitride layer |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910134374.1A Active CN101859702B (en) | 2009-04-10 | 2009-04-10 | Oxidenitride oxide storehouse containing plurality of oxynitrides layers |
Country Status (1)
Country | Link |
---|---|
CN (2) | CN101859702B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109003879A (en) * | 2017-06-06 | 2018-12-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of gate dielectric layer |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8680601B2 (en) | 2007-05-25 | 2014-03-25 | Cypress Semiconductor Corporation | Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region |
US9716153B2 (en) | 2007-05-25 | 2017-07-25 | Cypress Semiconductor Corporation | Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region |
US8940645B2 (en) | 2007-05-25 | 2015-01-27 | Cypress Semiconductor Corporation | Radical oxidation process for fabricating a nonvolatile charge trap memory device |
US8633537B2 (en) | 2007-05-25 | 2014-01-21 | Cypress Semiconductor Corporation | Memory transistor with multiple charge storing layers and a high work function gate electrode |
US9449831B2 (en) | 2007-05-25 | 2016-09-20 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US20090179253A1 (en) | 2007-05-25 | 2009-07-16 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US8643124B2 (en) | 2007-05-25 | 2014-02-04 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
TWI534897B (en) * | 2011-01-14 | 2016-05-21 | 賽普拉斯半導體公司 | Oxide-nitride-oxide stack having multiple oxynitride layers |
CN102420233A (en) * | 2011-11-02 | 2012-04-18 | 上海宏力半导体制造有限公司 | Method for improving data retention of SONOS (Silicon Oxide Nitride Oxide Semiconductor) and structure of SONOS |
CN102522332B (en) * | 2011-12-22 | 2016-03-02 | 上海华虹宏力半导体制造有限公司 | ONO structure and preparation method thereof, memory and preparation method thereof |
CN103311187A (en) * | 2012-03-07 | 2013-09-18 | 宜扬科技股份有限公司 | Method for making tunneling oxidation layer of NOR flash memory |
TWI629788B (en) * | 2012-07-01 | 2018-07-11 | 賽普拉斯半導體公司 | Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region |
CN108385059B (en) * | 2018-01-17 | 2020-08-18 | 维达力实业(深圳)有限公司 | High-brightness hard decorative film and manufacturing method and application thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1783513A (en) * | 2004-10-21 | 2006-06-07 | 三星电子株式会社 | Non-volatile memory cell structure with charge trapping layers and method of fabricating the same |
US20080293254A1 (en) * | 2007-05-25 | 2008-11-27 | Cypress Semiconductor Corporation | Single-wafer process for fabricating a nonvolatile charge trap memory device |
US20080290400A1 (en) * | 2007-05-25 | 2008-11-27 | Cypress Semiconductor Corporation | SONOS ONO stack scaling |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6709928B1 (en) * | 2001-07-31 | 2004-03-23 | Cypress Semiconductor Corporation | Semiconductor device having silicon-rich layer and method of manufacturing such a device |
US7301185B2 (en) * | 2004-11-29 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage |
US7612403B2 (en) * | 2005-05-17 | 2009-11-03 | Micron Technology, Inc. | Low power non-volatile memory and gate stack |
-
2009
- 2009-04-10 CN CN200910134374.1A patent/CN101859702B/en active Active
- 2009-04-10 CN CN201610911402.6A patent/CN106653761A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1783513A (en) * | 2004-10-21 | 2006-06-07 | 三星电子株式会社 | Non-volatile memory cell structure with charge trapping layers and method of fabricating the same |
US20080293254A1 (en) * | 2007-05-25 | 2008-11-27 | Cypress Semiconductor Corporation | Single-wafer process for fabricating a nonvolatile charge trap memory device |
US20080290400A1 (en) * | 2007-05-25 | 2008-11-27 | Cypress Semiconductor Corporation | SONOS ONO stack scaling |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109003879A (en) * | 2017-06-06 | 2018-12-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of gate dielectric layer |
CN109003879B (en) * | 2017-06-06 | 2021-03-19 | 中芯国际集成电路制造(上海)有限公司 | Forming method of gate dielectric layer |
Also Published As
Publication number | Publication date |
---|---|
CN101859702A (en) | 2010-10-13 |
CN101859702B (en) | 2016-12-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106653761A (en) | Oxide-nitride-oxide stack comprising multi-layer oxynitride layer | |
US20230017648A1 (en) | Oxide-nitride-oxide stack having multiple oxynitride layers | |
US9349824B2 (en) | Oxide-nitride-oxide stack having multiple oxynitride layers | |
US10896973B2 (en) | Oxide-nitride-oxide stack having multiple oxynitride layers | |
CN100477109C (en) | Semiconductor components and manufacture method thereof | |
US8067284B1 (en) | Oxynitride bilayer formed using a precursor inducing a high charge trap density in a top layer of the bilayer | |
US7419888B2 (en) | Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same | |
CN101517714B (en) | Sonos ono stack scaling down | |
CN100552886C (en) | Nonvolatile memory and manufacture method thereof | |
US7799670B2 (en) | Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices | |
US20070048957A1 (en) | Method of manufacturing a charge-trapping dielectric and method of manufacturing a sonos-type non-volatile semiconductor device | |
CN1378703A (en) | High temperature oxide deposition method for EEPROM device | |
CN101192532B (en) | Charge trap layer and method of manufacturing the same and charge trap semiconductor memory device | |
CN103346128A (en) | Manufacturing method of ONO structure in SONO device | |
CN102376555B (en) | Method for improving reliability of SONOS (Silicon Oxide Nitride Oxide Semiconductor) by oxidizing ON film as tunneling dielectric medium | |
TWI534897B (en) | Oxide-nitride-oxide stack having multiple oxynitride layers | |
Roizin et al. | ONO structures and oxynitrides in modern microelectronics: material science, characterization and application | |
US20220005933A1 (en) | Varied silicon richness silicon nitride formation | |
CN104781916A (en) | Radical oxidation process for fabricating a nonvolatile charge trap memory device | |
KR20070014953A (en) | Method of forming a silicon rich nano-crystalline structure using atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same | |
KR20100003963A (en) | Method for fabricating silicon nitride layer and method for fabricating non-volatile memory device using the same method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20190529 Address after: Dublin, Ireland Applicant after: Longitudinal Flash Storage Solutions Co., Ltd. Address before: American California Applicant before: Cypress Semiconductor Corp. |
|
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170510 |