KR100810519B1 - Non-volatile memory cell using mechanical switch and array thereof - Google Patents

Abstract

A non-volatile memory cell using a mechanical switch and an array thereof are provided to reduce power consumption by performing an operation at a low voltage. A dielectric layer(202) is formed on a substrate(201). A gate electrode(203) is formed on the dielectric layer. A source electrode(204) is separated from one side of the gate electrode and is formed on the dielectric layer. A drain electrode(205) is separated from the other side of the gate electrode and is formed on the dielectric layer. A moving electrode includes an adhesive part(206) formed on the source electrode and a moving part(207) connected electrically to the adhesive part and extended to an upper part of the drain electrode. A protrusion part is formed at the upper part of the drain electrode.

Description

Nonvolatile Memory Cells and Arrays Using Mechanical Switches {NON-VOLATILE MEMORY CELL USING MECHANICAL SWITCH AND ARRAY THEREOF}

1 is a conceptual diagram of a conventional mechanical switch.

2 (a) to 2 (b) are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to an embodiment of the present invention.

3A to 3B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

4A to 4B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

5A to 5B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

6A to 6B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

7A to 7B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

8A to 8B are views illustrating a nonvolatile memory cell and an array using a mechanical switch according to another embodiment of the present invention.

9A to 9B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

The present invention relates to nonvolatile memory cells and arrays thereof using mechanical switches.

Until now, the degree of integration of semiconductor transistors has rapidly increased in accordance with Moore's law, which has contributed greatly to the development of the semiconductor industry. In general, semiconductor transistors have been used as switching elements using on or off characteristics and as amplifying elements using current and voltage amplification characteristics, in particular, digital integration circuits. In the field, semiconductor transistors have been mainly used as switching elements. However, such a semiconductor transistor must be fabricated on a semiconductor substrate, and therefore, the body effect of the substrate must be taken into consideration, and in particular, the biggest problem is that charges are leaked by the internal leakage current of the semiconductor transistor. Have In addition, it has a problem of soft error rate (SER) because it is sensitive to external harmful environment such as radiation, and decreases the electrical reliability and integration degree due to gate oxide degradation of semiconductor transistors, thereby increasing the sub-threshold swing. Short channel effects such as swing reduction and hot electron injection are problematic.

In order to solve such various problems as switching elements of the conventional semiconductor transistor, mechanical switches using a micro-electromechanical system (MEMS) or NEMS technology have recently been researched and developed.

1 is a conceptual diagram of a conventional mechanical switch. Referring to Figure 1, conventional mechanical switches (US Pat. No. 6,534,839 and WH Teh, et. Al., "Switching charateristics of electrostatically actuated miniaturized micromechanical metallic catilevers", J. Vac. Sci. Technol. , B. 21, pp. 2360-2367, 2003) has a switch structure composed of a gate electrode 10, a drain electrode 30, and a source electrode 20 composed of an attachment portion 21 and a moving portion 22. The operation of the mechanical switch is such that the moving part 22 of the source electrode 20 is in electrical contact with the drain electrode 30 by the electrostatic force generated by the voltage difference between the gate electrode 10 and the source electrode 20. The source electrode 20 and the drain electrode 30 are electrically connected to each other, or the source electrode 20 and the drain electrode 30 are electrically blocked because no electrostatic force is generated.

In particular, the driving by the electrostatic force of the mechanical switch is in proportion to the applied voltage difference between the source electrode 20 and the gate electrode 10, the moving part 22 of the source electrode 20 is linear to the drain electrode 30 direction. Instead of contacting the drain electrode 30 by electrical displacement, the source electrode (not referred to as a pull-in voltage, V _pi ) is more than a predetermined voltage difference between the two electrodes. The electrostatic force between the moving part 22 and the gate electrode 10 of the 20 is greater than the elastic restoring force of the moving part 22 of the source electrode 20, that is, an unstable state in which the balance between the two is broken (hereinafter, referred to as a "pulling state"). Is generated and the moving part 22 of the source electrode 20 is in electrical contact with the drain electrode 30 at an instant. That is, the pull-in voltage may be defined as a voltage difference between the source electrode 20 and the gate electrode 10 required for the electrical connection between the source electrode 20 and the drain electrode 30 of the mechanical switch. This pull-in state occurs when the moving part 22 of the source electrode 20 moves by 1/3 of the distance between the moving part 22 of the source electrode 20 and the gate electrode 10. It is similar to the role of threshold voltage of MOS transistors (HC Nathanson, et. Al., "The resonant gate transistor", IEEE Transactions on Electron Devices , Vol. ED-14, No. 3, pp. 117- 133, 1967).

Recently, in the case of configuring an array including nonvolatile memory cells using such a mechanical switch (US Pat. No. 6,509,605), the driving voltage is low and the driving speed is high, resulting in low power consumption and fast write and erase operations. In addition, since it is mechanically driven, it is being researched and developed as a next-generation memory array that replaces the existing memory array as a memory array insensitive to radiation and having no electrical reliability deterioration.

However, since such an array cannot be controlled by a mechanical switch alone, there is a problem in that a memory array must be configured in combination with a complementary MOS transistor. Therefore, the structure and the process of the array is very complicated, there is a limit to the size (scaling limit), there is a problem that the density is reduced.

SUMMARY OF THE INVENTION The present invention provides a nonvolatile memory cell and an array thereof using a mechanical switch that does not use a MOS transistor.

In addition, another technical problem to be achieved by the present invention is to improve the degree of integration of a nonvolatile memory cell and its array using a mechanical switch.

In addition, it is possible to improve the operating characteristics of the nonvolatile memory cell and its array using a mechanical switch.

Technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

A nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention for achieving the above technical problem is spaced apart from a substrate, a dielectric layer formed on the substrate, a gate electrode formed on the dielectric layer, one side of the gate electrode A source electrode formed on the dielectric layer, a drain electrode formed on the dielectric layer, spaced apart from the other side of the gate electrode, and an attachment portion formed on the source electrode and the attachment portion electrically connected to the upper portion of the drain electrode. It includes a moving electrode including an extended moving portion.

Here, a protrusion may be formed in the moving part above the drain electrode.

Here, the substrate may include a non-conductive substrate and a conductive substrate formed on the non-conductive substrate.

A trench may be formed in the substrate under the drain electrode.

The drain electrode may be formed to fill the trench.

An array including a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention includes a plurality of nonvolatile memory cells using a mechanical switch according to an embodiment of the present invention. Is electrically connected to the source electrode, and the second signal processing line is electrically connected to the gate electrode.

A nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention is a substrate, a dielectric layer formed on the substrate, a drain electrode formed on the dielectric layer, a source electrode formed on the dielectric layer spaced apart from one side of the drain electrode A moving electrode including a gate electrode formed on the dielectric layer and spaced apart from the other side of the drain electrode, an attachment portion formed on the source electrode, and a moving portion electrically connected to the attachment portion and extending to an upper portion of the gate electrode; And a protrusion formed on the moving part above the drain electrode.

Here, the substrate may include a non-conductive substrate and a conductive substrate formed on the non-conductive substrate.

A trench may be formed in the substrate under the drain electrode.

The drain electrode may be formed to fill the trench.

An array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention includes a plurality of nonvolatile memory cells using a mechanical switch according to another embodiment of the present invention. Is electrically connected to the source electrode, and the second signal processing line is electrically connected to the gate electrode.

A nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention may include a substrate, a dielectric layer formed on the substrate, a drain electrode formed on the dielectric layer, and a first electrode formed on the dielectric layer spaced apart from one side of the drain electrode. A source electrode, a second source electrode spaced apart from the other side of the drain electrode on the dielectric layer, a first gate electrode formed on the dielectric layer between the drain electrode and the first source electrode, the drain electrode and the second source electrode A second gate electrode formed on the dielectric layer and a first attachment part formed on the first source electrode, a second attachment part formed on the second source electrode, and the first attachment part and the second attachment part It includes a moving electrode including a moving unit for connecting to.

Here, the substrate may include a non-conductive substrate and a conductive substrate formed on the non-conductive substrate.

Here, a protrusion may be formed in the moving part above the drain electrode.

A trench may be formed in the substrate under the drain electrode.

The drain electrode may be formed to fill the trench.

Here, the moving part may have a disk-shaped structure.

An array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention includes a plurality of nonvolatile memory cells using a mechanical switch according to another embodiment of the present invention, wherein the movable electrode Is a first signal processing line, and the first gate electrode and the second gate electrode are second signal processing lines.

Hereinafter, with reference to the accompanying drawings will be described in detail.

2 (a) to 2 (b) are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to an embodiment of the present invention.

FIG. 2A illustrates an array including a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention, and FIG. 2B illustrates a-a in FIG. A cross section of a memory cell using a mechanical switch in the 'direction.

First, a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention will be described in detail with reference to FIG. 2B.

As shown in FIG. 2B, a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention includes a substrate 201, a dielectric layer 202, a gate electrode 203, and a source electrode 204. ), A drain electrode 205, a moving electrode 208 including an attachment part 206 and a moving part 207.

In more detail, a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention includes a dielectric layer 202 formed on a substrate 201, a gate electrode 203 formed on the dielectric layer 202, and a gate electrode. Source electrode 204 formed on dielectric layer 202 spaced apart from one side of 203 and drain electrode 205 and source electrode 205 formed on dielectric layer 202 spaced apart from the other side of gate electrode 203. And a moving electrode 208 including an attachment portion 206 formed at the top portion and a moving portion 207 electrically connected to the attachment portion 206 and extending to an upper portion of the drain electrode 205.

Here, the dielectric layer 202 formed between the substrate 201, the drain electrode 205, and the substrate 201 and the drain electrode 205 becomes a capacitor having a flat structure for storing or releasing charge.

The substrate 201 may be made of a conductive semiconductor substrate, or may be manufactured by forming a conductive semiconductor substrate on a non-conductive substrate, and grounded. When produced with a conductive semiconductor substrate, a silicon substrate can be used.

The dielectric layer 202 may be formed of an insulating film, such as a silicon oxide film or a silicon nitride film.

The drain electrode 205 may be formed of a conductive material such as copper.

An array including a plurality of nonvolatile memory cells 200 using a mechanical switch according to an exemplary embodiment of the present invention will be described with reference to FIG. 2A.

As shown in FIG. 2A, an array including a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention is a nonvolatile memory using a mechanical switch according to an embodiment of the present invention. The cell 200 includes a first signal processing line 210 and a second signal processing line 220.

Here, the first signal processing line 210 and the second signal processing line 220 are lines for processing the same signal, respectively. In an exemplary embodiment, the first signal processing line 210 becomes a bit line B / L, and the second signal processing line 220 becomes a word line W / L.

The bit line 210 and the word line 220 cross each other, and in the nonvolatile memory cell 200 using a mechanical switch according to an embodiment of the present invention, the bit line 210 and the word line 220 cross each other. It is located near the site (side). In addition, the gate electrode 203 is electrically connected to the word line 220, and the attachment portion 206 of the moving electrode 208 is electrically connected to the bit line 210.

Therefore, the array including the nonvolatile memory cell 200 using the mechanical switch according to an embodiment of the present invention operates as follows.

Due to the difference between the voltage applied to the word line 220 and the voltage applied to the bit line 210, the moving part 207 contacts the drain electrode 205 so that the voltage applied to the bit line 210 is the drain electrode ( 205). That is, the difference between the voltage applied to the gate electrode 203 electrically connected to the word line 220 and the voltage applied to the bit line 210 electrically connected to the attachment part 206 is greater than or equal to the pull-in voltage V _pi . The electrostatic force is generated in the moving portion 207 is in electrical contact with the drain electrode 205 to store or discharge charges in the dielectric layer 202 between the substrate 201 and the drain electrode 205 while performing a nonvolatile memory operation. Perform.

Therefore, the nonvolatile memory cell and its array using the mechanical switch according to an embodiment of the present invention can perform the nonvolatile memory operation without using the semiconductor MOS transistor, and do not use the semiconductor MOS transistor. This is not very complicated, and the degree of integration can be improved without scaling limits.

In addition, it can be operated at lower operating voltage than conventional flash memory, which can reduce power consumption, speed up operation, and do not deteriorate electrical reliability such as destruction of gate insulating film, and military or satellite which is not sensitive to external harmful environment such as radiation. Can be used as

Here, as illustrated in FIG. 2B, a dimple serving as the protrusion 209 may be further formed on the moving part 207 on the drain electrode 205. Since the dimples as the protrusions 209 are further formed, not only the stiction during the mechanical switch manufacturing process but also the pull-in voltage V _pi may be lowered.

3A to 3B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

Figure 3 (a) is a view showing an array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention, Figure 3 (b) is a b-b in Figure 3 (a) A cross section of a memory cell using a mechanical switch in the 'direction.

First, a nonvolatile memory cell using a mechanical switch according to another exemplary embodiment of the present invention will be described in detail with reference to FIG. 3B.

As shown in FIG. 3B, in the nonvolatile memory cell using a mechanical switch according to another exemplary embodiment, trenches are formed in the substrate 301 under the drain electrode 305. Here, one or more trenches may be formed.

This configuration is different from the capacitor having a flat plate structure composed of the substrate 201, the dielectric layer 202, and the drain electrode 205 shown in Fig. 2B, and the substrate 301, the dielectric layer 302, and the drain electrode 305. Has a trench structure capacitor Due to the configuration features of the capacitor having such a trench structure, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention has a capacitance higher than that of the capacitor of the flat plate structure shown in FIG. It can have a can improve the operation characteristics of the nonvolatile memory.

The rest of the configuration is the same as a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention shown in FIG.

Next, as shown in (a) of FIG. 3, an array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention is a non-mechanical switch using a mechanical switch according to another embodiment of the present invention. The volatile memory cell 300 includes a first signal processing line 310 and a second signal processing line 320. Here, as shown in FIG. 2A, the gate electrode 305 is electrically connected to the word line, which is the second signal processing line 320, and the attachment part 306 is the first signal processing line 310. It is electrically connected to the bit line.

4A to 4B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

Figure 4 (a) is a view showing an array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention, Figure 4 (b) is a c- in Figure 4 (a) It is sectional drawing of the memory cell using a mechanical switch to c 'direction.

First, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention will be described in detail with reference to FIG. 4B.

As shown in FIG. 4B, in the nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention, trenches are formed in the substrate 401 under the drain electrode 405, and trenches are formed. The drain electrode 405 is formed to be buried. Here, one or more trenches may be formed.

This configuration is different from that of the capacitor having a flat structure composed of the substrate 201, the dielectric layer 202 and the drain electrode 205 shown in Fig. 2B, and the substrate 401, the dielectric layer 402 and the drain electrode ( 405 has a trench structure capacitor. Due to the configuration features of the capacitor having such a trench structure, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention is higher than the capacitance of the capacitor of the flat plate structure shown in FIG. Capacitance can be used to improve nonvolatile memory characteristics.

The rest of the configuration is the same as a nonvolatile memory cell using a mechanical switch according to an embodiment of the present invention shown in FIG.

Next, as shown in (a) of FIG. 4, an array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention is a mechanical switch according to another embodiment of the present invention. The nonvolatile memory cell 400, the first signal processing line 410, and the second signal processing line 420 may be used. Here, too, as shown in FIG. 2A, the gate electrode 405 is electrically connected to the word line, which is the second signal processing line 420, and the attachment part 406 is the first signal processing line 410. It is electrically connected to the bit line.

5A to 5B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

FIG. 5A is a view showing an array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention, and FIG. 5B is a line d- in FIG. Sectional drawing of a memory cell using a mechanical switch in the d 'direction.

First, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention will be described in detail with reference to FIG. 5B.

As shown in FIG. 5B, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention may include a substrate 501, a dielectric layer 502, a drain electrode 505, and a source electrode ( 504, a gate electrode 503, a moving electrode 508 including an attachment part 506 and a moving part 507, and a protrusion 509.

In more detail, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention includes a dielectric layer 502 formed on a substrate 501, a drain electrode 505 formed on the dielectric layer 502, and a drain. The source electrode 504 formed on the dielectric layer 502 and spaced apart from one side of the electrode 505, the gate electrode 503 and the source electrode 504 formed on the dielectric layer 502 spaced apart from the other side of the drain electrode 505. The upper portion of the movable electrode 508 and the drain electrode 503 including an attachment portion 506 formed on the upper portion and a movable portion 507 electrically connected to the attachment portion 506 and extending to an upper portion of the gate electrode 503. And a protrusion 509 formed on the moving part 507.

Here, the substrate 501, the drain electrode 505, and the dielectric layer 502 formed between the substrate 501 and the drain electrode 505 become a capacitor having a flat structure that stores or emits electric charges.

The substrate 501 may be made of a conductive semiconductor substrate, or may be manufactured by forming a conductive semiconductor substrate on a non-conductive substrate, and grounded. When produced with a conductive semiconductor substrate, a silicon substrate can be used.

The dielectric layer 502 may be formed of an insulating film such as a silicon oxide film or a silicon nitride film.

The drain electrode 505 may be formed of a conductive material such as copper.

An array including a plurality of nonvolatile memory cells using a mechanical switch according to another embodiment of the present invention will be described with reference to FIG.

As shown in (a) of FIG. 5, an array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention is a non-mechanical switch using a mechanical switch according to another embodiment of the present invention. The volatile memory cell 500 includes a volatile memory cell 500, a first signal processing line 510, and a second signal processing line 520.

Here, the first signal processing line 510 and the second signal processing line 520 are lines for processing the same signal, respectively. In another embodiment of the present invention, the first signal processing line 510 becomes a bit line B / L, and the second signal processing line 520 becomes a word line W / L.

The bit line 510 and the word line 520 cross each other, and the nonvolatile memory cell 500 using the mechanical switch according to another embodiment of the present invention may include the bit line 510 and the word line 520. It is located near (side) the intersection. In addition, the gate electrode 503 is electrically connected to the word line 520, and the attachment portion 506 of the moving electrode 508 is electrically connected to the bit line 510.

The array including the nonvolatile memory cell 500 using the mechanical switch according to another embodiment of the present invention operates as follows.

Due to the difference between the voltage applied to the word line 520 and the voltage applied to the bit line 510, the protrusion 509 formed in the moving part 507 contacts the drain electrode 505 and is applied to the bit line 510. The voltage is transferred to the drain electrode 505. That is, the difference between the voltage applied to the gate electrode 505 electrically connected to the word line 520 and the voltage applied to the bit line 510 electrically connected to the attachment part 506 is greater than or equal to the pull-in voltage V _pi . The electrostatic force is generated in the protrusion 509 of the moving part 507 is in electrical contact with the drain electrode 505 to store or discharge charge in the dielectric layer 502 between the substrate 501 and the drain electrode 505 Perform volatile memory operations. Here, the moving part 507 of the moving electrode 508 is not electrically connected to the gate electrode 503 by the protrusion 509.

Therefore, the nonvolatile memory cell and the array using the mechanical switch according to another embodiment of the present invention can perform the nonvolatile memory operation without using the semiconductor MOS transistor, and since the semiconductor MOS transistor is not used, The process is not very complex and the density can be improved without scaling limits.

In addition, it can be operated at lower operating voltage than conventional flash memory, which can reduce power consumption, speed up operation, and do not deteriorate electrical reliability such as gate insulating film destruction, and military or satellite which is not sensitive to external harmful environment such as radiation. Can be used as

6A to 6B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

FIG. 6A is a view showing an array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention, and FIG. 6B is an e-number in FIG. A cross section of a memory cell using a mechanical switch in the e 'direction.

First, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention will be described in detail with reference to FIG. 6B.

As shown in FIG. 6B, in the nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention, trenches are formed in the substrate 601 under the drain electrode 605, and trenches A drain electrode 605 is formed to be buried. Here, one or more trenches may be formed.

This configuration is different from that of the capacitor having a flat structure composed of the substrate 501, the dielectric layer 502, and the drain electrode 505 shown in Fig. 5B, and the substrate 601, the dielectric layer 602 and the drain electrode ( 605 has a trench structure capacitor. Due to the configuration of the capacitor having such a trench structure, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention shown in FIG. 6B is shown in FIG. 5B. It is possible to have a higher capacitance than that of a plate capacitor, thereby improving nonvolatile memory characteristics.

The rest of the configuration is the same as that of the nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention shown in FIG.

Next, as shown in (a) of FIG. 6, an array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention is a mechanical switch according to another embodiment of the present invention. The nonvolatile memory cell 600, the first signal processing line 610, and the second signal processing line 620 are included. Here, too, as shown in FIG. 5A, the gate electrode 605 is electrically connected to the word line, which is the second signal processing line 620, and the attaching part 606 is the first signal processing line 610. It is electrically connected to the bit line.

7A to 7B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

FIG. 7A is a view showing an array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention, and FIG. 7B is a cross-sectional view taken along the line f- in FIG. A cross section of a memory cell using a mechanical switch in the f 'direction.

First, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention will be described in detail with reference to FIG. 7B.

As shown in FIG. 7B, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention may include a substrate 701, a dielectric layer 702, a drain electrode 705, and a first source. The electrode 704a, the second source electrode 704b, the first gate electrode 703a, the second gate electrode 703b and the first attaching portion 706a, the second attaching portion 706b and the moving portion 707 It includes a moving electrode 708 including a.

In more detail, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention includes a dielectric layer 702 formed on a substrate 701, a drain electrode 705 formed on the dielectric layer 702, and a drain. The first source electrode 704a formed on the dielectric layer 702 spaced apart from one side of the electrode 705, the second source electrode 704b formed on the dielectric layer 702 spaced apart from the other side of the drain electrode 705, and the drain electrode. A first gate electrode 703a formed on the dielectric layer 702 between 705 and the first source electrode 704a and a dielectric layer 702 formed between the drain electrode 705 and the second source electrode 704b. First attachment portion 706a formed on the second gate electrode 703b and the first source electrode 704a, second attachment portion 706b and the first attachment portion 706a formed on the second source electrode 704b. ) And a moving electrode 708 including a moving part 707 for electrically connecting the second attachment part 706b.

Here, as shown in FIG. 7B, a trench of the substrate 701 under the drain electrode 705 may be formed, and a drain electrode 705 may be formed to fill the trench. By forming in this way, the capacitance of the capacitor composed of the substrate 701, the dielectric layer 702, and the drain electrode 705 can be higher than that of the capacitor of the flat plate structure.

The substrate 701 may be made of a conductive semiconductor substrate, or may be manufactured by forming a conductive semiconductor substrate on a non-conductive substrate, and grounded. When produced with a conductive semiconductor substrate, a silicon substrate can be used.

The dielectric layer 702 may be formed of an insulating film such as a silicon oxide film or a silicon nitride film.

The drain electrode 705 may be formed of a conductive material such as copper.

An array including a plurality of nonvolatile memory cells using a mechanical switch according to another embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 7A, an array including a nonvolatile memory cell using a mechanical switch according to another exemplary embodiment of the present invention may include a non-mechanical switch using a mechanical switch according to another exemplary embodiment of the present disclosure. The volatile memory cell 700 includes a volatile memory cell 700, a first signal processing line 710, and a second signal processing line 720. Here, the first signal processing line 710 and the second signal processing line 720 are lines for processing the same signal, respectively. In another embodiment of the present invention, the first signal processing line 710 becomes a bit line B / L, and the second signal processing line 720 becomes a word line W / L.

The array including the nonvolatile memory cell 700 using the mechanical switch according to another embodiment of the present invention is the first attachment portion 706a, the second attachment portion 706b in FIG. And the moving unit 707 itself constitutes the bit line 710 to have a fixed beam (bridge type) structure. The first gate electrode 703a and the second gate electrode 703b are electrically connected to the word line 720.

The array including the nonvolatile memory cell 700 using the mechanical switch according to another embodiment of the present invention operates as follows.

Due to the difference between the voltage applied to the word line 720 and the voltage applied to the bit line 710, the moving part 707 contacts the drain electrode 205 so that the voltage applied to the bit line 710 is the drain electrode ( 705). That is, a voltage applied to the first gate electrode 703a and the second gate electrode 703b electrically connected to the word line 720 and the first attaching portion 706a and the second attaching portion 706b. When the difference between the voltages applied to the bit lines 710 is greater than the pull-in voltage (V _pi ), an electrostatic force is generated so that the moving part 707 electrically contacts the drain electrode 705 to transfer charges to the substrate 701. A nonvolatile memory operation is performed while storing or emitting in the dielectric layer 702 between the electrodes 705.

Therefore, the nonvolatile memory cell and the array using the mechanical switch according to another embodiment of the present invention can perform the nonvolatile memory operation without using the semiconductor MOS transistor, and since the semiconductor MOS transistor is not used, The process is not very complex and the density can be improved without scaling limits.

In addition, it can be operated at lower operating voltage than conventional flash memory, which can reduce power consumption, speed up operation, and do not deteriorate electrical reliability such as gate insulating film destruction, and military or satellite which is not sensitive to external harmful environment such as radiation. Can be used as

Here, as illustrated in FIG. 7B, a dimple, which is a protrusion 709, may be further formed on the moving part 707 on the drain electrode 705. Since the dimples as the protrusions 709 are further formed, not only the stiction during the mechanical switch manufacturing process but also the effect of lowering the pull-in voltage V _pi is provided.

8A to 8B are views illustrating a nonvolatile memory cell and an array using a mechanical switch according to another embodiment of the present invention.

FIG. 8A is a view showing an array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention, and FIG. 8B is a g- diagram in FIG. 8A. A cross section of a memory cell using mechanical switches in the g 'and h-h' directions.

As shown in FIG. 8B, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention may include a bit line having a fixed beam (bridge) structure of FIG. 7B. Everything is the same except that 710 is replaced with a bitline 810 of a disk-like structure.

9A to 9B are diagrams illustrating a nonvolatile memory cell and an array using a mechanical switch according to another exemplary embodiment of the present invention.

FIG. 9A is a view showing an array including a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention, and FIG. 9B is a line i- in FIG. 9A. A cross section of a memory cell using mechanical switches in the i 'and j-j' directions.

First, as shown in FIG. 9B, a memory cell 900 using a mechanical switch according to another embodiment of the present invention is a trench-type capacitor in FIG. 7B. Has However, in this case, the drain electrode 905 is formed of a conductive material such as copper, which does not require a planarization process without filling the trench formed in the substrate 901. Here, one or more trenches may be formed.

As described above, a nonvolatile memory cell using a mechanical switch according to another embodiment of the present invention illustrated in FIG. 9B is illustrated in FIG. 7B except that only the structure of the drain electrode 905 is changed. It is the same as the nonvolatile memory cell using the mechanical switch shown.

This structure can increase the capacitance higher than that of a planar capacitor, thereby improving memory characteristics.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the above-described technical configuration of the present invention may be embodied in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced.

Therefore, since the embodiments described above are provided to completely inform the scope of the invention to those skilled in the art, it should be understood that they are exemplary in all respects and not limiting. The invention is only defined by the scope of the claims.

As described in detail above, the present invention provides a nonvolatile memory cell using a mechanical switch that does not use a semiconductor MOS transistor and an array thereof.

In addition, the present invention provides a non-volatile memory cell and its array using a mechanical switch with improved integration.

In addition, the present invention provides a nonvolatile memory cell and its array using a mechanical switch that can further improve the operation characteristics of the nonvolatile memory by changing the structure of the capacitor and the structure of the mechanical switch.

In addition, the present invention can be operated at a lower operating voltage than conventional flash memory to reduce the power consumption, the operation speed is high, there is no electrical reliability degradation such as gate insulating film breakdown, and military is not sensitive to external harmful environment such as radiation Another aspect of the present invention is to provide a nonvolatile memory cell and an array thereof using mechanical switches for satellites.

In addition, the present invention provides a non-volatile memory cell using a mechanical switch and an array thereof that can form a conductive substrate on any substrate instead of a semiconductor substrate and can be integrated regardless of the type of substrate.

Claims (18)

Board; A dielectric layer formed on the substrate; A gate electrode formed on the dielectric layer; A source electrode spaced apart from one side of the gate electrode and formed on the dielectric layer; A drain electrode spaced apart from the other side of the gate electrode and formed on the dielectric layer; And A moving electrode including an attachment portion formed on the source electrode and a moving portion electrically connected to the attachment portion and extending to an upper portion of the drain electrode; Non-volatile memory cell using a mechanical switch, including. The method of claim 1, A nonvolatile memory cell using a mechanical switch having a protrusion formed on the moving part above the drain electrode. The method of claim 1, The substrate is Non-conductive substrates; And A conductive substrate formed on the non-conductive substrate Non-volatile memory cell using a mechanical switch, including. The method of claim 1, And a trench formed in the substrate under the drain electrode. The method of claim 4, wherein The drain electrode, And a mechanical switch formed to fill the trench. The apparatus of claim 1, further comprising a plurality of nonvolatile memory cells using a mechanical switch according to claim 1, wherein a first signal processing line is electrically connected to the source electrode, and a second signal processing line is electrically connected to the gate electrode. Memory array using traditional switches. Board; A dielectric layer formed on the substrate; A drain electrode formed on the dielectric layer; A source electrode spaced apart from one side of the drain electrode and formed on the dielectric layer; A gate electrode spaced apart from the other side of the drain electrode and formed on the dielectric layer; A moving electrode including an attachment portion formed on the source electrode and a moving portion electrically connected to the attachment portion and extending to an upper portion of the gate electrode; And Protruding portion formed on the moving portion above the drain electrode Non-volatile memory cell using a mechanical switch, including. The method of claim 7, wherein The substrate is Non-conductive substrates; And A conductive substrate formed on the non-conductive substrate Non-volatile memory cell using a mechanical switch, including. The method of claim 7, wherein And a trench formed in the substrate under the drain electrode. The method of claim 9, The drain electrode, And a mechanical switch formed to fill the trench. A mechanical device comprising a plurality of nonvolatile memory cells using a mechanical switch according to claim 7, wherein a first signal processing line is electrically connected to the source electrode, and a second signal processing line is electrically connected to the gate electrode. Memory array using traditional switches. Board; A dielectric layer formed on the substrate; A drain electrode formed on the dielectric layer; A first source electrode spaced apart from one side of the drain electrode and formed on the dielectric layer; A second source electrode spaced apart from the other side of the drain electrode and formed on the dielectric layer; A first gate electrode formed on the dielectric layer between the drain electrode and the first source electrode; A second gate electrode formed on the dielectric layer between the drain electrode and the second source electrode; And A moving electrode including a first attaching part formed on the first source electrode, a second attaching part formed on the second source electrode, and a moving part electrically connecting the first attaching part and the second attaching part; Non-volatile memory cell using a mechanical switch, including. The method of claim 12, The substrate is Non-conductive substrates; And A conductive substrate formed on the non-conductive substrate Non-volatile memory cell using a mechanical switch, including. The method of claim 12, A nonvolatile memory cell using a mechanical switch having a protrusion formed on the moving part above the drain electrode. The method of claim 12, And a trench formed in the substrate under the drain electrode. The method of claim 12, The drain electrode, And a mechanical switch formed to fill the trench. The method of claim 12, The moving unit, A nonvolatile memory cell using a mechanical switch that has a disk structure. A plurality of nonvolatile memory cells using the mechanical switch of claim 12, wherein the moving electrode is a first signal processing line, the first gate electrode and the second gate electrode is a second signal processing line, Non-volatile memory array using mechanical switch.

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