JP5142550B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP5142550B2
JP5142550B2 JP2007041683A JP2007041683A JP5142550B2 JP 5142550 B2 JP5142550 B2 JP 5142550B2 JP 2007041683 A JP2007041683 A JP 2007041683A JP 2007041683 A JP2007041683 A JP 2007041683A JP 5142550 B2 JP5142550 B2 JP 5142550B2
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Japan
Prior art keywords
layer
semiconductor
thin film
semiconductor layer
film transistor
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP2007041683A
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English (en)
Japanese (ja)
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JP2008205330A (ja
JP2008205330A5 (enExample
Inventor
舜平 山崎
郁子 川俣
康行 荒井
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2007041683A priority Critical patent/JP5142550B2/ja
Publication of JP2008205330A publication Critical patent/JP2008205330A/ja
Publication of JP2008205330A5 publication Critical patent/JP2008205330A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/427—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer having different thicknesses of the semiconductor bodies in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

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  • Non-Volatile Memory (AREA)
  • Thin Film Transistor (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
JP2007041683A 2007-02-22 2007-02-22 半導体装置の作製方法 Expired - Fee Related JP5142550B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007041683A JP5142550B2 (ja) 2007-02-22 2007-02-22 半導体装置の作製方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007041683A JP5142550B2 (ja) 2007-02-22 2007-02-22 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2008205330A JP2008205330A (ja) 2008-09-04
JP2008205330A5 JP2008205330A5 (enExample) 2010-04-02
JP5142550B2 true JP5142550B2 (ja) 2013-02-13

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Family Applications (1)

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JP2007041683A Expired - Fee Related JP5142550B2 (ja) 2007-02-22 2007-02-22 半導体装置の作製方法

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JP (1) JP5142550B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010087392A1 (ja) 2009-01-30 2010-08-05 日鉱金属株式会社 バリア機能を有する金属元素と触媒能を有する金属元素との合金膜を有する基板
WO2011111290A1 (ja) * 2010-03-10 2011-09-15 パナソニック株式会社 不揮発性半導体記憶装置
US9490179B2 (en) 2010-05-21 2016-11-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and semiconductor device
KR101233348B1 (ko) * 2010-06-09 2013-02-14 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
CN102473737B (zh) 2010-06-22 2014-07-23 松下电器产业株式会社 发光显示装置及其制造方法
KR102298336B1 (ko) * 2014-06-20 2021-09-08 엘지디스플레이 주식회사 유기발광다이오드 표시장치
JP6407651B2 (ja) * 2014-10-01 2018-10-17 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN115206994A (zh) * 2021-04-09 2022-10-18 株式会社日本显示器 显示装置
CN115881798A (zh) * 2023-01-29 2023-03-31 合肥新晶集成电路有限公司 半导体结构及其制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03129777A (ja) * 1989-07-13 1991-06-03 Mitsubishi Electric Corp 電界効果型トランジスタを備えた半導体装置およびその製造方法
JPH09135030A (ja) * 1995-11-08 1997-05-20 Hitachi Ltd 半導体集積回路装置およびそれを用いたコンピュータシステム、ならびに半導体集積回路装置の製造方法
JPH11163367A (ja) * 1997-09-25 1999-06-18 Toshiba Corp 薄膜トランジスタ及びその製造方法
JP4823408B2 (ja) * 2000-06-08 2011-11-24 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
JP4050663B2 (ja) * 2003-06-23 2008-02-20 株式会社東芝 半導体装置およびその製造方法
JP2006032921A (ja) * 2004-06-14 2006-02-02 Semiconductor Energy Lab Co Ltd 半導体装置、及びそれらの作製方法

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JP2008205330A (ja) 2008-09-04

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