JP5109444B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a plurality of types of transistors are mixedly mounted.

  For example, in a manufacturing process of a semiconductor device in which a plurality of types of MOS transistors are mixedly mounted, well injection or channel injection corresponding to the type of the transistor is performed for each type of transistor. For this reason, a resist pattern is formed for each type of transistor, ion implantation is performed using the resist pattern as a mask, and then the resist pattern is peeled off. Through the manufacturing process as described above, when the number of types of transistors increases, the number of resist pattern peeling increases. For removing the resist pattern, a chemical solution such as a mixed solution of sulfuric acid and hydrogen peroxide solution (hereinafter referred to as sulfuric acid / hydrogen peroxide) or a mixed solution of ammonia and hydrogen peroxide solution (hereinafter referred to as ammonia / hydrogen peroxide solution) is used. Is done. A chemical solution such as sulfuric acid / hydrogen peroxide etches an oxide film (hereinafter referred to as “embedded oxide film”) that defines an element region. Therefore, as the number of resist pattern peeling increases, the buried oxide film gradually recedes. In addition, since the etching rate of the buried oxide film varies depending on the type of ions implanted, the height of the buried oxide film may vary from region to region of the semiconductor substrate.

  As a method of manufacturing a semiconductor device that protects a buried oxide film from a chemical solution, a method is known in which a silicon nitride film is formed on the buried oxide film, ion implantation is performed using a photoresist as a mask, and then the photoresist is peeled off by a chemical solution. (For example, refer to Patent Document 1 below).

FIG. 33 is a schematic diagram of a method of manufacturing a semiconductor device in the cited document 1, in which symbol a is an element region, symbol b is a buried oxide film and symbol c is a silicon nitride film. As shown in FIG. 33, since the buried oxide film b that defines the element region a is covered with the silicon nitride film c, even if a chemical solution is used for stripping the photoresist, it is affected by, for example, receding. There is no.
JP-A-2005-116907

  Incidentally, the semiconductor device manufacturing method disclosed in the cited document 1 prevents the formation of a groove at the end of the buried oxide film b when the photoresist is peeled off by a chemical solution. Therefore, as shown in FIG. 33, the silicon nitride film c covers the side surface of the buried oxide film b and further extends to the surface of the element region a. Therefore, when ions are implanted into the element region a, the ion concentration varies between a portion where the silicon nitride film c exists and a portion where the silicon nitride film c does not exist in the element region a.

  Therefore, the present invention provides a method of manufacturing a semiconductor device that can make the height of the buried oxide film after well implantation and channel implantation uniform without causing variations in the ion concentration of each element region.

According to one aspect of the present invention, a step of forming a trench in a semiconductor substrate to define first and second element regions, a step of embedding a first oxide film in the trench, Forming a film covering the entire first and second element regions and the first oxide film on the second element region and the first oxide film; and Forming a first resist pattern exposing the first region including the element region and the first region including a portion of the first oxide film, and using the first resist pattern as a mask, the entire first element region Injecting a first impurity through the film covering the substrate, supplying a first chemical after injecting the first impurity, removing the first resist pattern, and on the film Includes a part of the second element region and the first oxide film. Forming a second resist pattern exposing the second region, and implanting a second impurity through the film covering the entire second element region using the second resist pattern as a mask; , After injecting the second impurity, supplying a first chemical solution to remove the second resist pattern, and after removing the first resist pattern and the second resist pattern, by supplying a second liquid chemical, saw including a step of removing the film, after the injection of the first impurity, and, prior to removal of the film, said first element region of said film And a step of selectively thinning or removing only a portion corresponding to the step of etching, and a step of implanting a third impurity into the first element region after selectively thinning or removing the film. Equipment manufacturing A method is provided.
According to one aspect of the present invention, a step of forming a trench in a semiconductor substrate to define first and second element regions, a step of embedding a first oxide film in the trench, Forming a film covering the entire first and second element regions and the first oxide film on the second element region and the first oxide film; and Forming a first resist pattern exposing the first region including the element region and the first region including a portion of the first oxide film, and using the first resist pattern as a mask, the entire first element region Injecting a first impurity through the film covering the substrate, supplying a first chemical after injecting the first impurity, removing the first resist pattern, and on the film Includes a part of the second element region and the first oxide film. Forming a second resist pattern exposing the second region, and implanting a second impurity through the film covering the entire second element region using the second resist pattern as a mask; , After injecting the second impurity, supplying a first chemical solution to remove the second resist pattern, and after removing the first resist pattern and the second resist pattern, Supplying a second chemical solution and removing the film, and before implanting the first impurity and the second impurity, corresponding to the first and second element regions of the film A method for manufacturing a semiconductor device is provided in which the entire portion to be formed is thinned by etching.

  According to the present invention, the height of the buried oxide film after well implantation and channel implantation can be made uniform without causing variations in the ion concentration of each element region.

Hereinafter, the first and second embodiments will be described in detail with reference to the drawings.
(First embodiment)
[Manufacturing method in this embodiment]
1 to 23 are explanatory diagrams of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 1 to 23, the left side of the broken line is the first region R1 where the first transistor is formed, and the right side of the broken line is formed of the second transistor of a different type from the first transistor. This is the second region R2. In the present embodiment, the first transistor is an n-MOS transistor, and the second transistor is a p-MOS transistor.

  As shown in FIG. 1, first, an oxide film 2 is formed on a silicon substrate 1 by a thermal oxidation method. The thickness of the oxide film is, for example, 10 nm. Subsequently, a silicon nitride film 3 is formed on the oxide film 2 by, for example, CVD (Chemical Vapor Deposition). The film thickness of the silicon nitride film 3 is, for example, 80 nm to 100 nm. Then, a resist pattern is formed on the silicon nitride film 3 by photolithography, and the silicon nitride film 3 and the oxide film 2 are etched using the resist pattern as a mask.

  Next, as shown in FIG. 2, the silicon substrate 1 is etched by RIE (Reactive Ion Etching) using the silicon nitride film 3 as a mask. Thus, a silicon trench 1T is formed in the silicon substrate 1. The silicon trench 1T defines a plurality of element regions 1A and 1B in the silicon substrate 1. The element regions 1A and 1B are active regions where various transistors are formed. The depth of the silicon trench 1T is, for example, 200 nm to 350 nm. If necessary, an oxide film 4 may be formed on the inner surface of the silicon trench 1T by thermal oxidation as shown in FIG. The film thickness of the oxide film 4 is about 5 nm, for example.

  Next, as shown in FIG. 4, an oxide film 5 is deposited on the silicon trench 1T and the silicon nitride film 3, for example, by HDP-CVD (High Density Plasma Chemical Vapor Deposition). Thus, the oxide film 5 is embedded in the silicon trench 1T.

  Next, as shown in FIG. 5, the oxide film 5 is polished by CMP (Chemical Mechanical Polishing). In the present embodiment, using the silicon nitride film 3 as a stopper film, the oxide film 5 is polished until the thickness of the silicon nitride film 3 becomes, for example, 60 nm.

Next, as shown in FIG. 6, for example, a chemical solution such as phosphoric acid (H ₃ PO ₄ ) is supplied, and the silicon nitride film 3 is removed by wet etching. By removing the silicon nitride film 3, the oxide film 5 becomes higher than the element regions 1A and 1B. Subsequently, a chemical solution such as hydrofluoric acid (HF) is supplied, and the oxide film 2 is removed by wet etching. Then, an oxide film 7 is formed on the surface of the element regions 1A and 1B of the silicon substrate 1 by a thermal oxidation method. The oxide film 7 formed by the thermal oxidation method has a denser structure than the oxide film 5 formed by HDP-CVD. The film thickness of the oxide film 7 is, for example, 10 nm to 20 nm.

Next, as shown in FIG. 7, dichlorosilane gas (SiH ₂ Cl ₂ ) is supplied at a flow rate of 40 sccm and ammonia gas (NH ₃ ) at a flow rate of 100 sccm to 200 sccm, the pressure is 50 Pa, and the temperature is 700 ° C. to 800 ° C. A silicon nitride film (Si ₃ N ₄ ) 8 is formed on the oxide film 5 and the oxide film 7 by, for example, thermal CVD. The silicon nitride film 8 is more resistant to chemicals such as sulfuric acid / water and ammonia water than the first and second resist patterns P1 and P2 (described later). The thickness of the silicon nitride film 8 is, for example, 10 nm to 50 nm, but may be determined in consideration of the acceleration voltage in well implantation and channel implantation and the ion transmittance with respect to the silicon nitride film 8. If necessary, only the portions corresponding to the element regions 1A and 1B may be selectively thinned. For example, by forming a resist pattern on the silicon nitride film 8 and performing etching using the resist pattern as a mask, only portions corresponding to the element regions 1A and 1B can be selectively thinned. In the present embodiment, the silicon nitride film 8 is formed, but the present invention is not limited to this. For example, a polysilicon film or the like may be used as long as it has higher resistance to a chemical solution such as sulfuric acid / hydrogen peroxide than the first and second resist patterns P1 and P2.

  Next, as shown in FIG. 8, a first resist pattern P1 is formed on the silicon nitride film 8 by photolithography. The first resist pattern P1 exposes the first region R1 in which the n-MOS transistor is formed and covers the second region R2 in which the p-MOS transistor is formed. Then, using the first resist pattern P1 as a mask, well implantation and channel implantation are sequentially performed in the element region 1A formed in the first region R1. At this time, since the element region 1A formed in the first region R1 is entirely covered with the silicon nitride film 8, the ion concentration in the element region 1A can be made uniform. That is, the variation in the ion concentration in the element region 1A due to the presence or absence of the silicon nitride film 8 as in the cited document 1 can be prevented.

In this embodiment, for example, boron ions (B) are implanted as wells at a dose of 1.0 × 10 ¹³ cm ^{−2 to} 1.0 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 150 kev to 300 kev. Ion implantation. Subsequently, as channel implantation, for example, boron ions (B) are implanted at a dose of 1.0 × 10 ¹² cm ^{−2 to} 1.0 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 40 kev to 100 kev.

  Next, as shown in FIG. 9, a chemical solution such as sulfuric acid / hydrogen peroxide is supplied, and the first resist pattern P1 is removed by wet etching. At this time, the oxide film 5 formed in the first and second regions R1 and R2 is protected by the silicon nitride film 8 having higher resistance to sulfuric acid / hydrogen peroxide than the first resist pattern P1. For this reason, even if the first resist pattern P1 is removed, the oxide film 5 formed in the first and second regions R1 and R2 does not recede. In addition, it is not limited to chemical | medical solutions, such as sulfuric acid hydrogen peroxide, For example, you may use ammonia hydrogen peroxide. Then, a second resist pattern P2 is formed on the silicon nitride film 8 by photolithography. The second resist pattern P2 covers the first region R1 where the n-MOS transistor is formed and exposes the second region R2 where the p-MOS transistor is formed. Then, using the second resist pattern P2 as a mask, well implantation and channel implantation are sequentially performed in the element region 1B formed in the second region R2. At this time, since the entire element region 1B formed in the second region R2 is covered with the silicon nitride film 8, the ion concentration in the element region 1B can be made uniform. That is, the variation in the ion concentration in the element region 1B due to the presence or absence of the silicon nitride film 8 as in the cited document 1 can be prevented.

In the present embodiment, as well implantation, phosphorus ions (P) are implanted at a dose of 1.0 × 10 ¹³ cm ^{−2 to} 1.0 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 200 kev to 700 kev. . Subsequently, arsenic ions (As) are implanted at a dose of 1.0 × 10 ¹² cm ^{−2 to} 1.0 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 50 kev to 150 kev as channel implantation.

  Next, as shown in FIG. 10, a chemical solution such as sulfuric acid / hydrogen peroxide is supplied, and the second resist pattern P2 is removed by wet etching. At this time, the oxide film 5 formed in the first and second regions R1 and R2 is protected by the silicon nitride film 8 having higher resistance to sulfuric acid / hydrogen peroxide than the second resist pattern P2. For this reason, even if the second resist pattern P2 is peeled off, the oxide film 5 formed in the first and second regions R1 and R2 does not recede. In addition, it is not limited to chemical | medical solutions, such as sulfuric acid hydrogen peroxide, For example, you may use ammonia hydrogen peroxide.

  Next, as shown in FIG. 11, for example, a chemical solution such as phosphoric acid is supplied, and the silicon nitride film 8 is removed by wet etching. At this time, the element regions 1A and 1B are covered with the oxide film 7 and are not exposed to a chemical solution such as phosphoric acid.

  Next, as shown in FIG. 12, a chemical solution such as hydrofluoric acid is supplied, and the oxide film 7 is removed by wet etching. At this time, the oxide film 5 formed in the first and second regions R1 and R2 recedes by the wet etching. As described above, in this embodiment, the oxide film 5 is retracted only once when the oxide film 7 is removed, so that variation in the height of the oxide film 5 can be suppressed.

Next, as shown in FIG. 13, hydrogen (H ₂ ) is supplied at a flow rate of 10 sccm to 50 sccm and oxygen (O ₂ ) at a flow rate of 20 sccm to 100 sccm, the pressure is set to 10 Pa to 50 Pa, and the temperature is set to 700 ° C. to 800 ° C. A silicon oxide film 9 is formed on the surface of the element regions 1A and 1B by thermal CVD. The film thickness of the silicon oxide film 9 is, for example, 1 nm. Subsequently, silane gas (SiH ₄ ) is supplied at a flow rate of 50 sccm to 100 sccm, a pressure is set to 10 Pa to 50 Pa, a temperature is set to 500 ° C. to 600 ° C., and polysilicon is formed on the oxide film 5 and the silicon oxide film 9 by thermal CVD. A film 10 is formed. The thickness of the polysilicon film 10 is, for example, 100 nm to 150 nm.

  Next, as shown in FIG. 14, the antireflection film 11 and the photoresist film 12 are sequentially applied to the surface of the polysilicon film 10 by, for example, spin coating. Subsequently, the photoresist film 12 is patterned by a photolithography method to form a resist pattern 12 a on the surface of the antireflection film 11.

  Next, as shown in FIG. 15, the antireflection film 11, the polysilicon film 10, and the silicon oxide film 9 are etched using the resist pattern 12a as a mask, and the gate insulating film 13 and the gate are formed on the element regions 1A and 1B. The electrode 14 is formed. Then, the resist pattern 12a and the antireflection film 11 are removed.

Next, as shown in FIG. 16, a resist pattern 15 is formed by photolithography. The resist pattern 15 exposes the first region R1 in which the n-MOS transistor is formed and covers the second region R2 in which the p-MOS transistor is formed. Subsequently, ion implantation is performed using the gate electrode 14 and the resist pattern 15 as a mask to form a source extension region 1a and a drain extension region 1b in the element region 1A formed in the first region R1. Since the n-MOS transistor is formed in the first region R1, for example, phosphorus ions (P) are typically supplied at 1.0 × 10 ¹² cm ⁻² to 1.0 × under an acceleration voltage of 10 keV to 100 keV. Ions are implanted at a dose of 10 ¹⁶ cm ⁻² .

Next, as shown in FIG. 17, a chemical solution such as sulfuric acid / hydrogen peroxide is supplied, the resist pattern 15 is removed by wet etching, and then a resist pattern 16 is formed by photolithography. The resist pattern 16 covers the first region R1 in which the n-MOS transistor is formed, and exposes the second region R2 in which the p-MOS transistor is formed. Subsequently, ion implantation is performed using the gate electrode 14 and the resist pattern 16 as a mask to form a source extension region 1a and a drain extension region 1b in the element region 1B formed in the second region R2. Since the p-MOS transistor is formed in the second region R2, for example, boron ions (B) are supplied at an acceleration voltage of 1 keV to 50 keV and 1.0 × 10 ¹² cm ^{−2 to} 1.0 × 10 6. Ions are implanted with a dose of ¹⁶ cm ^-2 . Then, a chemical solution such as sulfuric acid / hydrogen peroxide is supplied, and the resist pattern 16 is removed by wet etching.

Next, as shown in FIG. 18, for example, Vista butylaminosilane (BTBAS) is supplied at a flow rate of about 10 sccm to 60 sccm and oxygen (O ₂ ) at a flow rate of about 100 sccm to 240 sccm, the temperature is about 530 ° C., and the pressure is about 20 Pa. As described above, a silicon oxide film is formed on the oxide film 5, the element regions 1A and 1B, and the gate electrode 14 by thermal CVD. Then, the silicon oxide film is anisotropically etched to form sidewall insulating films 17 on both side walls of the gate electrode 14. The thickness of the sidewall insulating film 17 is, for example, 90 nm.

Next, as shown in FIG. 19, a resist pattern 18 is formed by photolithography. The resist pattern 18 exposes the first region R1 where the n-MOS transistor is to be formed and covers the second region R2 where the p-MOS transistor is to be formed. Subsequently, ion implantation is performed using the gate electrode 14, the sidewall insulating film 17, and the resist pattern 18 as a mask, and a source region 1c and a drain region 1d are formed in the element region 1A formed in the first region R1, respectively. To do. In the present embodiment, for example, phosphorus ion (P) is typically used at a dose of 1.0 × 10 ¹² cm ^{−2 to} 1.0 × 10 ¹⁶ cm ⁻² under an acceleration voltage of 10 keV to 100 keV. Alternatively, arsenic ions (As) are typically implanted at a dose of 1.0 × 10 ¹² cm ^{−2 to} 1.0 × 10 ¹⁶ cm ⁻² under an acceleration voltage of 10 keV to 100 keV.

Next, as shown in FIG. 20, after supplying a chemical solution such as sulfuric acid / hydrogen peroxide and removing the resist pattern 18 by wet etching, a resist pattern 19 is formed by photolithography. The resist pattern 19 covers the first region R1 in which the n-MOS transistor is formed, and exposes the second region R2 in which the p-MOS transistor is formed. Subsequently, ion implantation is performed using the gate electrode 14, the sidewall insulating film 17, and the resist pattern 19 as a mask, thereby forming a source region 1c and a drain region 1d in the element region 1B formed in the second region R2, respectively. To do. In this embodiment, boron ions (B) are ion-implanted at a dose of 1.0 × 10 ¹² cm ^{−2 to} 1.0 × 10 ¹⁶ cm ⁻² under an acceleration voltage of 1 keV to 50 keV. Then, a chemical solution such as sulfuric acid / hydrogen peroxide is supplied, and the resist pattern 19 is removed by wet etching.

Next, as shown in FIG. 21, for example, silane gas (SiH ₄ ) is supplied at a flow rate of 100 sccm, for example, oxygen (O ₂ ) at a flow rate of 200 sccm to 300 sccm, and the pressure is set to 1 mTorr to 5 mTorr. An interlayer insulating film 21 is deposited on 1 A, 1 B, the sidewall insulating film 17, and the oxide film 5.

Next, as shown in FIG. 22, contact holes reaching the source region 1c and the drain region 1d are formed in the interlayer insulating film 21 by, for example, magnetron RIE (Reactive Ion Etching). Then, a barrier metal such as TiN is formed on the inner wall of the contact hole by thermal CVD. When TiN is used as the barrier metal, for example, titanium tetrachloride gas (TiCl ₄ ) is supplied at 100 sccm / min to 100 mg / min, for example, ammonia gas (NH ₃ ) at 100 sccm, and the pressure is set at 10 Torr. Subsequently, for example, silane gas (SiH ₄ ) is supplied at a flow rate of 90 sccm, for example, tungsten hexafluoride gas (WF ₆ ) at a flow rate of 30 sccm, and the first tungsten (W) film having good coverage on the barrier metal by, eg, thermal CVD. Is deposited. Further, for example, tungsten fluoride gas (WF ₆ ) is supplied at a flow rate of 90 sccm, for example, hydrogen (H ₂ ) at a flow rate of 500 sccm to 800 sccm, and the second tungsten is formed on the first tungsten (W) film by, eg, thermal CVD. (W) A film is formed. Thus, the contact made of tungsten (W) is buried in the contact hole, and the contact 22 electrically connected to the source region 1c and the drain region 1d is completed. This completes the main manufacturing process of the semiconductor device.
[Effects of this embodiment]
As described above, in this embodiment, the entire oxide film 7 formed on the surface of the element regions 1A and 1B is covered with the silicon nitride film 8, and the element regions 1A and 1B are formed through the silicon nitride film 8. Well implantation and channel implantation are performed. Therefore, after the well implantation and the channel implantation, there is no variation in the ion concentration of the element regions 1A and 1B due to the presence or absence of the protective film (silicon nitride film or polysilicon) as in the cited document 1.

  Further, since the oxide film 5 is covered with the silicon nitride film 8 when the well implantation and the channel implantation are performed, for example, sulfuric acid / hydrogen peroxide is removed in order to remove the first and second resist patterns P1 and P2. Even when the chemical solution is supplied, the oxide film 5 does not move backward. Therefore, there is no variation in the height of the oxide film 5 between the first region R1 and the second region R2 after the well implantation and the channel implantation.

  As described above, according to the present embodiment, after the well implantation and the channel implantation, the first region R1 and the second region R2 can be used in the element regions 1A and 1B without causing variations in ion concentrations. It becomes possible to make the height of the oxide film 5 defining the regions 1A and 1B uniform.

  Further, in the present embodiment, since the antireflection film 11 is applied by spin coating, the height of the oxide film 5 varies between the first region R1 and the second region R2, and the polysilicon film 10 If irregularities are formed on the surface, the thickness of the antireflection film 11 is not uniform. For this reason, the pattern width of the resist pattern 12a varies, and as a result, the line width of the gate electrode 14 also varies. However, according to the present embodiment, the height of the oxide film 5 that defines the element regions 1A and 1B can be made uniform in the first region R1 and the second region R2. The surface can be flat throughout. Thereby, the film thickness of the antireflection film 11 applied on the polysilicon film 10 can be made uniform, and the line width of the gate electrode 14 can be made uniform.

  Even when the source extension region 1a, the drain extension region 1b, the source region 1c, and the drain region 1d are formed, the oxide film 5 is retreated to some extent along with the peeling of the resist patterns 15, 16, 18, and 19. As expected, the amount of recession in the entire process can be suppressed to about half.

  Further, since the height of the oxide film 5 does not vary between the first region R1 and the second region R2 after the well implantation and the channel implantation, for example, the thickness of the stopper film when the oxide film 5 is polished. That is, by adjusting the thickness of the silicon nitride film 3 (see FIG. 5), as shown in FIG. 23, the step between the element region 1A formed in the first region R1 and the oxide film 5, The step between the element region 1B and the oxide film 5 formed in the second region R2 can be eliminated at the same time.

  Even if there is no variation in the height of the element regions 1A and 1B in the first region R1 and the second region R2, the film thickness of the antireflection film 11 depends on the viscosity and wettability of the antireflection film 11. Variations may occur. That is, even if there is no variation in the height of the element regions 1A and 1B, the line width of the gate electrode 14 may not be uniform. However, according to the present invention, the step between the element region 1A and the oxide film 5 and the step between the element region 1B and the oxide film 5 can be eliminated in both the first and second regions R1 and R2. Regardless of the viscosity or wettability of the prevention film 11, the film thickness of the antireflection film 11 can be made uniform, and the line width of the gate electrode 14 can be made uniform.

In this embodiment, a case where two types of transistors, that is, an n-MOS transistor and a p-MOS transistor are mixedly mounted has been described. However, the present invention is not limited to this. A combination of an n-MOS transistor and an n-MOS transistor, or a p-MOS transistor and a p-MOS transistor may be used as long as the type of ions used in the well implantation and the channel implantation, the acceleration voltage, or the dose amount are different. Transistors with different breakdown voltages may be mounted together. Further, three or more types of transistors may be mounted together.
(Second Embodiment)
[Method of Manufacturing Semiconductor Device in Present Embodiment]
24 to 32 are explanatory diagrams of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. Note that the description of the same configuration and operation as in the first embodiment will be omitted. As described above, in the first embodiment, well injection and channel injection are performed through the silicon nitride film 8. However, in this embodiment, in order to make the ion concentration of the element regions 1A and 1B uniform by channel implantation, the oxide film 7 is formed after removing the silicon nitride film 8 corresponding to the element regions 1A and 1B. The channel implantation will be performed in a completely exposed state.

  As described above, when the silicon nitride film 8 is formed on the oxide film 5 and the oxide film 7 as shown in FIG. 7, the first film is formed on the silicon nitride film 8 by photolithography as shown in FIG. 1 resist pattern P1 is formed. Then, well implantation is performed on the element region 1A formed in the first region R1, using the first resist pattern P1 as a mask. Here, channel implantation is not performed.

  Next, as shown in FIG. 25, a chemical solution such as sulfuric acid / hydrogen peroxide is supplied, and the first resist pattern P1 is removed by wet etching. Then, a second resist pattern P2 is formed on the silicon nitride film 8 by photolithography. Then, well implantation is performed on the element region 1B formed in the second region R2 using the second resist pattern P2 as a mask. Here, channel implantation is not performed.

  Next, as shown in FIG. 26, a chemical solution such as sulfuric acid / hydrogen peroxide is supplied, and the second resist pattern P2 is peeled off by wet etching.

  Next, as shown in FIG. 27, a photoresist film 23 is applied to the surface of the silicon nitride film 8 by, for example, spin coating. Subsequently, the photoresist film 23 is patterned by photolithography to form a resist pattern 23 a on the surface of the silicon nitride film 8. Resist pattern 23a exposes only portions corresponding to element regions 1A and 1B and covers only portions corresponding to oxide film 5.

  Next, as shown in FIG. 28, the silicon nitride film 8 is removed by dry etching, for example, using the resist pattern 23a as a mask. Thus, only the oxide film 7 corresponding to the element regions 1A and 1B is exposed. Then, a chemical solution such as sulfuric acid / hydrogen peroxide is supplied, and the resist pattern 23a is removed by wet etching.

  Next, as shown in FIG. 29, a third resist pattern P3 is formed on the oxide film 7 and the silicon nitride film 8 by photolithography. The third resist pattern P3 exposes the first region R1 in which the n-MOS transistor is formed and covers the second region R2 in which the p-MOS transistor is formed. Then, channel implantation is performed on the element region 1A formed in the first region R1, using the third resist pattern P3 as a mask. At this time, since the silicon nitride film 8 is removed and the entire oxide film 7 is exposed in the portion corresponding to the element region 1A formed in the first region R1, the ion concentration in the element region 1A is made uniform. can do. That is, the variation in the ion concentration in the element region 1A due to the presence or absence of the silicon nitride film 8 as in the cited document 1 can be prevented.

  Next, as shown in FIG. 30, a chemical solution such as sulfuric acid / hydrogen peroxide is supplied, and the third resist pattern P3 is removed by wet etching. Then, a fourth resist pattern P4 is formed on the oxide film 7 and the silicon nitride film 8 by photolithography. The fourth resist pattern P4 covers the first region R1 in which the n-MOS transistor is formed and exposes the second region R2 in which the p-MOS transistor is formed. Then, channel implantation is performed on the element region 1B formed in the second region R2 using the fourth resist pattern P4 as a mask. At this time, since the silicon nitride film 8 is removed and the entire oxide film 7 is exposed in the portion corresponding to the element region 1B formed in the second region R2, the ion concentration in the element region 1B is made uniform. can do. That is, the variation in the ion concentration in the element region 1B due to the presence or absence of the silicon nitride film 8 as in the cited document 1 can be prevented.

  Next, as shown in FIG. 31, a chemical solution such as sulfuric acid / hydrogen peroxide is supplied, and the fourth resist pattern P4 is removed by wet etching.

Next, as shown in FIG. 32, for example, a chemical solution such as phosphoric acid is supplied, and the silicon nitride film 8 is removed by wet etching. Thereafter, the main manufacturing process of the semiconductor device is completed through the same processes as those of the first embodiment.
[Effects of Second Embodiment]
As described above, in this embodiment, channel implantation is performed after the silicon nitride film 8 corresponding to the element regions 1A and 1B is removed. As described above, by removing the silicon nitride film 8, the ion concentration of each of the element regions 1A and 1B is made uniform even in channel implantation in which ions are implanted into the shallower regions of the element regions 1A and 1B than the well implantation. It becomes possible.

  In this embodiment, the silicon nitride film 8 corresponding to the element regions 1A and 1B is completely removed before performing channel implantation. However, the present invention is not limited to this. Absent. For example, the silicon nitride film 8 corresponding to the element regions 1A and 1B may be thinned.

  In this embodiment, dry etching is used when removing the silicon nitride film 8 corresponding to the element regions 1A and 1B. However, the present invention is not limited to this. For example, wet etching may be performed after dry etching is performed. In this case, it is preferable that the opening width of the resist pattern used in dry etching is narrower than the element region, considering that wet etching performed later is isotropic etching.

  According to the above embodiment, the following configurations are obtained.

[Appendix 1]
Forming a trench in a semiconductor substrate to define first and second element regions;
Burying a first oxide film in the trench;
Forming a film covering all of the first and second element regions and the first oxide film on the first and second element regions and the first oxide film;
Forming a first resist pattern exposing the first element region and the first region including a part of the first oxide film on the film;
Implanting a first impurity through the film covering the entire first element region using the first resist pattern as a mask;
A step of supplying a first chemical after removing the first impurity and removing the first resist pattern;
Forming a second resist pattern on the film to expose the second element region and a second region including a part of the first oxide film;
Implanting a second impurity through the film covering the entire second element region using the second resist pattern as a mask;
Supplying a first chemical after implanting the second impurity and removing the second resist pattern;
Supplying the second chemical solution after removing the first resist pattern and the second resist pattern, and removing the film;
A method for manufacturing a semiconductor device, comprising:

[Appendix 2]
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a second oxide film on the surfaces of the first and second element regions before forming the film.

[Appendix 3]
2. The method of manufacturing a semiconductor device according to appendix 1, wherein the film is a silicon nitride film or a polysilicon film.

[Appendix 4]
2. The semiconductor according to claim 1, wherein the entire portion corresponding to the first and second element regions of the film is thinned by etching before implanting the first impurity and the second impurity. Device manufacturing method.

[Appendix 5]
Etching the entire portion corresponding to the first element region of the film after etching the first impurity and before removing the film; and
Injecting a third impurity through the film covering the entire first element region after thinning the film;
The method for manufacturing a semiconductor device according to appendix 1, further comprising:

[Appendix 6]
Selectively removing a portion of the film corresponding to the first element region by etching after implanting the first impurity and before removing the film;
Implanting a third impurity into the first element region after selectively removing the film;
The method for manufacturing a semiconductor device according to appendix 1, further comprising:

[Appendix 7]
7. The method of manufacturing a semiconductor device according to claim 5, wherein the implantation of the first impurity is a well implantation, and the implantation of the third impurity is a channel implantation.

[Appendix 8]
2. The method of manufacturing a semiconductor device according to appendix 1, wherein the first chemical solution is a solution containing sulfuric acid and hydrogen peroxide solution or a solution containing ammonia and hydrogen peroxide solution.

[Appendix 9]
2. The method for manufacturing a semiconductor device according to appendix 1, wherein the second chemical solution is a solution containing phosphoric acid.

[Appendix 10]
Forming an insulating film on the first and second element regions after removing the film;
Forming a conductive film on the insulating film;
Patterning the conductive film to form a gate electrode of a transistor;
The method of manufacturing a semiconductor device according to claim 1, comprising:

[Appendix 11]
The step of patterning the conductive film includes:
Forming a coating type antireflection film on the conductive film;
Forming a resist film on the antireflection film;
Patterning the resist film by a photolithography method;
Etching the conductive film using the resist film or the antireflection film as a mask;
Item 14. The method for manufacturing a semiconductor device according to appendix 10, wherein

[Appendix 12]
Forming a trench in a semiconductor substrate to define an element region;
Burying an oxide film in the trench;
Forming a film covering the entire element region and the oxide film on the element region and the oxide film;
Forming a resist pattern on the film in which a portion corresponding to the element region is exposed;
Injecting impurities into the element region through the film covering the entire element region using the resist pattern as a mask;
Supplying the first chemical solution after implanting the impurities and removing the resist pattern;
After removing the resist pattern, supplying a second chemical solution to remove the film;
A method for manufacturing a semiconductor device, comprising:

Explanatory drawing (the 1) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 2) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 3) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 4) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 5) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 6) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 7) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 8) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 9) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 10) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 11) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 12) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 13) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 14) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 15) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 16) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention (the 17) Explanatory drawing (the 18) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 19) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 20) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 21) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 22) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 23) of the manufacturing process of the semiconductor device in the 1st Embodiment of this invention. Explanatory drawing (the 1) of the manufacturing process of the semiconductor device in the 2nd Embodiment of this invention. Explanatory drawing (the 2) of the manufacturing process of the semiconductor device in the 2nd Embodiment of this invention. Explanatory drawing (the 3) of the manufacturing process of the semiconductor device in the 2nd Embodiment of this invention. Explanatory drawing (the 4) of the manufacturing process of the semiconductor device in the 2nd Embodiment of this invention. Explanatory drawing (the 5) of the manufacturing process of the semiconductor device in the 2nd Embodiment of this invention. Explanatory drawing (the 6) of the manufacturing process of the semiconductor device in the 2nd Embodiment of this invention. Explanatory drawing (the 7) of the manufacturing process of the semiconductor device in the 2nd Embodiment of this invention. Explanatory drawing (the 8) of the manufacturing process of the semiconductor device in the 2nd Embodiment of this invention. Explanatory drawing (the 9) of the manufacturing process of the semiconductor device in the 2nd Embodiment of this invention. Schematic of the manufacturing method of the semiconductor device in cited reference 1.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate (semiconductor substrate), 1A ... Element region, 1B ... Element region, 1T ... Silicon trench (trench), 5 ... Oxide film (first oxide film), 7 ... Oxide film (second oxide film) 8 ... Silicon nitride film (film), 9 ... Silicon oxide film (insulating film), 10 ... Polysilicon film (conductive film), 11 ... Antireflection film, 12 ... Photoresist film, P1 ... First resist pattern, P2 ... second resist pattern, P3 ... third resist pattern, P4 ... fourth resist pattern, R1 ... first region, R2 ... second region.

Claims (5)

Forming a trench in a semiconductor substrate to define first and second element regions;
Burying a first oxide film in the trench;
Forming a film covering all of the first and second element regions and the first oxide film on the first and second element regions and the first oxide film;
Forming a first resist pattern exposing the first element region and the first region including a part of the first oxide film on the film;
Implanting a first impurity through the film covering the entire first element region using the first resist pattern as a mask;
A step of supplying a first chemical after removing the first impurity and removing the first resist pattern;
Forming a second resist pattern on the film to expose the second element region and a second region including a part of the first oxide film;
Implanting a second impurity through the film covering the entire second element region using the second resist pattern as a mask;
Supplying a first chemical after implanting the second impurity and removing the second resist pattern;
After removing the first resist pattern and the second resist pattern, and supplies the second liquid chemical, saw including a step of removing the film,
A step of selectively thinning or removing only a portion of the film corresponding to the first element region by etching after implanting the first impurity and before removing the film;
Injecting a third impurity into the first element region after selectively thinning or removing the film;
A method for manufacturing a semiconductor device , further comprising : Forming a trench in a semiconductor substrate to define first and second element regions;
Burying a first oxide film in the trench;
Forming a film covering all of the first and second element regions and the first oxide film on the first and second element regions and the first oxide film;
Forming a first resist pattern exposing the first element region and the first region including a part of the first oxide film on the film;
Implanting a first impurity through the film covering the entire first element region using the first resist pattern as a mask;
A step of supplying a first chemical after removing the first impurity and removing the first resist pattern;
Forming a second resist pattern on the film to expose the second element region and a second region including a part of the first oxide film;
Implanting a second impurity through the film covering the entire second element region using the second resist pattern as a mask;
Supplying a first chemical after implanting the second impurity and removing the second resist pattern;
After removing the first resist pattern and the second resist pattern, and supplies the second liquid chemical, saw including a step of removing the film,
A method of manufacturing a semiconductor device, characterized in that an entire portion corresponding to the first and second element regions of the film is thinned by etching before implanting the first impurity and the second impurity . Before forming the film, the first method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that it comprises a step of forming a second oxide film on the surface of the second element region. The film manufacturing method of a semiconductor device according to any one of claims 1-3, characterized in that a silicon nitride film or a polysilicon film. Forming an insulating film on the first and second element regions after removing the film;
Forming a conductive film on the insulating film;
Patterning the conductive film to form a gate electrode of a transistor;
5. The method of manufacturing a semiconductor device according to claim 1, comprising:

Images