JP2002222942A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the film taper of an insulating film in an element separating area with a simple method in the manufacturing process of a semiconductor device. SOLUTION: An element separation insulating film 3 is formed on the surface of a silicon substrate 1 by a silicon oxidized film of a first insulating material, and a silicon nitride film 10 of a second insulating material different in etching speed from the first insulating material is stuck to the whole face of a protection insulating film 4. The protection insulating film 4 is selectively etched, a protection insulating film opening 5 is formed and the gate insulating film 11 of a MOS transistor is formed in the protection insulating film opening 5. Then, the gate electrode 6 or the side wall insulating film 14 of the MOS transistor is formed on the gate insulating film 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure for preventing an insulating film in an element isolation region from being thinned and a method of forming the same.

[0002]

2. Description of the Related Art Insulated gate field effect transistors (MO)
The miniaturization and the densification of the structure of a semiconductor element such as an S transistor are still being vigorously promoted. For miniaturization, a semiconductor element having a size of up to 0.20 μm is currently used, and semiconductor devices such as a memory device or a logic device based on this size as a design standard have been put into practical use or studied for development.

[0003] Such miniaturization is the most effective method for achieving high performance or multifunctionality due to high integration, high speed, etc. of a semiconductor device, and is indispensable for the manufacture of semiconductor devices in the future. With the miniaturization of such semiconductor elements, an element isolation region for electrically isolating the semiconductor elements has been formed by burying an insulator in a trench (groove). That is, STI (S
hallow Trench Isolation) has been used.

Hereinafter, a MOS transistor surrounded by a trench isolation region will be schematically described with reference to FIG. FIG. 8A is a plan view of the MOS transistor, and FIG. 8B is a cross-sectional view taken along the line XY of FIG. 8A.

As shown in FIGS. 8A and 8B, a device active region 102 on the surface of a silicon substrate 101 is surrounded by a trench device isolation region 103. Here, a silicon oxide film is embedded in the trench isolation region 3. Then, a gate insulating film 104 is formed of an oxynitride film or the like on the surface of the element active region 102, and a gate electrode 105 is formed on the gate insulating film 104.

Next, source / drain diffusion layers 106 and 107 of the MOS transistor are formed in a self-aligned manner (self-alignment) with the gate electrode 105 and the trench element isolation region 103.

In the above-described manufacturing process of the MOS transistor, the etching process of the silicon oxide film is frequently used in the manufacturing process after the trench element isolation region 103 is formed. For example, there is a step of etching and removing a buffer oxide film on the surface of the element active region 102 used for ion implantation with a hydrofluoric acid solution in order to form a well layer. Alternatively, LDD (Li
Source of Glyly Doped Drain) structure
When forming a drain diffusion layer, there is an etch back of a silicon oxide film for forming a sidewall insulating film on a side wall of a gate electrode. This etch back is performed by dry etching using reactive ion etching (RIE).

In the above-described etching process of the silicon oxide film, the silicon oxide film forming the trench element isolation region 103 is subjected to film burrs, and a recess 108 is formed as shown in FIG. Alternatively, the surface of the silicon oxide film filling the trench element isolation region 103 is etched away in the above-described etching process. Then, the thickness of the silicon oxide film filling the trench element isolation region 103 decreases.

[0009] The film veri- fication of the silicon oxide film in such an element isolation region is not limited to the above-described trench element isolation method, but is a well-known technique such as LOCOS (Local Oxid).
This also occurs in the case of an element isolation region formed by the ation of silicon method.

[0010] The above-mentioned element isolation region is used to insulate and isolate semiconductor elements constituting a semiconductor device. In recent years, many semiconductor devices having a system function have been manufactured. Among them, a semiconductor device in which a memory and a logic are mixedly mounted, such as a flash memory and a logic, has been produced. Here, referring to FIG. 9, a case where the element of the floating gate type MOS transistor and the area of the MOS transistor constituting the flash memory are separated from each other will be schematically described.

As shown in FIG. 9, a P-well layer 111 is formed on the surface of a silicon substrate 110 by ion implantation and heat treatment. Then, element isolation regions 112, 112a, and 112b are formed in predetermined regions on the surface of the P well layer 111. Here, the element isolation regions 112, 112a, 112b are formed by the trench element isolation method or the LOCOS method described above.

Then, a gate electrode 114 is formed on the surface of the P-well layer 111 via a gate insulating film 113 in a region where the MOS transistor is to be formed. Further, N-type source / drain diffusion layers 115 and 115a are formed so as to be self-aligned with the gate electrode 114 and the element isolation regions 112 and 112a.

In the formation region of the floating gate type MOS transistor, the floating gate electrode 11 is stacked on the surface of the P well layer 111 via the tunnel oxide film 116.
7. An intermediate insulating film 118 and a control gate electrode 119 are formed. Further, N-type diffusion layers 120 and 120a are formed so as to be self-aligned with the element isolation regions 112 and 112b and the control gate electrode 119 and the like.

As shown in FIG. 9, the MOS transistor and the floating gate type transistor are insulated and separated by the element isolation region 112.

[0015]

SUMMARY OF THE INVENTION The present inventors have studied in detail the above-mentioned film burrs in element isolation regions of various semiconductor devices. As a result, it has been found that in a semiconductor device that uses a relatively high voltage for a part thereof, such as a semiconductor device in which a flash memory is mixedly mounted, the above-described film verification of the insulating film in the element isolation region has a very severe influence. In the case of a floating gate type MOS transistor as shown in FIG. 9 which constitutes a flash memory cell, when electrons as information storage charges are extracted from the floating gate electrode to the diffusion layer 120,
A high voltage of about 10 V for the diffusion layer 120 is applied. At this time, the source / drain diffusion layer 11 of the MOS transistor
When 5 is at the ground potential, a leak current easily flows through the lower portion of the element isolation region 112. In this case, it is necessary to prevent the film from being separated from the element isolation region 112.

Further, in the case of a semiconductor device composed of fine MOS transistors, the following problems are peculiar to the silicon oxide film in the trench isolation region. That is, a hump phenomenon easily occurs in the sub-threshold characteristic of the MOS transistor.
This will be described with reference to FIG. FIG.
4 shows a relationship between a source-drain current and a gate voltage of an OS transistor. Here, a so-called sub-threshold region and a region in a channel generation state (that is, an ON state) are shown. As shown by the broken line as an abnormal characteristic in the figure, in the sub-threshold region, the normal MOS
The source-drain current will be higher than in the case of a transistor (shown by a solid line). This current becomes the same as that of a normal MOS transistor when the MOS transistor is completely turned on. The bump shown by the broken line in the source-drain current-gate voltage characteristics as shown in FIG. 10 is called hump.

The occurrence of such humps appears when the formation of the recess 108 described with reference to FIG. When such a hump phenomenon occurs, the threshold value of the MOS transistor becomes smaller than a design value. Further, the reliability of the gate insulating film of the MOS transistor decreases. For these reasons, defective semiconductor devices frequently occur, and the yield is reduced.

An object of the present invention is to make it possible to easily prevent the insulating film in the element isolation region from becoming thin in the manufacturing process of a semiconductor device. Another object of the present invention is to provide a method for easily forming a MOS transistor having a plurality of types of gate insulating films.

[0019]

For this purpose, in the semiconductor device of the present invention, the element isolation region on the surface of the semiconductor substrate is made of a first insulating material, and the insulated gate field effect transistor on the semiconductor substrate is provided with the element isolation region. A gate electrode of the MOS transistor is provided on the element isolation region via a protective insulating film made of a second insulating material having a different etching rate from the first insulating material, the area being partitioned by a region; . The protective insulating film has oxidation resistance.

In the method of manufacturing a semiconductor device according to the present invention, after forming an element isolation region on a surface of a semiconductor substrate with a first insulating material, a second insulating material having a different etching rate from the first insulating material is used.
Depositing a protective insulating film made of an insulating material on the entire surface, selectively etching the protective insulating film on a predetermined region of the semiconductor substrate to form an opening, and forming the opening in the opening. Forming a gate electrode of the MOS transistor on the gate insulating film after forming the gate insulating film of the MOS transistor.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, after an element isolation region is formed on a surface of a semiconductor substrate with a first insulating material, an etching rate is different from that of the first insulating material and oxidation resistance is reduced. Depositing a protective insulating film over the entire surface with a second insulating material, and selectively etching the protective insulating film on a predetermined region of the semiconductor substrate to form a first opening and a second opening. Forming an oxide film on the surface of the semiconductor substrate at the first opening and the second opening through thermal oxidation using the protective insulating film as an oxidation mask; and forming the first opening or Selectively removing the oxide film in one of the second openings;
Forming a gate insulating film of a different MOS transistor in the first opening and the second opening by performing thermal oxidation or oxynitriding again using the protective insulating film as an oxidation mask; Forming a gate electrode of a MOS transistor on each of the different gate insulating films after forming a gate insulating film of the transistor.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, after the protective insulating film is deposited on the entire surface and before the opening is formed, the well layer is formed by ion implantation of impurities and heat treatment thereof. Is formed on the surface of the semiconductor substrate.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, after the gate electrode is formed, a sidewall of the gate electrode is formed by depositing an insulating film and etching back the insulating film using the protective insulating film as an etching mask. Next, a sidewall insulating film is formed.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, after forming the sidewall insulating film, a source / drain diffusion layer of a MOS transistor is formed by ion implantation of impurities and heat treatment thereof, and thereafter, the protection layer is formed. The insulating film is removed by etching.

Here, the first insulating material is silicon oxide, and the second insulating material is silicon nitride.

According to the present invention, in the process of manufacturing a semiconductor device, the above-mentioned protective insulating film covers the element isolation region and protects it from etching. For this reason, the film erosion of the insulating film in the element isolation region is greatly suppressed. Also,
By using the protective insulating film as a mask for oxidation or oxynitridation, a MOS transistor having a plurality of types of gate insulating films can be easily formed. Then, higher integration or higher density of the semiconductor device is promoted.

[0027]

Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view for explaining the features of the structure of the present invention. 2 to 4 are cross-sectional views of a semiconductor device for illustrating the present invention in the order of manufacturing steps. Here, FIGS. 2 to 4 are cross-sectional views taken along the line AB shown in FIG.

As shown in FIG. 1, an N-well layer 2 is formed on the surface of a silicon substrate 1, and an element isolation insulating film 3 is formed so as to surround an element active region. Then, a protective insulating film 4 covering the surface of the silicon substrate 1 and the element isolation insulating film 3 is formed. Here, the protective insulating film 4 in the channel region of the MOS transistor is removed, and the protective insulating film opening 5 is formed.
Is formed. Then, a gate electrode 6 is formed on the silicon substrate via the gate insulating film formed on the silicon substrate in the protective insulating film opening 5. Further, the element isolation insulating film 3
Source and self-aligned with gate electrode 6
A drain diffusion layer 7 is formed. In this way MOS
The basic structure of the transistor is formed. Further, a resistance diffusion layer 8 is formed in a predetermined region of N well layer 2, and an N well resistance region is formed.

Next, a method of manufacturing the above-described structure will be described with reference to FIGS. As shown in FIG. 2A, an N well layer 2 is formed in a predetermined region of the silicon substrate 1 by ion implantation of phosphorus impurities and heat treatment. Then, the element isolation insulating film 3 is formed of a silicon oxide film serving as a first insulating material by a trench element isolation method or a LOCOS method.

Next, a silicon oxide film 9 having a thickness of about 10 nm is deposited on the entire surface by a chemical vapor deposition (CVD) method.
Further, as shown in FIG. 2B, a silicon nitride film 10 serving as a second insulating material having a thickness of about 20 nm is formed on the silicon oxide film 9 by lamination. The silicon oxide film 9 and the silicon nitride film 10 to be laminated are formed by the protective insulating film
Becomes

The above-mentioned N-well layer 2 may be formed by ion-implanting phosphorus impurities and heat-treating after forming the element isolation insulating film 3 and the silicon oxide film 9 first. In this case, the manufacturing process is shortened. Here, a high-energy ion implantation method of 500 keV or more is used for phosphorus impurity ions.

Next, as shown in FIG. 2C, the silicon nitride film 10 is selectively etched by a known photolithography technique and a dry etching technique to form a protective insulating film opening 5a. Here, the RI of the silicon nitride film 10 is
In E, a mixed gas of NF ₃ and CO is used as a reaction gas.

Then, as shown in FIG. 3A, the silicon nitride film 1 is wet-etched with a dilute hydrofluoric acid solution.
By using 0 as an etching mask, the silicon oxide film 9 is selectively removed to form a protective insulating film opening 5. In the wet etching process of the silicon oxide film 9, the surface of the element isolation insulating film 3 is not etched at all. This is because the silicon nitride film 10 is completely protected.

Next, as shown in FIG. 3B, a gate insulating film 11 is formed on the surface of the N well layer 2 at the opening 5 of the protective insulating film. This gate insulating film 11 is formed of an oxynitride film having a thickness of about 5 nm. Then, as shown in FIG. 3C, a gate electrode 6 having a polycide structure is formed by a known photolithography technique and a dry etching technique. Here, the dimension of the gate electrode 6 in the channel direction is 0.3 μm.
And the cap oxide film 12 used as the etching mask remains on the upper portion. Further, a shallow diffusion layer 13 is formed by ion implantation of boron impurities and heat treatment. Here, the implantation energy of boron ions is set to about 50 keV.

Next, a silicon oxide film having a thickness of about 300 nm is deposited on the entire surface by the CVD method, and this silicon oxide film is subjected to anisotropic dry etching (etch back). Thus, as shown in FIG. 3D, the side wall insulating film 14 is formed on the side walls of the gate electrode 6 and the cap oxide film 12.
To form As a reaction gas in this etch-back step, a mixed gas of C ₄ F ₈ , O ₂ , and Ar is used.

In the step of etching back the silicon oxide film for forming the side wall insulating film 14, the surface of the element isolation insulating film 3 is completely protected by the silicon nitride film 10 and is never etched.

Next, as shown in FIG. 4A, the above-described silicon nitride film 10 is removed by wet etching.
In this etching step, a chemical chemical of hot phosphoric acid is used. This chemical solution does not etch the silicon oxide film 9. Therefore, even in this step, the element isolation insulating film 3 is not etched at all.

Next, as shown in FIG. 4B, the LD which becomes self-aligned with the element isolation insulating film 3 and the gate electrode 6 by ion implantation of high concentration boron impurity and heat treatment.
A source / drain diffusion layer 7 having a D structure is formed.

Next, as shown in FIG. 4C, ion implantation of high concentration arsenic or phosphorus impurities and heat treatment
On the surface of the well layer 2, a resistance diffusion layer 8 which is self-aligned with the element isolation insulating film 3 is formed. Since then. MOS
The electrodes of the transistor or resistor are formed,
The description is omitted.

As described above, in the present invention, by forming the protective insulating film 4 and forming the protective insulating film opening 5 in the channel region of the MOS transistor, the element isolation insulating film is etched in the semiconductor device manufacturing process. The film burring is greatly reduced.

Here, in the structure shown in FIG. 1, the protective insulating film opening 5 is provided inside the element active region. Therefore, the gate insulating film 11 and the protective insulating film 4 exist below the gate electrode 6 of the MOS transistor. Therefore, in the structure shown in FIG. 1, the effective film thickness needs to be larger than that of the gate insulating film 11 so that the channel region is not formed under the protective insulating film 4 in the element active region.

As a method for preventing the area under the protective insulating film 4 from becoming a channel region, a structure shown in FIG. 5 can be considered. This structure will be described below. Here, differences from FIG. 1 will be mainly described. In this case, as shown in FIG. 5, the protective insulating film opening 15 is formed so as to protrude from the element active region 16 and straddle the element isolation insulating film 3. For this purpose, a gate insulating film is formed uniformly in the channel region of the MOS transistor, and the protective insulating film 4 is formed.
Are not formed at all.

Next, a second embodiment of the present invention will be described with reference to FIGS. 6 and 7 are schematic sectional views in the order of the manufacturing steps of the MOS transistor. The feature of the second embodiment resides in that a MOS transistor having gate insulating films having different thicknesses is formed by using the present invention.
Here, the same components as those in FIGS. 1 to 5 are denoted by the same reference numerals.

As shown in FIG. 6A, the silicon substrate 1
Selectively use trench isolation or LOCO
The element isolation insulating film 3 is formed of a silicon oxide film by the S method.
Next, a thermal oxide film 17 having a thickness of about 5 nm is formed by thermal oxidation of the surface of the silicon substrate 1. Further, a silicon nitride film 10 having a thickness of about 20 nm is formed on the thermal oxide film 17 by lamination. The laminated thermal oxide film 17 and silicon nitride film 1
0 is the protective insulating film 4 described above.

Next, as shown in FIG. 6A, the silicon nitride film 10 is selectively etched by a known photolithography technique and a dry etching technique to form a protective insulating film opening 5a. Here, the RI of the silicon nitride film 10 is
In E, a mixed gas of NF ₃ and CO is used as a reaction gas.

Next, as shown in FIG. 6B, a resist mask 18 is formed so as to cover the thermal oxide film 17 in a predetermined region. Then, the thermal oxide film 17 is selectively removed by wet etching with a diluted hydrofluoric acid solution to remove the protective insulating film opening 5.
To form In the wet etching process of the silicon oxide film 9, the surface of the element isolation insulating film 3 is not etched at all. This is because the silicon nitride film 10 is completely protected.

Next, the resist mask 18 is removed by a known method, and further cleaned, and the silicon substrate 1 is subjected to a thermal oxidation treatment or an oxynitridation treatment. In this way, FIG.
As shown in FIG. 6, a first gate insulating film 19 having a thickness of about 5 nm is formed in the protective insulating film opening 5 at the same time as FIG.
Thermal oxide film 17 under resist mask 18 described in (b)
To form a second gate insulating film 20. Here, the thickness of the second gate insulating film is 10 nm. In the thermal oxidation process or the oxynitridation process, the silicon nitride film 10 has a function of completely preventing the surface of the silicon substrate 1 under the silicon nitride film 10 from being oxidized.

Then, as shown in FIG. 7B, gate electrodes 6 and 6a having a polycide structure are formed by a known photolithography technique and a dry etching technique. Here, the dimension of the gate electrodes 6 and 6a in the channel direction is 0.3
It is about μm. In this manner, a MOS transistor having the thin first gate insulating film below the gate electrode 6 and the thick second gate insulating film 20 below the gate electrode 6a can be formed.

In the following steps, as described in the first embodiment, a side wall insulating film is formed on the side walls of the gate electrodes 6, 6a, and further, a source / drain diffusion layer of a MOS transistor is formed. Here, arsenic or phosphorus impurities are used for ion implantation for forming the source / drain diffusion layers. Since then. Although an electrode of the MOS transistor is formed, the description is omitted.

In this embodiment, a MOS transistor having two types of gate insulating films can be easily formed. Then, similarly to the first embodiment, it is possible to greatly reduce the amount of the film isolation of the element isolation insulating film.

In the first embodiment, a P-channel type MOS
The case where a transistor is formed has been described. In the second embodiment, the case where an N-channel MOS transistor is formed has been described. The present invention can be similarly applied to the case where an N-channel MOS transistor is formed in the first embodiment. The present invention can be similarly applied to the case where a P-channel MOS transistor is formed in the second embodiment.

Further, in the embodiment of the present invention, the protective insulating film is formed by a laminated film of a silicon nitride film / silicon oxide film, but is not limited to this. The same effect can be obtained by using an insulating film different from the alumina film or the silicon oxide film instead of the silicon nitride film.

[0053]

As described above, in the main part of the present invention, after forming an element isolation region on the surface of a semiconductor substrate, a protective insulating material composed of an insulating material different from the insulating material forming the element isolation region is used. The membrane is coated over the entire surface. Then, in the manufacturing process of the MOS transistor constituting the semiconductor device, the above-mentioned protective insulating film covers the element isolation region and protects it from etching.

In this way, the film erosion of the insulating film in the element isolation region is greatly suppressed. Further, by using the protective insulating film as a mask for oxidation or oxynitridation,
A MOS transistor having a plurality of types of gate insulating films can be easily formed. Then, higher integration or higher density of the semiconductor device is promoted.

[Brief description of the drawings]

FIG. 1 is a plan view of a MOS transistor region for explaining the present invention.

FIG. 2 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view of a semiconductor device for illustrating a continuation of the above process, in the order of the manufacturing process.

FIG. 4 is a cross-sectional view of a semiconductor device for illustrating a continuation of the above process in the order of the manufacturing process.

FIG. 5 is a plan view of a MOS transistor region for describing the present invention.

FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention in the order of manufacturing steps.

FIG. 7 is a cross-sectional view illustrating the continuation of the above process in the order of the manufacturing process of the semiconductor device.

FIG. 8 is a plan view and a cross-sectional view of a MOS transistor having a trench element isolation region for explaining a conventional technique.

FIG. 9 is a cross-sectional view of a semiconductor device illustrating element isolation between semiconductor elements in a conventional technique.

FIG. 10 is a graph showing MOS transistor characteristics for explaining a problem of the conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 N well layer 3 Element isolation insulating film 4 Protective insulating film 5, 5a, 15 Protective insulating film opening 6, 6a Gate electrode 7 Source / drain diffusion layer 8 Resistance diffusion layer 9 Silicon oxide film 10 Silicon nitride film 11 Gate Insulating film 12 Cap oxide film 13 Shallow diffusion layer 14 Side wall insulating film 16 Element active region 17 Thermal oxide film 18 Resist mask 19 First gate insulating film 20 Second gate insulating film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 27/088 H01L 21/94 A 5F083 27/08 331 27/08 102C 5F101 21/8247 27/10 434 27 / 115 29/78 371 27/10 481 29/788 29/792 F term (reference) 4M108 AA05 AB05 AB27 AC55 AD13 5F001 AA01 AA25 AB08 AD17 AD60 AD61 AD62 AG03 AG07 AG10 AG28 AG40 5F032 AA14 AA34 AA44 BB06 CA03 CA17 DA02 DA28 5F040 DA00 DB01 DB10 EA08 EC01 EC07 EC13 ED03 EF02 EK01 EK05 FA05 FA16 FB02 FC21 FC22 5F048 AA04 AA07 AB01 AC01 AC03 AC10 BA01 BB05 BB08 BB16 BC06 BE03 BG12 BG14 DA25 5F083 EP02 EP23 ER22 JA05 PR03A07 PR05 PR05 BA01 BA07 BB05 BD07 BD35 BD36 BD37 BH05 BH13 BH14 BH19 BH21

Claims (8)

[Claims] An element isolation region on a surface of a semiconductor substrate is made of a first insulating material, and an insulated gate field effect transistor (hereinafter, referred to as a MOS transistor) on the semiconductor substrate is partitioned by the element isolation region. The MO is formed on the element isolation region via a protective insulating film made of a second insulating material having a different etching rate from that of the first insulating material.
A semiconductor device, wherein a gate electrode of an S transistor is provided. 2. The semiconductor device according to claim 1, wherein said protective insulating film has oxidation resistance. 3. After forming an element isolation region on a semiconductor substrate surface with a first insulating material, a protective insulating film made of a second insulating material having a different etching rate from that of the first insulating material is coated on the entire surface. Depositing, selectively etching the protective insulating film on a predetermined region of the semiconductor substrate to form an opening, and forming the gate insulating film of a MOS transistor in the opening after the gate insulating film. MO on
Forming a gate electrode of an S-transistor. 4. A protective insulating film made of a second insulating material having an etching rate different from that of the first insulating material and having oxidation resistance after forming an element isolation region on the surface of the semiconductor substrate with the first insulating material. Forming a first opening and a second opening by selectively etching the protective insulating film on a predetermined region of the semiconductor substrate;
Forming an oxide film on the surface of the semiconductor substrate at the first opening and the second opening through thermal oxidation using the protective insulating film as an oxidation mask; and forming an oxide film on the first opening or the second opening. A step of selectively removing the oxide film in one of the openings, and another thermal oxidation or oxynitridation using the protective insulating film as an oxidation mask to form the first opening and the second opening together. Forming a gate insulating film of a different MOS transistor, and forming a gate electrode of the MOS transistor on the different gate insulating film after forming the gate insulating film of the MOS transistor in the opening. A method for manufacturing a semiconductor device. 5. A well layer is formed on the surface of the semiconductor substrate by ion implantation of impurities and heat treatment thereof after the protective insulating film is deposited on the entire surface and before the opening is formed. 5. The method for manufacturing a semiconductor device according to claim 3, wherein 6. After forming the gate electrode, forming a sidewall insulating film on a side wall of the gate electrode by depositing an insulating film and etching back the insulating film using the protective insulating film as an etching mask. Claim 3, characterized in that:
A method for manufacturing a semiconductor device according to claim 4. 7. The method according to claim 7, wherein after forming the sidewall insulating film, a source / drain diffusion layer of a MOS transistor is formed by ion implantation of impurities and heat treatment thereof, and thereafter, the protective insulating film is removed by etching. The method of manufacturing a semiconductor device according to claim 6. 8. The method according to claim 3, wherein the first insulating material is silicon oxide, and the second insulating material is silicon nitride. Of manufacturing a semiconductor device.