JP6953224B2 - Manufacturing method of semiconductor devices and semiconductor devices - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device and the semiconductor device.

As an element separation structure of a semiconductor device, STI (shallow trench isolation) is known in which a trench is provided on the surface of a silicon substrate and the trench is filled with an insulating material such as a silicon oxide film.

When manufacturing such a semiconductor device, first, STI is formed on a silicon substrate, and then thermal oxidation is performed to form a gate oxide film. Then, after forming the gate electrode on the gate oxide film, the source and drain of the transistor are formed by executing the injection of impurities and the heat treatment step.

By the way, when the silicon substrate is repeatedly subjected to high heat (for example, 800 degrees) by repeating the above-mentioned thermal oxidation and heat treatment steps, a difference in thermal stress is generated between the silicon substrate and the insulating material, and the silicon substrate is crystallized accordingly. There was a risk of defects.

Therefore, in order to avoid such a problem, a method for manufacturing a semiconductor device for forming a gate oxide film by the following method has been proposed (see, for example, Patent Document 1).

That is, first, a silicon oxide film grown by oxidation by pyrolysis is formed, and a silicon oxide film grown by vacuum vapor deposition by thermal decomposition of _{SiH 4 gas is formed on the upper part of the silicon oxide film.} Then, these two layers a silicon oxide film, as well as oxidized by rapid heating in N ₂ O or NO gas, by sequentially growing a silicon oxide film containing nitrogen to trace, to obtain a gate oxide film.

According to such a manufacturing method, since the amount of heat treatment when forming the gate oxide film can be suppressed, the difference in thermal stress generated between the silicon substrate and the insulating material can be suppressed, and crystal defects of the silicon substrate can be prevented. Become.

Japanese Unexamined Patent Publication No. 2006-352003

By the way, after the formation of the gate oxide film described above, the surface of the silicon substrate is also exposed to high heat in the thermal step for forming the high-concentration diffusion layer that bears the source and drain of the transistor. Therefore, due to the thermal step, thermal stress is generated at the boundary between the silicon substrate and the silicon oxide material of STI due to the difference in the coefficient of thermal expansion between the two, which may lead to the occurrence of crystal defects.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device capable of preventing the occurrence of crystal defects and improving the yield.

The method for manufacturing a semiconductor device according to the present invention includes a first step of forming a trench at a boundary of a semiconductor device region, a second step of filling the trench with an insulating film, and a first step on the upper surface of the device region. A third step of forming the gate electrode of 1 and forming a second gate electrode on the upper surface of the insulating film, and using the second gate electrode formed on the upper surface of the insulating film as a mask in the trench. A fourth step of removing a portion of the filled insulating film in contact with the element region, a fifth step of injecting impurities into the element region to form a diffusion layer, and a heat treatment of the element region. It has a sixth step of activating the impurities contained in the diffusion layer by applying the above.

Further, the method for manufacturing a semiconductor device according to the present invention includes a first step of forming a trench at a boundary of a semiconductor device region, a second step of filling the trench with an insulating film, and an upper surface of the device region. A third step of forming a first gate electrode and a second gate electrode on the upper surface of the insulating film, and a fourth step of injecting impurities into the device region to form a diffusion layer. A fifth step of removing a portion of the insulating film filled in the trench that is in contact with the element region, using the second gate electrode formed on the upper surface of the insulating film as a mask, and the element region. It has a sixth step of activating the impurities contained in the diffusion layer by subjecting the device to a heat treatment.

Further, the semiconductor device according to the present invention has a semiconductor substrate including an element region in which the first gate electrode and the diffusion layer are formed and an element separation region adjacent to the element region, and the element separation region. Is a trench formed over the element separation region, an insulating film formed in the trench and separated from the inner surface of the trench, and a second insulating film formed on the upper surface of the insulating film. Includes gate electrodes and.

In the present invention, an element separation region for separating adjacent element regions is formed by the following procedure. That is, first, in the element separation region, a trench filled with an insulating film is formed at the boundary between the element separation region and the element region, and a gate electrode is formed on the upper surface of the insulating film.

Then, using the gate electrode formed on the upper surface of the insulating film as a mask, the portion of the insulating film filled in the trench that is in contact with the element region is removed, and then impurities are injected into the element region to form a diffusion layer. By forming and heat-treating, impurities contained in the diffusion layer are activated.

As a result, at the time of performing the above-mentioned heat treatment, the side wall of the element region and the side wall of the insulating film are separated from each other.

Therefore, even if high heat is applied to the insulating film and the element region having different coefficients of thermal expansion by such heat treatment, the stress from the side wall of the insulating film is not applied to the side wall of the element region. Therefore, according to the present invention, it is possible to prevent crystal defects in the device region and improve the yield.

It is a figure which shows the upper surface and the cross section of a semiconductor device 100. It is a flow chart which shows the manufacturing procedure of the semiconductor device 100. It is a flow chart which shows the manufacturing procedure of the semiconductor device 100. It is a process cross-sectional view at the initial stage of manufacturing in a semiconductor device 100. It is a process sectional view in the trench etching process S1. It is a process cross-sectional view in the trench oxide film forming step S2. It is a process sectional view in STI forming process S3. It is a process sectional view in the polysilicon forming process S4. It is a process sectional view in the gate electrode etching process S5. It is a process sectional view in the 1st LDD forming process S6. It is a process sectional view in the 2nd LDD forming process S7. It is a process sectional view in the insulating film forming step S8. It is a process sectional view in the sidewall etching process S9. It is a process sectional view in the oxide film removal step S10 in a trench. It is a process cross-sectional view in the mask oxide film forming step S11. It is a process sectional view in the trench burying process S12. It is a process sectional view in the 1st high-concentration diffusion layer formation step S13. It is a process sectional view in the 2nd high-concentration diffusion layer formation step S14. It is a process sectional view in the organic insulating film removal step S15 and the annealing step S16. It is a process sectional view in the insulation layer formation step S17. It is a process sectional view in the contact hole forming step S18. It is a process sectional view in the contact plug forming process S19. It is a process sectional view in the wiring layer formation step S20. It is a process sectional view in the wiring layer etching process S21. It is a flow figure which shows another example of the manufacturing procedure of a semiconductor device 100. It is a process cross-sectional view in the 1st mask oxide film forming process S101. It is a process sectional view in the 1st high-concentration diffusion layer formation step S102. It is a process sectional view in the 2nd high-concentration diffusion layer formation step S103. It is a process sectional view in the oxide film removal step S104 in a trench. It is a process cross-sectional view in the 2nd mask oxide film forming process S105.

Hereinafter, examples of the present invention will be described in detail.

FIG. 1A is a top view of a part of the semiconductor device 100 according to the present invention as viewed from above the element forming surface. FIG. 1B is a cross-sectional view taken along the line XX in FIG. 1A. Note that FIGS. 1 (a) and 1 (b) show the configuration of MOS (Metal Oxide Semiconductor) type transistors TR1 and TR2 adjacent to each other and the element separation region ISA of the STI structure.

As shown in FIG. 1 (b), the transistor TR1 is formed on a semiconductor substrate 10 made of, for example, Si (silicon), and is formed in a first conductive type (for example, p type) well 11 having a convex shape. It is formed.

As shown in FIG. 1B, a second conductive type (for example, n type) high-concentration diffusion layer 12d as a drain of the transistor TR1 and a second conductive type as a source of the transistor TR1 are formed on the upper surface of the well 11. The high-concentration diffusion layer 12s of the above is formed so as to be separated from each other. LDD (Lightly Doped Drain) layers 13d and 13s as a second conductive type low-concentration diffusion layer are formed between the high-concentration diffusion layers 12d and 12s on the upper surface of the well 11 so as to be separated from each other. ..

A gate electrode 15 made of polysilicon or the like is formed on the surface of the region between the LDD layers 13d and 13s on the upper surface of the well 11 via the gate oxide film 14. The side wall of the gate electrode 15 is covered with a sidewall 16 made of an insulating film or the like.

As described above, the drain (12d, 13d), the source (12s, 13s), the gate oxide film 14, and the gate electrode 15 are formed in the convex region of the well 11, that is, the first element region E1 shown in FIG. 1 (b). The transistor TR1 having the above is formed.

Further, the transistor TR2 is formed on the semiconductor substrate 10 described above, and is formed in a second conductive type (for example, n type) well 21 having a convex shape.

As shown in FIG. 1B, a first conductive type high-concentration diffusion layer 22d as a drain of the transistor TR2 and a first conductive type high-concentration diffusion layer as a source of the transistor TR2 are formed on the upper surface of the well 21. 22s and 22s are formed so as to be separated from each other. The first conductive type LDD layers 23d and 23s are formed so as to be separated from each other between the high-concentration diffusion layers 22d and 22s on the upper surface of the well 21.

A gate electrode 25 made of polysilicon or the like is formed on the surface of the region between the LDD layers 23d and 23s on the upper surface of the well 21 via the gate oxide film 24. The side wall of the gate electrode 25 is covered with a sidewall 26 made of an insulating film or the like.

As described above, the drain (22d, 23d), the source (22s, 23s), the gate oxide film 24, and the gate electrode 25 are formed in the convex region of the well 21, that is, the second element region E2 shown in FIG. 1 (b). A second transistor TR2 having the above is formed.

The element separation region ISA is adjacent to the element regions E1 and E2, and includes a trench 30 formed at a boundary between the element regions E1 and E2 and the element separation region ISA. An oxide film 31 is formed on the bottom of the trench 30. The oxide film 31 has a thickness in which the film thickness from the bottom of the trench 30 to the upper surface of the trench 30 corresponds to the height of the convex portion of the well 11 or 21. A gate electrode 35 is formed on the upper surface of the oxide film 31. The side wall of the gate electrode 35 is covered with a sidewall 36 made of an insulating film or the like.

The gate electrode 35 formed in the element separation region ISA is a spare electrode used for wiring for connecting elements, a capacitor electrode, or the like.

That is, the element separation region ISA is
The element regions E1 and E2 are electrically separated from each other, and wiring for connecting the elements, an electrode of a capacitor, and the like are provided.

As shown in FIG. 1B, the side wall of the oxide film 31 is separated from the side wall of any of the wells 11 and 12.

The surfaces of the wells (11, 21), the high-concentration diffusion layer (12d, 12s, 22d, 22s), the gate electrodes (15, 25, 35), the sidewalls (16, 26, 36) and the oxide film 31 are , As shown in FIG. 1 (b), it is covered with a mask oxide film 41. An insulating layer 51 that protects each element formed in the semiconductor device 100 is formed on the mask oxide film 41.

Each of the high-concentration diffusion layers 12d, 12s, 22d and 22s is a metal wiring layer 70 formed on the upper surface of the insulating layer 51 via a contact 65 penetrating the insulating layer 51 as shown in FIG. 1 (b). Is combined with. Further, each of the gate electrodes 15 and 25 is coupled to the metal wiring layer 70 formed on the upper surface of the insulating layer 51 via the contact 65 penetrating the insulating layer 51 (not shown). Further, the gate electrode 35 is also coupled to the metal wiring layer 70 formed on the upper surface of the insulating layer 51 via the contact 65 penetrating the insulating layer 51 (not shown).

The contact 65 includes a barrier metal 61 formed on the side surface and the bottom surface of the contact hole, and a metal plug 60 for filling the contact hole.

As shown in FIG. 1B, the contact 65 is coupled to the metal wiring layer 70 formed on the upper surface of the insulating layer 51. The metal wiring layer 70 is a lower barrier made of an upper barrier metal 71, a conductive member 72 made of an alloy such as Al (aluminum) -Cu (copper), and Ti (titanium) or TiN (titanium nitride). It has a laminated structure with metal 73. The lower barrier metal 73 is coupled to the contact 65.

Hereinafter, the manufacturing method of the semiconductor device 100 shown in FIG. 1 will be described along with the manufacturing flow shown in FIGS. 2 and 3.

In manufacturing the semiconductor device 100, as shown in FIG. 4, the oxide film 301 and the nitride film 302 are formed on the main surface of the semiconductor substrate 10 on which the first conductive type well 11 and the second conductive type well 21 are formed. Prepare a wafer in which is laminated. The oxide film 301 is a silicon thermal oxide film obtained by thermally oxidizing the upper surfaces of silicon of wells 11 and 21, for example, and the nitride film 302 is nitrided formed by, for example, a CVD (chemical vapor deposition) method. It is silicon.

First, the trench etching step S1 is executed on the wafer shown in FIG.

In the trench etching step S1, a photoresist is formed on the upper surface of the nitride film 302 other than the element separation region ISA. Then, for example, _{by dry etching using a mixed gas of Cl 2} (chlorine) and O ₂ (oxygen) or HBr (hydrogen bromide) and O ₂ , a trench 300 as shown in FIG. 5 is formed in the element separation region ISA. do.

Here, the convex region of the well 11 is the first element region E1, and the convex region of the well 21 is the second element region E2. Further, the region adjacent to these element regions E1 and E2 is the element separation region ISA.

Next, the trench oxide film forming step S2 is executed on the wafer shown in FIG.

In the trench oxide film forming step S2, first, a thermal oxide film is formed on the side walls of the wells 11 and 21 formed by the trench 300, that is, on the inner wall formed by the trench 300. Then, an oxide film made of, for example, SiO ₂ (silicon oxide) or the like is formed in the trench 300 and on the upper surface of the nitride film 302 by the CVD method. After that, the oxide film formed on the upper surface of the nitride film 302 is removed by polishing with CMP (chemical mechanical polishing) to form the oxide film 303 as shown in FIG.

Next, the STI forming step S3 is executed on the wafer shown in FIG.

In the STI forming step S3, first, the upper portion of the oxide film 303 in the trench 300 is removed by wet etching using HF (hydrofluoric acid), and the height of the oxide film 303 is adjusted. Next, the nitride film 302 exposed on the upper surface of the wafer is removed by wet etching using a phosphoric acid solution to form an STI in which the oxide film 303 is embedded in the trench 300, as shown in FIG. ..

Next, the polysilicon forming step S4 is executed on the wafer shown in FIG. 7.

In the polysilicon forming step S4, first, the oxide film 301 on the main surface of the semiconductor substrate 10 is removed by wet etching using HF (hydrofluoric acid), and the exposed main surface of the semiconductor substrate 10 is thermally oxidized. The gate oxide film 140 is formed at. Then, as shown in FIG. 8, a polysilicon film 304 is formed on the upper surfaces of the gate oxide film 140 and the oxide film 303 by the thermal CVD method.

Next, the gate electrode etching step S5 is executed on the wafer shown in FIG.

In the gate electrode etching step S5, a photoresist is formed in the region where the gate electrode is to be formed on the upper surface of the polysilicon film 304. Then, as shown in FIG. 9, the gate electrode 15 is formed on the well 11, the gate electrode 25 is formed on the well 21, and the gate electrode 35 is formed on the oxide film 303 by dry etching.

Next, the first LDD forming step S6 is executed on the wafer shown in FIG.

In the first LDD forming step S6, as shown in FIG. 10, the element forming region of the well 21, the upper surface of the oxide film 303, and the gate electrode 35 are covered with the resist 305. ^{Then, for example, P +} (phosphorus) or As ⁺ (arsenic) as a second conductive type impurity is implanted into the entire surface of the wafer by an ion implanter. As a result, as shown in FIG. 10, the LDD layer 306 as the second conductive type low-concentration diffusion layer is formed in the region not covered by the resist 305 and the gate electrode 15 on the upper surface portion of the well 11.

Next, the second LDD forming step S7 is executed on the wafer from which the resist 305 has been removed from the wafer shown in FIG.

In the second LDD forming step S7, as shown in FIG. 11, the element forming region of the well 11 is covered with resist 307, and the entire surface of the wafer is covered with, for example, B ⁺ (boron) as a first conductive type impurity by an ion implanter. ) Is injected. As a result, as shown in FIG. 11, the LDD layer 308 as the first conductive type low-concentration diffusion layer is formed in the region not covered by the resist 307 and the gate electrode 25 on the upper surface of the well 21.

Next, the insulating film forming step S8 is executed on the wafer from which the resist 307 has been removed from the wafer shown in FIG.

In the insulating film forming step S8, for example, _{by a CVD method using a mixed gas containing SiH 2} Cl ₂ (dichlorosilane) and NH ₃ (ammonia), as shown in FIG. 12, insulation containing silicon nitride over the entire surface of the wafer is performed. It forms a film 309.

Next, the sidewall etching step S9 is executed on the wafer shown in FIG.

In the sidewall etching step S9, the entire surface of the wafer is etched back by anisotropic dry etching. As a result, as shown in FIG. 13, a sidewall 16 is formed on the side wall of the gate electrode 15, a sidewall 26 is formed on the side wall of the gate electrode 25, and a sidewall 36 is formed on the side wall of the gate electrode 35, respectively.

Next, the oxide film removal step S10 in the trench is executed on the wafer shown in FIG.

In the trench oxide film removing step S10, the wafer shown in FIG. 13 is anisotropically dried using a mixed gas composed of _{, for example, C 4} F ₈ (octafluorocyclobutane), Ar (argon) and O _{2 (oxygen).} Etch. By this anisotropic dry etching, the portions of the oxide film 303 embedded in the trench 300 that are in contact with the wells 11 and 21 and the LDD layers 306 and 308 are formed by using the gate electrode 35 and the sidewall 36 as masks. Remove. Further, by this anisotropic dry etching, the portion of the oxide film 140 that is not masked by the gate electrodes 15 and 25 and the sidewalls 16 and 26 is removed.

As a result, as shown in FIG. 14, the portion of the oxide film 303 embedded in the trench 300 that has been removed by the anisotropic dry etching is left as a new trench 30 as shown in FIG. The portion becomes the oxide film 31. At this time, the side wall of the oxide film 31 and the side walls of the wells 11 and 21 are separated from each other by a trench 30.

Next, the mask oxide film forming step S11 is executed on the wafer shown in FIG.

In the mask oxide film forming step S11, as shown in FIG. 15, a mask oxide film 41 having a thickness of 100 to 200 angstroms _{, for example, SiO 2 or the like is formed on the entire surface of the wafer based on the CVD method.} The mask oxide film 41 protects the device from contamination by carbon contained in the organic insulating film described later.

Next, the trench burying step S12 is executed on the wafer shown in FIG.

In the trench burying step S12, first, an organic insulating material containing carbon is coated on the entire surface of the wafer by using a coating device such as a coater. Next, among the organic insulators deposited on the wafer surface, the organic insulators other than the organic insulators deposited on the trench 30 are removed by etching back by dry etching. As a result, as shown in FIG. 16, an organic insulating film 311 made of an organic insulating material is formed in the trench 30. When the organic insulating film 311 formed in the trench 30 is used to inject impurities in the following first high-concentration diffusion layer forming step S13 and second high-concentration diffusion layer forming step S14, the side wall of the trench 30 And the injection of impurities into the bottom surface is blocked.

Next, the first high-concentration diffusion layer forming step S13 is executed on the wafer shown in FIG.

In the first high-concentration diffusion layer forming step S13, as shown in FIG. 17, the element forming region of the well 21 is coated with the resist 312, and the entire surface of the wafer is covered with the ion implanter, for example, as a second conductive type impurity. Inject P ⁺ (phosphorus) or As ⁺ (arsenic). As a result, in the formed region of the LDD layer 306 formed in the well 11, as shown in FIG. 17, high-concentration impurities are injected into the portion not masked by the sidewall 16, and that portion is the high-concentration diffusion layer. It becomes 12d and 12s. On the other hand, in the formed region of the LDD layer 306, impurities are not injected into the portion masked by the sidewall 16, so that the portion becomes the LDD layers 13d and 13s as the low-concentration diffusion layer.

Next, the second high-concentration diffusion layer forming step S14 is executed on the wafer from which the resist 312 is removed from the wafer shown in FIG.

In the second high-concentration diffusion layer forming step S14, as shown in FIG. 18, the element forming region of the well 11 is coated with the resist 313, and the entire surface of the wafer is covered with the ion implanter, for example, as a first conductive type impurity. Inject B ⁺ (boron). As a result, in the formed region of the LDD layer 308 formed in the well 21, as shown in FIG. 18, high-concentration impurities are injected into the portion not masked by the sidewall 26, and that portion is the high-concentration diffusion layer. It becomes 22d and 22s. On the other hand, in the formed region of the LDD layer 308, impurities are not injected into the portion masked by the sidewall 26, so that the portion becomes the LDD layers 23d and 23s as the low-concentration diffusion layer.

Next, the organic insulating film removing step S15 is executed on the wafer from which the resist 313 has been removed from the wafer shown in FIG.

In the organic insulating film removing step S15, the organic insulating film 311 embedded in the trench 30 is removed as shown in FIG. 19 by ashing _{the surface of the wafer with O 2 plasma.}

Next, the annealing step S16 is executed on the wafer shown in FIG.

In the annealing step S16, heat of, for example, about 1000 degrees is applied to the wafer by, for example, lamp annealing. Thereby, the recovery of each of the high-concentration diffusion layers 12d, 12s, 22d and 22s and the LDD layers 13d, 13s, 23d and 23s damaged by the injection of impurities and the activation of impurities are aimed at.

Next, the insulating layer forming step S17 is executed on the wafer subjected to the annealing step S16.

In the insulating layer forming step S17, based on the CVD method, the insulating layer 51 made of a non-doped plasma oxide film such as an NSG (None-doped Silicate Glass) film is formed on the entire surface of the wafer including the inside of the trench 30 as shown in FIG. To form.

Next, the contact hole forming step S18 is executed on the wafer shown in FIG.

In the contact hole forming step S18, the insulating layer 51 is dry-etched using a resist covering a region other than the region of the contact 65 shown in FIG. 1 on the upper surface of the insulating layer 51 as a mask. As a result, contact holes 314 that expose the gate electrodes 15, 25, 35 and the high-concentration diffusion layers 12d, 12s, 22d, and 22s are formed as shown in FIG.

Next, the contact plug forming step S19 is executed on the wafer shown in FIG.

In the contact plug forming step S19, first, a barrier metal such as Ti (titanium) or TiN (titanium nitride) is formed over the entire surface of the wafer shown in FIG. As a result, the barrier metal 61 is formed on the inner wall of the insulating layer 51 formed by the contact holes 314, the gate electrodes 15, 25, 35 exposed by the contact holes 314, and the high-concentration diffusion layers 12d, 12s, 22d, and 22s. Next, tungsten, which is a refractory metal, is formed over the entire surface of the wafer. As a result, tungsten is formed in the contact holes 314, and a laminated film of the barrier metal 61 and the metal plug 60 is formed in each contact hole 314. Then, the tungsten and titanium formed on the upper surface of the insulating layer 51 are removed by polishing with CMP or etching back. As a result, a contact plug is formed in the contact hole 314 as shown in FIG.

Next, the wiring layer forming step S20 is executed on the wafer shown in FIG.

In the wiring layer forming step S20, as shown in FIG. 23, a lower barrier metal 73 made of, for example, Ti (titanium) or TiN (titanium nitride), for example, Al—Cu (aluminum, copper) is placed on the upper surface of the insulating layer 51 by sputtering. ) And other conductive members 72 and the upper barrier metal layer 71 are laminated.

Next, the wiring layer etching step S21 is executed on the wafer shown in FIG. 23.

In the wiring layer etching step S21, the region corresponding to the metal wiring is masked with a resist on the upper surface of the barrier metal layer 71, and the upper barrier metal layer 71, the conductive member 72, and the lower barrier metal 73 are etched. As a result, as shown in FIG. 24, a metal wiring layer 70 having a laminated structure of the upper barrier metal layer 71, the conductive member 72, and the lower barrier metal 73 is formed on the upper surface of the insulating layer 51.

By performing the series of steps (S1 to S21) shown in FIGS. 2 and 3 on the wafer in this way, the semiconductor device 100 shown in FIGS. 1 (a) and 1 (b) is manufactured.

According to such a manufacturing method, when the annealing step S16 is executed, as shown in FIG. 19, a trench 30 is formed between the side wall of the insulating film 31 formed in the element separation region ISA and the side wall of each of the wells 11 and 21. Spatially separated by.

Therefore, in the annealing step S16, even if high heat is applied to the insulating films 31 and the wells 11 and 12 having different coefficients of thermal expansion, stress from the side walls of the insulating film 31 is applied to the side walls of the wells 11 and 21 respectively. It doesn't hang. Therefore, since crystal defects in the wells 11 and 12 can be prevented, the yield can be improved.

In the above embodiment, the sidewalls (16, 26, 36) are formed (FIGS. 13, S9), the trench 30 is formed (FIGS. 14, S10), and then the high-concentration diffusion layer is formed (FIG. 17, S9). 18, S13, S14).

However, after the above-mentioned sidewalls (16, 26, 36) are formed, the high-concentration diffusion layer may be formed before the trench 30 is formed.

FIG. 25 is a manufacturing flow chart showing another example of the manufacturing method of the semiconductor device 100, which was made in view of the above points. In another example, the steps S101 to S105 described below are executed instead of the steps S10 to S15 shown in FIG. 3, and the other steps S1 to S9 and S16 to S21 are described above. Is the same as.

Therefore, steps S101 to S105 shown in FIG. 25 are extracted below to explain another example of the method for manufacturing the semiconductor device 100.

That is, after executing the sidewall etching step S9 shown in FIG. 2, the first mask oxide film forming step S101 is executed on the wafer shown in FIG.

In the first mask oxide film forming step S101, as shown in FIG. 26, a mask oxide film 401 made of _{, for example, SiO 2 is formed on the entire surface of the wafer based on the CVD method.} The mask oxide film 401 prevents crystal defects due to impurity injection in the high-concentration diffusion layer forming step described later.

Next, the first high-concentration diffusion layer forming step S102 is executed on the wafer shown in FIG. 26.

In the first high-concentration diffusion layer forming step S102, as shown in FIG. 27, the element forming region of the well 21 is coated with the resist 402, and the entire surface of the wafer is covered with, for example, P as a second conductive type impurity by an ion implanter. ^{Inject +} (phosphorus) or As ⁺ (arsenic). As a result, in the formed region of the LDD layer 306 formed in the well 11, high-concentration impurities are injected into the portion not masked by the sidewall 16 as shown in FIG. 27, and that portion is the high-concentration diffusion layer 12d. And 12s. On the other hand, in the formed region of the LDD layer 306, impurities are not injected into the portion masked by the sidewall 16, so that the portion becomes the LDD layers 13d and 13s as the low-concentration diffusion layer.

Next, the second high-concentration diffusion layer forming step S103 is executed on the wafer from which the resist 402 has been removed from the wafer shown in FIG. 27.

In the second high-concentration diffusion layer forming step S103, as shown in FIG. 28, the element forming region of the well 11 is coated with the resist 403, and the entire surface of the wafer is covered with, for example, B as a first conductive type impurity by an ion implanter. ⁺ Inject (boron). As a result, in the formed region of the LDD layer 308 formed in the well 21, high-concentration impurities are injected into the portion not masked by the sidewall 26 as shown in FIG. 28, and that portion is the high-concentration diffusion layer. It becomes 22d and 22s. On the other hand, in the formed region of the LDD layer 308, impurities are not injected into the portion masked by the sidewall 26, so that the portion becomes the LDD layers 23d and 23s as the low-concentration diffusion layer.

Next, the oxide film removal step S104 in the trench is executed on the wafer from which the resist 403 has been removed from the wafer shown in FIG. 28.

In the trench oxide film removing step S104, the wafer is dry-etched using, for example, a mixed gas composed of _{C 4} F ₈ (octafluorocyclobutane), Ar (argon) and O _{2 (oxygen).} By this anisotropic dry etching, the portions of the oxide film 303 embedded in the trench 300 that are in contact with the wells 11 and 21 and the LDD layers 306 and 308 are formed by using the gate electrode 35 and the sidewall 36 as masks. Remove. Further, the anisotropic dry etching removes a part of the oxide film 140 together with the masked oxide film 401, that is, a part not masked by the gate electrodes 15, 25, sidewalls 16 and 26.

As a result, as shown in FIG. 29, the portion of the oxide film 303 embedded in the trench 300 that has been removed by the anisotropic dry etching becomes a new trench 30 as shown in FIG. 29. The remaining portion becomes the oxide film 31. At this time, the side wall of the oxide film 31 and the side walls of the wells 11 and 21 are separated from each other by a trench 30.

Next, the second mask oxide film forming step S105 is executed on the wafer shown in FIG. 29.

In the second mask oxide film forming step S105, as shown in FIG. 30, a mask oxide film 41 having a thickness of 100 to 200 angstroms _{, for example, SiO 2 or the like is formed on the entire surface of the wafer based on the CVD method.}

Then, after the execution of the second mask oxide film forming step S105, the annealing step S16, the insulating layer forming step S17, the contact hole forming step S18, the contact plug forming step S19, and the wiring layer forming step S20 described above are similarly performed in FIG. Are executed sequentially.

Therefore, also in the manufacturing method shown in FIG. 25, as in the manufacturing method shown in FIG. 3, when the annealing step S16 is executed, as shown in FIG. 30, between the side wall of the insulating film 31 and the side walls of the wells 11 and 21 respectively. Are spatially separated by a trench 30.

Therefore, in the annealing step S16, even if high heat is applied to the insulating films 31 and the wells 11 and 12 having different coefficients of thermal expansion, stress from the side walls of the insulating film 31 is applied to the side walls of the wells 11 and 21 respectively. It doesn't hang. As a result, crystal defects in the wells 11 and 12 can be prevented, so that the yield can be improved.

Further, in the manufacturing method shown in FIG. 25, the oxide film removing step S104 in the trench for removing the oxide film 303 embedded in the trench 300 is performed in the first and second high-concentration diffusion layer forming steps S102 and the second high-concentration diffusion layer forming step S102 for forming the high-concentration diffusion layer. It is executed after S103.

This eliminates the need for burying and removing 311 of the organic insulating film (S12, S15) required by the manufacturing method shown in FIG. 3, and up to the high-concentration diffusion layer forming step (S102, S103), conventional manufacturing. It becomes possible to adopt the method. Therefore, it is possible to reduce the time required for changing from the conventional manufacturing method to the manufacturing method shown in FIG. 25.

In the above embodiment, for example, the trench 300 is filled with the oxide film 303 made of silicon oxide, but the trench 300 may be filled with an insulating film made of an insulating material other than silicon oxide.

In short, the method for manufacturing the semiconductor device according to the present invention may be any one that executes the following first to sixth steps.

That is, in the first step (S1), a trench (300) is formed at the boundary of the element regions (11, 21) of the semiconductor. In the second step (S2), the trench is filled with the insulating film (303). In the third step (S4, S5), the first gate electrode (15, 25) is formed on the upper surface of the element region, and the second gate electrode (35) is formed on the upper surface of the insulating film. In the fourth step (S10), the portion of the insulating film filled in the trench that is in contact with the element region is removed by using the second gate electrode (35) formed on the upper surface of the insulating film as a mask. In the fifth step (S13, S14), impurities are injected into the device region to form a diffusion layer (12d, 12s, 22s, 22d). In the sixth step (S16), impurities contained in the diffusion layer are activated by heat-treating the element region.

Further, instead of the fourth step (S10), the fourth step (S102, S103) of injecting impurities into the element region to form the diffusion layer (12d, 12s, 22s, 22d) is executed, and the above. Instead of the fifth step (S13, S14), the fifth step (S104) of removing the portion (30) of the insulating film filled in the trench in contact with the element region is executed.

11, 21 wells 12d, 12s, 22d, 22s High concentration diffusion layer 15, 25, 35 Gate electrode 30, 300 Trench 31, 303 Oxidation film 100 Semiconductor device ISA Element separation region TR1, TR2 Transistor

Claims (7)

The first step of forming a trench at the boundary of the semiconductor device region,
The second step of filling the trench with the insulating film and
A third step of forming the first gate electrode on the upper surface of the element region and forming the second gate electrode on the upper surface of the insulating film.
A fourth step of removing a portion of the insulating film filled in the trench that is in contact with the element region, using the second gate electrode formed on the upper surface of the insulating film as a mask.
The fifth step of injecting impurities into the device region to form a diffusion layer, and
A method for manufacturing a semiconductor device, which comprises a sixth step of activating the impurities contained in the diffusion layer by subjecting the element region to heat treatment. Following the fourth step, the organic insulating material is embedded in the region containing a part of the insulating film removed in the fourth step in the trench, and then the fifth step is executed.
The method for manufacturing a semiconductor device according to claim 1, wherein following the fifth step, the organic insulating material is removed and then the sixth step is executed. Following the third step, the fourth step is executed after forming sidewalls on each of the first gate electrode and the second gate electrode.
In the fourth step, anisotropic etching is performed using each of the first gate electrode, the second gate electrode, and the sidewall as a mask, and the element region in the insulating film is subjected to anisotropic etching. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the contacting portion is removed. The first gate electrode and the second gate electrode contain polysilicon.
The method for manufacturing a semiconductor device according to claim 3, wherein the sidewall contains silicon nitride. The device region contains silicon and
The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein in the second step, silicon oxide is filled in the trench as the insulating film. The first step of forming a trench at the boundary of the semiconductor device region,
The second step of filling the trench with the insulating film and
A third step of forming the first gate electrode on the upper surface of the element region and forming the second gate electrode on the upper surface of the insulating film.
The fourth step of injecting impurities into the device region to form a diffusion layer, and
A fifth step of removing a portion of the insulating film filled in the trench that is in contact with the element region, using the second gate electrode formed on the upper surface of the insulating film as a mask.
A method for manufacturing a semiconductor device, which comprises a sixth step of activating the impurities contained in the diffusion layer by subjecting the element region to heat treatment. The element region where the first gate electrode and diffusion layer are formed, and
It has a semiconductor substrate including an element separation region adjacent to the element region.
The element separation region is
A trench formed over the element separation region and
An insulating film formed in the trench and separated from the inner surface of the trench,
A semiconductor device including a second gate electrode formed on the upper surface of the insulating film.

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