JP5181710B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of performing ion implantation on a semiconductor substrate.

A semiconductor device manufacturing process may include a step of forming an ion implantation region by performing ion implantation on a semiconductor substrate. In general, the ion implantation region is formed by forming an ion implantation mask that can define the region into which ions are implanted by forming an opening in an implantation blocking layer that blocks ion implantation. Implemented. By forming an appropriate ion implantation mask, it becomes easy to form a desired ion implantation region, which contributes to the stability of the characteristics of the semiconductor device. For this reason, conventionally, many studies have been made on the formation of an ion implantation mask, and various techniques have been proposed (see, for example, Patent Document 1).
JP 2006-332180 A

  In the above-described step of forming the ion implantation region, a plurality of ion implantation regions having different implantation amounts and ion types are often formed adjacent to each other. The relative positional relationship between adjacent ion implantation regions (positioning accuracy of ion implantation regions) greatly affects the characteristics of the manufactured semiconductor device. On the other hand, in recent years, with the progress of higher integration of circuits in which semiconductor devices are used, semiconductor devices are increasingly required to be miniaturized. Therefore, further improvement in the alignment accuracy of the ion implantation region is required.

  More specifically, for example, when ion implantation regions having different conductivity types are formed adjacent to each other, an ion implantation mask for forming one ion implantation region is first formed and ion implantation is performed. After the ion implantation mask is removed, an ion implantation mask for forming the other ion implantation region is newly formed, and further ion implantation is performed. Here, the alignment error of each ion implantation mask is, for example, about 0.5 μm. For this reason, the alignment errors of the adjacent ion implantation regions formed using these ion implantation masks (relative positional relationship errors) are accumulated by the alignment errors of the two ion implantation masks, and the maximum is 1 μm. It will be about. In view of the recent demand for improvement in alignment accuracy, this alignment error is not necessarily small enough, and is a factor that hinders the stability of the characteristics of the semiconductor device.

  Therefore, an object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device having stable characteristics by suppressing an alignment error of an ion implantation region.

  A method of manufacturing a semiconductor device according to the present invention includes a step of preparing a semiconductor substrate, a step of forming a first implantation blocking layer for blocking ion implantation on the semiconductor substrate, and a plurality of layers in the first implantation blocking layer. A step of forming a through hole, a step of forming a second implantation blocking layer that blocks ion implantation by closing the plurality of through holes, and a second step of closing at least one through hole of the plurality of through holes. And a step of removing the injection blocking layer. Furthermore, in the method of manufacturing a semiconductor device according to the present invention, the first ion implantation is performed on the semiconductor substrate through the at least one through hole, and the at least one through hole is closed. Forming a third injection blocking layer for blocking injection, and removing a second injection blocking layer for closing at least one other through hole different from the at least one through hole among the plurality of through holes. And a step of performing second ion implantation on the semiconductor substrate through the at least one other through hole.

  In the method for manufacturing a semiconductor device according to the present invention, regions where ion implantation regions are formed by the first ion implantation and the second ion implantation are formed in separate implantation blocking layers for performing the respective ion implantations. It is not defined by the opening, but is defined by a plurality of through holes formed in the first injection blocking layer. That is, in the method of manufacturing a semiconductor device of the present invention, when forming a plurality of ion implantation regions, a single implantation blocking layer is not formed, but a single implantation blocking layer is formed. A region in which an ion implantation region is formed is defined by a plurality of through holes formed in the implantation blocking layer. Therefore, errors that occur in the production of the injection blocking layer a plurality of times and the formation of openings in the injection blocking layer do not accumulate. As a result, according to the method for manufacturing a semiconductor device of the present invention, a semiconductor device having stable characteristics can be manufactured by suppressing the alignment error of the ion implantation region.

  In the method for manufacturing a semiconductor device, preferably, the second injection blocking layer is a tungsten film made of tungsten.

  Tungsten (W) is excellent in heat resistance, so that not only ion implantation at a high temperature is possible, but also high density, so that ion implantation can be effectively prevented even when the film thickness is small. Therefore, the semiconductor device manufacturing method of the present invention can be easily implemented by adopting the tungsten film as the second implantation blocking layer.

  Preferably, in the method for manufacturing a semiconductor device, the third implantation blocking layer is a tungsten film made of tungsten.

  Similarly to the second injection blocking layer, the method for manufacturing a semiconductor device of the present invention can be easily carried out by using the third injection blocking layer as a tungsten film.

  Preferably, in the method for manufacturing the semiconductor device, the tungsten film has a thickness of 0.4 μm or more and 2 μm or less, which is thinner than the thickness of the first implantation blocking layer.

  When the thickness of the tungsten film is less than 0.4 μm, ion implantation may not be effectively prevented. On the other hand, if the thickness of the tungsten film exceeds 2 μm, the subsequent removal may be difficult, or it may take a long time for the removal. Further, when the thickness of the tungsten film is equal to or greater than the thickness of the first injection blocking layer, the through hole formed in the first injection blocking layer is completely filled with the tungsten film, and further, the tungsten extends to the outside of the through hole. The formation of a film cannot be avoided, which may adversely affect the subsequent processes. On the other hand, by making the thickness of the tungsten film 0.4 μm or more and 2 μm or less and making it thinner than the thickness of the first implantation blocking layer, the subsequent removal can be easily performed while effectively blocking the ion implantation. It is possible to suppress adverse effects on subsequent processes.

  Preferably, in the semiconductor device manufacturing method, the tungsten film is formed by a CVD (Chemical Vapor Deposition) method. Thereby, it becomes easy to selectively form a tungsten film in the through hole.

  Preferably, in the method for manufacturing a semiconductor device, the first injection blocking layer is composed of at least one selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

  A tungsten film is difficult to be formed on the silicon oxide film, the silicon nitride film, and the silicon oxynitride film. Therefore, the second injection blocking layer in which the tungsten film is employed by forming the first injection blocking layer from at least one selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In addition, it is possible to suppress the third injection blocking layer from being formed in a region other than the through hole, and it is possible to suppress adverse effects on subsequent processes.

  In the method for manufacturing the semiconductor device, preferably, the thickness of the first injection blocking layer is not less than 1 μm and not more than 5 μm.

  When at least one selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film is employed as the first implantation blocking layer, ion implantation is effective when the thickness of the first implantation blocking layer is less than 1 μm. There is a risk that it cannot be prevented. On the other hand, if the thickness of the first injection blocking layer exceeds 5 μm, it may be difficult to form the through hole in the first injection blocking layer. Therefore, the thickness of the first injection blocking layer is preferably 1 μm or more and 5 μm or less.

  Preferably, in the method for manufacturing the semiconductor device, in the step of removing the second injection blocking layer, the second injection blocking layer is removed by etching using a gas containing at least one of sulfur hexafluoride and chlorine.

When at least one selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film is employed as the first injection blocking layer, at least one of sulfur hexafluoride (SF ₆ ) and chlorine (Cl) In the etching using the gas containing the first injection blocking layer, it is difficult to etch. As a result, the second injection blocking layer can be easily removed by selective etching, and the semiconductor device manufacturing method of the present invention can be easily implemented.

  Preferably, in the manufacturing method of the semiconductor device, after the step of preparing the semiconductor substrate and before the step of forming the first injection blocking layer, a simple substance of titanium, a simple substance of tantalum, and The method further includes the step of forming a first intermediate layer including at least one selected from the group consisting of compounds containing at least one of titanium and tantalum.

  As a result, at least one selected from the group consisting of a simple substance of titanium (Ti) or tantalum (Ta) and a compound containing at least one of Ti or Ta is provided between the semiconductor substrate and the first injection blocking layer. A first intermediate layer containing is formed. The first intermediate layer can function as an adhesion layer that is in close contact with the semiconductor substrate, and can also function as an etching stop layer when the through hole is formed in the first injection element layer. Therefore, according to the above configuration, ion implantation is effectively blocked by the second implantation blocking layer and the third implantation blocking layer, and damage to the semiconductor substrate when the through hole is formed in the first implantation element layer is suppressed. can do.

  Preferably, in the method for manufacturing a semiconductor device, the thickness of the first intermediate layer is not less than 5 nm and not more than 100 nm. If the thickness of the first intermediate layer is less than 5 nm, it is difficult to form the first intermediate layer uniformly, and a region where the first intermediate layer is not formed may be formed on the semiconductor substrate. On the other hand, if the thickness of the first intermediate layer exceeds 100 nm, the accuracy of ion implantation may be reduced. Therefore, the thickness of the first intermediate layer is preferably 5 nm or more and 100 nm or less.

  Preferably, in the method of manufacturing a semiconductor device, the first injection blocking is performed on the side wall and the through hole of the through hole after the step of forming the through hole and before the step of forming the second injection blocking layer. Forming an intermediate layer including at least one selected from the group consisting of a simple substance of titanium, a simple substance of tantalum, and a compound containing at least one of titanium and tantalum on a semiconductor substrate exposed from the layer; It has more.

  The second intermediate layer including at least one selected from the group consisting of a simple substance of Ti, a simple substance of Ta, and a compound containing at least one of Ti or Ta is a through hole of the semiconductor substrate and the first injection blocking layer. It can function as an adhesion layer that is in close contact with the inner wall. Therefore, according to the above configuration, ion implantation is effectively blocked by the second implantation blocking layer and the third implantation blocking layer.

  Preferably in the method for manufacturing a semiconductor device, the thickness of the second intermediate layer is not less than 5 nm and not more than 100 nm. If the thickness of the second intermediate layer is less than 5 nm, it is difficult to form the second intermediate layer uniformly, and the second intermediate layer is formed on the side wall of the through hole and the semiconductor substrate exposed from the first injection blocking layer in the through hole. There is a possibility that a region where no layer is formed is formed. On the other hand, if the thickness of the second intermediate layer exceeds 100 nm, the dimensional accuracy of the semiconductor device may be reduced. Therefore, the thickness of the second intermediate layer is preferably 5 nm or more and 100 nm or less.

  In the semiconductor device manufacturing method, the second intermediate layer is preferably formed by a CVD method. By employing the CVD method, the second intermediate layer can be easily formed on the semiconductor substrate exposed from the first injection blocking layer in the side wall of the through hole and the through hole.

  Preferably, in the semiconductor device manufacturing method, the first ion implantation and the plurality of ion implantation regions formed by the second ion implantation are electrically connected after the step of performing the second ion implantation. The method further includes the step of simultaneously forming a plurality of electrodes.

  Thereby, the characteristics of the semiconductor device can be further stabilized. Note that the plurality of electrodes are more preferably formed using a single mask. Thereby, the characteristics of the semiconductor device can be further stabilized.

  In the method for manufacturing a semiconductor device, preferably, the electrode includes at least one of nickel and a compound containing nickel.

  An electrode including at least one of nickel and a nickel-containing compound can ensure ohmic contact with both a p-type region whose conductivity type is p-type and an n-type region whose conductivity type is n-type. It is suitable as the electrode.

  Preferably, in the semiconductor device manufacturing method, the region of the semiconductor substrate on which the first ion implantation and the second ion implantation are performed is made of silicon carbide.

  Since the diffusion coefficient of impurities in silicon carbide (SiC) is small, it is preferable to introduce impurities by ion implantation in order to form a region having a different impurity concentration from the surroundings in a region made of SiC. Therefore, the method for manufacturing a semiconductor device of the present invention is particularly suitable when the region of the semiconductor substrate on which the first ion implantation and the second ion implantation are performed is made of SiC.

  As is apparent from the above description, according to the method for manufacturing a semiconductor device of the present invention, a semiconductor device with stable characteristics can be manufactured by suppressing the alignment error of the ion implantation region.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view showing the configuration of a junction field effect transistor (JFET) as a semiconductor device according to the first embodiment which is an embodiment of the present invention. With reference to FIG. 1, the configuration of a JFET as a semiconductor device in the first embodiment will be described.

  Referring to FIG. 1, JFET 1 is made of SiC and has an n-type substrate 11 having a conductivity type of n-type, a first p-type layer 12 formed on n-type substrate 11, and a first p-type. An n-type layer 13 formed on the layer 12 and a second p-type layer 14 formed on the n-type layer 13 are provided. The n-type substrate 11, the first p-type layer 12, the n-type layer 13 and the second p-type layer 14 constitute an SiC substrate 10 as a semiconductor substrate. Here, the p-type layer and the n-type layer are layers made of SiC whose conductivity types are p-type and n-type, respectively.

  The second p-type layer 14 and the n-type layer 13 include the first n-type region 15 and the second n-type region 15 containing impurities (n-type impurities) having a higher conductivity type than the n-type layer 13. The n-type region 17 is formed and has a higher concentration than the first p-type layer 12 and the second p-type layer 14 so as to be sandwiched between the first n-type region 15 and the second n-type region 17. A first p-type region 16 containing an impurity having a p-type conductivity (p-type impurity) is formed. That is, the first n-type region 15, the first p-type region 16, and the second n-type region 17 are formed so as to penetrate the second p-type layer 14 and reach the n-type layer 13. Yes. The bottoms of the first n-type region 15, the first p-type region 16, and the second n-type region 17 are the upper surfaces of the first p-type layer 12 (the first p-type layer 12 and the n-type region). It is arranged at a distance from the boundary portion with the layer 13.

  Further, on the side opposite to the first p-type region 16 when viewed from the first n-type region 15, the upper surface 14A of the second p-type layer 14 (the main surface on the side opposite to the n-type layer 13 side) is provided. A groove portion 31 is formed so as to penetrate the second p-type layer 14 from the surface to the n-type layer 13. That is, the bottom wall 31 </ b> A of the groove portion 31 is located inside the n-type layer 13 at a distance from the interface between the first p-type layer 12 and the n-type layer 13. Furthermore, p having a higher concentration than the first p-type layer 12 and the second p-type layer 14 so as to penetrate the n-type layer 13 from the bottom wall 31A of the groove 31 and reach the first p-type layer 12. A second p-type region 23 containing a type impurity is formed. The bottom of the second p-type region 23 is arranged at a distance from the upper surface of the n-type substrate 11 (the boundary between the n-type substrate 11 and the first p-type layer 12). First n-type region 15, first p-type region 16, second n-type region 17, and second p-type region 23 are ions formed by performing ion implantation on SiC substrate 10. This is an injection region.

  Furthermore, the source electrode 19, the gate electrode 21, and the upper surface of the first n-type region 15, the first p-type region 16, the second n-type region 17, and the second p-type region 23 are contacted. A drain electrode 22 and a potential holding electrode 24 are respectively formed. The source electrode 19, the gate electrode 21, the drain electrode 22, and the potential holding electrode 24 are respectively a first n-type region 15, a first p-type region 16, a second n-type region 17, and a second p-type region 23. It is made of a material that can be in ohmic contact with, for example, NiSi (nickel silicide).

  An oxide film 18 is formed between the source electrode 19, the gate electrode 21, the drain electrode 22, and the potential holding electrode 24, which are electrodes, and other adjacent electrodes. More specifically, the oxide film 18 as an insulating film is formed on the upper surface 14A of the second p-type layer 14, the bottom wall 31A and the side wall 31B of the groove 31, and the source electrode 19, the gate electrode 21, the drain electrode 22 and It is formed so as to cover the entire region other than the region where the potential holding electrode 24 is formed. Thereby, the adjacent electrodes are insulated from each other.

  Further, a source wiring 25, a gate wiring 26 and a drain wiring 27 are formed so as to be in contact with the upper surfaces of the source electrode 19, the gate electrode 21 and the drain electrode 22, and are electrically connected to the respective electrodes. The source wiring 25 is also in contact with the upper surface of the potential holding electrode 24 and is also electrically connected to the potential holding electrode 24. That is, the source wiring 25 is formed so as to extend from the upper surface of the source electrode 19 to the upper surface of the potential holding electrode 24, so that the potential holding electrode 24 has the same potential as the source electrode 19. Is held in. Source wiring 25, gate wiring 26 and drain wiring 27 are made of a conductor such as aluminum (Al), for example.

  Next, the operation of JFET 1 will be described. Referring to FIG. 1, in a state where the voltage of gate electrode 21 is 0 V, in n-type layer 13, a region sandwiched between first p-type region 16 and second n-type region 17 and the sandwiched portion The region sandwiched between the region and the first p-type layer 12 (drift region) and the region sandwiched between the first p-type region 16 and the first p-type layer 12 (channel region) are depleted. However, the first n-type region 15 and the second n-type region 17 are electrically connected via the n-type layer 13. Therefore, a current flows as electrons move from the first n-type region 15 toward the second n-type region 17.

  On the other hand, when a negative voltage is applied to the gate electrode 21, depletion of the channel region and the drift region proceeds, and the first n-type region 15 and the second n-type region 17 are electrically connected to each other. It is in a blocked state. For this reason, electrons cannot move from the first n-type region 15 toward the second n-type region 17 and no current flows.

  Next, a method for manufacturing JFET 1 as a semiconductor device in the first embodiment will be described. FIG. 2 is a flowchart showing an outline of a method for manufacturing a JFET which is a semiconductor device according to the first embodiment which is an embodiment of the present invention. 3 to 16 are schematic cross-sectional views for explaining the method of manufacturing the JFET in the first embodiment.

Referring to FIG. 2, in the method of manufacturing JFET 1 in the present embodiment, first, a substrate preparation step is performed as a step (S10). Specifically, in step (S10), as shown in FIG. 3, an n-type substrate 11 made of SiC containing high-concentration n-type impurities is prepared, and on one main surface of the n-type substrate 11, For example, the first p-type layer 12, the n-type layer 13, and the second p-type layer 14 made of SiC are sequentially formed by vapor phase epitaxial growth. In vapor phase epitaxial growth, for example, silane (SiH ₄ ) gas and propane (C ₃ H ₈ ) gas can be used as a material gas, and hydrogen (H ₂ ) gas can be used as a carrier gas. Further, as a p-type impurity source for forming a p-type layer, for example, diborane (B ₂ H ₆ ) or trimethylaluminum (TMA) is used, and as an n-type impurity for forming an n-type layer, for example, nitrogen ( N ₂ ) can be employed. Through the above procedure, SiC substrate 10 as a semiconductor substrate in which first p-type layer 12, n-type layer 13 and second p-type layer 14 are formed on n-type substrate 11 is prepared.

Next, with reference to FIG. 2, a groove part formation process is implemented as process (S20). Specifically, in the step (S20), as shown in FIG. 4, the upper surface 14A of the second p-type layer 14 penetrates the second p-type layer 14 and reaches the n-type layer 13. A groove 31 is formed. The groove 31 is formed by, for example, forming a mask layer having an opening at a position where the desired groove 31 is formed on the upper surface 14A of the second p-type layer 14, and then performing dry etching using SF ₆ gas. Can do.

Next, with reference to FIG. 2, a 1st injection | pouring prevention layer formation process is implemented as process (S30). Specifically, in the step (S30), as shown in FIG. 5, the first injection blocking layer 32 made of, for example, SiO ₂ that is a silicon oxide film fills the groove 31 and the second p-type layer 14. Is formed so as to cover the entire upper surface 14A. The formation of the first injection blocking layer 32 can be performed by, for example, a CVD method. The thickness of the first injection blocking layer 32 can be set to, for example, about 2.5 μm. As a result, a first implantation blocking layer 32 that blocks ion implantation is formed on SiC substrate 10. As will be described later, when W (tungsten) is adopted as the second injection blocking layer, the material of the first injection blocking layer 32 may be SiON, SiN, etc. in addition to the above-described SiO ₂ .

  Next, with reference to FIG. 2, a through-hole formation process is implemented as process (S40). Specifically, in step (S40), as shown in FIG. 6, the first n-type region 15, the first p-type region 16, the second n-type region 17, and Through holes 32B, 32C, 32D, and 32A are formed at positions corresponding to regions where the second p-type region 23 is to be formed (see FIG. 1). The through holes 32B, 32C, 32D and 32A can be formed as follows, for example.

First, a resist is applied on the first injection blocking layer 32 formed in the step (S30), and exposure and development are performed, so that openings are formed at positions corresponding to desired through holes 32B, 32C, 32D, and 32A. A resist layer (mask layer) is formed. Then, using the resist layer as a mask, for example, by RIE (Reactive Ion Etching) using a mixed gas of CF ₄ (carbon tetrafluoride) and CHF ₃ (methane trifluoride) as an etching gas. Dry etching is performed to form the through holes 32B, 32C, 32D and 32A. Then, after the etching is completed, the resist layer is removed. Through the above procedure, the first n-type region 15, the first p-type region 16, the second n-type region 17, and the second p-type region 23 are to be formed in the first injection blocking layer 32. A plurality of through holes 32B, 32C, 32D, and 32A are formed to expose the upper surface 14A of the second p-type layer 14 at a position corresponding to.

  Next, referring to FIG. 2, as a step (S50), a second injection blocking layer forming step is performed. Specifically, in the step (S50), as shown in FIG. 7, on the upper surface 14A of the second p-type layer 14 exposed from the through holes 32B, 32C, 32D and 32A, the through holes 32B, 32C, A second injection blocking layer 33, which is a W film made of W (tungsten), is formed so as to partially fill 32D and 32A. That is, the second injection blocking layer 33 thinner than the thickness of the first injection blocking layer 32 is formed on the upper surface 14A of the second p-type layer 14 exposed from the through holes 32B, 32C, 32D and 32A. Here, the second injection blocking layer 33 is selectively formed on the upper surface 14A of the second p-type layer 14 exposed from the through holes 32B, 32C, 32D and 32A, for example, by employing a CVD method. can do. The thickness of the second injection blocking layer 33 can be set to, for example, about 0.8 μm. By the above procedure, the second implantation blocking layer 33 that blocks ion implantation by closing all of the plurality of through holes 32B, 32C, 32D, and 32A is formed.

  Next, with reference to FIG. 2, a 1st through-hole opening process is implemented as process (S60). Specifically, in the step (S60), as shown in FIG. 8, the second injection blocking layer 33 that closes the plurality of through holes 32B, 32C, 32D, and 32A formed in the step (S50) is penetrated. The second injection blocking layer 33 that closes the holes 32B and 32D is removed, and the through holes 32B and 32D are opened. The removal of the second injection blocking layer 33 can be performed, for example, as follows.

First, a resist is applied to fill the through holes 32B, 32C, 32D, and 32A and cover the entire upper surface of the first injection blocking layer 32 to form a resist film 34. Thereafter, exposure and development are performed to form an opening 34A in the resist film 34 so as to overlap the entire through holes 32B and 32D in a plan view and not to overlap the through holes 32A and 32C. Then, the resist film 34 in which the opening 34A is formed is used as a mask, and the second injection blocking layer 33 that closes the through holes 32B and 32D is removed by dry etching using, for example, SF ₆ as an etching gas. Note that Cl ₂ (chlorine), CCl ₄ (carbon tetrachloride), BCl ₃ (boron trichloride), or the like may be employed as the etching gas.

Next, with reference to FIG. 2, a 1st ion implantation process is implemented as process (S70). Specifically, in step (S70), referring to FIG. 8, after the resist film 34 used in the above step (S60) is removed, as shown in FIG. By using second implantation blocking layer 33 as a mask, ions are implanted into n-type layer 13 and second p-type layer 14 through through holes 32B and 32D opened in step (S60). The ion species to be implanted can be, for example, P (phosphorus), N (nitrogen), As (arsenic), or the like. Further, the dose amount can be set to, for example, about 2 × 10 ¹⁴ cm ⁻² . Thereby, a first n-type region 15 and a second n-type region 17 that penetrate through the second p-type layer 14 and reach the n-type layer 13 are formed.

  Next, with reference to FIG. 2, a 3rd injection | pouring prevention layer formation process is implemented as process (S80). Specifically, in the step (S80), as shown in FIG. 10, a through hole is formed on the upper surface 14A of the second p-type layer 14 exposed from the through holes 32B and 32D opened in the step (S60). A third injection blocking layer 35, which is a W film made of W, is formed so as to partially fill 32B and 32D. That is, the third injection blocking layer 35 thinner than the thickness of the first injection blocking layer 32 is formed on the upper surface 14A of the second p-type layer 14 exposed from the through holes 32B and 32D.

  Here, like the second injection blocking layer 33, the third injection blocking layer 35 is formed on the upper surface 14A of the second p-type layer 14 exposed from the through holes 32B and 32D by employing, for example, the CVD method. And on the second injection blocking layer 33 in the through holes 32A and 32C. The thickness of the third injection blocking layer 35 can be set to, for example, about 0.8 μm. As a result, the third implantation blocking layer 35 that blocks the ion implantation is formed by closing the through holes 32B and 32D opened in the step (S60). The third injection blocking layer 35 is formed on the second injection blocking layer 33 in the through holes 32A and 32C. In order to prevent these from adversely affecting the subsequent process, the total value of the thickness of the third injection blocking layer 35 and the thickness of the second injection blocking layer 33 in the through holes 32A and 32C is the first injection blocking layer 32. It is preferable that the thickness is smaller.

  Next, with reference to FIG. 2, a 2nd through-hole opening process is implemented as process (S90). Specifically, in step (S90), with reference to FIG. 10, among the second injection blocking layers 33 that close the plurality of through holes 32B, 32C, 32D, and 32A formed in step (S50), the through hole The second injection blocking layer 33 that closes 32A and 32C and the third injection blocking layer 35 formed in the step (S80) are removed, and the through holes 32A and 32C are opened. The removal of the second injection blocking layer 33 and the third injection blocking layer 35 can be performed, for example, as follows.

First, referring to FIG. 11, a resist film 34 is formed by applying a resist so as to fill the through holes 32B, 32C, 32D and 32A and cover the entire upper surface of the first injection blocking layer 32. Thereafter, by performing exposure and development, an opening 34B is formed in the resist film 34 so as to overlap the entire through holes 32A and 32C in a plan view and not to overlap the through holes 32B and 32D. Then, the resist film 34 in which the opening 34B is formed is used as a mask, and the second injection blocking layer 33 and the third injection blocking that close the through holes 32A and 32C by dry etching using, for example, SF ₆ as an etching gas. Layer 35 is removed. The second procedure closes the through holes 32A and 32C different from the through holes 32B and 32D opened in the step (S60) among the through holes 32B, 32C, 32D and 32A formed in the step (S40) by the above procedure. The injection blocking layer 33 and the third injection blocking layer 35 are removed.

Next, with reference to FIG. 2, a 2nd ion implantation process is implemented as process (S100). Specifically, in step (S100), referring to FIG. 11, after removal of resist film 34 used in step (S90), as shown in FIG. By using the third injection blocking layer 35 as a mask, the first p-type layer 12, the n-type layer 13 and the second p-type layer 14 are passed through the through holes 32A and 32C opened in the step (S90). Ion implantation is performed. The ion species to be implanted can be, for example, Al, B (boron) or the like. Further, the dose amount can be set to, for example, about 3 × 10 ¹⁴ cm ⁻² . As a result, the first p-type region 16 that penetrates the second p-type layer 14 and reaches the n-type layer 13 and the bottom wall 31A of the groove 31 penetrates the n-type layer 13 and the first p-type layer. A second p-type region 23 reaching 12 is formed.

  Next, referring to FIG. 2, an activation annealing step is performed as a step (S110). Specifically, in the step (S110), referring to FIG. 12, first, the first implantation blocking layer 32 and the third implantation blocking layer 35 used for the ion implantation described above are, for example, HF (hydrofluoric acid) and APM. (Ammonia Peroxide Mixture; ammonia-hydrogen peroxide solution mixture) or the like, and the SiC substrate 10 in which ion implantation is completed is completed as shown in FIG. Thereafter, activation annealing is performed by heating SiC substrate 10 to 1700 ° C. in an inert gas atmosphere such as argon and holding it for 30 minutes. Thereby, impurities such as P and Al introduced into SiC substrate 10 in step (S70) and step (S100) are activated and can function as n-type impurities or p-type impurities.

  Next, with reference to FIG. 2, an oxide film formation process is implemented as process (S120). Specifically, in step (S120), referring to FIG. 13, SiC substrate 10 on which step (S110) has been performed is subjected to, for example, thermal oxidation, so that the second p as shown in FIG. An oxide film 18 (field oxide film) is formed as an insulating film covering the upper surface 14A of the mold layer 14 and the bottom wall 31A and the side wall 31B of the groove 31. The thickness of the oxide film 18 is, for example, about 0.1 μm.

  Next, with reference to FIG. 2, an electrode formation process is implemented as process (S130). Specifically, in step (S130), referring to FIG. 1, first n-type region 15, first p-type region 16, second n-type region 17, and second p-type region 23 are formed. A source electrode 19, a gate electrode 21, a drain electrode 22, and a potential holding electrode 24 made of, for example, NiSi are formed so as to contact the upper surface. The source electrode 19, the gate electrode 21, the drain electrode 22, and the potential holding electrode 24 can be formed, for example, as follows.

  First, referring to FIG. 15, a resist is applied to fill groove portion 31 and cover the entire upper surface 14 </ b> A of second p-type layer 14 to form resist film 34. Thereafter, exposure and development are performed, so that the first n-type region 15, the first p-type region 16, the second p-type layer 14 are formed on the upper surface 14 </ b> A of the second p-type layer 14 and the bottom wall 31 </ b> A of the groove 31. An opening 34C corresponding to the region where the n-type region 17 and the second p-type region 23 are formed is formed. Then, the resist film 34 in which the opening 34C is formed is used as a mask, and the first n-type region 15, the first p-type region 16, the second n-type region 17 and the second n-type region 17 are formed by, for example, RIE. The oxide film 18 on the p-type region 23 is removed.

  Thereafter, for example, Ni (nickel) is deposited, so that first n-type region 15, first p-type region 16, second n-type region 17, and second p-type region exposed from oxide film 18 are exposed. A nickel layer 29 is formed on the resist film 34 and the resist film 34. Further, by removing the resist film 34, the nickel layer 29 on the resist film 34 is removed (lifted off), and the first n-type region 15, the first p-type region 16 exposed from the oxide film 18, The nickel layer 29 remains on the second n-type region 17 and the second p-type region 23. Then, the SiC substrate 10 on which the above procedure is completed is heated to, for example, 1000 ° C., whereby the nickel layer 29 is silicided. As a result, as shown in FIG. 16, the source made of NiSi capable of making ohmic contact with the first n-type region 15, the first p-type region 16, the second n-type region 17, and the second p-type region 23. Electrode 19, gate electrode 21, drain electrode 22, and potential holding electrode 24 are formed.

  By the above procedure, the first n-type region 15, the first p-type region 16, the second n-type region 17 and the first n-type region 17 which are ion implantation regions formed by the ion implantation in the steps (S70) and (S100). The source electrode 19, the gate electrode 21, the drain electrode 22, and the potential holding electrode 24 that are electrically connected to the two p-type regions 23, respectively, are formed using a single mask (resist film 34 in which the opening 34C is formed). Formed simultaneously.

  Next, with reference to FIG. 2, a wiring formation process is implemented as process (S140). Specifically, in step (S140), referring to FIG. 1, source wiring 25, gate wiring 26, and drain wiring 27 are formed in contact with the upper surfaces of source electrode 19, gate electrode 21, and drain electrode 22, respectively. The For the source wiring 25, the gate wiring 26 and the drain wiring 27, for example, a resist layer having an opening is formed in a desired region where the source wiring 25, the gate wiring 26 and the drain wiring 27 are to be formed. At the same time, it can be formed by removing Al on the resist layer (lift-off).

  The JFET 1 in the present embodiment is completed through the above steps. Here, in the method of manufacturing JFET 1 as the semiconductor device in the present embodiment, the first n-type region 15 and the second n-type region formed by performing the ion implantation in the step (S70) and the step (S100). The positions where the n-type region 17, the first p-type region 16, and the second p-type region 23 are formed are not defined by the openings formed in the separate injection blocking layers, but the first injection blocking layer 32. Are defined by a plurality of through holes 32A, 32B, 32C and 32D. That is, in the method of manufacturing the semiconductor device in the present embodiment, the first n-type region 15 and the second n-type region 17, the first p-type region 16 and the second p-type region 23 are formed. Rather than forming separate injection blocking layers, a single first injection blocking layer 32 is formed, and a plurality of through holes 32A, 32B, 32C and 32D formed in the first injection blocking layer 32 are The formation positions of the n-type region 15 and the second n-type region 17, the first p-type region 16 and the second p-type region 23 are defined. Therefore, errors that occur in the production of the injection blocking layer a plurality of times and the formation of openings in the injection blocking layer do not accumulate.

  More specifically, referring to FIG. 1, the shortest distance in the ion implantation region of JFET 1 is that first p-type region 16 functioning as a gate region and first p-type region functioning as a source region. For example, this distance is required to be 0.5 μm. Correspondingly, the distance between the through hole 32B and the through hole 32C is 0.5 μm with reference to FIG. 8 and 11, the opening 34A or opening 34B of the resist film 34 when the through holes 32B and 32D or the through holes 32A and 32C are opened has a desired entire through hole as viewed in a plan view. As long as it is formed so as not to overlap and not overlap with an adjacent through hole, that is, unless it is formed including an alignment error exceeding 0.5 μm, which is the distance between the through hole 32B and the through hole 32C, the alignment error. Are not cumulative.

  As described above, according to the method for manufacturing a JFET in the present embodiment, it is possible to manufacture a JFET having stable characteristics by suppressing an alignment error in the ion implantation region.

(Embodiment 2)
Next, a method for manufacturing JFET 1 as a semiconductor device in the second embodiment of the present invention will be described. FIG. 17 is a flowchart showing an outline of a method for manufacturing a JFET which is a semiconductor device in the second embodiment which is an embodiment of the present invention. 18 to 20 are schematic cross-sectional views for explaining the method of manufacturing the JFET in the second embodiment.

  Referring to FIGS. 2 and 17, the JFET manufacturing method in the second embodiment and the JFET manufacturing method in the first embodiment described above have basically the same configuration. However, in the second embodiment, after the step (S20) is performed and before the step (S30) is performed, the first intermediate layer forming step is performed as the step (S200). It is different from 1.

Specifically, referring to FIG. 17, after steps (S10) to (S20) are performed as in the first embodiment, in step (S200), as shown in FIG. Is formed so as to cover the upper surface 14A of the second p-type layer 14 and the bottom wall 31A and side wall 31B of the groove 31. Then, by performing the step (S30) as in the case of the first embodiment, as shown in FIG. 18, the upper surface 14A and the groove portion 31 of the first injection blocking layer 32 and the second p-type layer 14 are obtained. In the RIE using, for example, a mixed gas of CF ₄ and CHF ₃ as an etching gas, the first intermediate layer 41 made of Ti having a low etching rate is disposed between the bottom wall 31A of the first and second walls 31A. Therefore, in the step (S40) in which the through holes 32B, 32C, 32D and 32A are formed by the RIE, as shown in FIG. 19, it can function as an etching stop layer. As a result, damage to SiC substrate 10 in the step (S40) can be suppressed.

  Furthermore, the first intermediate layer 41 made of Ti is excellent in adhesion with SiC. Therefore, referring to FIG. 20, in step (S50), the second injection blocking layer 33 made of W, the upper surface 14A of the second p-type layer 14 made of SiC, and the bottom wall 31A of the groove 31 are The first intermediate layer 41 can be brought into close contact, and ion implantation is more effectively prevented by the implantation inhibition layer made of W.

(Embodiment 3)
Next, a method for manufacturing JFET 1 as a semiconductor device in the third embodiment of the present invention will be described. FIG. 21 is a flowchart showing an outline of a method for manufacturing a JFET which is a semiconductor device in the third embodiment which is an embodiment of the present invention. 22 and 23 are schematic cross-sectional views for explaining the method of manufacturing the JFET in the third embodiment.

  Referring to FIGS. 2 and 21, the method for manufacturing the JFET in the third embodiment and the method for manufacturing the JFET in the first embodiment described above have basically the same configuration. However, in the third embodiment, the second intermediate layer forming step is performed as the step (S300) after the step (S40) is performed and before the step (S50) is performed. It is different from 1.

  Specifically, referring to FIG. 21, after steps (S10) to (S40) are performed as in the first embodiment, in step (S300), for example, as shown in FIG. ) Of the second intermediate layer 42 is exposed from the first injection blocking layer 32 in the side walls of the through holes 32A, 32B, 32C and 32D and the through holes 32A, 32B, 32C and 32D. 14 is formed so as to cover the upper surface 14A of 14 and the bottom wall 31A of the groove 31. The second intermediate layer 42 includes, for example, the sidewalls of the through holes 32A, 32B, 32C and 32D and the upper surface of the second p-type layer 14 exposed from the first injection blocking layer 32 in the through holes 32A, 32B, 32C and 32D. 14A and the bottom wall 31A of the groove 31 can be selectively formed.

Here, the second intermediate layer 42 made of Ti is excellent in adhesion to the SiC and SiO _2. Therefore, referring to FIG. 23, when the second injection blocking layer 33 is formed in the step (S50), the second injection blocking layer 33 includes the side walls of the through holes 32A, 32B, 32C and 32D, and the through holes. 32A, 32B, 32C and 32D are in close contact with the upper surface 14A of the second p-type layer 14 exposed from the first injection blocking layer 32 and the bottom wall 31A of the groove 31 via the second intermediate layer 42. It becomes possible. As a result, ion implantation is more effectively blocked by the second implantation blocking layer 33 made of W.

  In the second and third embodiments, the case where only one of the first intermediate layer forming step and the second intermediate layer forming step is performed has been described. However, the method for manufacturing a semiconductor device of the present invention is not limited to this. However, the present invention is not limited to this, and both the first intermediate layer forming step and the second intermediate layer forming step may be performed. In the second and third embodiments, the case where Ti is employed as the material of the first intermediate layer 41 and the second intermediate layer 42 has been described. However, the material of the first intermediate layer 41 and the second intermediate layer 42 is described. May be a simple substance of tantalum or a compound containing at least one of titanium and tantalum. Here, examples of the compound containing at least one of titanium and tantalum include Ti, TiN, Ta, and TaN.

In the above embodiment, the case where SiO ₂ is used as the first injection blocking layer of the present invention and W is used as the second injection blocking layer and the third injection blocking layer has been described. The combination of the blocking layer and the second injection blocking layer and the third injection blocking layer is obtained by removing the second injection blocking layer and the third injection blocking layer that close the through hole of the first injection blocking layer, for example, by etching. Any material can be used as long as the second injection blocking layer and the third injection blocking layer can be removed at a higher etching rate than the first injection blocking layer. Specifically, for example, the selection ratio of the second injection blocking layer and the third injection blocking layer to the first injection blocking layer may be 3 or more. For example, SiN is used as the first injection blocking layer in addition to the above combination. In this case, W or the like can be adopted as the second injection blocking layer and the third injection blocking layer.

  In the above embodiment, the JFET is exemplified as the semiconductor device manufactured by the semiconductor device manufacturing method of the present invention. However, the semiconductor device that can be manufactured by the semiconductor device manufacturing method of the present invention is described here. Not limited. The method for manufacturing a semiconductor device of the present invention is suitable for a method for manufacturing a semiconductor device in which a plurality of ion implantation regions need to be formed under different conditions, and can be applied to the manufacture of various semiconductor devices.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The method for manufacturing a semiconductor device of the present invention can be applied particularly advantageously to a method for manufacturing a semiconductor device including a step of performing ion implantation on a semiconductor substrate.

1 is a schematic cross-sectional view showing a configuration of a junction field effect transistor as a semiconductor device in a first embodiment. 3 is a flowchart showing an outline of a method for manufacturing a JFET which is a semiconductor device in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the first embodiment. 5 is a flowchart showing an outline of a method for manufacturing a JFET which is a semiconductor device in a second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the second embodiment. 10 is a flowchart showing an outline of a method for manufacturing a JFET which is a semiconductor device in a third embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the third embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the JFET in the third embodiment.

Explanation of symbols

  1 JFET, 10 SiC substrate, 11 n-type substrate, 12 first p-type layer, 13 n-type layer, 14 second p-type layer, 14A upper surface, 15 first n-type region, 16 first p Type region, 17 second n type region, 18 oxide film, 19 source electrode, 21 gate electrode, 22 drain electrode, 23 second p type region, 24 potential holding electrode, 25 source wiring, 26 gate wiring, 27 drain Wiring, 29 nickel layer, 31 groove, 31A bottom wall, 31B side wall, 32 first injection blocking layer, 32A, 32B, 32C, 32D through hole, 34 resist film, 34A, 34B, 34C opening, 35 third injection blocking layer 41 First intermediate layer, 42 Second intermediate layer.

Claims (16)

Preparing a semiconductor substrate;
Forming a first implantation blocking layer for blocking ion implantation on the semiconductor substrate;
Forming a plurality of through holes in the first injection blocking layer;
Forming a second implantation blocking layer that blocks ion implantation by closing the plurality of through holes;
Removing the second injection blocking layer that closes at least one of the plurality of through holes; and
Performing a first ion implantation on the semiconductor substrate through the at least one through hole;
Forming a third implantation blocking layer that blocks ion implantation by closing the at least one through hole;
Removing the second injection blocking layer that closes at least one other through hole different from the at least one through hole among the plurality of through holes;
Performing a second ion implantation on the semiconductor substrate through the at least one other through-hole.   The method of manufacturing a semiconductor device according to claim 1, wherein the second injection blocking layer is a tungsten film made of tungsten.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the third injection blocking layer is a tungsten film made of tungsten.   4. The method of manufacturing a semiconductor device according to claim 2, wherein a thickness of the tungsten film is not less than 0.4 μm and not more than 2 μm, and is thinner than a thickness of the first injection blocking layer.   The method for manufacturing a semiconductor device according to claim 2, wherein the tungsten film is formed by a CVD method.   6. The semiconductor device according to claim 2, wherein the first injection blocking layer includes at least one selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Manufacturing method.   The method of manufacturing a semiconductor device according to claim 6, wherein the thickness of the first injection blocking layer is not less than 1 μm and not more than 5 μm.   8. The step of removing the second injection blocking layer, wherein the second injection blocking layer is removed by etching using a gas containing at least one of sulfur hexafluoride and chlorine. A method for manufacturing a semiconductor device.   After the step of preparing the semiconductor substrate and before the step of forming the first injection blocking layer, on the semiconductor substrate, a simple substance of titanium, a simple substance of tantalum, and at least one of titanium or tantalum The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a first intermediate layer including at least one selected from the group consisting of compounds containing one. .   The method for manufacturing a semiconductor device according to claim 9, wherein the thickness of the first intermediate layer is not less than 5 nm and not more than 100 nm.   The semiconductor exposed from the first injection blocking layer in the side wall of the through hole and in the through hole after the step of forming the through hole and before the step of forming the second injection blocking layer The method further includes forming a second intermediate layer including at least one selected from the group consisting of a simple substance of titanium, a simple substance of tantalum, and a compound containing at least one of titanium and tantalum on the substrate. The method for manufacturing a semiconductor device according to claim 1.   The method of manufacturing a semiconductor device according to claim 11, wherein a thickness of the second intermediate layer is not less than 5 nm and not more than 100 nm.   The method of manufacturing a semiconductor device according to claim 11, wherein the second intermediate layer is formed by a CVD method.   After the step of performing the second ion implantation, a plurality of electrodes electrically connected to the plurality of ion implantation regions formed by the first ion implantation and the second ion implantation are simultaneously formed. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of:   The method of manufacturing a semiconductor device according to claim 14, wherein the electrode includes at least one of nickel and a compound containing nickel.   The method of manufacturing a semiconductor device according to claim 1, wherein a region of the semiconductor substrate on which the first ion implantation and the second ion implantation are performed is made of silicon carbide.

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