JP5319240B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, wherein an etching height is not varied by a change in an etching speed due to ion implantation to an element isolation insulating film when forming a CMOS having an STI type element isolation structure. <P>SOLUTION: The method for manufacturing the semiconductor device includes: a step for forming an element isolation region having an STI structure on a silicon substrate 21; and a step for forming a first well and a second well by doping first impurity elements into a first element region 21A of the silicon substrate 21 by first ion implantation in a state that the first region 21A of the silicon substrate 21 and an element isolation insulating film 21IB of a second element region 21B are covered with an opened first resist pattern R21B and doping second impurity elements into the second element region 21B of the silicon substrate 21 by second ion implantation in a state that the second region 21B of the silicon substrate 21 and an element isolation insulating film 21IA of the first element region 21A are covered with an opened second resist pattern R21A. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates generally to the manufacture of semiconductor devices, and more particularly to a method of manufacturing a semiconductor device having an STI type element isolation structure.

  Today's miniaturized semiconductor devices, especially logic semiconductor devices that require high-speed operation, often use CMOS elements that consume less power and can operate at high speed. In a CMOS device, a p-channel MOS transistor and an n-channel MOS transistor formed adjacent to each other in a semiconductor substrate are connected in series. Also in a general semiconductor device, a p-channel MOS transistor and an n-channel MOS transistor are generally formed in the same semiconductor substrate.

  Further, in today's high-speed semiconductor devices including CMOS elements, in order to reduce the element area, a so-called STI structure in which an element isolation trench is formed in a semiconductor substrate and filled with an element isolation insulating film is generally used. It is.

  A p-channel MOS transistor is generally formed in an n-type well formed corresponding to an element region in a semiconductor substrate, and includes a p-type source and drain diffusion region and an LDD diffusion region. An n-channel MOS transistor is generally formed in a p-type well formed corresponding to an element region in a semiconductor substrate, and includes an n-type source and drain region and an LDD diffusion region.

The manufacturing process of the semiconductor device includes various ion implantation processes for forming these well regions and diffusion regions. The type of impurity element to be introduced is different between the p-channel MOS transistor and the n-channel MOS transistor. For example, when ion implantation of the p-channel MOS transistor is performed, the n-channel MOS transistor formation region is masked with a resist pattern or the like. In addition, when ion implantation of an n-channel MOS transistor is performed, a p-channel MOS transistor formation region is masked with a resist pattern or the like.
JP 2001-68543 A

  On the other hand, in the STI structure that defines the element region of the p-channel MOS transistor and the STI structure that defines the element structure of the n-channel MOS transistor, the element isolation insulating film filling the element isolation groove is formed on the semiconductor device. In the manufacturing process, ion implantation of different impurity elements is repeatedly performed, and in the manufacturing process of the semiconductor device, the element isolation insulating film into which various impurity elements are introduced may be repeatedly etched.

  1A to 1N show a method of manufacturing a conventional semiconductor device including a p-channel MOS transistor and an n-channel MOS transistor.

  Referring to FIG. 1A, a thin stress relaxation pad oxide film 12 and a silicon nitride film 13 are formed on a silicon substrate 11.

  Next, the silicon nitride film 13 and the pad oxide film 12 are patterned, and an opening 13A is formed in the silicon nitride film 13 and the pad oxide film 12 corresponding to the element isolation trench formation region, thereby forming the structure shown in FIG. A structure is obtained, and the silicon substrate 11 is further dry-etched by reactive ion etching (RIE) using the silicon nitride film 13 as a hard mask, so that the element isolation trench 11T is formed in the silicon substrate 11 and the region 11A. And it forms in the area | region 11B collectively, and the structure of FIG. 1C is obtained. The element isolation trench 11T defines an element region 11A of an n-channel MOS transistor and an element region 11B of a p-channel MOS transistor in the silicon substrate 11.

  Next, a silicon oxide film 14 is formed on the structure of FIG. 1C by high-density plasma CVD so as to fill the element isolation trench 11T, to obtain the structure of FIG. 1D, and in the structure of FIG. The element isolation trench 11T is filled with the element isolation oxide film 14IA or 14IB by polishing the oxide film 14 by chemical mechanical polishing (CMP) until the underlying silicon nitride film 13 is exposed. The structure shown in is obtained. However, the element isolation oxide film 14IA forms an element isolation region that defines the element region 11A, and the element isolation oxide film 14IB forms an element isolation region that defines the element region 11B.

  Further, in the structure of FIG. 1E, the silicon nitride film 13 is selectively removed with respect to the element isolation oxide films 14IA and 14IB to obtain the structure of FIG. 1F.

  Further, a resist film R1 covering the element region 11B is formed on the structure of FIG. 1F, and B + is introduced into the region 11A by ion implantation using the resist film R1 as a mask, and a p-type well 11pW of an n-channel MOS transistor and A p-type channel doped region (not shown) is formed to obtain the structure of FIG. 1G. At this time, the element isolation oxide film 14IA that defines the element region 11A is also exposed from the resist film R1, and the B + ion implantation occurs also in the element isolation oxide film 14IA that defines the element region 11A. It should be noted that.

  Further, the resist film R1 is removed, and a resist film R2 covering the element region 11A is formed on the structure of FIG. 1G, and P + or As + is introduced into the element region 11B by ion implantation using the resist film R2 as a mask. Then, an n-type well 11nW and an n-type channel doped region (not shown) of the p-channel MOS transistor are formed, and the structure of FIG. 1H is obtained. At this time, the element isolation oxide film 14IB defining the element region 11B is also exposed from the resist film R2, and the As + or P + ion implantation is applied to the element isolation oxide film 14IB defining the element region 11B. Note that it has occurred.

  Further, the resist film R2 is removed, and the pad oxide film 12 is removed by HF to obtain the structure of FIG. 1I. In the HF treatment process of FIG. 1I, the element isolation insulating film 14IA that defines the element region 11A is changed to a composition containing B at a high concentration in the surface portion by the B + ion implantation process shown in FIG. 1G. It should be noted. In the HF processing step of FIG. 1I, the element isolation insulating film 14IB that defines the element region 11B has a composition containing As or P at a high concentration in the surface portion by the As + or P + ion implantation step shown in FIG. 1H. Note that it is changing.

  FIG. 2 is a graph showing a change in the etching rate when the silicon oxide film doped with the impurity element is etched with HF, depending on the ion implantation amount of the impurity element. However, the vertical axis represents the etching rate normalized with respect to the etching rate of the undoped silicon oxide film. Note that the etching rate greatly depends on the type, concentration, and composition of the chemical solution used, and also depends on how the crystals are disturbed by ion implantation. That is, it also depends on conditions such as the acceleration voltage of ion implantation. Therefore, this figure is only an example showing the effect of ion implantation. The relationship of FIG. 2 is for a silicon oxide film doped with B or P. In the experiment of FIG. 2, the silicon oxide film is formed on the silicon substrate by a high density plasma CVD method. It is known that a silicon oxide film formed by a high-density plasma CVD method generally has a high film density and exhibits higher etching resistance against an etchant such as HF than an ordinary silicon oxide film.

On the other hand, referring to FIG. 2, the etching rate of the silicon oxide film formed by such a high-density plasma CVD method is higher when the ion implantation amount of the impurity element is small than when ion implantation is not performed. Although it hardly increases, it can be seen that the ion implantation rate increases rapidly when the ion implantation amount exceeds approximately 1 × 10 ¹³ cm ⁻² .

  Such a change in the etching rate of the silicon oxide film depending on the impurity concentration differs depending on the type of impurity element to be introduced. As a result, when the etching process of FIG. 1I is performed, element isolation in the region 11B into which P is introduced. The insulating film 14I is more greatly etched than the element isolation insulating film 14I in the region 11A into which B is introduced, and the element isolation insulating film 14I has a height that defines the element region 11A. The element isolation insulating film 14I that defines the element region 11B becomes uneven.

  Therefore, a thermal oxide film 15 serving as a gate insulating film is further formed on the structure of FIG. 1I by thermal oxidation of the silicon substrate 11 as shown in FIG. 1J, and a polysilicon film 16G is further formed on the structure of FIG. 1J. The structure shown in FIG. 1K is obtained by depositing by the CVD method or the like, the antireflection film 17 and the resist film 18 are formed on the structure of FIG. 1K as shown in FIG. 1L, and the resist film 18 is formed as shown in FIG. 1M. Patterning is performed corresponding to a desired gate electrode pattern to form resist patterns 18GA and 18GB in the element regions 11A and 11B, respectively, and the polysilicon film 16 is patterned using the resist pattern 18G as a mask to form the gate electrode shown in FIG. 1N. When 16GA and 16GB are formed in the element regions 11A and 11B, respectively, the element regions 11A and 1A of the element isolation insulating film 14I are formed. Due to the difference in height between B, as shown in FIG. 1M, the thickness H1 of the antireflection film 17 immediately below the resist pattern 18GA is different from the thickness H2 of the antireflection film 17 immediately below the resist pattern 18GB. A situation occurs. As a result, when the exposure conditions for forming the resist pattern 18GA are optimized, the exposure conditions for the resist pattern 18GB deviate from the optimum conditions, or vice versa. Also in the RIE process in the patterning step, if one process condition is optimized, the other process condition deviates from the optimum condition, resulting in under-etching or over-etching. As a result, even if a desired pattern width, that is, a gate length is obtained for the gate electrode pattern 16GA, a desired pattern width, that is, a gate length cannot be obtained for the gate electrode pattern 16GB, or vice versa. To do.

  FIG. 3 shows a state immediately after development, that is, the resist film 18 and the antireflection film when the polysilicon pattern 16G extending by connecting the element isolation insulating films 14IA and 14IB having different heights is formed by a photolithography process. Although the film 17 still remains, the thickness of the polysilicon pattern 16G continuously changes from the element isolation insulating film 14IA to the element isolation insulating film 14IB, and accordingly, the polysilicon pattern It can be seen that the pattern width of 16G also changes continuously in the same manner.

  Such a problem becomes prominent particularly in the manufacture of an ultra-miniaturized ultra high-speed semiconductor device having a gate length of about 100 nm or less.

  According to one aspect, a method of manufacturing a semiconductor device includes a step of forming an element isolation region having an STI structure on a silicon substrate, a first impurity element in the first region of the silicon substrate, Introducing the first region in a state where the second region is covered with a first resist pattern by a first ion implantation step to form a first well having a first conductivity type in the first region; and the silicon substrate A second impurity element having a conductivity type opposite to that of the first impurity element, and a second resist pattern in which the element region is covered with a second resist pattern. Forming a second well having a second conductivity type opposite to the first conductivity type in the second region, wherein the first resist pattern includes the element isolation. The second region of the region A first opening that exposes an element isolation region included in the first isolation well is formed, and in the step of forming the first well, a portion of the element isolation region that is exposed through the first opening is formed. The first impurity element is introduced by the first ion implantation step, and a second resist pattern that exposes an element isolation region included in the first region of the element isolation region is provided. In the step of forming the second well in which the opening is formed, the second impurity element is exposed to the second ion in a portion of the element isolation region exposed at the second opening. It is introduced by an injection process.

  According to another aspect, a method of manufacturing a semiconductor device includes a step of forming an element isolation region having an STI structure on a silicon substrate, the silicon substrate is covered with a first resist pattern that exposes the element isolation region, Using the first resist pattern as a mask, a step of selectively introducing a first impurity element into the element isolation region by ion implantation; a second impurity element in the first region of the silicon substrate; Introducing a second well of the substrate by ion implantation in a state where the second resist pattern is covered with a second resist pattern, and forming a first well having a first conductivity type in the first region; A third impurity element having a conductivity type opposite to that of the first impurity element is introduced into the second region by ion implantation in a state where the element region is covered with a third resist pattern; Forming a second well having a second conductivity type opposite to the first conductivity type in the second region, wherein the first impurity element is any one of the second and third impurity elements. It is characterized by having a larger atomic weight.

  According to the above embodiment, ion implantation of two types of impurity elements having opposite conductivity types is added to each of the STI type element isolation regions on the silicon substrate in both the first region and the second region. As a result, an impurity element having a large mass, that is, an impurity element having an atomic weight larger than two kinds of impurity elements having opposite conductivity types introduced later is commonly ionized in the first region and the second region. As a result of the implantation, the surface portion of each of the STI type element isolation regions has substantially the same etching resistance in both the first region and the second region, and thereafter Even if an etching process is used in the manufacturing process of the semiconductor device, the height of the element isolation region between the first region and the second region depends on the effect of the introduced impurity element. And thus there is no problem that different to become. Accordingly, a member having a great influence on the operation performance of the semiconductor device, such as a gate electrode, can be formed in each region with a dimension having an optimum value as designed.

[First Embodiment]
4A to 4T show a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 4A, a thin stress relaxation pad oxide film 22 and a silicon nitride film 23 are formed on a silicon substrate 21 to a thickness of 10 nm and 100 nm, respectively, by a thermal oxidation method and a CVD method. Yes.

  Next, the silicon nitride film 23 and the pad oxide film 22 are patterned by dry etching using an RIE (reactive ion etching) method, and the silicon nitride film 23 and the pad corresponding to a desired element isolation trench formation region. By forming the opening 23A in the oxide film 22, the structure of FIG. 4B is obtained.

  Further, the silicon substrate 21 is patterned by dry etching using the RIE method using the silicon nitride film 23 as a hard mask, and an element region 21A of an n-channel MOS transistor and an element of a p-channel MOS transistor are formed in the silicon substrate 21. The element isolation trenches 21T that define the region 21B are collectively formed to a depth of, for example, 200 nm to 350 nm to obtain the structure of FIG. 4C.

  Next, a silicon oxide film 24 is formed on the structure of FIG. 4C by high-density plasma CVD so as to fill the element isolation trench 21T, thereby obtaining the structure of FIG. 4D. Further, in the structure of FIG. The element isolation trench 21T is filled with the element isolation oxide film 24IA or 21IB by polishing the oxide film 24 by chemical mechanical polishing (CMP) until the underlying silicon nitride film 23 is exposed, as shown in FIG. 4E. The structure shown in is obtained. Here, the silicon nitride film 23 has a low polishing rate during the CMP process and acts as a polishing stopper. The element isolation oxide film 21IA defines the element region 21A, and the element isolation oxide film 21IB defines the element region 21B.

Further, in the structure of FIG. 4E, the silicon nitride film 23 is selectively removed with respect to the element isolation oxide films 21IA and 21IB to obtain the structure of FIG. 4F. The removal of the silicon nitride film 23 can be performed by wet etching using phosphoric acid (H ₃ PO ₄ ), for example. In the structure of FIG. 4F, the pad oxide film 22 is removed by wet etching using hydrofluoric acid (HF), and the exposed silicon surface is subjected to a heat treatment at a temperature of 800 ° C. to 1000 ° C. in an oxygen atmosphere. Thus, the sacrificial oxide film 22S is formed to a thickness of 5 to 20 nm. In the structure of FIG. 4F, as a result of the removal of the silicon nitride film 23, the element isolation oxide film 24I protrudes upward from the surface of the silicon substrate 21 at a height of 60 to 120 nm, typically about 100 nm.

Further, a resist film R21B is formed on the structure of FIG. 4F so as to cover the element region 21B, and boron ions (B +) are formed on the element isolation oxide film 21IA of the element isolation region that defines the element region 21A and the element region 21A. ) Are introduced by ion implantation to form the p-type well 21WA and p-type channel doped region 21thA of the n-channel MOS transistor in the element region 21A, thereby obtaining the structure of FIG. 4G. At this time, the resist film R21B is formed with a resist opening R21b that exposes the element isolation insulating film 21IB in the element isolation region that defines the element region 21B. As a result, B + Are simultaneously introduced into the element isolation insulating film 21IB that defines the above. The resist opening R21b is formed by exposing and developing the resist film R21B using a first reticle having a reticle pattern corresponding to the region 21A and the element isolation insulating films 21IA and 21IB. Here, the well 21WA is formed by ion-implanting B + at a dose of 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 100 keV to 300 keV (well implantation), while the channel The doped region 21thA is formed by ion-implanting B + with a dose of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 5 keV to 50 keV (channel implantation).

  Here, the projection range of the channel implantation for forming the channel dope region 21thA is 1/10 or less of the projection range of the well implantation, and the dose amount of the channel implantation and the dose amount of the well implantation are substantially the same. It should be noted that there are. For this reason, the dose at the time of channel implantation is 10 times or more that of well implantation when converted per unit volume. Since the energy loss of the implanted ions can be approximated to be the maximum in the vicinity of the projection range, the etching rate of the element isolation insulating film 21I is mainly determined by damage due to channel implantation. In the process of FIG. 4G, boron (B) is introduced into the element isolation insulating films 21IA and 21IB with the same dose under the same acceleration voltage regardless of the regions 21A and 21B.

Next, the resist film R21B is removed by wet etching using sulfuric acid / hydrogen peroxide, and a resist film R21A is formed on the structure of FIG. 4G so as to cover the element region 21A. Arsenic ions (As +) and phosphorus ions (P +) are sequentially introduced by ion implantation into the element isolation insulating film 21IB of the element isolation region that defines 21B and the element region 21B, and the n-type well 21WB and n-type of the p-channel MOS transistor are introduced. A channel doped region 21thB is formed to obtain the structure of FIG. 4H. At this time, the resist film R21A is provided with a resist opening R21a that exposes the element isolation insulating film 21IA that defines the element region 21A. As a result, As + or P + defines the element region 21B. It is simultaneously introduced into the element isolation insulating film 21IB in the element isolation region to be formed. The resist opening R21a is formed by exposing and developing the resist film R21A using a second reticle having a reticle pattern corresponding to the element region 21B and the element isolation insulating films 21IA and 21IB. Here, the well 21WB is formed by ion-implanting phosphorus ions (P +) at a dose of 5 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 200 keV to 900 keV. This process is also called well implantation. On the other hand, the channel dope region 21thB is formed by ion-implanting P + or As + at a dose of 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 20 keV to 200 keV. This process is also called channel implantation.

  Again, the projected range of channel implantation for forming the channel dope region 21thB is 1/10 or less of the projected range of well implantation for forming the well 21WB, and the dose amount of the channel implantation and the dose of well implantation. Since the amounts are almost the same, the dose during channel implantation is 10 times or more that of well implantation when converted per unit volume. Since the energy loss of the implanted ions can be approximated to be the maximum in the vicinity of the projection range, the etching rate of the element isolation insulating film 21I is mainly determined by damage due to channel implantation. As described above, in the process of FIG. 4H, regardless of the regions 21A and 21B, boron (B) and phosphorus (P) or arsenic (As) are applied to the element isolation insulating film 21I at the same dose under the same acceleration voltage. Has been introduced.

  Further, the resist film R21A is removed by wet etching using sulfuric acid / hydrogen peroxide and the sacrificial oxide film 22S is removed by HF to obtain the structure of FIG. 4I. In the HF processing step of FIG. 4I, the element isolation insulating film 21I in the region 11A has the same concentration by B and P or As and therefore substantially the same impurity regardless of the regions 21A and 21B as described above. Since the distribution profile is doped, the element isolation insulating films 21IA and 21IB have the same receding amount δ when etching with HF, and the upper end portion of the element isolation insulating film 21I has the above-mentioned as shown in FIG. A structure having substantially the same height on the surface of the silicon substrate 21 is obtained.

  Further, a thermal oxidation process is performed on the structure of FIG. 4I to form a thermal oxide film 22G having a thickness of, for example, 1 nm as a gate insulating film on the exposed surface of the silicon substrate 21, thereby obtaining the structure of FIG. 4J. Further, a polysilicon film 23 is formed on the structure of FIG. 4J by a CVD method to a thickness of, for example, 100 nm to 150 nm to obtain the structure of FIG. 4K.

  Further, an antireflection film 24Rf and a resist film R22 are formed on the structure of FIG. 4K by spin coating, and the resist film R22 is exposed and developed by a photolithography process, so that the element region 21A corresponds to the gate electrode pattern. A resist pattern R22A corresponding to the gate electrode pattern is formed in the element region 21B. In the present embodiment, the antireflection film 24Rf is formed by a coating method.

  Further, the polysilicon film 23 is dry-etched by RIE using the resist patterns R22A and R22B as a mask, and the resist patterns R22A and R22B and the antireflection film 24 are removed, and as shown in FIG. , 21B are respectively provided with a gate electrode pattern 23GA and a gate electrode pattern 23GB on the gate insulating film 22G. The gate electrode patterns 23GA and 23GB have a gate length of, for example, 45 nm or less.

  In the structure of FIG. 4N, since the element isolation insulating films 21IA and 21IB have the same height, even in the patterning step of FIG. 4M, the width of the gate electrode pattern as described above with reference to FIG. There is no problem that the gate length deviates from the desired value.

Further, a resist film R23B is formed on the structure of FIG. 4N, and the resist film R23B is exposed and developed using the first reticle used in the ion implantation process of FIG. 4G as a mask. At the same time as forming an opening R23Bo exposing the element isolation insulating film 21IA in the element isolation region to be formed, a resist opening R23b exposing the element isolation insulating film 21IB is formed in the resist film R23A. Further, using the resist film R23B as a mask, As + or P + is ion-implanted at a dose of 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² cm ⁻² under an acceleration voltage of 20 to 200 keV, for example. 21, n-type source extension regions 21a and 21b are formed on both sides of the gate electrode 23GA in the element region 21A to obtain the structure shown in FIG. At that time, the same amount of As + or P + ions is implanted into the element isolation insulating films 21IA and 21IB. From FIG. 4O, the channel dope regions 21thA and 21thB are not shown because the drawings are complicated.

Next, from the structure shown in FIG. 4O, the resist film R23B is removed by wet etching using sulfuric acid / hydrogen peroxide or the like, and a resist film R23A is formed on the silicon substrate 21. Further, the resist film R23A is exposed and developed using the second reticle used in the ion implantation process of FIG. 4H as a mask to expose the element region 21B and the element isolation insulating film 21IB in the element isolation region defining this. Simultaneously with the formation of the opening R23Ao, a resist opening R23a exposing the element isolation insulating film 21IA is formed in the resist film R23A. Further, B + is ion-implanted with a dose of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of, for example, 5 to 50 keV using the resist film R23B as a mask. N-type source extension regions 21c and 21d are formed on both sides of the gate electrode 23GB in the region 21B to obtain the structure shown in FIG. 4P. At that time, the element isolation insulating films 21IA and 21IB are ion-implanted with the same amount of B +.

  Further, the resist film R23A is removed by wet etching using sulfuric acid / hydrogen peroxide, and a silicon oxide film (not shown) is formed on the gate electrodes 23GA and 23GB by the CVD method. Etching back by dry etching using an etching (RIE) method, as shown in FIG. 4Q, sidewall insulating films 23GAw are formed on both side walls of the gate electrode 23GA, and sidewall insulating films 23GBw are formed on the side walls of the gate electrode 23GB. Is formed. Also in FIG. 4Q, after the etch-back process, the element isolation insulating films 21IA and 21IB show the same receding amount.

Further, a resist film R24B is formed on the structure shown in FIG. 4Q, and the resist film R24B is exposed and developed using the first reticle used in the ion implantation process shown in FIG. 4G as a mask. At the same time as forming the opening R24Bo exposing the element isolation insulating film 21IA in the element isolation region to be formed, the resist opening R24b exposing the element isolation insulating film 21IB is formed in the resist film R24B. Further, As + or P + is ion-implanted at a dose of 1 × 10 ¹¹ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 20 to 200 keV, for example, using the resist film R24B as a mask. N + type source regions 21e and 21f are formed outside the sidewall insulating film 23GAw on both sides of the gate electrode 23GA in the element region 21A to obtain the structure of FIG. 4R. At that time, the same amount of As + or P + ions is implanted into the element isolation insulating films 21IA and 21IB.

Next, the resist film R24B is removed by wet etching using sulfuric acid / hydrogen peroxide and further, a resist film R24A is formed on the silicon substrate 21, and the second film used in the ion implantation process of FIG. 4H. The resist film R24B is exposed and developed using a reticle as a mask to form the opening R24Ao exposing the element region 21B and the element isolation insulating film 21IB in the element isolation region defining the element region 21B, and at the same time, in the resist film R24A, A resist opening R24a exposing the element isolation insulating film 21IA is formed. Further, using the resist film R24A as a mask, As + or P + is ion-implanted at a dose of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 5 to 50 keV, for example, The p + -type source regions 21g and 21h are formed outside the sidewall insulating film 23GBw on both sides of the gate electrode 23GB in the element region 21A to obtain the structure of FIG. 4S. At this time, the same amount of B + ions are implanted into the element isolation insulating films 21IA and 21IB.

  Further, an insulating film 25 covering the entire surface of the silicon substrate 21 is formed on the structure of FIG. 4S by, for example, a high density plasma CVD method, and the source region 21e, the drain region 21f, and the source region 21g are formed on the insulating film 25, respectively. Contact plugs 25A, 25B, 25C, and 25D that contact the drain region 21h are formed, and the semiconductor device having the structure of FIG. 4T is obtained. It is also possible to form a multilayer wiring structure on the structure of FIG. 4T.

  As described above, according to the processes of FIGS. 4A to 4T, the retraction amounts of the element isolation insulating films 21IA and 21IB are the same, and the pattern width obtained when patterning the gate electrode 23GA or 23GB deviates from the design value. In addition, even when a multi-layer wiring structure is formed on the structure of FIG. 4T, the wiring pattern position shifts due to the different projecting heights of the element isolation insulating films 21IA and 21IB on the silicon substrate 21. And problems such as misalignment of the pattern width can be avoided.

  In this embodiment, an additional mask process is not required as compared with a normal method for manufacturing a semiconductor device, and the manufacturing cost of the semiconductor device does not increase.

[Second Embodiment]
5A to 5F show a method for manufacturing a semiconductor device according to the second embodiment of the present invention. However, in FIGS. 5A to 5F, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  This embodiment is a continuation of FIG. 4F of the previous embodiment. First, on the structure of FIG. 4F, an insulating film 31 having resistance to wet etching by sulfuric acid / hydrogen peroxide, such as SiN film or polysilicon film, The sacrificial oxide film 22S and the protruding element isolation insulating films 21IA and 21IB are formed to cover the surface, and the structure shown in FIG. 5A is obtained. In the following description, the insulating film 31 is made of a SiN film. The insulating film 31 is formed to have a film thickness that allows the impurity element ions to pass through during various ion implantations that are performed thereafter. For example, when the SiN film is used, the insulating film 31 is formed to have a film thickness of 10 to 50 nm. The

Next, a resist film R21B is formed on the structure of FIG. 5A so as to cover the element region 21B, and boron ions (on the element isolation oxide film 21IA in the element isolation region defining the element region 21A and the element region 21A) are formed. B +) is introduced by ion implantation to form the p-type well 21WA and p-type channel doped region 21thA of the n-channel MOS transistor in the element region 21A, thereby obtaining the structure of FIG. 5B. At this time, the resist film R21B is formed with a resist opening R21b that exposes the element isolation insulating film 21IB in the element isolation region that defines the element region 21B. As a result, B + Are simultaneously introduced into the element isolation insulating film 21IB that defines the above. The resist opening R21b is formed by exposing and developing the resist film R21B using a first reticle having a reticle pattern corresponding to the region 21A and the element isolation insulating films 21IA and 21IB. Here, the well 21WA is formed by ion-implanting B + with a dose of 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 150 to 300 keV (well implantation), while the channel The doped region 21thA is formed by ion-implanting B + with a dose of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 40 keV to 100 keV (channel implantation).

Next, the resist film R21B is removed by wet etching using sulfuric acid / hydrogen peroxide, and a resist film R21A is formed on the structure of FIG. 5B so as to cover the element region 21A. As + or P + is introduced by ion implantation into the element isolation insulating film 21IB of the element isolation region that defines 21B and the element region 21B, thereby forming the n-type well 21WB and the n-type channel doped region 21thB of the p-channel MOS transistor, The structure of FIG. 5C is obtained. At this time, the resist film R21A is provided with a resist opening R21a that exposes the element isolation insulating film 21IA that defines the element region 21A. As a result, As + or P + defines the element region 21B. It is simultaneously introduced into the element isolation insulating film 21IB in the element isolation region to be formed. The resist opening R21a is formed by exposing and developing the resist film R21A using a second reticle having a reticle pattern corresponding to the element region 21B and the element isolation insulating films 21IA and 21IB. Here, the well 21WB is formed by ion implantation of phosphorus ions (P +) at a dose of 5 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 200 keV to 900 keV (well implantation). On the other hand, the channel doped region 21thB is formed by ion-implanting P + or arsenic ions (As +) at a dose of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 50 keV to 200 keV. (Channel injection).

  Further, in the structure of FIG. 5C, the resist film R21A is selectively removed by wet etching using sulfuric acid-hydrogen peroxide or ammonia hydrogen peroxide to obtain the structure of FIG. 5D. In this embodiment, since the projecting portions of the element isolation insulating films 21IA and 21IB are protected by the SiN film 31 having high etching resistance, the element isolation even when the resist film R21B or R21A is removed by the wet etching. The insulating films 21IA and 21IB are not eroded by the wet etching, and the protrusion does not retreat.

  Further, the SiN film 31 is removed by wet etching using phosphoric acid to obtain the structure of FIG. 5E, and the sacrificial oxide film 22S is further removed by wet etching using HF to obtain the structure of FIG. 5F. Also in this embodiment, in the element isolation insulating films 21IA and 21IB, the dose amount of P or As, that is, the ion implantation amount is equal, and the dose amount of B, that is, the ion implantation amount is also equal, and the element isolation insulating films 21IA and 21IB. Indicates the same amount of recession δ during wet etching using HF. Further, when the SiN film 31 is removed by wet etching as shown in FIG. 5E, the element regions 21A and 21B are covered with the sacrificial oxide film 22S, so that the surface of the silicon substrate 21 serving as a channel region is formed. There is no damage.

  After the step of FIG. 5F, a desired semiconductor device can be obtained by executing the processes described in FIG. 4J and subsequent steps.

[Third Embodiment]
6A to 6E show a method for manufacturing a semiconductor device according to the third embodiment of the present invention. This embodiment is a continuation of the process of FIG. 4F of the first embodiment, and in the following description, the same reference numerals are given to the portions described above, and the description is omitted.

Referring to FIG. 6A, a resist film R31 having resist openings R31A and R31B exposing element isolation oxide films 21IA and 21IB, respectively, is formed on the structure shown in FIG. 4F, and the resist film R31 is masked. Then, a heavy impurity element such as indium (In) having a larger atomic weight than B, As, P, etc. used in the subsequent ion implantation process is ion-implanted, so that the upper portions of the element isolation insulating films 21IA and 21IB, for example, Damage is intentionally caused by the In to a depth of up to 40 nm. For example, the In ion implantation can be performed under an acceleration voltage of 70 keV and a dose of 3.0 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 6B, the resist film R31 is removed by wet etching using sulfuric acid / hydrogen peroxide, and further, the element region 21A is formed on the structure of FIG. A resist film R32 having an exposed resist opening R32A including the film 21IA is formed, and B + is initially applied under an acceleration voltage of 100 to 300 keV with the resist film R32 as a mask, 1 × 10 ¹³ cm ⁻² to 1 × 10 ^14. Ions are implanted at a dose of cm ⁻² to form a p-type well 21WA in the element region 21A, thereby obtaining the structure of FIG. 6C.

Further, in the step of FIG. 6C, B + is ion-implanted with a dose of 2 × 10 ¹³ cm ⁻² under an acceleration voltage of 10 keV using the resist film R32 as a mask, and p along the surface of the substrate 21 in the element region 21A. A type channel doped region 21thA is formed.

  Unlike the previous embodiment, in FIG. 6C, the resist film R32 includes the element isolation insulating film 21IB and the element region 21B on the surface of the silicon substrate 21 except for the element region 21A and the element isolation insulating film 21IA. Note that it covers continuously.

Next, the resist film R32 is removed by wet etching using sulfuric acid / hydrogen peroxide, and the element region 21B is exposed on the silicon substrate 21 including the peripheral element isolation oxide film 21IB. A resist film R33 having an opening R33B is formed. As + is ionized at a dose of 5 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² under an acceleration voltage of 200 to 900 keV at first using the resist film R33 as a mask. The n-type well 21WB is formed in the element region 21B to obtain the structure of FIG. 6D.

6D, P + is ion-implanted at a dose of 2 × 10 ¹³ cm ⁻² under an acceleration voltage of 50 keV using the resist film R33 as a mask, and n-type channel doping is performed along the substrate surface in the element region 21B. Region 21thB is formed.

  Unlike the previous embodiment, in FIG. 6D, the resist film R33 includes the element isolation insulating film 21IA and the element region 21A on the surface of the silicon substrate 21 except for the element region 21B and the element isolation insulating film 21IB. Note that it covers continuously.

  Further, in the structure of FIG. 6D, the resist film R33 is removed by wet etching using sulfuric acid / hydrogen peroxide, and the sacrificial oxide film 22S is removed by wet etching using HF. obtain.

  In the structure of FIG. 6E, since the element isolation oxide films 21IA and 21IB are first deeply ion-implanted with an element such as heavy In, the portion damaged by In is wet etching using the above-described sulfuric acid / hydrogen peroxide, Alternatively, it is removed by wet etching using HF, but the etching amount δ of the element isolation oxide film 21IA and the element isolation oxide film 21IB is substantially the same as in the case of FIG. 4I. This is because in the B + and As + ion implantation process, the projected range of B + ions and As + ions is about 40 nm, and almost overlaps with the projected range of In + ions in the In + ion implantation process.

  Therefore, after the process of FIG. 6E, by performing the process described with reference to FIGS. 4J to 4T in the previous embodiment, a semiconductor device having the same configuration as that of FIG. 4T can be obtained.

  Also in this embodiment, the retraction amounts of the element isolation insulating films 21IA and 21IB are the same, and the problem that the width of the obtained pattern deviates from the design value when the gate electrode 23GA or 23GB is patterned is avoided. Further, even when a multilayer wiring structure is formed on the structure of FIG. 1T, the positional deviation of the wiring pattern and the deviation of the pattern width due to the different projecting heights of the element isolation insulating films 21IA and 21IB on the silicon substrate 21. The problem can be avoided.

  In the present embodiment, the mask process of FIG. 6A is required more than the ordinary method for manufacturing a semiconductor device. In return, the same process as that conventionally used in the steps of FIGS. 6C and 6D is used. A mask process can be used, and an increase in manufacturing cost of the semiconductor device can be suppressed as much as possible.

In this embodiment, As + can be used instead of In + in the process of FIG. 6A. When As is used in place of In, As + may be ion-implanted at a dose of 4.5 × 10 ¹³ cm ⁻² or more under an acceleration voltage of 50 keV in the process of FIG. 6A.

  Further, the In ion implantation step of FIG. 6A can be performed after the ion implantation step of FIG. 6C or FIG. 6D.

[Fourth Embodiment]
By the way, in the case of the first embodiment, for example, in the process of FIG. 4G or FIG. If the resist opening R21b or R21a is misaligned, unnecessary ion implantation is performed in the element region 21A or the element region 21B, and the electrical characteristics of the n-channel MOS transistor or the p-channel MOS transistor deviate from the desired values. There is a risk that.

  7A to 7G show a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention, which solves the above problems. However, the same reference numerals are given to portions corresponding to the portions described above, and the description thereof is omitted.

In this embodiment, following the step of FIG. 4C, a liner film 24L made of BSG or PSG is first covered by CVD on the structure of FIG. 4C so as to cover the side wall surface and the bottom surface of the element isolation trench 21T. For example, the film is formed to a thickness of, for example, 10 nm to 50 nm, and then the element isolation trench 21T is filled with the silicon oxide film 24 made of undoped silica glass by a high density plasma CVD method to obtain the structure of FIG. 7A. Here, when the liner film 24L is formed of a BSG film, the ratio (B ₂ O ₃ / SiO ₂ ) of the B ₂ O ₃ component to the SiO ₂ component in the film is 0.1 or more in terms of molar ratio, When the liner film 24L is composed of a PSG film, the ratio (P ₂ O ₅ / SiO ₂ ) of the P ₂ O ₅ component to the SiO ₂ component in the film is preferably 0.008 or more in molar ratio. .

In any case, the concentration of B or P in the liner film 24L is realized by adjusting the composition of the source gas in the CVD process for forming the liner film 24. For example, when the liner film 24L is a B ₂ O ₃ film, silane (SiH ₄ ) gas, nitrogen gas, oxygen gas, and diborane (B ₂ H ₆ ) gas are used as raw materials. The flow rate ratio (B ₂ H ₆ / SiH ₄ ) is set to 0.05 or more, for example. Also for example, the liner film 24L if the P ₂ O ₅ film, using a silane gas and nitrogen gas and oxygen gas and phosphine (PH ₃₎ gas as a raw material, the flow rate ratio for the case, silane gas phosphine gas (PH ₃ / SiH ₄ ) is set to 0.02 or more, for example. In the liner film 24L thus formed, an increase in etching rate due to damage during ion implantation can be suppressed to 5% or less. For this reason, even if ion implantation of an impurity element occurs in the liner film 24L due to a positional shift of a resist mask, which will be described later, a large change in etching rate does not occur in the liner film 24L.

  The formation of the silicon oxide film 24 can be performed in the same manner as in the first embodiment.

  Next, the silicon oxide film 24 including the liner film 24L below it is polished by CMP until the silicon nitride film 23 is exposed to obtain the structure of FIG. 7B.

Further, the silicon nitride film 23 is removed by wet etching using, for example, H ₃ PO _4, and the pad oxide film 22 is removed by wet etching using HF, so that the surface of the silicon substrate 21 is exposed.

  In this step, in particular, the portion of the liner film 24L containing B or P recedes with a receding amount δL larger than the element isolation oxide film 21IA or 21IB made of an undoped silicon oxide film, and the structure shown in FIG. 7C is obtained. .

  Next, the structure of FIG. 7C is thermally oxidized, and a sacrificial oxide film 22S is formed on the exposed surface of the silicon substrate 21 with a thermal oxide film having a thickness of 5 to 20 nm to obtain the structure of FIG. 7D.

  Next, the resist film R21B is exposed on the structure of FIG. 7D including the element isolation insulating film 21IA in the element region 21A, and the resist opening R21b is element isolation insulating in the element region 21B. Only the film 21IB is exposed, and B + ion implantation is performed to form the p-type well 21A and the p-type channel doped region 21thA in the element region 21A as shown in FIG. 7E, and at the same time, the element isolation insulating film Introduce B into 21IB.

  At this time, even if the resist film R21B is displaced and the resist opening R21b is displaced from the element isolation insulating film 21IB, the degree of displacement is small, and the element region 21B is not exposed to the extent that the liner film 21L is exposed. In this case, B is not introduced into the element region 21B, and the electrical characteristics of the p-channel MOS transistor formed in the element region 21B in a later step are not modulated from a desired value.

  Next, the resist film R21A is exposed on the structure of FIG. 7E including the element isolation insulating film 21IB in the element region 21B, and the resist opening R21a is element isolation insulating in the element region 21A. Only the film 21IA is formed to be exposed, As + ion implantation is performed, and the p-type well 21B and the p-type channel doped region 21thB are formed in the element region 21B as shown in FIG. As or P is introduced into 21IA.

  At this time, even if the resist film R21A is displaced and the resist opening R21a is displaced from the element isolation insulating film 21IA, the degree of displacement is small, and the element region 21A is not exposed to the extent that the liner film 21L is exposed. In this case, As or P is not introduced into the element region 21A, and the electrical characteristics of the n-channel MOS transistor formed in the element region 21A in a later step are not modulated from a desired value.

  Further, after removing the resist film R21A, the sacrificial oxide film 22S is removed by wet etching with HF to obtain a structure shown in FIG. 7G. At that time, since the element isolation insulating films 21IA and 21IB are introduced with the same amount of B and P or As, both show the same etching recession amount δ. Further, the liner film 24L has been previously retracted in the process of FIG. 7C, and the element isolation oxide films 21IA and 21IB are retracted in the process of FIG. 7G, and therefore, the element isolation oxide film 21IA or 21IB and the liner film 24L are separated. The step can be kept relatively small.

  Furthermore, after the process of FIG. 7G, a desired semiconductor device can be obtained by executing the processes described above with reference to FIGS. The semiconductor device according to the present embodiment is characterized in that the element isolation region includes the liner insulating film 24L that covers the side wall surface and the bottom surface of the element isolation trench, and the element isolation oxide film 21IA or 21IB that fills the inside.

  In this embodiment, a thermal oxide film can be used instead of the liner film 24L, and B-doped glass (BSG) or P-doped glass (PSG) can be used instead of the undoped silicon oxide film 24. It is also possible to use a thermal oxide film as the liner film 24L and an undoped silicon oxide film 24 as the silicon oxide film 24.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
Forming an element isolation region having an STI structure on a silicon substrate;
A first impurity element is introduced into the first region of the silicon substrate by a first ion implantation process in a state where the second region of the silicon substrate is covered with a first resist pattern, and the first region is introduced. Forming a first well having a first conductivity type in
In the second region of the silicon substrate, a second impurity element which is an impurity element having a conductivity opposite to that of the first impurity element is applied to the second region in a state where the element region is covered with a second resist pattern. Forming a second well having a second conductivity type opposite to the first conductivity type in the second region,
Including
The first resist pattern has a first opening that exposes an element isolation region included in the second region of the element isolation regions,
In the step of forming the first well, the first impurity element is introduced into the portion of the element isolation region exposed in the first opening by the first ion implantation step,
The second resist pattern has a second opening that exposes an element isolation region included in the first region of the element isolation regions,
In the step of forming the second well, the second impurity element is introduced into the portion of the element isolation region exposed at the second opening by the second ion implantation step. A method of manufacturing a semiconductor device.
(Appendix 2)
Further, after the formation of the first and second wells, in the first element region defined by the element isolation region in the first region of the silicon substrate, and in the second region of the silicon substrate Forming first and second gate electrodes respectively in a second element region defined by the element isolation region;
The silicon substrate is covered with a third resist pattern that exposes the first region, the second impurity element of the second conductivity type is formed in the first element region, and the third resist pattern is used as a mask. The first and second diffusion regions having the second conductivity type are formed in the first element region adjacent to the left and right sides of the first gate electrode, respectively. And a process of
The silicon substrate is covered with a fourth resist pattern that exposes the second region, the second element region is filled with the fourth impurity element of the second conductivity type, and the fourth resist pattern is used as a mask. In the second element region, first and second diffusion regions having the first conductivity type are formed adjacent to the left and right sides of the second gate electrode, respectively. And a process of
Including
In the third resist pattern, a third opening that exposes an element isolation region that defines the second element region of the element isolation region is formed,
In the step of forming the first and second diffusion regions, the third impurity element is introduced into the portion of the element isolation region exposed at the third opening by the third ion implantation step. And
The fourth resist pattern is formed with a fourth opening that exposes an element isolation region that defines the first element region of the element isolation region.
In the step of forming the third and fourth diffusion regions, the fourth impurity element is introduced into the portion of the element isolation region exposed at the fourth opening by the fourth ion implantation step. The method of manufacturing a semiconductor device according to appendix 1, wherein:
(Appendix 3)
The first resist pattern and the third resist pattern are exposed by a first exposure mask, and the second resist pattern and the fourth resist pattern are exposed by a second exposure mask. The method for manufacturing a semiconductor device according to appendix 2.
(Appendix 4)
The first resist pattern covers a peripheral portion of each element isolation region included in the second region and exposes a central portion, and the second resist pattern includes individual portions included in the first region. 5. The method for manufacturing a semiconductor device according to any one of appendices 1 to 4, wherein the peripheral portion of the element isolation region is covered and the central portion is exposed.
(Appendix 5)
5. The method of manufacturing a semiconductor device according to appendix 4, wherein in the individual element isolation regions, the central portion and the peripheral portion have different compositions.
(Appendix 6)
Forming an element isolation region having an STI structure on a silicon substrate;
Covering the silicon substrate with a first resist pattern that exposes the element isolation region, and selectively introducing a first impurity element into the element isolation region by ion implantation using the first resist pattern as a mask; When,
A second impurity element is introduced into the first region of the silicon substrate by ion implantation in a state where the second region of the silicon substrate is covered with a second resist pattern, and a first conductive element is introduced into the first region. Forming a first well having a mold;
A third impurity element having a conductivity type opposite to that of the first impurity element is introduced into the second region of the silicon substrate by ion implantation in a state where the element region is covered with a third resist pattern; Forming a second well having a second conductivity type opposite to the first conductivity type in the second region,
The method of manufacturing a semiconductor device, wherein the first impurity element has an atomic weight equal to or larger than an atomic weight of an impurity element having a larger atomic weight among the second and third impurity elements.
(Appendix 7)
The step of forming the element isolation region includes a step of forming a fourth resist pattern that exposes a portion where the element isolation region is formed on the silicon substrate, and etching the silicon substrate using the fourth resist pattern as a mask. A step of forming an element isolation groove, a step of filling the element isolation groove with an insulating film, a step of chemically mechanically polishing the insulating film, and forming an element isolation insulating film in the element isolation groove. The method for manufacturing a semiconductor device according to appendix 6, wherein the fourth resist pattern is formed using the same exposure mask as the first resist pattern.
(Appendix 8)
8. The method of manufacturing a semiconductor device according to appendix 6 or 7, wherein the first impurity element is In or As.
(Appendix 9)
Further, after the formation of the first and second wells, the first element region defined by the element isolation region in the first region of the silicon substrate, and the second region of the silicon substrate in the second region Forming first and second gate electrodes respectively in a second element region defined by the element isolation region;
The silicon substrate is covered with a fifth resist pattern that exposes the first region, the fourth impurity element of the second conductivity type is formed in the first element region, and the third resist pattern is used as a mask. Forming the first and second diffusion regions having the second conductivity type in the first element region adjacent to the left and right of the first gate electrode, respectively,
The silicon substrate is covered with a sixth resist pattern that exposes the second region, the fifth impurity element of the second conductivity type is formed in the second element region, and the fourth resist pattern is used as a mask. Forming the first and second diffusion regions having the first conductivity type in the second element region adjacent to the left and right sides of the second gate electrode, respectively.
The manufacturing method of the semiconductor device as described in any one of the supplementary notes 6-8 characterized by including.

It is FIG. (1) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (2) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (3) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (4) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (5) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (6) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (7) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (The 8) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (9) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (10) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (11) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (12) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (13) which shows the manufacturing process of the conventional semiconductor device. It is FIG. (14) which shows the manufacturing process of the conventional semiconductor device. It is a figure explaining the subject of one Embodiment. It is another figure explaining the subject of one Embodiment. FIG. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment; FIG. 9 is a diagram (part 2) illustrating a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram (No. 3) for illustrating a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a diagram (part 4) illustrating a manufacturing process of the semiconductor device according to the first embodiment; FIG. 8 is a diagram (No. 5) for illustrating a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a view (No. 6) illustrating a manufacturing step of the semiconductor device according to the first embodiment; FIG. 7 is a view (No. 7) for illustrating a manufacturing step of the semiconductor device according to the first embodiment; FIG. 8 is a diagram (No. 8) for illustrating a manufacturing step of the semiconductor device according to the first embodiment; FIG. 9 is a diagram (No. 9) for illustrating a manufacturing step of the semiconductor device according to the first embodiment; FIG. 10 is a diagram (No. 10) for illustrating a manufacturing step of the semiconductor device according to the first embodiment; FIG. 11 is a view (No. 11) showing a manufacturing step of the semiconductor device according to the first embodiment; FIG. 12 is a view (No. 12) showing a manufacturing step of the semiconductor device according to the first embodiment; FIG. 13 is a view (No. 13) showing a manufacturing step of the semiconductor device according to the first embodiment; It is FIG. (14) which shows the manufacturing process of the semiconductor device by 1st Embodiment. FIG. 15 is a view (No. 15) showing a manufacturing step of the semiconductor device according to the first embodiment; It is FIG. (16) which shows the manufacturing process of the semiconductor device by 1st Embodiment. FIG. 17 is a view (No. 17) showing a manufacturing step of the semiconductor device according to the first embodiment; It is FIG. (18) which shows the manufacturing process of the semiconductor device by 1st Embodiment. FIG. 19 is a diagram (19) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. 20 is a view (No. 20) illustrating the process for manufacturing the semiconductor device according to the first embodiment; FIG. 10 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the second embodiment; FIG. 11 is a diagram (part 2) illustrating a manufacturing process of the semiconductor device according to the second embodiment; FIG. 11 is a diagram (No. 3) for illustrating a manufacturing step of the semiconductor device according to the second embodiment; FIG. 14 is a diagram (No. 4) for illustrating a manufacturing step of the semiconductor device according to the second embodiment; It is FIG. (5) which shows the manufacturing process of the semiconductor device by 2nd Embodiment. It is FIG. (6) which shows the manufacturing process of the semiconductor device by 2nd Embodiment. It is FIG. (1) which shows the manufacturing process of the semiconductor device by 3rd Embodiment. It is FIG. (2) which shows the manufacturing process of the semiconductor device by 3rd Embodiment. FIG. 10 is a diagram (No. 3) for illustrating a manufacturing step of the semiconductor device according to the third embodiment; It is FIG. (4) which shows the manufacturing process of the semiconductor device by 3rd Embodiment. It is FIG. (5) which shows the manufacturing process of the semiconductor device by 3rd Embodiment. It is FIG. (1) which shows the manufacturing process of the semiconductor device by 4th Embodiment. It is FIG. (2) which shows the manufacturing process of the semiconductor device by 4th Embodiment. It is FIG. (The 3) which shows the manufacturing process of the semiconductor device by 4th Embodiment. It is FIG. (4) which shows the manufacturing process of the semiconductor device by 4th Embodiment. It is FIG. (5) which shows the manufacturing process of the semiconductor device by 4th Embodiment. It is FIG. (6) which shows the manufacturing process of the semiconductor device by 4th Embodiment. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device by 4th Embodiment.

Explanation of symbols

11, 21 Silicon substrate 11A, 11B, 21A, 21B Element region 11T, 21T Element isolation groove 12, 22 Pad oxide film 13, 23 Silicon nitride film 13A, 23A Opening 14, 24 Silicon oxide film 14IA, 14IB, 21A, 21B Element isolation oxide film 15, 22G Gate insulating film 16G, 23 Polysilicon film 17, 24 Antireflection film 18, R1, R2, R21A, R21B, R22 Resist film 21a, 21c Source extension region 21b, 21d Drain extension region 21e, 21g Source region 21f, 21h Drain region 21WA p-type well 21WB n-type well 21thA p-type channel doped region 21thB n-type channel doped region 22S sacrificial oxide film 23GA, 23GB gate electrode 23GAw, 2 GBw gate electrode side wall insulating film 25 insulating film 25A, 25B, 25C, 25D contact plugs 24L liner film 31 a silicon nitride film R21a, R21b, R23Ao, R23Bo, R23a, R23b resist opening

Claims (6)

Forming an element isolation region having an STI structure on a silicon substrate;
A first impurity element is introduced into the first region of the silicon substrate by a first ion implantation process in a state where the second region of the silicon substrate is covered with a first resist pattern, and the first region is introduced. Forming a first well having a first conductivity type in
In the second region of the silicon substrate, a second impurity element which is an impurity element having a conductivity opposite to that of the first impurity element is applied to the second region in a state where the element region is covered with a second resist pattern. Forming a second well having a second conductivity type opposite to the first conductivity type in the second region,
Including
The first resist pattern has a first opening that exposes an element isolation region included in the second region of the element isolation regions,
In the step of forming the first well, the first impurity element is introduced into the portion of the element isolation region exposed in the first opening by the first ion implantation step,
The second resist pattern has a second opening that exposes an element isolation region included in the first region of the element isolation regions,
In the step of forming the second well, the second impurity element is introduced into the portion of the element isolation region exposed at the second opening by the second ion implantation step. A method of manufacturing a semiconductor device. Further, after the formation of the first and second wells, in the first element region defined by the element isolation region in the first region of the silicon substrate, and in the second region of the silicon substrate Forming first and second gate electrodes respectively in a second element region defined by the element isolation region;
The silicon substrate is covered with a third resist pattern that exposes the first region, the second impurity element of the second conductivity type is formed in the first element region, and the third resist pattern is used as a mask. The first and second diffusion regions having the second conductivity type are formed in the first element region adjacent to the left and right sides of the first gate electrode, respectively. And a process of
The silicon substrate is covered with a fourth resist pattern that exposes the second region, the second element region is filled with the fourth impurity element of the second conductivity type, and the fourth resist pattern is used as a mask. In the second element region, first and second diffusion regions having the first conductivity type are formed adjacent to the left and right sides of the second gate electrode, respectively. And a process of
Including
In the third resist pattern, a third opening that exposes an element isolation region that defines the second element region of the element isolation region is formed,
In the step of forming the first and second diffusion regions, the third impurity element is introduced into the portion of the element isolation region exposed at the third opening by the third ion implantation step. And
The fourth resist pattern is formed with a fourth opening that exposes an element isolation region that defines the first element region of the element isolation region.
In the step of forming the third and fourth diffusion regions, the fourth impurity element is introduced into the portion of the element isolation region exposed at the fourth opening by the fourth ion implantation step. The method of manufacturing a semiconductor device according to claim 1, wherein:   The first resist pattern and the third resist pattern are exposed by a first exposure mask, and the second resist pattern and the fourth resist pattern are exposed by a second exposure mask. A method for manufacturing a semiconductor device according to claim 2. The first resist pattern covers a peripheral portion of each element isolation region included in the second region and exposes a central portion, and the second resist pattern includes individual portions included in the first region. according among claim 1-3, the method of manufacturing a semiconductor apparatus according to any one claim characterized by exposing a central portion covering the periphery of the element isolation region. Forming an element isolation region having an STI structure on a silicon substrate;
Covering the silicon substrate with a first resist pattern that exposes the element isolation region, and selectively introducing a first impurity element into the element isolation region by ion implantation using the first resist pattern as a mask; When,
A second impurity element is introduced into the first region of the silicon substrate by ion implantation in a state where the second region of the silicon substrate is covered with a second resist pattern, and a first conductive element is introduced into the first region. Forming a first well having a mold;
A third impurity element having a conductivity type opposite to that of the first impurity element is introduced into the second region of the silicon substrate by ion implantation in a state where the element region is covered with a third resist pattern; Forming a second well having a second conductivity type opposite to the first conductivity type in the second region,
The method of manufacturing a semiconductor device, wherein the first impurity element has an atomic weight equal to or larger than an atomic weight of an impurity element having a larger atomic weight among the second and third impurity elements.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the first impurity element is In or As.

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