JP2000315791A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PMOS transistor in which decrease of a threshold value and deterioration of cut-off characteristic are prevented by preventing boron punch through in a gate electrode, and a manufacturing method of the transistor. SOLUTION: A gate oxide film, a gate electrode 105 into which boron is introduced, and source/drain regions 106, 108 are formed on an Si substrate 101, and a side wall 107 of an Si oxide film is formed on the side surface of the gate electrode, thereby constituting a PMOS transistor. A direct Si nitride film 109 is formed so as to cover the PMOS, and an interlayer insulating film of SiO2 is formed on the film 109. Since the direct Si nitride film is grown by using material containing heavy hydrogen, chemical species of hydrogen which is diffused in the gate electrode by heat treatment during and after film formation become heavy hydrogen D. Since diffusion speed of D is lower than that of ordinary hydrogen H1, and hydrogen concentration of the gate electrode and in the vicinity of a gate oxide film interface is lower than that of an ordinary case, diffusion of bron in the gate electrode 105 is restrained, and decrease of a threshold value of the PMOSFET and deterioration of cut-off characteristic are restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a gate electrode into which an impurity such as boron is implanted, and more particularly to a semiconductor device suitable for being applied to a semiconductor device having a PMOSFET having a P-type gate and a method of manufacturing the same. Things.

[0002]

2. Description of the Related Art In response to recent demands for lower voltage and lower power consumption of semiconductor devices, a technique has been proposed in which a gate insulating film of a MOS transistor is made thinner and impurities are introduced into polycrystalline silicon serving as a gate. Have been.
For example, P-type impurities such as boron are ion-implanted into a gate electrode of a PMOS transistor (PMOSFET) to make the gate electrode P-type. However, in the case of a PMOS transistor having a P-type gate electrode, when a silicon nitride film is formed in contact with the gate electrode in a subsequent step, hydrogen taken in the silicon nitride film or hydrogen generated at the time of film formation. Is known to diffuse into the gate electrode to promote the diffusion of boron in the gate electrode. For example, Japanese Patent Application Laid-Open No. 10-22396 discloses an LPCVD method in which a gate electrode of a PMOS transistor is formed, boron is injected into the gate electrode, and dichlorosilane and ammonia gas are mixed under reduced pressure.
When a silicon nitride film is formed by a method and a side wall (gate side wall) in contact with a side surface of the gate electrode is formed by the silicon nitride film, hydrogen taken into the side wall by a heat treatment is diffused into the gate electrode. It is reported that boron diffusion will proceed. For example, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.37, N
O.8, AUGUST 1990, pp1842-1849. When the diffusion of boron is promoted, as described in the above-mentioned publication, boron existing near the gate oxide film interface in the gate electrode is diffused through the gate oxide film to the channel region immediately below. In other words, a so-called boron penetration diffusion phenomenon occurs, which causes a problem that the threshold value of the PMOS transistor is lowered and the cutoff characteristic is deteriorated.

For this reason, by forming the gate side wall with a silicon oxide film, it is possible to prevent the incorporation of hydrogen into the gate side wall when the side wall is formed with a silicon nitride film as described in the above-mentioned publication, and to prevent the penetration and diffusion of boron. Can be suppressed. However, on the other hand, it is sometimes unavoidable to form a silicon nitride film on the gate electrode, and in such a semiconductor device, it is difficult to solve the problem associated with the boron diffusion described above. In other words, conventionally, the source
In order to realize a contact structure for a drain region, there is a technique of forming a silicon nitride film called a direct silicon nitride film from a gate electrode on a MOS transistor including source / drain regions.

FIG. 6 is a schematic process diagram showing one example.
As shown in FIG. 6A, an STI (Shallow Trench Isolation) 202 is formed on a silicon substrate 201 to define an element formation region, and then a gate insulating film 204 and a gate electrode 205 are formed by a conventional method. At the same time, low-concentration boron is implanted into the silicon
The DD region 206 is formed. At this time, boron is also injected into the gate electrode 205. Further, after forming a sidewall 207 with a silicon oxide film on the side surface of the gate electrode 205, high-concentration boron is implanted into the silicon substrate 201 to form a source / drain region 208, thereby forming a PMOS transistor. Then, a direct silicon nitride film 209 is formed so as to cover the MOS transistor, and an interlayer insulating film 2 covering the MOS transistor is formed thereon.
10 is formed of a silicon oxide film (BPSG, BSG).

Next, as shown in FIG. 6B, the interlayer insulating film 210 is selectively etched using a mask 214 such as a photoresist to open a contact hole 211. At this time, if the opening of the contact hole 211 in the interlayer insulating film 210 is insufficient, the electrical connection to the source / drain region 208 becomes poor, so that the contact hole 2
At the time of opening 11, the interlayer insulating film 210 is slightly over-etched, and even if the interlayer insulating film 210 varies in thickness, all the contact holes 211 are completely opened. Therefore, if FIG.
As shown in (c), the direct silicon nitride film 209 is formed.
Is not present and the contact hole 211 is displaced to the right in the figure, the side wall 20 depends on the direction of displacement of the contact hole 211.
7 and STI 202 are etched. Therefore, when the contact hole 211 is filled with a conductive material, when the sidewall 207 is etched, the filling material causes deterioration of transistor characteristics due to contact implantation, or when a part of the STI 202 is etched, A part of the conductive material in the contact hole 211 penetrates into the etched portion, and short-circuits the adjacent source / drain region 206.

On the other hand, as shown in FIG.
By forming the direct silicon nitride film 209, as shown in FIG. 6B, when the interlayer insulating film 210 of the silicon oxide film is over-etched, the progress of the etching is prevented by the direct silicon nitride film 209. The STI 20
2 is not etched. Therefore, it is possible to prevent the occurrence of the above-described element failure due to the overetching of the sidewall 207 and the STI 202 when the interlayer insulating film 210 is overetched. After that, although not shown, the source / drain region 208 can be opened by selectively etching the direct silicon nitride film 209.

[0007]

As described above, in a semiconductor device that requires the direct silicon nitride film 209 to cope with the positional deviation of the contact hole, the semiconductor device is not compatible with the silicon oxide film forming the interlayer insulating film 210. Since it is necessary to obtain etching selectivity, the sidewall 20
7, the direct silicon nitride film 209 cannot be replaced with a silicon oxide film as in the case where the silicon nitride film is replaced with a silicon oxide film. for that reason,
When the direct silicon nitride film 209 is formed, as described above, hydrogen is taken into the direct silicon nitride film 209, and this hydrogen or hydrogen generated at the time of film formation diffuses into the gate electrode 205,
The diffusion of the boron implanted into the gate electrode 205 is promoted, and the penetration phenomenon of boron occurs, which makes it difficult to prevent the threshold value of the PMOS transistor from being lowered and the cutoff characteristic from being deteriorated.

An object of the present invention is to suppress the diffusion of boron existing at the interface between a gate electrode and a gate oxide film in a PMOS transistor in which boron is implanted into the gate electrode and in a semiconductor device including a silicon nitride film on the gate electrode. And
It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, in which a decrease in threshold voltage and a decrease in cutoff characteristics are prevented.

[0009]

According to the present invention, there is provided a semiconductor device having a PMOS transistor having a gate electrode into which boron is introduced, and a silicon nitride film formed on the gate electrode, wherein the silicon nitride film has It is characterized by being formed by a source gas containing hydrogen. Here, the silicon nitride film covers the PMOS transistor and is configured as a direct silicon nitride film provided below the interlayer insulating film. Alternatively, the silicon nitride film is configured as a sidewall provided on a side surface of the gate electrode.

The present invention also provides a semiconductor device including a step of forming a gate electrode on a silicon substrate and introducing boron into the gate electrode, and a step of forming a silicon nitride film so as to cover the gate electrode. In the manufacturing method, the step of forming the silicon nitride film is characterized in that the silicon nitride film is grown using a source gas containing deuterium. The step of forming the silicon nitride film can be applied to a step of forming a direct silicon nitride film which covers a PMOS transistor and is provided below an interlayer insulating film, or is formed as a sidewall provided on a side surface of the gate electrode. Applicable to the process. In particular, in the manufacturing method of the present invention, in the manufacturing process of the silicon nitride film, it is preferable to grow the silicon nitride film by LPCVD using deuterated silane and deuterated ammonia as a source gas.

In the present invention, in the production of a silicon nitride film,
Since a source gas containing deuterium is used, deuterium is taken into the grown silicon nitride film and diffused into the gate electrode, or deuterium is directly diffused into the gate electrode. Since deuterium has a larger mass number than hydrogen, the diffusion of deuterium is slower than that of hydrogen. Therefore, even if the heat treatment is performed after forming the silicon nitride film,
Since the diffusion of deuterium in the gate electrode is slower than ordinary hydrogen, the concentration of hydrogen near the interface between the gate electrode and the gate oxide film is low, and the boron Diffusion toward the oxide film and the substrate is suppressed. As a result, so-called boron penetration is suppressed, so that a decrease in the threshold value of the PMOS transistor can be prevented, and cutoff characteristics are improved.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are sectional views showing a first embodiment of the present invention in the order of manufacturing steps. First, FIG.
1A, an STI 102 is formed on a silicon substrate 101 as an element isolation oxide film. This STI102
A shallow groove is formed by forming a resist mask (not shown) on the surface of the silicon substrate 101 and etching the element isolation region shallowly, a silicon oxide film is grown in the shallow groove, and the surface is formed by a CMP method or the like. It is formed by flat polishing. Next, as shown in FIG.
After the natural oxide film formed on the surface of the silicon substrate 101 is removed by washing using an acid such as dilute hydrofluoric acid, the silicon substrate is oxidized again to form a gate oxide film 104. Further, a polycrystalline silicon film is formed on the entire surface by a CVD method. Then, by photolithography technology using a resist pattern (not shown) as a mask,
The polycrystalline silicon film is selectively etched by dry etching using a gas such as HBr or Cl to form a gate electrode 105. Then, as shown in FIG.
Using the gate electrode 105 as a mask, boron is ion-implanted into the silicon substrate 101 at a low concentration to form an LDD region 1.
06 is formed. At this time, boron is also introduced into the gate electrode 105.

Next, as shown in FIG. 2A, a silicon oxide film is formed on the entire surface of the silicon substrate 101,
The side wall 107 is formed on the side surface of the gate electrode 105 by etching back the silicon oxide film by anisotropic dry etching. Then, using the gate electrode 105 and the side wall 107 as a mask, boron is ion-implanted at a high concentration,
A drain region 108 is formed. This allows PMOS
A transistor is formed.

Next, as shown in FIG. 2B, a direct silicon nitride film 109 is formed on the entire surface. In the manufacturing process of the direct silicon nitride film 109, a deuterium compound is used as a source gas instead of a conventional hydrogen compound. In this embodiment, deuterated silane (SiD ₄ )
And deuterated annimore (ND ₃ ) are grown by LPCVD. 3SiD ₄ + 4ND ₃ → Si ₃ D ₄ + 12D _{2 The} growth conditions are, for example, SiD ₄ , 4N at 700 ° C.
The partial pressure of D ₃ is 0.3 Torr. As a result, deuterium is taken into the grown direct silicon nitride film 109 instead of conventional hydrogen, and at the same time, deuterium is diffused into the gate electrode.

Next, as shown in FIG. 2C, after an interlayer insulating film 110 of a silicon oxide film is formed on the above-mentioned direct silicon nitride film 109, dry etching is performed using a resist pattern (not shown) as a mask. A contact hole 111 is opened at a required position of the interlayer insulating film 110, in this embodiment, at a position corresponding to the drain region 108 of the PMOS transistor. This contact hole 1
In the opening step 11, a slight over-etching is performed on the thickness of the interlayer insulating film 110, so that the target MO can be formed regardless of the variation in the thickness of the interlayer insulating film 110.
All the contact holes of the S transistor are reliably opened until they reach the direct silicon nitride film 109. At this time, the direct silicon nitride film 109 is not removed by etching due to the etching selectivity between the silicon oxide film and the direct silicon nitride film.
Therefore, even if the contact hole 111 is misaligned, the sidewall 107 or the ST
The silicon oxide film constituting I102 is not etched.

Then, as shown in FIG. 3, the direct silicon nitride film 109 exposed in the contact hole 111 is dry-etched to remove the direct silicon nitride film 109, thereby forming a lower drain region. The surface of the silicon substrate 101 is exposed. Further, a conductive polycrystalline silicon film 112 into which impurities are introduced is deposited and etched back to bury the polycrystalline silicon film 112 in the contact hole 111 to form a contact plug 112. As a result, a contact plug 112 electrically connected to the drain region 108 is formed, and a wiring layer formed on the interlayer insulating film in a later step can be connected to the drain region.

As described above, in the above embodiment, the PMO
Direct silicon nitride film 109 covering S transistor
Is provided, the direct silicon nitride film 109 allows the side wall 1 to be formed even if a positional shift occurs when the contact hole 111 is opened in the interlayer insulating film 110.
07 and the STI 102 are prevented from being etched, and the gate electrode 105 and the silicon substrate 101 are prevented from being exposed in the contact hole 111. Therefore, even when the contact plug 112 is formed in a subsequent step to make an electrical connection to the drain region 108, the contact plug 112 is short-circuited to the gate electrode 105, or the contact plug 112 is
A situation in which the drain region 102 is short-circuited by direct electrical connection to the silicon substrate 101 via the exposed region of the semiconductor substrate 102 is prevented.

The direct silicon nitride film 10
In the manufacture of No. 9, since deuterated silane and deuterated annimore are used, deuterium is taken into the grown direct silicon nitride film 109, and at the same time, deuterium is diffused into the gate electrode 105. Will be. Since deuterium has a higher mass number than hydrogen, when the same heat is applied, the diffusion of deuterium is usually slower than that of hydrogen of mass number. Therefore, when the heat treatment step after the formation of the direct silicon nitride film 109, for example, the heat treatment step in the step of forming the contact plug 112 in the above embodiment, the direct silicon nitride film 109 Deuterium diffused into the gate electrode 105 and deuterium directly diffused into the gate electrode 105 as described above, due to slow diffusion in the gate electrode 105, the The hydrogen concentration in the vicinity of the interface is reduced, so that the diffusion of boron in the gate electrode 105 is also suppressed, so that the boron existing at the interface is not diffused into the gate oxide film 104. As a result, it is possible to prevent a decrease in the threshold value of the PMOS transistor, which is caused by the penetration of boron, and to improve cutoff characteristics.

Here, in the above embodiment, the embodiment of the semiconductor device having the direct silicon nitride film 109 covering the PMOS transistor has been described. However, the present invention is similarly applied to a semiconductor device having no direct silicon nitride film. It is possible to apply to. That is, as described in the official gazette described in the related art, the present invention can be applied to a semiconductor device having a gate sidewall formed of a silicon nitride film. This embodiment will be briefly described with reference to FIG. First, as shown in FIG. 4A, an STI 102 is formed on a silicon substrate 101 as an element isolation oxide film. This STI
102, a resist mask (not shown) is formed on the surface of the silicon substrate 101, a shallow groove is formed by etching the element isolation region shallowly, a silicon oxide film is grown in the shallow groove, and the surface is formed by a CMP method. It is formed by polishing flat by the method described above. Next, as shown in FIG. 4B, the natural oxide film formed on the surface of the silicon substrate 101 in the element formation region 103 is removed by cleaning using an acid such as dilute hydrofluoric acid, and then the silicon oxide is formed again. The substrate is oxidized to form a gate oxide film 104. Further, a polycrystalline silicon film is formed on the entire surface by a CVD method. The gate electrode 105 is formed by selectively etching the polycrystalline silicon film by dry etching using a gas such as HBr or Cl by a photolithography technique using a resist pattern (not shown) as a mask. Next, FIG.
Then, boron is ion-implanted into the silicon substrate 101 at a low concentration using the gate electrode 105 as a mask, as shown in FIG.
The DD region 106 is formed. At this time, boron is also introduced into the gate electrode 105.

Next, as shown in FIG. 5A, a silicon nitride film is formed on the entire surface of the silicon substrate 101,
In addition, the silicon nitride film is etched back by anisotropic dry etching to form sidewalls 113 on the side surfaces of the gate electrode 105. In the growth of the silicon nitride film forming the sidewalls 113, as in the first embodiment, deuterated silane (SiD ₄ ) and deuterated annimore (ND ₃ ) are used as source gases by LPCVD. Growing by.
As a result, deuterium is taken into the grown silicon nitride film, that is, the sidewall 113, instead of conventional hydrogen. Thereafter, the gate electrode 10
Boron is ion-implanted at a high concentration by using the mask 5 and the side walls 107 as masks to form source / drain regions 108. As a result, a PMOS transistor is formed.

After that, as shown in FIG. 5B, after forming an interlayer insulating film 110 of a silicon oxide film, the drain region 108 of the PMOS transistor is dry-etched using a resist pattern (not shown) as a mask. A contact hole 111 is opened in the interlayer insulating film at a location corresponding to the above. At the time of opening the contact hole 111, the direct silicon nitride film (109) as in the first embodiment does not exist in this embodiment, but the side wall 113 of the silicon nitride film is formed on the side surface of the gate electrode 105. Some contact holes 1
Even if the position shift of 11 occurs, the etching of the underlying silicon oxide film is prevented by the sidewall 113, so that at least the gate electrode 105 is not exposed in the contact hole 111. In doing so,
Conductive polycrystalline silicon film 11 with impurities introduced
2 is deposited and etched back to fill the contact hole 111 and form a contact plug 112. As a result, a contact plug 112 electrically connected to the drain region 108 is formed, and a wiring layer formed in the interlayer insulating film in a later step can be connected to the drain region 108.

As described above, also in this embodiment,
In the production of a silicon nitride film forming a sidewall in contact with a gate electrode of a PMOS transistor, deuterated silane and deuterated annimore are used, so that deuterium is incorporated into the grown silicon nitride film and the gate electrode. Will be. Therefore, even when the heat treatment step after the formation of the silicon nitride film, that is, the heat treatment step in the step of forming the source / drain regions in this example, the diffusion species is deuterium. Since the deuterium diffuses slowly in the gate electrode, the diffusion of boron existing at the interface between the gate electrode and the gate oxide film into the gate oxide film and the semiconductor substrate is suppressed, and so-called boron penetration is suppressed. In addition, a decrease in the threshold value of the PMOS transistor can be prevented, and the cutoff characteristic can be improved.

Here, in the above embodiment, the PMOS transistor is described as an example of the semiconductor device of the present invention. However, the NM is integrated with the PMOS transistor.
Semiconductor device of CMOS structure having OS transistor, Bi-CM integrally having bipolar transistor
In a semiconductor device having an OS structure, the present invention can be applied to a portion relating to a structure of the PMOS transistor and a manufacturing process thereof. Further, it goes without saying that the silicon nitride film in contact with the gate electrode of the PMOS transistor is not limited to the direct silicon nitride film and the sidewalls in the above embodiments.

[0024]

As described above, according to the present invention, in the production of a silicon nitride film provided in contact with a gate electrode into which boron is introduced, since a source gas containing deuterium is used, the silicon nitride film to be grown and the gate Deuterium is taken into the electrode instead of ordinary hydrogen. for that reason,
By the heat treatment process after forming the silicon nitride film,
Since the diffusion of deuterium in the gate electrode is slower than in the case of hydrogen having a normal mass number, the concentration of hydrogen near the interface between the gate electrode and the gate oxide film is reduced, and boron in the gate oxide film existing at the interface is reduced Penetration is suppressed. This allows P
It is possible to obtain a semiconductor device in which the threshold of a MOS transistor can be prevented from lowering and cutoff characteristics are improved, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a second sectional view showing the first embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a sectional view showing a completed state of the first embodiment of the present invention.

FIG. 4 is a first cross-sectional view showing a second embodiment of the present invention in the order of manufacturing steps.

FIG. 5 is a second sectional view showing the second embodiment of the present invention in the order of manufacturing steps.

FIG. 6 is a cross-sectional view showing an example of a conventional manufacturing method and its problems.

[Explanation of symbols]

 101 silicon substrate 102 STI 104 gate oxide film 105 gate electrode 106 LDD 107 sidewall (silicon oxide film) 108 source / drain region 109 direct silicon nitride film 110 interlayer insulating film (silicon oxide film) 111 contact hole 112 contact plug 113 sidewall (Silicon nitride film 201 Silicon substrate 202 STI 204 Gate oxide film 205 Gate electrode 206 LDD 207 Side wall 208 Source / drain region 209 Silicon nitride film 210 Interlayer insulating film (silicon oxide film) 211 Contact hole

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5F040 DA00 DA06 DA14 DC01 EC07 EC28 EF02 EH03 EK05 EL06 FA05 FA07 FC00 FC10 5F048 AA07 AC03 AC05 BA01 BB07 BC06 BF05 BG14 DA25 DA27 5F058 BA05 BA20 BC08 BF04 BF23 BF30 BJ01

Claims (7)

[Claims] 1. A semiconductor device comprising: a PMOS transistor having a gate electrode into which boron is introduced; and a silicon nitride film formed on the gate electrode, wherein the silicon nitride film uses a source gas containing deuterium. A semiconductor device characterized by being formed by deposition. 2. The semiconductor device according to claim 1, wherein the silicon nitride film is a direct silicon nitride film that covers the PMOS transistor and is provided below the interlayer insulating film.
3. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein said silicon nitride film is a sidewall provided on a side surface of said gate electrode. 4. A method of manufacturing a semiconductor device, comprising: forming a gate electrode on a silicon substrate and introducing boron into the gate electrode; and forming a silicon nitride film so as to cover the gate electrode. The method of manufacturing a semiconductor device, wherein in the step of forming the silicon nitride film, the silicon nitride film is grown using a source containing deuterium. 5. A step of forming a gate oxide film and a gate electrode on a silicon substrate; a step of introducing boron into the gate electrode; and a step of forming source / drain regions by introducing impurities into the silicon substrate. A method of forming a PMOS transistor, comprising: forming a direct silicon nitride film covering the gate electrode and the source / drain regions; and performing a heat treatment after forming the direct silicon nitride film. The method of manufacturing a semiconductor device, wherein in the step of forming a direct silicon nitride film, the direct silicon nitride film is grown using a source gas containing deuterium. 6. A step of forming a gate oxide film and a gate electrode on a silicon substrate, a step of introducing boron into the gate electrode, a step of forming a silicon nitride film so as to cover the gate electrode, and forming the silicon nitride film. Forming a PMOS transistor including a step of forming a sidewall on a side surface of the gate electrode by etching back the substrate and a step of forming a source / drain region by introducing an impurity into the silicon substrate. A method of manufacturing a semiconductor device, wherein in the step of forming a silicon nitride film, the silicon nitride film is grown using a source gas containing deuterium. 7. In the step of manufacturing the silicon nitride film, the silicon nitride film is grown by LPCVD (low pressure chemical vapor deposition) using deuterated silane and deuterated ammonia as a source gas. Claim 4
7. The method for manufacturing a semiconductor device according to any one of the above items.