JP5106822B2 - Semiconductor device, inspection device, and manufacturing method of semiconductor device - Google Patents

Semiconductor device, inspection device, and manufacturing method of semiconductor device Download PDF

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JP5106822B2
JP5106822B2 JP2006293061A JP2006293061A JP5106822B2 JP 5106822 B2 JP5106822 B2 JP 5106822B2 JP 2006293061 A JP2006293061 A JP 2006293061A JP 2006293061 A JP2006293061 A JP 2006293061A JP 5106822 B2 JP5106822 B2 JP 5106822B2
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昌浩 加藤
能克 黒田
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Mitsubishi Heavy Industries Ltd
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Abstract

<P>PROBLEM TO BE SOLVED: To enable easy wire bonding using a general-purposed bonding machine by forming an electrode on the side surface of at least one IC chip and three-dimensionally mounting a plurality of IC chips. <P>SOLUTION: This semiconductor device includes a stereoscopic substrate, a first IC chip 7 attached on one surface of the substrate and having a surface electrode formed on an upper surface, a second IC chip 8 attached on a surface adjacent to the one surface of the substrate and having a side surface electrode formed on its side surface, and a boding wire 12 for connecting the surface electrode of the first IC chip to the side surface electrode of the second IC chip. With this configuration, the plurality of IC chips can be three-dimensionally mounted and a semiconductor device can be made compact. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は、主として、各種の計測センサを備えた計測装置において、半導体チップ、集積回路等のＩＣチップを、３次元的に実装する半導体装置、検査装置、半導体装置の製造方法及びチップの製造方法に関するものである。   The present invention mainly relates to a semiconductor device, an inspection device, a semiconductor device manufacturing method, and a chip manufacturing method in which an IC chip such as a semiconductor chip or an integrated circuit is three-dimensionally mounted in a measuring device including various measuring sensors. It is about.

半導体装置として、図１２に図示のように、基板１０１上に集積回路（ＩＣチップ）１００ａを複数個、２次元的に配置したものが提案されている（例えば、特許文献１。）。
そして、複数個の集積回路１００ａの内の１個を、光学或いはＸ線センサ用の集積回路１００ａとする場合、光学或いはＸ線センサの集積回路１００ａは被計測対象物に向くように配置する必要がある。
この場合、その他の演算処理用の集積回路（ＩＣチップ）１００ａも同一の基板１０１上に平面的に配置されるため、被計測対象物に向く面（基板）が大きくなり、狭隘部の計測用の半導体装置に適さないという問題がある。 As a semiconductor device, as shown in FIG. 12, a semiconductor device in which a plurality of integrated circuits (IC chips) 100a are two-dimensionally arranged on a substrate 101 has been proposed (for example, Patent Document 1).
When one of the plurality of integrated circuits 100a is used as an integrated circuit 100a for an optical or X-ray sensor, the integrated circuit 100a for the optical or X-ray sensor needs to be arranged so as to face the object to be measured. There is.
In this case, since other integrated circuits (IC chips) 100a for arithmetic processing are also arranged in a plane on the same substrate 101, the surface (substrate) facing the object to be measured becomes large, and is used for measuring narrow portions. There is a problem that the semiconductor device is not suitable.

本発明は、上述の構成が有していた問題を解決するために、少なくとも一つのＩＣチップの側面に電極を形成するものである。   The present invention forms electrodes on the side surface of at least one IC chip in order to solve the problems of the above-described configuration.

なお、ＩＣチップの側面に電極を形成するものとしては、例えば、図１３に図示のものも提案されている（例えば、特許文献２。）。
図１３に図示のものにおいて、１００ｂはＩＣチップ、１０２は半導体集積回路の内の受光素子領域、１０２ａはＩＣチップ１０１の表面（第一の表面）と側面（第二の表面）に跨る接続用配線部の一部（上端延長部）をなす再配線層（表面側）、１０２ｂは同じく側面電極（側面側）、１０３ａは側面絶縁層、１０３ｂはＩＣチップ１０１の裏面（第三の表面）に形成された裏面側絶縁層である。 In addition, as what forms an electrode in the side surface of an IC chip, the thing shown in FIG. 13 is proposed (for example, patent document 2).
In FIG. 13, 100 b is an IC chip, 102 is a light receiving element region in the semiconductor integrated circuit, and 102 a is for connection across the surface (first surface) and side surface (second surface) of the IC chip 101. A rewiring layer (front surface side) forming a part of the wiring portion (upper end extension), 102b is also a side electrode (side surface side), 103a is a side surface insulating layer, and 103b is a back surface (third surface) of the IC chip 101. It is the formed back side insulating layer.

また、図１４に図示のものも提案されている（例えば、特許文献３。）。
図１４に図示のものにおいて、半導体装置１００ｃは、半導体チップが形成された面に設けられた表面電極１０４と、表面電極１０４と導通され、半導体装置１００ｃの実装面にほぼ垂直な側面に溝状に形成された側面電極１０５とを備えている。なお、一般的な電極用のメッキ材料１０６を用いて表面電極１０４および側面電極１０５形成用孔内にメッキ処理を施し、両者を導通状態としている。 Moreover, the thing shown in FIG. 14 is also proposed (for example, patent document 3).
In the semiconductor device 100c shown in FIG. 14, a semiconductor device 100c has a surface electrode 104 provided on a surface on which a semiconductor chip is formed and a groove-like shape on a side surface that is electrically connected to the surface electrode 104 and substantially perpendicular to the mounting surface of the semiconductor device 100c. And a side electrode 105 formed on the substrate. In addition, the plating process is performed in the hole for forming the surface electrode 104 and the side electrode 105 using a general electrode plating material 106, and both are made conductive.

しかしながら、特許文献２、特許文献３に記載のものも、ＩＣチップの側面に電極を形成することは記載されているものの、複数のＩＣチップをどのように３次元的に実装するかについては何等記載されておらず、狭隘部の計測用の半導体装置には適さないという問題がある。   However, although the methods described in Patent Document 2 and Patent Document 3 also describe forming electrodes on the side surfaces of the IC chip, what about how to three-dimensionally mount a plurality of IC chips? There is a problem that it is not described and is not suitable for a semiconductor device for measuring a narrow portion.

特表２００４−５３６４４９号公報JP-T-2004-536449 特開２００２−１９８４６３号公報JP 2002-198463 A 特開２００２−２９９３７２号公報JP 2002-299372 A

本発明は、上述の構成が有していた問題を解決しようとするものであり、少なくとも一つのＩＣチップの側面に電極を形成すると共に複数のＩＣチップを３次元的に実装することにより、汎用のボンディングマシンにより容易にワイヤボンディングが可能な、半導体装置、半導体装置の製造方法及びチップの製造方法を提供することを目的とするものである。   The present invention is intended to solve the problems of the above-described configuration, and by forming electrodes on the side surface of at least one IC chip and mounting a plurality of IC chips three-dimensionally, An object of the present invention is to provide a semiconductor device, a method for manufacturing a semiconductor device, and a method for manufacturing a chip, which can be easily bonded by a bonding machine.

上記の問題点に対し本発明は、以下の各手段を以って課題の解決を図る。   In order to solve the above problems, the present invention aims to solve the problems by the following means.

第１の手段の半導体装置は、立体的な基板と、
前記基板の１つの面に取り付けられると共に上面に表面電極が形成された第１のＩＣチップと、
前記基板の前記１つの面に隣接する表面に取り付けられると共に側面に側面電極が形成された、ＩＣが組み込まれた第２のＩＣチップ又は配線パターンが表面に形成されたチップと、
前記第１のＩＣチップの前記表面電極と前記第２のＩＣチップ又は前記チップの前記側面電極とを直接接続するボンディングワイヤとを備えたことを特徴とする。 The semiconductor device of the first means includes a three-dimensional substrate,
A first IC chip surface electrode is formed on the upper surface with attached to one face of the substrate,
It said one side electrode on the side surfaces with mounted on the front surface adjacent to a surface of the substrate is formed, a chip having the second IC chip or the wiring pattern is formed on the surface of IC is incorporated,
A bonding wire for directly connecting the surface electrode of the first IC chip and the second IC chip or the side electrode of the chip is provided.

第２の手段は、前記第１の手段の半導体装置において、前記第１のＩＣチップは、ＣＣＤカメラ用の受光素子又はＸ線検出素子を含む各種の電磁波検出素子を有していることを特徴とする。 The second means is the semiconductor device of the first means, wherein the first IC chip has various electromagnetic wave detecting elements including a light receiving element or an X-ray detecting element for a CCD camera. And

第３の手段の検査装置は、第２の手段に記載の前記半導体装置を、前面が光或いはＸ線を含む前記電磁波検出素子に対応した各種の電磁波が透過可能な窓部を有する収納筒内に収納したことを特徴とする。 An inspection apparatus according to a third means includes: the semiconductor device according to the second means, wherein the front surface includes a window portion through which various electromagnetic waves corresponding to the electromagnetic wave detection element including light or X-rays can be transmitted. It is characterized by being housed in.

第４の手段の半導体装置の製造方法は、上面に表面電極が形成された第１のＩＣチップと、側面に側面電極が形成された、ＩＣが組み込まれた第２のＩＣチップ又は配線パターンが表面に形成されたチップと、立体的な基板とを有し、
前記基板の１つの面に前記第１のＩＣチップを取り付け、
前記基板の前記１つの面に隣接する表面に前記第２のＩＣチップ又は前記チップを取り付け、
前記第１のＩＣチップの前記表面電極と前記第２のＩＣチップ又は前記チップの前記側面電極とをボンディングワイヤにより直接接続することを特徴とする。 According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a first IC chip having a surface electrode formed on an upper surface; and a second IC chip or wiring pattern having a side electrode formed on a side surface and having an IC incorporated therein. Having a chip formed on the surface and a three-dimensional substrate;
Attaching the first IC chip to one surface of the substrate;
The second IC chip or the chip mounting on the front surface adjacent to the one surface of the substrate,
The surface electrode of the first IC chip and the side electrode of the second IC chip or the chip are directly connected by a bonding wire.

第５の手段の半導体装置の製造方法は、シリコン基材の所定の位置にスルーホールを穿孔し、
前記シリコン基材の上面、下面及びスルーホールの側面に絶縁層を形成し、
前記シリコン基材の上面の前記絶縁層上に表面電極を形成すると共に前記スルーホールの内側面に側面電極を形成し、
前記スルーホール及び前記側面電極の無い部分に、前記スルーホールを横切る分断線に沿って切込部を形成し、
その後、前記分断線に沿って劈開或いは切り欠き誘導することにより、ＩＣが組み込まれた第２のＩＣチップ又は配線パターンが表面に形成されたチップを形成し、
立体的な基板の１つの面に第１のＩＣチップを取り付け、
前記基板の前記１つの面に隣接する表面に前記第２のＩＣチップ又は前記チップを取り付け、
前記第１のＩＣチップの前記表面電極と前記第２のＩＣチップ又は前記チップの前記側面電極とをボンディングワイヤにより直接接続することを特徴とする。 According to a fifth method of manufacturing a semiconductor device, a through hole is drilled at a predetermined position of a silicon substrate.
Forming an insulating layer on the upper surface, lower surface and side surface of the through hole of the silicon substrate;
Forming a surface electrode on the insulating layer on the upper surface of the silicon substrate and forming a side electrode on the inner surface of the through-hole;
In the part without the through-hole and the side electrode, a cut portion is formed along a dividing line across the through-hole,
Then, by cleaving or notching along the dividing line, a second IC chip incorporating an IC or a chip having a wiring pattern formed on the surface is formed .
A first IC chip is attached to one surface of a three-dimensional substrate,
The second IC chip or the chip mounting on the front surface adjacent to the one surface of the substrate,
The surface electrode of the first IC chip and the side electrode of the second IC chip or the chip are directly connected by a bonding wire.

特許請求の範囲に記載の各請求項に係る発明は、上記の各手段を採用しており、ＩＣチップと、このＩＣチップに３次元的に隣接するチップとを３次元的に実装すると共に、ＩＣチップの表面電極と３次元的に隣接するチップの側面電極とをボンディングワイヤにより接続するようにしたので、半導体装置をコンパクトにすることができると共に、ワイヤボンディング作業を向上させることができる。
また、チップの製造時の不良品の発生率を減少させることができる。 The invention according to each claim recited in the claims employs each of the above-described means, and three-dimensionally mounts an IC chip and a chip three-dimensionally adjacent to the IC chip, Since the surface electrode of the IC chip and the side electrode of the three-dimensionally adjacent chip are connected by the bonding wire, the semiconductor device can be made compact and the wire bonding operation can be improved.
In addition, it is possible to reduce the occurrence rate of defective products during chip manufacturing.

以下、本発明の各実施の形態に係る半導体装置、検査装置、半導体装置の製造方法及びチップの製造方法につき説明する。   Hereinafter, a semiconductor device, an inspection device, a semiconductor device manufacturing method, and a chip manufacturing method according to each embodiment of the present invention will be described.

（本発明の第１の実施の形態に係る半導体装置）
先ず、本発明の第１の実施の形態に係る半導体装置の構成につき説明する。
図１は、本発明の第１の実施の形態に係る半導体装置を組み込んだ狭隘部検出装置の側面図である。
図２は、図１のワイヤボンディング部の拡大斜視図である。 (Semiconductor device according to the first embodiment of the present invention)
First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described.
FIG. 1 is a side view of a narrowed portion detection apparatus incorporating a semiconductor device according to the first embodiment of the present invention.
FIG. 2 is an enlarged perspective view of the wire bonding portion of FIG.

先ず、図１に基づき、本発明の第１の実施の形態に係る半導体装置を組み込んだ検出装置の構成につき説明する。
図１に図示のように、狭隘部用の検査装置１は、例えば、小径の円筒状の収納筒２と、収納筒２の先端に取り付けられると共に検出する光或いはＸ線等の各種の電磁波が透過可能な窓部３とにより構成されている。 First, based on FIG. 1, the structure of the detection apparatus incorporating the semiconductor device according to the first embodiment of the present invention will be described.
As shown in FIG. 1, an inspection apparatus 1 for a narrow portion includes, for example, a small-diameter cylindrical storage cylinder 2 and various electromagnetic waves such as light or X-rays that are attached to the tip of the storage cylinder 2 and detected. It is comprised by the window part 3 which can permeate | transmit.

そして、収納筒２内には、ＣＣＤカメラ用の受光素子又はＸ線検出素子等の各種の電磁波検出素子を有する検出用のＩＣチップ７と、ＩＣチップ７に隣接する処理用のチップ８とが３次元的に実装された半導体装置１５が収納されている。
半導体装置１５は、基板４、基板４に取り付けられた検出用のＩＣチップ７、複数個の処理用のチップ８、及び図示略の電源電線、信号電線、サポートの等により構成されている。
なお、ＩＣチップに３次元的に隣接するチップ８は、ＩＣが組み込まれたＩＣチップの場合も、単に配線パターンのみが表面に形成されたチップの場合もある。 In the storage cylinder 2, a detection IC chip 7 having various electromagnetic wave detection elements such as a light receiving element for a CCD camera or an X-ray detection element, and a processing chip 8 adjacent to the IC chip 7 are provided. A semiconductor device 15 mounted three-dimensionally is accommodated.
The semiconductor device 15 includes a substrate 4, a detection IC chip 7 attached to the substrate 4, a plurality of processing chips 8, a power supply wire, a signal wire, a support (not shown), and the like.
Note that the chip 8 that is three-dimensionally adjacent to the IC chip may be an IC chip in which an IC is incorporated or a chip in which only a wiring pattern is formed on the surface.

以下、各部材の詳細な構成につき説明する。
基板４の形状は、四角柱、円柱、平行６面体等の立体的（３次元的）なものであり、基板４の内部は空洞でも良く、空洞でなくても良い。 Hereinafter, the detailed configuration of each member will be described.
The shape of the substrate 4 is a three-dimensional (three-dimensional) shape such as a quadrangular prism, a cylinder, or a parallelepiped, and the inside of the substrate 4 may or may not be a cavity.

基板４の頂部（先端）の基板頂面６には、ＩＣチップ７が取り付けられている。
ＩＣチップ７は、例えば、図１３（特許文献２）に図示の受光素子領域１０２を有するＩＣチップ１００ｂと同様の構造のものを採用することができる。
ＩＣチップ７の基板は、図２に図示のように、中層のシリコン基材１３と、シリコン基材１３の上面及び下面に形成されたＳｉＯ２等の酸化膜である絶縁層１４とにより形成されている。 An IC chip 7 is attached to the substrate top surface 6 at the top (tip) of the substrate 4.
As the IC chip 7, for example, one having the same structure as the IC chip 100b having the light receiving element region 102 shown in FIG. 13 (Patent Document 2) can be adopted.
As shown in FIG. 2, the substrate of the IC chip 7 is formed by a middle-layer silicon substrate 13 and an insulating layer 14 that is an oxide film such as SiO 2 formed on the upper and lower surfaces of the silicon substrate 13. Yes.

ＩＣチップ７の上面の絶縁層１４上には、図示略の多数のＣＣＤカメラ用の受光素子或いはＸ線検出素子等が格子状に形成されている。
ＩＣチップ７の表面（絶縁層１４上）の周辺には、受光素子或いはＸ線感知素子等からの信号を取り出すための多数の表面電極９が、蒸着、或いはエッティング等により形成されている。
但し、図１３に図示の側面電極１０２ｂは必ずしも必要ではない。
なお、ＩＣチップ７の高さは、通常、０．１〜２ｍｍである。 On the insulating layer 14 on the upper surface of the IC chip 7, a number of light receiving elements or X-ray detection elements for a CCD camera (not shown) are formed in a lattice shape.
On the periphery of the surface of the IC chip 7 (on the insulating layer 14), a large number of surface electrodes 9 for taking out signals from a light receiving element or an X-ray sensing element are formed by vapor deposition or etching.
However, the side electrode 102b illustrated in FIG. 13 is not necessarily required.
The height of the IC chip 7 is usually 0.1 to 2 mm.

一方、図１に図示のように、基板４の側面の基板側面５には、読出し、信号処理を行なう少なくとも１個のＩＣチップ７に３次元的に隣接するチップ８が取り付けられている。
チップ８は、１個でも、２個でも、或いは３個でも良い。
チップ８の基板は、図２に図示のように、中層のシリコン基材１３と、シリコン基材１３の上面及び下面に形成されたＳｉＯ２等の酸化膜である絶縁層１４とにより形成されている。 On the other hand, as shown in FIG. 1, a chip 8 that is three-dimensionally adjacent to at least one IC chip 7 that performs reading and signal processing is attached to the side surface 5 of the side surface of the substrate 4.
One, two, or three chips 8 may be used.
As shown in FIG. 2, the substrate of the chip 8 is formed by a middle-layer silicon base 13 and an insulating layer 14 that is an oxide film such as SiO 2 formed on the upper and lower surfaces of the silicon base 13. .

チップ８の上面の絶縁層１４上（外側）には、図示略の演算処理回路が形成されている。
チップ８の表面（絶縁層１４上）の周辺には、後述する側面電極１０ａに導通した多数の表面電極１１が、蒸着、或いはエッティング等により形成されている。
チップ８の側面には、各表面電極１１に導通した多数の側面電極１０ａが蒸着、或いはエッティング等により形成されている。
そして、ＩＣチップ７の表面の各表面電極９とチップ８の側面の側面電極１０ａとは、金線、アルミ線、銅線等のボンディングワイヤ１２により接続されている。
なお、チップ８の側面電極のボンディングワイヤ１２により接続される面は、平面状となっている。 An arithmetic processing circuit (not shown) is formed on the insulating layer 14 (outside) on the upper surface of the chip 8.
On the periphery of the surface of the chip 8 (on the insulating layer 14), a large number of surface electrodes 11 conducted to a side electrode 10a described later are formed by vapor deposition or etching.
On the side surface of the chip 8, a large number of side surface electrodes 10 a electrically connected to the respective surface electrodes 11 are formed by vapor deposition or etching.
Each surface electrode 9 on the surface of the IC chip 7 and the side electrode 10a on the side surface of the chip 8 are connected to each other by bonding wires 12 such as a gold wire, an aluminum wire, or a copper wire.
In addition, the surface connected by the bonding wire 12 of the side electrode of the chip 8 is planar.

このように、基板頂面６のＩＣチップ７と基板側面５のチップ８とは、互いに９０°の角度をなすように、即ち、３次元的に実装されている。
このような構成とすることにより、図１２〜図１４に図示の従来のものに比べて、ＩＣチップ７及びのチップ８からなる半導体装置１５の大きさは小さくなり、半導体装置１５を収納する収納筒２も細くすることができる。 Thus, the IC chip 7 on the substrate top surface 6 and the chip 8 on the substrate side surface 5 are mounted so as to form an angle of 90 ° with each other, that is, in a three-dimensional manner.
By adopting such a configuration, the size of the semiconductor device 15 including the IC chip 7 and the chip 8 is smaller than that of the conventional device shown in FIGS. The tube 2 can also be made thinner.

（本発明の第２の実施の形態係る半導体装置）
次に、本発明の第２の実施の形態に係る半導体装置の構成につき説明する。
図３は、本発明の第２の実施の形態に係る半導体装置を組み込んだ狭隘部検出装置の側面図である。
図４は、図３のワイヤボンディング部の拡大斜視図である。 (Semiconductor device according to the second embodiment of the present invention)
Next, the configuration of the semiconductor device according to the second embodiment of the present invention will be described.
FIG. 3 is a side view of a narrowed portion detection device incorporating a semiconductor device according to the second embodiment of the present invention.
FIG. 4 is an enlarged perspective view of the wire bonding portion of FIG.

なお、図１、図２に図示の本発明の第１の実施の形態に係る半導体装置においては、チップ８の側面に、各表面電極１１に導通した多数の側面電極１０ａが蒸着、或いはエッティング等により形成されている。
この場合、チップ８の側面に側面電極１０ａを形成することは技術的に難しい。
そこで、本発明の第２の実施の形態に係る半導体装置は、本発明の第１の実施の形態に係る半導体装置における側面電極１０ａに代えて、スルーホール型の側面電極１０ｂを形成したものである。 In the semiconductor device according to the first embodiment of the present invention shown in FIGS. 1 and 2, a large number of side electrodes 10 a electrically connected to each surface electrode 11 are deposited or etched on the side surface of the chip 8. Etc. are formed.
In this case, it is technically difficult to form the side electrode 10 a on the side surface of the chip 8.
Therefore, the semiconductor device according to the second embodiment of the present invention is formed by forming a through-hole type side electrode 10b instead of the side electrode 10a in the semiconductor device according to the first embodiment of the present invention. is there.

従って、本発明の第１の実施の形態に係る半導体装置と異なる点は、側面電極１０ｂの形状のみであり、本発明の第１の実施の形態に係るものと同様に、収納筒２、窓部３、基板側面５及び基板頂面６により形成された基板４、表面に表面電極９が形成されたＩＣチップ７等を備えている。   Accordingly, the semiconductor device according to the first embodiment of the present invention is different from the semiconductor device according to the first embodiment only in the shape of the side surface electrode 10b, and similarly to the one according to the first embodiment of the present invention, the storage cylinder 2, the window The substrate 4 is formed by the portion 3, the substrate side surface 5 and the substrate top surface 6, the IC chip 7 having the surface electrode 9 formed on the surface, and the like.

即ち、本発明の第２の実施の形態に係る半導体装置においては、図４に図示のように、チップ８の側面には断面が半円状の凹部が形成され、その凹部に断面が半円状の側面電極１０ｂが、蒸着、或いはエッティング等により形成されている。
この断面が半円状の側面電極１０ｂは、本発明の第２の実施の形態に係る半導体装置と同様に、各表面電極１１に導通している。
そして、ＩＣチップ７の表面の各表面電極９とチップ８の側面の断面が半円状の側面電極１０ｂとは、金線、アルミ線、銅線等のボンディングワイヤ１２により接続されている。 That is, in the semiconductor device according to the second embodiment of the present invention, as shown in FIG. 4, a concave portion having a semicircular cross section is formed on the side surface of the chip 8, and the semicircular cross section is formed in the concave portion. The side electrode 10b is formed by vapor deposition or etching.
The side electrode 10b having a semicircular cross section is electrically connected to each surface electrode 11 as in the semiconductor device according to the second embodiment of the present invention.
Each surface electrode 9 on the surface of the IC chip 7 and the side electrode 10b having a semicircular cross section on the side surface of the chip 8 are connected by a bonding wire 12 such as a gold wire, an aluminum wire, or a copper wire.

このように、本発明の第１の実施の形態に係る半導体装置においても、基板頂面６のＩＣチップ７と基板側面５のチップ８とは、互いに９０°の角度をなすように、即ち、３次元的に実装されており、図１２〜図１４に図示の従来のものに比べて、ＩＣチップ７及びのチップ８からなる半導体装置１５をコンパクトにすることができ、半導体装置１５を収納する収納筒２も細くすることができる。   Thus, also in the semiconductor device according to the first embodiment of the present invention, the IC chip 7 on the substrate top surface 6 and the chip 8 on the substrate side surface 5 form an angle of 90 ° with each other, that is, The semiconductor device 15 which is three-dimensionally mounted and can be made more compact than the conventional device shown in FIGS. 12 to 14 can be made more compact and accommodates the semiconductor device 15. The storage cylinder 2 can also be made thin.

（半導体装置におけるＩＣチップの構成及び製造方法）
次に、本発明の各実施の形態に係る半導体装置におけるＩＣチップの構成及び製造方法につき説明する。
図５は、本発明の各実施の形態に係る半導体装置におけるＩＣチップが形成されたウエハの外観斜視図である。
図６は、本発明の各実施の形態に係る半導体装置におけるＩＣチップが形成されたウエハのその他の例の外観斜視図である。
図７は、本発明の各実施の形態に係る半導体装置におけるＩＣチップの電極部の拡大斜視図である。
図８は、図７における側面電極部分の拡大側面図である。
図９は、本発明の各実施の形態に係る半導体装置におけるワイヤボンディング方法を示す説明図である。
図１０は、従来のウエハの切断状況を示す図である。
図１１は、従来の製造されたＩＣチップの電極部の斜視図である。 (Configuration and manufacturing method of IC chip in semiconductor device)
Next, the configuration and manufacturing method of the IC chip in the semiconductor device according to each embodiment of the present invention will be described.
FIG. 5 is an external perspective view of a wafer on which an IC chip is formed in the semiconductor device according to each embodiment of the present invention.
FIG. 6 is an external perspective view of another example of a wafer on which an IC chip is formed in the semiconductor device according to each embodiment of the present invention.
FIG. 7 is an enlarged perspective view of the electrode portion of the IC chip in the semiconductor device according to each embodiment of the present invention.
FIG. 8 is an enlarged side view of the side electrode portion in FIG.
FIG. 9 is an explanatory view showing a wire bonding method in the semiconductor device according to each embodiment of the present invention.
FIG. 10 is a diagram showing a conventional wafer cutting state.
FIG. 11 is a perspective view of an electrode portion of a conventionally manufactured IC chip.

（ＩＣチップの構成及び製造方法）
先ず、図５〜図９に基づき、図１０、図１１に図示の従来のものと比較しながら、本発明の各実施の形態に係る半導体装置におけるＩＣチップの構成及び製造方法につき説明する。
図５に図示のように、ウエハであるシリコン基材１３（図８参照）の所定の位置に、周知の方法で、側面電極１０ｂ用のスルーホールを穿孔する。
次に、ウエハであるシリコン基材１３の上面、下面及びスルーホールの側面に、ＳｉＯ２等の酸化膜である絶縁層１４をコーティングして形成する。
なお、絶縁層１４の厚さは、１μｍ前後である。
次に、シリコン基材１３の上面の絶縁層１４上にＬＳＩ、表面電極１１等を、蒸着、エッチング、コーティング等周知の方法で形成し、スルーホールの内側面に側面電極１０ｂを形成する。
このようにして、ウエハ上に、多数のチップ８が格子状に形成される。 (Configuration and manufacturing method of IC chip)
First, based on FIGS. 5 to 9, the configuration and manufacturing method of an IC chip in a semiconductor device according to each embodiment of the present invention will be described in comparison with the conventional one shown in FIGS. 10 and 11.
As shown in FIG. 5, a through hole for the side electrode 10b is drilled at a predetermined position of a silicon substrate 13 (see FIG. 8) as a wafer by a known method.
Next, an insulating layer 14 that is an oxide film such as SiO 2 is formed on the upper and lower surfaces of the silicon substrate 13 that is a wafer and the side surfaces of the through holes.
The thickness of the insulating layer 14 is around 1 μm.
Next, an LSI, a surface electrode 11 and the like are formed on the insulating layer 14 on the upper surface of the silicon substrate 13 by a known method such as vapor deposition, etching, coating, and the side electrode 10b is formed on the inner surface of the through hole.
In this way, a large number of chips 8 are formed in a lattice pattern on the wafer.

その後、隣接するチップ８間のスルーホール及び側面電極１０ｂの無い部分に、分断線Ｘ、Ｙに沿って切り込みを入れて、切込部２０、２１を形成する。
なお、分断線Ｘ、Ｙは、スルーホールを横切る線である。
この切込部２０、２１は、シリコン基材１３及び上下面の絶縁層１４の全てを切断するものとする必要はなく、図８に図示のように、上面の絶縁層１４及びシリコン基材１３を浅く切り込んだもので良い。 Thereafter, incisions 20 and 21 are formed by cutting along the dividing lines X and Y in portions where there is no through hole between the adjacent chips 8 and the side surface electrode 10b.
The dividing lines X and Y are lines that cross the through hole.
The cut portions 20 and 21 do not need to cut all of the silicon base material 13 and the upper and lower insulating layers 14, and as shown in FIG. 8, the upper insulating layer 14 and the silicon base material 13. You can cut it shallowly.

このようにして、切込部２０、２１は、ウエハの分断線Ｘ、Ｙに沿って直線状に、且つ、側面電極１０ｂが形成されたスルーホールと重ならないように形成される。
その後、分断線Ｘ、Ｙに沿って、劈開或いは切り欠き誘導することにより、個々のチップ８が形成される。 In this way, the notches 20 and 21 are formed linearly along the dividing lines X and Y of the wafer and so as not to overlap the through-hole in which the side electrode 10b is formed.
Thereafter, each chip 8 is formed by cleaving or notching along the dividing lines X and Y.

なお、切込部２０、２１に代えて、図６に図示のように、側面電極１０ｂを有するスルーホールを穿孔するときに、側面電極１０ｂを有するスルーホールに並べて、分断線Ｘ、Ｙ上に、同時に側面電極１０ｂの無いスルーホール１６を並べて穿孔するようにしても良い。
即ち、スルーホールを分断線Ｘ、Ｙに沿って連続的に穿設し、一部のスルーホールの内側面に側面電極１０ｂを形成する。
このようにすることにより、切込部２０、２１を形成する工程を省略することができる。
この場合も、分断線Ｘ、Ｙに沿って、劈開或いは切り欠き誘導することにより、個々のチップ８が形成される。 In place of the notches 20 and 21, as shown in FIG. 6, when the through hole having the side electrode 10b is drilled, the through holes having the side electrode 10b are arranged on the dividing lines X and Y. At the same time, the through-holes 16 without the side electrode 10b may be aligned and perforated.
That is, the through hole is continuously drilled along the dividing lines X and Y, and the side electrode 10b is formed on the inner side surface of a part of the through hole.
By doing in this way, the process of forming the notches 20 and 21 can be omitted.
Also in this case, the individual chips 8 are formed by cleaving or notching along the dividing lines X and Y.

なお、従来は、図１０に図示のように、シリコン基材１３、上下面の絶縁層１４、表面電極１１及びスルーホールの側面電極１０ｂの全てを、ダイシングカッター２２により切断していた。
この場合、側面電極１０ｂ或いは側面電極に導通した表面電極１１の一部が、ダイシングカッター２２の刃により誘導・引き伸ばされる可能性がある。
そして、図１０、図１１に図示のように、この引き伸ばされた側面電極片２３は、絶縁層１４の厚さが１μｍ前後であるため、絶縁層１４を突き抜けて、シリコン基材１３に到達する。
従って、従来のダイシングカッター２２により切断する方法では、複数の側面電極１０ｂ或いは表面電極１１が、引き伸ばされた側面電極片２３により、シリコン基材１３を介して短絡する可能性があるという問題があった。 Conventionally, as shown in FIG. 10, all of the silicon base material 13, the upper and lower insulating layers 14, the surface electrode 11, and the side electrode 10 b of the through hole are cut by a dicing cutter 22.
In this case, there is a possibility that a part of the side electrode 10 b or the surface electrode 11 that is conducted to the side electrode is guided and stretched by the blade of the dicing cutter 22.
As shown in FIGS. 10 and 11, the extended side electrode piece 23 penetrates the insulating layer 14 and reaches the silicon base material 13 because the insulating layer 14 has a thickness of about 1 μm. .
Therefore, the conventional method of cutting with the dicing cutter 22 has a problem that the side electrode 10b or the surface electrode 11 may be short-circuited through the silicon base material 13 by the extended side electrode piece 23. It was.

これに対し、本発明の各実施の形態に係る半導体装置におけるＩＣチップの製造方法では、劈開或いは切り欠き誘導することにより、個々のチップ８を形成するようにしているので、引き伸ばされた側面電極片２３によりシリコン基材１３を介して短絡することを防止することができる。
なお、たとえ、側面電極片２３が発生したとしても、この側面電極片２３は、シリコン基材１３に向かって延在するのではなく分断線Ｘ、Ｙと直角の方向に延在する。
したがって、シリコン基材１３を介して短絡する可能性が減少するため、ＩＣチップの製造時の不良品の発生率を減少させることができる。 On the other hand, in the method of manufacturing an IC chip in the semiconductor device according to each embodiment of the present invention, each chip 8 is formed by cleaving or notching, so that the extended side electrode It is possible to prevent a short circuit through the silicon substrate 13 by the piece 23.
Even if the side electrode piece 23 is generated, the side electrode piece 23 does not extend toward the silicon substrate 13 but extends in a direction perpendicular to the dividing lines X and Y.
Therefore, since the possibility of short-circuiting through the silicon substrate 13 is reduced, it is possible to reduce the incidence of defective products when manufacturing IC chips.

（ＩＣチップ取り付け及びワイヤボンディング）
そして、図３、図４に図示のように、上述のごとく製造されたチップ８を基板４の基板側面５に取り付けると共に、従来の方法で製造されたＩＣチップ７を基板４の頂部（先端）の基板頂面６に取り付ける。
このとき、チップ８とＩＣチップ７とは、互いに９０°の角度をなすように、即ち、３次元的に取り付けられている。
また、チップ８の側面の上端は、基板頂面６と同じレベルになるようにする。
なお、チップ８の上端を基板頂面６から突き出して、チップ８の上端がＩＣチップ７の上面と同じレベルになるようにしても良い。 (IC chip attachment and wire bonding)
3 and 4, the chip 8 manufactured as described above is attached to the substrate side surface 5 of the substrate 4, and the IC chip 7 manufactured by the conventional method is attached to the top (tip) of the substrate 4. Is attached to the top surface 6 of the substrate.
At this time, the chip 8 and the IC chip 7 are attached to form an angle of 90 ° with each other, that is, in a three-dimensional manner.
Further, the upper end of the side surface of the chip 8 is set at the same level as the top surface 6 of the substrate.
The upper end of the chip 8 may protrude from the top surface 6 of the substrate so that the upper end of the chip 8 is at the same level as the upper surface of the IC chip 7.

その後、図９に図示のように、ボンディングマシンのキャピラリー２４をキャピラリー２４ｘ１の位置に移動して、ＩＣチップ７の表面電極９にボンディングワイヤ１２（図３、図４参照）の先端を接続する。
そして、ボンディングワイヤ１２を繰出しながらキャピラリー２４をキャピラリー２４ｘ２の位置に移動して、チップ８の側面電極１０ｂ（１０ａ）にボンディングワイヤ１２の先端を接続する。 Thereafter, as shown in FIG. 9, the capillary 24 of the bonding machine is moved to the position of the capillary 24 × 1, and the tip of the bonding wire 12 (see FIGS. 3 and 4) is connected to the surface electrode 9 of the IC chip 7.
Then, the capillary 24 is moved to the position of the capillary 24 x 2 while feeding the bonding wire 12, and the tip of the bonding wire 12 is connected to the side electrode 10 b (10 a) of the chip 8.

このワイヤボンディング作業において、キャピラリー２４の移動距離は、ＩＣチップ７の高さ（０．１〜２ｍｍ）及び水平方向（数ｍｍ）を加えた距離Ｌｏであり、しかもキャピラリー２４の向きを変えることなく行なえる。
従って、作業時間は従来のように各ＩＣチップを同一平面上に並べた場合と殆ど変らない。 In this wire bonding operation, the moving distance of the capillary 24 is a distance Lo obtained by adding the height (0.1 to 2 mm) and the horizontal direction (several mm) of the IC chip 7, and without changing the direction of the capillary 24. Yes.
Accordingly, the working time is almost the same as when the IC chips are arranged on the same plane as in the prior art.

これに対し、ＩＣチップ７の表面電極９とチップ８の表面電極１１とを接続する場合、キャピラリー２４を、図９に点線で図示のように向きも変えてキャピラリー２４ｚのようにしなければならない。
この場合、キャピラリー２４の先端部の移動距離は上述の場合の移動距離Ｌｏとあまり変らないものの、キャピラリー２４を把持する図示略の支持部材の移動距離Ｌｘは何倍にもなり、しかもキャピラリー２４の向きを変える必要があり、作業効率は大幅に低下する。 On the other hand, when the surface electrode 9 of the IC chip 7 and the surface electrode 11 of the chip 8 are connected, the capillary 24 must be changed to the direction of the capillary 24z as shown by the dotted line in FIG.
In this case, the moving distance of the tip of the capillary 24 is not much different from the moving distance Lo in the above case, but the moving distance Lx of a support member (not shown) that holds the capillary 24 is several times larger. It is necessary to change the direction, and work efficiency is greatly reduced.

一方、本発明の各実施の形態に係る半導体装置の製造方法によれば、ＩＣチップ７の表面電極９とチップ８の側面電極１０ｂ（１０ａ）とをボンディングワイヤ１２により接続するようにしたので、平面的に取付けられた複数のＩＣチップのワイヤボンディング作業における作業効率と殆ど同じとすることができる。
言い換えれば、従来、複数のＩＣチップを３次元的に設けられたのものでは、ワイヤボンディング作業のみならず、別途接続線等を設ける必要があり作業効率が悪かったが、本実施の形態のもの或いは方法によれば、作業効率が格段に向上する。 On the other hand, according to the method of manufacturing a semiconductor device according to each embodiment of the present invention, the surface electrode 9 of the IC chip 7 and the side electrode 10b (10a) of the chip 8 are connected by the bonding wire 12. The work efficiency in wire bonding work of a plurality of IC chips mounted in a plane can be made almost the same.
In other words, conventionally, in the case where a plurality of IC chips are provided three-dimensionally, it is necessary to provide a separate connection line or the like in addition to the wire bonding work, but the work efficiency is low. According to the method, the working efficiency is remarkably improved.

（その他の実施の形態）
以上、本発明の各実施の形態について説明したが、本発明は上記の各実施の形態に限定されず、本発明の範囲内でその具体的構造に種々の変更を加えてよいことはいうまでもない。
例えば、ＩＣチップ７に側面電極１０ａ、１０ｂを形成し、ＩＣチップ７に形成された側面電極１０ａ、１０ｂとチップ８の表面の表面電極１１とをボンディングワイヤ１２により接続するようにしても良い。 (Other embodiments)
Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications may be made to the specific structure within the scope of the present invention. Nor.
For example, the side electrodes 10 a and 10 b may be formed on the IC chip 7, and the side electrodes 10 a and 10 b formed on the IC chip 7 and the surface electrode 11 on the surface of the chip 8 may be connected by the bonding wire 12.

また、チップ８の４つの側面の内の１つの面のみをＩＣチップ７と３次元的に取り付ける場合は、図５に図示のチップ８が格子状に形成されたウエハにおいて、分断線Ｘのみに、且つ１つ置きにスルーホールを穿孔し、側面電極に導通した表面電極１１、切込部２１を形成して、スルーホールの無い分断線Ｘ、及び全ての分断線Ｙを従来のようにダイシングカッター２２により切断するようにしても良い。   Further, when only one of the four side surfaces of the chip 8 is three-dimensionally attached to the IC chip 7, only the dividing line X is formed on the wafer in which the chips 8 shown in FIG. In addition, every other through hole is drilled to form the surface electrode 11 and the cut portion 21 that are connected to the side electrode, and the dividing line X without any through hole and all the dividing lines Y are diced as before. You may make it cut | disconnect with the cutter 22. FIG.

また、基板４の外形形状を円筒状とし、チップ８を取り付ける側面の部分のみを平らに研削し、円筒状の基板４の頂部にＩＣチップ７を取り付け、平らに研削した側面にチップ８を取り付けることにより、ＩＣチップ７とチップ８とを３次元的に実装し、ＩＣチップ７の上面の表面電極９とチップ８の側面の側面電極１０ａ、１０ｂとをボンディングワイヤ１２により接続するようにしても良い。   Further, the outer shape of the substrate 4 is cylindrical, and only the side portion to which the chip 8 is attached is ground flat, the IC chip 7 is attached to the top of the cylindrical substrate 4, and the chip 8 is attached to the flat ground side surface. Thus, the IC chip 7 and the chip 8 are three-dimensionally mounted, and the surface electrode 9 on the upper surface of the IC chip 7 and the side electrodes 10a and 10b on the side surfaces of the chip 8 are connected by the bonding wires 12. good.

本発明の第１の実施の形態に係る半導体装置を組み込んだ狭隘部検出装置の側面図である。1 is a side view of a narrowed portion detection device incorporating a semiconductor device according to a first embodiment of the present invention. 図１のワイヤボンディング部の拡大斜視図である。It is an expansion perspective view of the wire bonding part of FIG. 本発明の第２の実施の形態に係る半導体装置を組み込んだ狭隘部検出装置の側面図である。It is a side view of the narrow part detection apparatus incorporating the semiconductor device which concerns on the 2nd Embodiment of this invention. 図３のワイヤボンディング部の拡大斜視図である。It is an expansion perspective view of the wire bonding part of FIG. 本発明の各実施の形態に係る半導体装置におけるＩＣチップが形成されたウエハの外観斜視図である。It is an external appearance perspective view of the wafer in which the IC chip in the semiconductor device concerning each embodiment of the present invention was formed. 本発明の各実施の形態に係る半導体装置におけるＩＣチップが形成されたウエハのその他の例の外観斜視図である。It is an external appearance perspective view of the other example of the wafer in which the IC chip in the semiconductor device which concerns on each embodiment of this invention was formed. 本発明の各実施の形態に係る半導体装置におけるＩＣチップの電極部の拡大斜視図である。It is an expansion perspective view of the electrode part of the IC chip in the semiconductor device concerning each embodiment of the present invention. 図７における側面電極部分の拡大側面図である。It is an enlarged side view of the side electrode part in FIG. 本発明の各実施の形態に係る半導体装置におけるワイヤボンディング方法を示す説明図である。It is explanatory drawing which shows the wire bonding method in the semiconductor device which concerns on each embodiment of this invention. 従来のウエハの切断状況を示す図である。It is a figure which shows the cutting condition of the conventional wafer. 従来の製造されたＩＣチップの電極部の斜視図である。It is a perspective view of the electrode part of the IC chip manufactured conventionally. 従来の集積回路を２次元的に配置した基板の側面図である。It is a side view of the board | substrate which has arrange | positioned the conventional integrated circuit two-dimensionally. 従来の側面に電極が形成されたＩＣチップの斜視図である。It is a perspective view of the IC chip in which the electrode was formed in the conventional side surface. 従来の側面に溝状に側面電極が形成されたＩＣチップの斜視図である。It is a perspective view of the IC chip by which the side electrode was formed in the groove shape on the conventional side surface.

符号の説明Explanation of symbols

１ 検査装置
２ 収納筒
３ 窓部
４ 基板
５ 基板側面
６ 基板頂面
７ ＩＣチップ
８ チップ
９ 表面電極
１０ａ、１０ｂ 側面電極
１１ 表面電極
１２ ボンディングワイヤ
１３ シリコン基材
１４ 絶縁層
１５ 半導体装置
１６ 側面電極の無いスルーホール
２０、２１ 切込部
Ｘ、Ｙ 分断線
２２ ダイシングカッター
２３ 側面電極片
２４ｘ１、２４ｘ２、２４ｚ キャピラリー DESCRIPTION OF SYMBOLS 1 Inspection apparatus 2 Storage cylinder 3 Window part 4 Substrate 5 Substrate side surface 6 Substrate top surface 7 IC chip 8 Chip 9 Surface electrode 10a, 10b Side surface electrode 11 Surface electrode 12 Bonding wire 13 Silicon substrate 14 Insulating layer 15 Semiconductor device 16 Side surface electrode Through hole 20, 21 Notch X, Y Cut line 22 Dicing cutter 23 Side electrode piece 24x1, 24x2, 24z Capillary

Claims (5)

立体的な基板と、
前記基板の１つの面に取り付けられると共に上面に表面電極が形成された第１のＩＣチップと、
前記基板の前記１つの面に隣接する表面に取り付けられると共に側面に側面電極が形成された、ＩＣが組み込まれた第２のＩＣチップ又は配線パターンが表面に形成されたチップと、
前記第１のＩＣチップの前記表面電極と前記第２のＩＣチップ又は前記チップの前記側面電極とを直接接続するボンディングワイヤとを備えたことを特徴とする半導体装置。 A three-dimensional substrate,
A first IC chip surface electrode is formed on the upper surface with attached to one face of the substrate,
It said one side electrode on the side surfaces with mounted on the front surface adjacent to a surface of the substrate is formed, a chip having the second IC chip or the wiring pattern is formed on the surface of IC is incorporated,
A semiconductor device comprising: a bonding wire that directly connects the surface electrode of the first IC chip and the second IC chip or the side electrode of the chip. 前記第１のＩＣチップは、ＣＣＤカメラ用の受光素子又はＸ線検出素子を含む各種の電磁波検出素子を有していることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first IC chip has various electromagnetic wave detection elements including a light receiving element or an X-ray detection element for a CCD camera. 請求項２に記載の前記半導体装置を、前面が光或いはＸ線を含む前記電磁波検出素子に対応した各種の電磁波が透過可能な窓部を有する収納筒内に収納したことを特徴とする検査装置。 3. The inspection apparatus according to claim 2, wherein the semiconductor device according to claim 2 is housed in a housing cylinder having a window portion through which various electromagnetic waves corresponding to the electromagnetic wave detecting element including light or X-rays can be transmitted. . 上面に表面電極が形成された第１のＩＣチップと、側面に側面電極が形成された、ＩＣが組み込まれた第２のＩＣチップ又は配線パターンが表面に形成されたチップと、立体的な基板とを有し、
前記基板の１つの面に前記第１のＩＣチップを取り付け、
前記基板の前記１つの面に隣接する表面に前記第２のＩＣチップ又は前記チップを取り付け、
前記第１のＩＣチップの前記表面電極と前記第２のＩＣチップ又は前記チップの前記側面電極とをボンディングワイヤにより直接接続することを特徴とする半導体装置の製造方法。 A first IC chip having a surface electrode formed on the upper surface, a second IC chip having a side electrode formed on the side surface, a second IC chip incorporating an IC or a chip having a wiring pattern formed on the surface, and a three-dimensional substrate And
Attaching the first IC chip to one surface of the substrate;
The second IC chip or the chip mounting on the front surface adjacent to the one surface of the substrate,
A method of manufacturing a semiconductor device, wherein the surface electrode of the first IC chip and the side electrode of the second IC chip or the chip are directly connected by a bonding wire. シリコン基材の所定の位置にスルーホールを穿孔し、
前記シリコン基材の上面、下面及びスルーホールの側面に絶縁層を形成し、
前記シリコン基材の上面の前記絶縁層上に表面電極を形成すると共に前記スルーホールの内側面に側面電極を形成し、
前記スルーホール及び前記側面電極の無い部分に、前記スルーホールを横切る分断線に沿って切込部を形成し、
その後、前記分断線に沿って劈開或いは切り欠き誘導することにより、ＩＣが組み込まれた第２のＩＣチップ又は配線パターンが表面に形成されたチップを形成し、
立体的な基板の１つの面に第１のＩＣチップを取り付け、
前記基板の前記１つの面に隣接する表面に前記第２のＩＣチップ又は前記チップを取り付け、
前記第１のＩＣチップの前記表面電極と前記第２のＩＣチップ又は前記チップの前記側面電極とをボンディングワイヤにより直接接続することを特徴とする半導体装置の製造方法。 Drill a through hole in a predetermined position on the silicon substrate,
Forming an insulating layer on the upper surface, lower surface and side surface of the through hole of the silicon substrate;
Forming a surface electrode on the insulating layer on the upper surface of the silicon substrate and forming a side electrode on the inner surface of the through-hole;
In the part without the through-hole and the side electrode, a cut portion is formed along a dividing line across the through-hole,
Then, by cleaving or notching along the dividing line, a second IC chip incorporating an IC or a chip having a wiring pattern formed on the surface is formed .
A first IC chip is attached to one surface of a three-dimensional substrate,
The second IC chip or the chip mounting on the front surface adjacent to the one surface of the substrate,
A method of manufacturing a semiconductor device, wherein the surface electrode of the first IC chip and the side electrode of the second IC chip or the chip are directly connected by a bonding wire.
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