JP2001024144A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2001024144A
JP2001024144A JP19491599A JP19491599A JP2001024144A JP 2001024144 A JP2001024144 A JP 2001024144A JP 19491599 A JP19491599 A JP 19491599A JP 19491599 A JP19491599 A JP 19491599A JP 2001024144 A JP2001024144 A JP 2001024144A
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip
semiconductor device
semiconductor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19491599A
Other languages
Japanese (ja)
Inventor
Yoshio Adachi
喜雄 安達
Takashi Oguchi
孝 大口
Kinya Kasai
金也 河西
Tadao Kawamata
忠雄 川又
Hiroshi Sugawara
宏 菅原
Tamotsu Kaneko
金子  保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP19491599A priority Critical patent/JP2001024144A/en
Publication of JP2001024144A publication Critical patent/JP2001024144A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To effectively obtain decoupling of high-frequency components in an internal circuit for an LSI. SOLUTION: A chip capacitor 4 for removing a high-frequency component is inserted into a through-hole 3 formed to a semiconductor chip substrate 1. Since the chip capacitor 4 is arranged at a position nearest to an internal circuit for an LSI, unnecessary impedance does not exist between the internal circuit for the LSI and the chip capacitor 4, the internal circuit is decoupled effectively, and the semiconductor device can be operated stably.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
特に、半導体チップ内の回路の高周波成分を効果的に除
去することのできる半導体装置に関する。
The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device capable of effectively removing a high frequency component of a circuit in a semiconductor chip.

【0002】[0002]

【従来の技術】図4は、従来の半導体装置の斜視図であ
る。この半導体装置を製造する際には、半導体チップ40
2を半導体チップ基板401に単独で載置して接着し、その
後、半導体チップ基板401のボンディング端子405との間
をボンディイングワイヤ404で接続し、外装を行いLS
Iとして完成させる。なお、LSI基板の中に部品を実
装することもある。
2. Description of the Related Art FIG. 4 is a perspective view of a conventional semiconductor device. When manufacturing this semiconductor device, the semiconductor chip 40
2 is placed alone on the semiconductor chip substrate 401 and adhered, and then connected to the bonding terminals 405 of the semiconductor chip substrate 401 with bonding wires 404, and the package is packaged.
Complete as I. In some cases, components are mounted on an LSI substrate.

【0003】[0003]

【発明が解決しようとする課題】近年、LSIの増幅・
処理する周波数は飛躍的に高いところまで対応すること
が求められ、また実現しないと商品として十分な価値を
有しない。LSIを高い周波数まで動作させるために
は、LSIの内部回路の高周波成分を効果的に除去して
高周波ポテンシャルを下げることが必要である。そし
て、高周波ポテンシャルを下げれば下げるほど回路は安
定し、高い増幅度の設定や、高周波対応が可能になる。
SUMMARY OF THE INVENTION In recent years, LSI amplification and
It is required that the frequency to be processed be dramatically increased, and if it is not realized, it will not have sufficient value as a commercial product. In order to operate an LSI up to a high frequency, it is necessary to effectively remove high-frequency components of an internal circuit of the LSI to lower a high-frequency potential. The lower the high-frequency potential is, the more stable the circuit is, and it is possible to set a high amplification degree and to support high frequencies.

【0004】そこで、半導体チップ402の内部回路の高
周波成分を除去するために、半導体チップ基板401の表
面に高周波成分除去用のチップコンデンサ403を設ける
ことが考えられる。このように構成することにより、半
導体チップ402の内部回路の高周波成分をチップコンデ
ンサ403により除去することができる。
In order to remove high-frequency components from the internal circuit of the semiconductor chip 402, it is conceivable to provide a chip capacitor 403 for removing high-frequency components on the surface of the semiconductor chip substrate 401. With this configuration, the high frequency component of the internal circuit of the semiconductor chip 402 can be removed by the chip capacitor 403.

【0005】しかしながら、以上のような構成を有する
LSIでは、その内部回路の高周波成分を除去する効果
が不十分であるため、LSIの動作が不安定になってし
まう。以下、図5に示したLSIの等価回路を用いてそ
の理由を説明する。
However, in the LSI having the above configuration, the effect of removing the high-frequency component of the internal circuit is insufficient, so that the operation of the LSI becomes unstable. Hereinafter, the reason will be described using the equivalent circuit of the LSI shown in FIG.

【0006】図5において、半導体チップ402に低周波
から高周波までの回路のデカップリングあるいはフイル
ター回路を設けることにより、LSIを非常に安定させ
ながら高利得の増幅機能を得ることは可能である。しか
し、LSI内の回路408のデカップリングあるいはフイ
ルタリングを行うために、回路408の両端の電圧e1の高
周波成分の除去を目的としてチップ基板401に実装した
チップコンデンサ403が純粋のコンデンサであり、e1の
高周波成分を限りなく除去する性能を持っているとして
も、回路408とコンデンサ403との間には以下の(1)〜
(3)に記載するインピーダンスが介在する。
In FIG. 5, by providing a semiconductor chip 402 with a decoupling or filter circuit for circuits from low to high frequencies, it is possible to obtain a high gain amplifying function while making the LSI very stable. However, in order to perform decoupling or filtering of the circuit 408 in the LSI, the chip capacitor 403 mounted on the chip substrate 401 for the purpose of removing the high frequency component of the voltage e1 across the circuit 408 is a pure capacitor. Even if it has the performance of removing the high frequency components as much as possible, between the circuit 408 and the capacitor 403, the following (1) to
The impedance described in (3) is interposed.

【0007】(1)ボンディングL:L1・・・半導体チ
ップ402から半導体チップ基板401までの誘導成分 (2)回路L:L2・・・LSIのリード端子406からチ
ップコンデンサ403までの回路の誘導成分 (3)アースL:L3・・・半導体チップ402のアースリ
ードからチップコンデンサ403のアース端子までの誘導
成分 なお、図5において本体基板アース409は、図4のLS
Iを取り付ける基板のアースである。
(1) Bonding L: L1... Inductive component from semiconductor chip 402 to semiconductor chip substrate 401 (2) Circuit L: L2... Inductive component of circuit from LSI lead terminal 406 to chip capacitor 403 (3) Ground L: L3... Inductive component from the ground lead of the semiconductor chip 402 to the ground terminal of the chip capacitor 403. In FIG. 5, the body substrate ground 409 is LS in FIG.
This is the ground for the board on which I is mounted.

【0008】この結果、回路408の両端の電圧e1は以下
の式〔1〕で表される。 e1=Z1(L1)i+Z2(L2)i+Z3(C)i+Z4(L3)i …〔1〕 除去目的の周波数に対してZ3は近似的に無視する値とな
るから、e1は以下の式〔2〕で表される。 e1=Z1(L1)i+Z2(L2)i+Z4(L3)i …〔2〕
As a result, the voltage e1 across the circuit 408 is expressed by the following equation [1]. e1 = Z1 (L1) i + Z2 (L2) i + Z3 (C) i + Z4 (L3) i [1] Since Z3 is a value that is approximately ignored for the frequency to be removed, e1 is It is represented by the following equation [2]. e1 = Z1 (L1) i + Z2 (L2) i + Z4 (L3) i ... [2]

【0009】この式〔2〕から分かるように、e1の電圧
を除去する目的でコンデンサ403を実装しても、コンデ
ンサ403までの経路の誘導成分が存在することにより、
回路408の両端の高周波成分を除去出来ないため、LS
Iの動作が不安定になる。
As can be seen from equation (2), even if the capacitor 403 is mounted for the purpose of removing the voltage of e1, the induction component of the path to the capacitor 403 exists,
Since high-frequency components at both ends of the circuit 408 cannot be removed, LS
The operation of I becomes unstable.

【0010】本発明はこのような問題点に鑑みてなされ
たものであって、LSIの内部回路の高周波成分の除去
を効果的に行える半導体装置を提供することを目的とす
る。
The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device capable of effectively removing high-frequency components from an internal circuit of an LSI.

【0011】[0011]

【課題を解決するための手段】前記課題を解決するため
に本発明では、半導体チップ基板と、前記半導体チップ
基板の表面に実装された半導体チップとを備えた半導体
装置において、前記半導体チップ基板に形成された貫通
孔に前記半導体チップ内回路の高周波成分除去用のチッ
プコンデンサが挿入され、固定された構成とした。この
ように構成したことにより、半導体チップとチップコン
デンサとの間の不要なインピーダンスをなくし、効果的
な高周波成分除去を行うことができる。
According to the present invention, there is provided a semiconductor device having a semiconductor chip substrate and a semiconductor chip mounted on a surface of the semiconductor chip substrate. A chip capacitor for removing a high-frequency component of the circuit in the semiconductor chip is inserted into the formed through hole and fixed. With this configuration, unnecessary impedance between the semiconductor chip and the chip capacitor can be eliminated, and effective high-frequency component removal can be performed.

【0012】[0012]

【発明の実施の形態】本発明の請求項1に記載の発明
は、半導体チップ基板と、前記半導体チップ基板表面に
実装された半導体チップとを備えた半導体装置におい
て、前記半導体チップ基板に形成された貫通孔に前記半
導体チップ内回路の高周波成分除去用のチップコンデン
サが挿入され、固定された半導体装置であり、チップ基
板の貫通孔に挿入されたチップコンデンサにより、半導
体チップ内回路の高周波成分が除去されるという作用を
有する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor chip substrate and a semiconductor chip mounted on a surface of the semiconductor chip substrate. A chip capacitor for removing a high-frequency component of the circuit in the semiconductor chip is inserted into the through hole, and the semiconductor device is fixed. It has the effect of being removed.

【0013】本発明の請求項2に記載の発明は、請求項
1記載の半導体装置において、前記チップコンデンサに
おける前記基板表面側の端子と前記半導体チップとの間
がボンディングワイヤにより直接接続されている半導体
装置であり、半導体チップ内回路の高周波成分がボンデ
ィングワイヤを通り、チップコンデンサにより除去され
るという作用を有する。
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a terminal on the substrate surface side of the chip capacitor and the semiconductor chip are directly connected by a bonding wire. The semiconductor device has a function that a high frequency component of a circuit in a semiconductor chip passes through a bonding wire and is removed by a chip capacitor.

【0014】本発明の請求項3に記載の発明は、請求項
1記載の半導体装置において、前記貫通孔の横断面形状
を略8の字形とした半導体装置であり、チップコンデン
サの自重による落下を防止するという作用を有する。
According to a third aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the cross-sectional shape of the through-hole is substantially eight-shaped. It has the effect of preventing.

【0015】本発明の請求項4に記載の発明は、請求項
1記載の半導体装置において、前記チップ基板の裏面側
の全面にアースパターンが形成されている半導体装置で
あり、半導体チップ内回路の高周波成分をチップコンデ
ンサからチップ基板の裏面側の全面のアースパターンに
流すという作用を有する。
According to a fourth aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein an earth pattern is formed on the entire back surface of the chip substrate. It has the effect of flowing high frequency components from the chip capacitor to the ground pattern on the entire back side of the chip substrate.

【0016】以下、本発明の実施の形態について図面を
参照しながら詳細に説明する。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

【0017】図1は、本発明を適用した半導体装置の断
面図である。なお、この半導体装置全体の基本的な構造
は、チップコンデンサの実装部分を除けば、図4に示し
た半導体装置と同一であるため、斜視図は省略する。
FIG. 1 is a sectional view of a semiconductor device to which the present invention is applied. Note that the basic structure of the entire semiconductor device is the same as that of the semiconductor device shown in FIG. 4 except for a mounting portion of a chip capacitor, and thus a perspective view is omitted.

【0018】図1に示すように、本発明を適用した半導
体装置では、半導体チップ基板1の表面に半導体チップ
2が実装されている。また、半導体チップ基板1の裏面
の全面にアースパターン9が形成され、アースパターン
9の右端にはアース端子7が立設されている。半導体チ
ップ基板1に空けられた貫通孔であるチップコンデンサ
挿入孔3には、チップコンデンサ4が挿入されている。
チップコンデンサ4において半導体チップ基板1の表面
側に露出している側は、ボンディングワイヤ5により半
導体チップ2のデカップリング回路と直接的に接続され
ている。そして、チップコンデンサ4において半導体チ
ップ基板1の裏面側に露出している側は、はんだ6によ
りアースパターン9に接合されている。半導体チップ2
はアースリード8により半導体チップ基板1の表面のア
ースパターン(図示せず)に接続されている。そして、
このアースパターンはスルーホールなど(図示せず)に
よりアース端子7に接続されている。
As shown in FIG. 1, in a semiconductor device to which the present invention is applied, a semiconductor chip 2 is mounted on a surface of a semiconductor chip substrate 1. A ground pattern 9 is formed on the entire back surface of the semiconductor chip substrate 1, and a ground terminal 7 is provided upright on the right end of the ground pattern 9. A chip capacitor 4 is inserted into a chip capacitor insertion hole 3 which is a through hole formed in the semiconductor chip substrate 1.
The side of the chip capacitor 4 that is exposed on the front side of the semiconductor chip substrate 1 is directly connected to the decoupling circuit of the semiconductor chip 2 by bonding wires 5. The side of the chip capacitor 4 that is exposed on the back side of the semiconductor chip substrate 1 is joined to the ground pattern 9 by solder 6. Semiconductor chip 2
Are connected to ground patterns (not shown) on the surface of the semiconductor chip substrate 1 by ground leads 8. And
This ground pattern is connected to the ground terminal 7 through a through hole or the like (not shown).

【0019】チップコンデンサ4は、チップコンデンサ
挿入孔3に自動挿入される。その際、チップコンデンサ
4が自重で落下等しないように、チップコンデンサ挿入
孔3を図2の平面図のように、略8の字形に構成し、狭
くなっている部位でチップコンデンサ4を支え、チップ
コンデンサ4の四角がチップ挿入孔3に当るようにして
位置を決め、半導体チップ2からのボンディングに対応
する。
The chip capacitor 4 is automatically inserted into the chip capacitor insertion hole 3. At that time, in order to prevent the chip capacitor 4 from dropping by its own weight or the like, the chip capacitor insertion hole 3 is formed in an approximately figure-eight shape as shown in the plan view of FIG. 2, and the chip capacitor 4 is supported at a narrow portion. The position is determined so that the square of the chip capacitor 4 hits the chip insertion hole 3, which corresponds to bonding from the semiconductor chip 2.

【0020】次に、以上のように構成された半導体装置
のチップコンデンサの高周波成分除去作用について図3
の等価回路を用いて説明する。この等価回路より、半導
体チップ2の回路11の両端の電圧e2は下記の式〔3〕で
表される。 e2=Z4(L4) …〔3〕 この式において、L4は半導体チップ2から半導体チッ
プ基板1までの誘導成分(ボンティングL)である。
Next, the action of removing the high-frequency component of the chip capacitor of the semiconductor device configured as described above will be described with reference to FIG.
This will be described using the equivalent circuit of FIG. From this equivalent circuit, the voltage e2 across the circuit 11 of the semiconductor chip 2 is expressed by the following equation [3]. e2 = Z4 (L4) (3) In this equation, L4 is an induction component (bonding L) from the semiconductor chip 2 to the semiconductor chip substrate 1.

【0021】式〔2〕と式〔3〕とを比較することによ
り、 0<e2<e1 となることが分かる。
By comparing Equations [2] and [3], it can be seen that 0 <e2 <e1.

【0022】回路のデカップリングはチップコンデンサ
により0Vになれば理想的である。本発明の実施の形態
では、コンデンサの容量と回路のインピーダンスとによ
り異なるが、高周波性能は従来例よりも格段に向上す
る。
The decoupling of the circuit is ideal if it becomes 0 V by the chip capacitor. In the embodiment of the present invention, although it differs depending on the capacitance of the capacitor and the impedance of the circuit, the high frequency performance is remarkably improved as compared with the conventional example.

【0023】[0023]

【発明の効果】以上のように、本発明に係る半導体装置
では、半導体チップ基板に形成された貫通孔に半導体チ
ップ内回路の高周波成分除去用のチップコンデンサを挿
入し、固定したので、半導体チップとチップコンデンサ
との間の不要なインピーダンスをなくし、高周波デカッ
プリングが必要な回路の高周波成分を効果的に除去でき
るという効果が得られる。
As described above, in the semiconductor device according to the present invention, the chip capacitor for removing the high-frequency component of the circuit in the semiconductor chip is inserted and fixed in the through hole formed in the semiconductor chip substrate. This eliminates unnecessary impedance between the chip and the chip capacitor, and effectively removes high frequency components of a circuit requiring high frequency decoupling.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明を適用した半導体装置の断面図、FIG. 1 is a cross-sectional view of a semiconductor device to which the present invention is applied.

【図2】本発明を適用した半導体装置の要部の平面図、FIG. 2 is a plan view of a main part of a semiconductor device to which the present invention is applied;

【図3】本発明を適用した半導体装置の等価回路、FIG. 3 is an equivalent circuit of a semiconductor device to which the present invention is applied;

【図4】従来の半導体装置の斜視図、FIG. 4 is a perspective view of a conventional semiconductor device;

【図5】従来の半導体装置の等価回路である。FIG. 5 is an equivalent circuit of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体チップ基板 2 半導体チップ 3 チップコンデンサ挿入孔 4 チップコンデンサ 5 ボンディングワイヤ 6、10 はんだ 7 アース端子 8 アースリード 9 アースパターン DESCRIPTION OF SYMBOLS 1 Semiconductor chip board 2 Semiconductor chip 3 Chip capacitor insertion hole 4 Chip capacitor 5 Bonding wire 6, 10 Solder 7 Ground terminal 8 Ground lead 9 Ground pattern

フロントページの続き (72)発明者 河西 金也 神奈川県横浜市港北区綱島東四丁目3番1 号 松下通信工業株式会社内 (72)発明者 川又 忠雄 神奈川県横浜市港北区綱島東四丁目3番1 号 松下通信工業株式会社内 (72)発明者 菅原 宏 神奈川県横浜市港北区綱島東四丁目3番1 号 松下通信工業株式会社内 (72)発明者 金子 保 神奈川県横浜市港北区綱島東四丁目3番1 号 松下通信工業株式会社内Continuing from the front page (72) Inventor Kanaya Kasai 4-3-1 Tsunashima Higashi, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Inside Matsushita Communication Industrial Co., Ltd. (72) Inventor Tadao Kawamata 4-3-1 Tsunashima Higashi, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture No. 1 Matsushita Communication Industrial Co., Ltd. (72) Inventor Hiroshi Sugawara 4-3-1 Tsunashima Higashi, Kohoku-ku, Yokohama, Kanagawa Prefecture Inside Matsushita Communication Industrial Co., Ltd. (72) Inventor Tamotsu Kaneko Tsunashima, Kohoku-ku, Yokohama, Kanagawa Prefecture Matsushita Communication Industrial Co., Ltd.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップ基板と、前記半導体チップ
基板表面に実装された半導体チップとを備えた半導体装
置において、前記半導体チップ基板に形成された貫通孔
に前記半導体チップ内回路の高周波成分除去用のチップ
コンデンサが挿入され、固定されたことを特徴とする半
導体装置。
1. A semiconductor device comprising a semiconductor chip substrate and a semiconductor chip mounted on a surface of the semiconductor chip substrate, wherein a through-hole formed in the semiconductor chip substrate has a through hole for removing a high-frequency component of a circuit in the semiconductor chip. Wherein the chip capacitor is inserted and fixed.
【請求項2】 前記チップコンデンサにおける前記基板
表面側の端子と前記半導体チップとの間がボンディング
ワイヤにより直接接続されていることを特徴とする請求
項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein a terminal on the substrate surface side of the chip capacitor and the semiconductor chip are directly connected by a bonding wire.
【請求項3】 前記貫通孔の断面形状を略8の字形とし
たことを特徴とする請求項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the cross-sectional shape of said through hole is substantially a figure eight.
【請求項4】 前記チップ基板の裏面側の全面にアース
パターンが形成されていることを特徴とする請求項1記
載の半導体装置。
4. The semiconductor device according to claim 1, wherein a ground pattern is formed on the entire back surface of said chip substrate.
JP19491599A 1999-07-08 1999-07-08 Semiconductor device Pending JP2001024144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19491599A JP2001024144A (en) 1999-07-08 1999-07-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19491599A JP2001024144A (en) 1999-07-08 1999-07-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2001024144A true JP2001024144A (en) 2001-01-26

Family

ID=16332469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19491599A Pending JP2001024144A (en) 1999-07-08 1999-07-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2001024144A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1387603A1 (en) * 2002-07-30 2004-02-04 Agilent Technologies, Inc. - a Delaware corporation - Electronic assembly and method of manufacture thereof
JP2008112752A (en) * 2006-10-27 2008-05-15 Mitsubishi Heavy Ind Ltd Semiconductor device, inspection instrument, manufacturing method of semiconductor device, and manufacturing method of chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1387603A1 (en) * 2002-07-30 2004-02-04 Agilent Technologies, Inc. - a Delaware corporation - Electronic assembly and method of manufacture thereof
JP2008112752A (en) * 2006-10-27 2008-05-15 Mitsubishi Heavy Ind Ltd Semiconductor device, inspection instrument, manufacturing method of semiconductor device, and manufacturing method of chip

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