JP5352131B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP5352131B2
JP5352131B2 JP2008149682A JP2008149682A JP5352131B2 JP 5352131 B2 JP5352131 B2 JP 5352131B2 JP 2008149682 A JP2008149682 A JP 2008149682A JP 2008149682 A JP2008149682 A JP 2008149682A JP 5352131 B2 JP5352131 B2 JP 5352131B2
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light receiving
receiving portion
region
wiring
electrode
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JP2009295880A (en
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誠 照井
茂 山田
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Lapis Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Solid State Image Pick-Up Elements (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

本発明は、半導体装置の製造方法に関するものであり、特に、半導体基板の受光部形成面に保護部材を有する半導体装置の製造方法に関する。 The present invention relates to the production how the semi conductor device, in particular, relates to the production how the semi conductor device that having a protective member on the light receiving portion forming surface of the semiconductor substrate.

ＣＣＤセンサ等の固体撮像素子（半導体装置）は、ウエハレベルチップサイズパッケージ（ＷＣＳＰ）を用いている。この固体撮像素子は、受光部が設けられたイメージセンサチップと、受光部を覆って保護するカバーガラスと、イメージセンサチップとカバーガラスとの間に配置されるスペーサーとから構成されている（例えば、特許文献１参照）。   A solid-state imaging device (semiconductor device) such as a CCD sensor uses a wafer level chip size package (WCSP). This solid-state imaging device includes an image sensor chip provided with a light receiving unit, a cover glass that covers and protects the light receiving unit, and a spacer disposed between the image sensor chip and the cover glass (for example, , See Patent Document 1).

また、このような固体撮像素子の一般的な製造工程は、ウエハ上のイメージセンサチップにカバーガラスを貼り合わせた後、基板に貫通配線を設け、裏面配線を介して外部端子を形成するものである（例えば、特許文献１参照）。   In addition, a general manufacturing process of such a solid-state imaging device is such that a cover glass is bonded to an image sensor chip on a wafer, a through wiring is provided on a substrate, and an external terminal is formed through a back surface wiring. Yes (see, for example, Patent Document 1).

特開２００７−１８４６８０公報JP 2007-184680 A

しかしながら、このような構成の半導体装置では、カバーガラスをイメージセンサチップに貼り合わせた後に貫通配線を形成しているため、最終製品での貫通配線部の電気的な導通チェックが難しいという問題があった。   However, in the semiconductor device having such a configuration, since the through wiring is formed after the cover glass is bonded to the image sensor chip, there is a problem that it is difficult to check the electrical continuity of the through wiring portion in the final product. It was.

本発明は、前記問題点に鑑みなされたものであり、以下の目的を達成することを課題とする。
即ち、本発明の目的は、保護部材を形成した後でも半導体基板に形成された貫通配線の導通を確認することができる半導体装置の製造方法を提供することにある。 This invention is made | formed in view of the said problem, and makes it a subject to achieve the following objectives.
It is an object of the present invention is to provide a manufacturing how a semi conductor device that can be confirmed continuity even after the formation of the protective member is formed on the semiconductor substrate through wiring.

本発明者は鋭意検討した結果、下記の半導体装置の製造方法を用いることにより、上記問題を解決できることを見出し、上記目的を達成するに至った。 The present inventors have a result of intensive studies, by using the manufacturing method of the semi-conductor device following, we can solve the above problems, leading to achieve the above object.

即ち、本発明の半導体装置の製造方法は、受光部が形成された複数の受光部形成領域と、該受光部形成領域を区画する格子状の区画領域と、を有する半導体ウエハの該受光部形成領域に、該受光部と電気的に接続された受光部接続電極、及び該受光部と電気的に接続されてなく、少なくとも２つが互いに電気的に接続されたテスト用電極を同時に形成する第１工程と、光透過性の保護部材を、前記受光部が封止されるように接続部を介して設ける第２工程と、前記受光部接続電極及び前記テスト用電極が露出するように、前記半導体ウエハに前記受光部形成領域を有する面と前記受光部形成領域とは反対側の面を貫通する貫通孔を設け、該貫通孔に前記受光部接続電極と電気的に接続する受光部接続貫通配線及び前記テスト用電極と電気的に接続するテスト用貫通配線を同時に形成する第３工程と、前記区画領域に沿うように、前記半導体ウエハ及び前記光透過性の保護部材を裁断する第４工程と、をこの順に有することを特徴とする。 That is , in the method for manufacturing a semiconductor device of the present invention, the light receiving portion formation of a semiconductor wafer having a plurality of light receiving portion forming regions in which the light receiving portions are formed and a grid-like partition region that partitions the light receiving portion forming regions. A first light-receiving unit connection electrode electrically connected to the light-receiving unit and a test electrode that is not electrically connected to the light-receiving unit and at least two of which are electrically connected to each other are simultaneously formed in the region. a step, the optically transparent protecting member, a second step of the light receiving portion is provided via a connection to be sealed, so that the light receiving portion connecting electrode and the test electrode is exposed, said semiconductor A light-receiving-unit connection through-wiring that has a through-hole penetrating a surface having the light-receiving-portion-forming region and a surface opposite to the light-receiving-portion forming region on the wafer, and is electrically connected to the light-receiving-unit connection electrode in the through-hole and electrically with said test electrode A third step of simultaneously forming a test through wiring connection, along with the divided area, and characterized by comprising a fourth step of cutting the semiconductor wafer and the light transparent protective member, in this order To do.

また、本発明の半導体装置の製造方法は、受光部が形成された複数の受光部形成領域と、該受光部形成領域を区画する格子状の区画領域と、を有する半導体ウエハの該受光部形成領域に、該受光部と電気的に接続された受光部接続電極を形成すると同時に、前記区画領域に、前記受光部と電気的に接続されてなく、少なくとも２つが互いに電気的に接続されたテスト用電極を形成する第１工程と、前記受光部が封止されるように、接続部を介して光透過性の保護部材を設ける第２工程と、前記受光部接続電極及び前記テスト用電極が露出するように、前記半導体ウエハに前記区画領域を有する面と前記区画領域の反対側の面とを貫通する貫通孔を設け、該貫通孔に前記受光部接続電極と電気的に接続する受光部接続貫通配線及び前記テスト用電極と電気的に接続されたテスト用貫通配線を同時に形成する第３工程と、前記テスト用貫通配線が電気的に導通しているか否かを検査する検査工程と、前記区画領域に沿うように、前記半導体ウエハ及び前記光透過性の保護部材を裁断する第４工程と、をこの順に有することを特徴とする。 A method of manufacturing a semiconductor device of the present invention, the light receiving semiconductor wafers to be closed and a plurality of light receiving portions forms a region where the light receiving portion is formed, a lattice shape of divided areas defining the light receiving portion forming region, the At the same time, the light receiving portion connection electrode electrically connected to the light receiving portion is formed in the portion forming region, and at the same time , at least two of the light receiving portions are not electrically connected to the partition region. and a first step of forming a test electrode, so that the light receiving portion is sealed, a second step of Ru formed light transparent protective member through the connecting portion, the light receiving portion connecting electrode and the test A through hole penetrating the surface having the partition region and the surface opposite to the partition region is provided in the semiconductor wafer so that the electrode for exposure is exposed, and is electrically connected to the light receiving portion connection electrode in the through hole light-receiving unit connected through wiring and the test for An inspection step of inspecting a third step of forming electrode and electrically connected to the test through wiring simultaneously, the test through wiring whether electrically conducting, along the defined areas And a fourth step of cutting the semiconductor wafer and the light-transmissive protective member in this order .

本発明によれば、保護部材を形成した後でも半導体基板に形成された貫通配線の導通を検査することができる半導体装置の製造方法を提供することができる。 According to the present invention, it is possible to provide a manufacturing how a semi conductor device that can be inspected conduction even after forming a protective member formed on the semiconductor substrate through wiring.

以下、図面を参照して、この発明の実施の形態につき説明する。なお、図面には、この発明が理解できる程度に各構成部位の形状、大きさ及び配置関係が概略的に示されているにすぎず、これによりこの発明が特に限定されるものではない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the shape, size, and arrangement relationship of each component are schematically shown to such an extent that the present invention can be understood, and the present invention is not particularly limited thereby.

＜半導体装置＞
〔第１の実施形態〕
図１（Ａ）は本発明の第１の実施形態における半導体装置１００の上面透視図であり、図１（Ｂ）は図１（Ａ）中のＸ−Ｘ’断面図であり、図１（Ｃ）は、図１（Ａ）中のＹ−Ｙ’断面図である。 <Semiconductor device>
[First Embodiment]
1A is a top perspective view of the semiconductor device 100 according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line XX ′ in FIG. C) is a YY ′ cross-sectional view in FIG.

本発明の半導体装置１００は、図１（Ｂ）のように、半導体基板１２０の受光部１０５が形成されている受光部形成面に、受光部１０５と電気的に接続されている電極１０６を有する。
また、前記受光部形成面には、図１（Ｃ）のように、受光部１０５とは電気的に接続されていない電極１０８が形成されており、この電極１０８はアルミニウム等からなる配線１３０にて少なくとも２つが電気的に接続されている。
このように、半導体基板１２０には、図１（Ａ）のように、前記受光部形成面に電極１０６、１０８が形成されており、受光部（図１では不図示）の外周縁部近傍に位置している。 As shown in FIG. 1B, the semiconductor device 100 of the present invention has an electrode 106 electrically connected to the light receiving portion 105 on the light receiving portion forming surface of the semiconductor substrate 120 where the light receiving portion 105 is formed. .
Further, as shown in FIG. 1C, an electrode 108 that is not electrically connected to the light receiving portion 105 is formed on the light receiving portion forming surface, and this electrode 108 is formed on a wiring 130 made of aluminum or the like. And at least two are electrically connected.
As described above, as shown in FIG. 1A, the electrodes 106 and 108 are formed on the light receiving portion forming surface on the semiconductor substrate 120, and in the vicinity of the outer peripheral edge of the light receiving portion (not shown in FIG. 1). positioned.

外部端子１０４は、図１（Ｂ）のように、電極１０６、及び貫通配線１１１を介して受光部１０５と電気的に接続されている。すなわち、受光部１０５で検出された入射光は電気信号に変換され、電極１０６、貫通配線１１１を介して外部端子１０４から外部に送信されることになる。この貫通配線１１１は、半導体基板１２０の受光部形成面（以下、適宜、「表面」と称する）と、当該受光部形成面とは反対側の面（以下、適宜、「裏面」と称する）と、を貫通している。
この貫通配線１１１には、裏面側で外部端子１０４と接続するために配線が引き出されており、保護膜１１２で被覆されている。また、保護膜１１２は、外部端子１０４の表面を露出するように形成されている。
他方、貫通配線１１３は、貫通配線１１１と同様に、半導体基板１２０の表面と裏面とを貫通している配線であり、半導体基板１２０の裏面に位置する外部端子（不図示）と接続されている。 The external terminal 104 is electrically connected to the light receiving unit 105 through the electrode 106 and the through wiring 111 as shown in FIG. In other words, incident light detected by the light receiving unit 105 is converted into an electric signal and transmitted from the external terminal 104 to the outside via the electrode 106 and the through wiring 111. The through wiring 111 includes a light receiving portion forming surface (hereinafter referred to as “front surface” as appropriate) of the semiconductor substrate 120 and a surface opposite to the light receiving portion forming surface (hereinafter referred to as “back surface” as appropriate). , Through.
In the through wiring 111, wiring is drawn out to connect to the external terminal 104 on the back surface side, and is covered with the protective film 112. The protective film 112 is formed so as to expose the surface of the external terminal 104.
On the other hand, the through wiring 113 is a wiring penetrating the front surface and the back surface of the semiconductor substrate 120, similarly to the through wiring 111, and is connected to an external terminal (not shown) located on the back surface of the semiconductor substrate 120. .

また、前述の電極１０６、１０８は、図１（Ｂ）、及び図１（Ｃ）のようにエポキシ樹脂等からなる接着剤で覆われており、接続部１０２を構成している。
この接続部１０２には、半導体基板１２０の受光部形成面側から見たときに、半導体基板１２０の外周縁部に位置する。すなわち、接続部１０２は受光部１０５を囲うように形成されていることになる。そして、本発明の半導体装置１００は、半導体基板１２０上に接続部１０２を介して光透過性の保護部材１０１が設けられている。なお、センサの種類（例えばＵＶセンサなど）によっては、受光部全面に形成したままでも良い。
この保護部材１０１は、受光部形成領域を外部から保護するという機能を有するが、これに加え、外部から受ける光を受光部に伝える機能をも必要とする。例えば、受光部に要求される光が可視光である場合には、保護部材１０１は、可視光を透過させる機能を有することが必要である。保護部材１０１には、可視光のみを選択的に透過させるために、その表面に紫外光や赤外光をカットするコーティングが施されていてもよい。すなわち、保護部材１０１は、受光部が要求する特定の波長の光を透過させるフィルター機能を有していてもよい。以上のように、保護部材１０１の材料は、ガラスに限定されるものではなく、上述の機能を備えていれば、例えばプラスティック等の材料でもよい。 Further, the electrodes 106 and 108 described above are covered with an adhesive made of an epoxy resin or the like as shown in FIGS.
The connection portion 102 is located on the outer peripheral edge portion of the semiconductor substrate 120 when viewed from the light receiving portion forming surface side of the semiconductor substrate 120. That is, the connection part 102 is formed so as to surround the light receiving part 105. In the semiconductor device 100 of the present invention, a light transmissive protective member 101 is provided on a semiconductor substrate 120 via a connection portion 102. Depending on the type of sensor (for example, a UV sensor), it may be formed on the entire surface of the light receiving unit.
The protective member 101 has a function of protecting the light receiving portion forming region from the outside, but in addition to this, it also needs a function of transmitting light received from the outside to the light receiving portion. For example, when the light required for the light receiving unit is visible light, the protective member 101 needs to have a function of transmitting visible light. In order to selectively transmit only visible light, the protective member 101 may be provided with a coating that cuts ultraviolet light or infrared light on the surface thereof. That is, the protection member 101 may have a filter function that transmits light of a specific wavelength required by the light receiving unit. As described above, the material of the protective member 101 is not limited to glass, and may be a material such as plastic as long as it has the above-described function.

このように、本発明の半導体装置１００は、図１（Ａ）、及び図１（Ｃ）のように、受光部（図１（Ａ）、図１（Ｃ）では不図示）と電気的に接続されていなく、尚且つ少なくとも２つが配線１３０を介して互いに電気的に接続された電極（以下、適宜、「テスト用電極」と称する）１０８を備えることが特徴である。
このテスト用電極１０８は、図１（Ｃ）のように、半導体基板１２０の受光部形成面から受光部形成面とは反対側の面を貫通する貫通配線１１３を介して、外部端子（図１（Ｃ）では不図示）を電気的に接続するものである。この貫通配線１１３は、図１（Ｂ）に示す受光部１０５に接続された電極１０６と外部端子１０４とを電気的に接続する貫通配線１１１と同時に形成されるものである。従って、図１（Ｃ）に示す貫通配線１１３の導通を検査することにより、図１（Ｂ）に示す貫通配線１１１の導通を検査したものとみなすことができる。
これらの貫通配線１１１、１１３は、半導体基板１２０の裏面に設けられている外部端子（不図示）と接続されており、保護部材１０１を設けた後であっても半導体基板１２０の裏面に露出している。すなわち、半導体ウエハから個片化した後の最終製品の状態で、貫通配線の導通を検査することができる。
テスト用電極１０８の数は、１つの半導体装置に少なくとも２つを備えていればよく、図１（Ａ）のように、２つの角部に合計で４つ形成されていてもよい。 As described above, the semiconductor device 100 of the present invention is electrically connected to the light receiving portion (not shown in FIGS. 1A and 1C) as shown in FIGS. 1A and 1C. It is characterized in that it includes electrodes 108 that are not connected and at least two of which are electrically connected to each other via a wiring 130 (hereinafter, referred to as “test electrodes” as appropriate) 108.
As shown in FIG. 1C, the test electrode 108 is connected to an external terminal (FIG. 1) through a through-wiring 113 that penetrates from the light receiving portion forming surface of the semiconductor substrate 120 to the surface opposite to the light receiving portion forming surface. (C) (not shown) is electrically connected. The through wiring 113 is formed simultaneously with the through wiring 111 that electrically connects the electrode 106 connected to the light receiving unit 105 and the external terminal 104 shown in FIG. Therefore, by inspecting the continuity of the through wiring 113 shown in FIG. 1C, it can be considered that the continuity of the through wiring 111 shown in FIG. 1B is inspected.
These through wires 111 and 113 are connected to external terminals (not shown) provided on the back surface of the semiconductor substrate 120 and are exposed on the back surface of the semiconductor substrate 120 even after the protection member 101 is provided. ing. That is, the continuity of the through wiring can be inspected in the state of the final product after being separated from the semiconductor wafer.
As long as at least two test electrodes 108 are provided in one semiconductor device, a total of four test electrodes 108 may be formed at two corners as shown in FIG.

〔第２の実施形態〕
本発明の第２の実施形態における半導体装置２００は、図２のように、配線２３０、及び電極２０８が、電極２０８側から見たときに、４つの角部近傍領域２５０に位置する構造を有していることが好ましい。すなわち、テスト用電極２０８を８つ備える構造となる。
このように、配線２３０や配線２０８が４つの角部近傍領域２５０に位置すると、仮に貫通配線（不図示）の導通不良が発生していたとしても、半導体装置２５０の導通不良が発生している位置を容易に見極めることができる。 [Second Embodiment]
As shown in FIG. 2, the semiconductor device 200 according to the second embodiment of the present invention has a structure in which the wiring 230 and the electrode 208 are positioned in the four corner vicinity regions 250 when viewed from the electrode 208 side. It is preferable. That is, the structure has eight test electrodes 208.
As described above, when the wiring 230 and the wiring 208 are positioned in the four corner vicinity regions 250, even if the conduction failure of the through wiring (not shown) occurs, the conduction failure of the semiconductor device 250 occurs. The position can be easily determined.

なお、本発明の半導体装置は、カメラモジュール、指紋センサ、照度センサ、紫外線センサに用いることができるが、特にカメラモジュールとして用いることが有用である。   Note that the semiconductor device of the present invention can be used for a camera module, a fingerprint sensor, an illuminance sensor, and an ultraviolet sensor, but is particularly useful as a camera module.

＜半導体装置の製造方法＞
本発明の第１の実施形態における半導体装置の製造方法は、保護部材を設けた後においても貫通配線の導通を検査することが可能な半導体装置を、従来と同様の工程数にて製造することが可能である点が特徴である。
テスト用電極は、受光部と電気的に接続されていないが、受光部と電気的に接続している電極と同じ方法で同時に形成することができる。また、テスト用電極と電気的に接続されている貫通配線も、受光部と電気的に接続されている電極に接続されている貫通配線を形成する工程にて同時に形成することができる。すなわち、貫通配線の導通を検査するための機能を、受光部に接続されている電極、及び貫通配線のそれぞれを形成する工程にて同時に形成することができる。従って、工程数が増加することなく、保護部材を形成した後においても貫通配線の導通検査を行うことが可能な半導体装置を製造することができる。
以下に、図１に示す半導体装置１００の製造方法を、図３〜図５の工程断面図及び上面概略図に沿って説明する。なお、図３、４の工程断面図は、図１のＸ−Ｘ’の断面における工程断面図を表す。 <Method for Manufacturing Semiconductor Device>
The method for manufacturing a semiconductor device according to the first embodiment of the present invention is to manufacture a semiconductor device capable of inspecting the continuity of through wiring even after providing a protective member, with the same number of steps as in the prior art. The feature is that it is possible.
The test electrode is not electrically connected to the light receiving part, but can be formed simultaneously by the same method as the electrode electrically connected to the light receiving part. Further, the through wiring electrically connected to the test electrode can be formed simultaneously in the step of forming the through wiring connected to the electrode electrically connected to the light receiving portion. That is, the function for inspecting the continuity of the through wiring can be simultaneously formed in the process of forming each of the electrode connected to the light receiving portion and the through wiring. Therefore, it is possible to manufacture a semiconductor device capable of performing a continuity inspection of the through wiring even after the protective member is formed without increasing the number of steps.
A method for manufacturing the semiconductor device 100 shown in FIG. 1 will be described below with reference to process cross-sectional views and a top schematic view of FIGS. 3 and 4 are cross-sectional views taken along the line XX ′ in FIG.

〔第１の実施形態〕
［第１工程］
まず、図３（Ａ）のように、半導体ウエハ１２０を準備する。この半導体ウエハ１２０は、センサ素子等からなる受光部１０５及び受光部１０５を制御し受光部１０５から出力される電気信号を処理する回路素子（不図示）が形成された受光部形成領域（以下、適宜、「表面」と称する）と、この表面の反対側の面（以下、適宜、「裏面」と称する）とを有する。また、図５のように、半導体ウエハ１２０の表面には、受光部形成領域１４０と、受光部形成領域１４０とを区画する格子状の区画領域１５０と、を有する。図３（Ａ）に示すように、受光部形成領域１４０は、センサ素子（例えばイメージセンサ素子）からなる受光部１０５と、電極１０６が形成された領域である。また、受光部形成領域１４０には、受光部１０５と電気的に接続されている電極１０６の他に、受光部１０５と電気的に接続されていないテスト用電極（不図示）も電極１０５と同様に形成されている。このテスト用電極は、少なくとも２つが配線により電気的に接続されている必要があるため、それぞれの電極を配線により接続する。この配線を形成するには、スパッタおよびホトリソグラフィ技術により、容易に形成することができる。このように配線を形成したテスト用電極は、図１（Ｃ）のような断面構造を有することになる。 [First Embodiment]
[First step]
First, as shown in FIG. 3A, a semiconductor wafer 120 is prepared. The semiconductor wafer 120 includes a light receiving part 105 (not shown) in which a light receiving part 105 made of a sensor element and the like and a circuit element (not shown) for processing an electric signal output from the light receiving part 105 are formed (hereinafter referred to as “light receiving part forming region”). And a surface opposite to the surface (hereinafter referred to as “rear surface” as appropriate). Further, as shown in FIG. 5, the surface of the semiconductor wafer 120 has a light receiving portion forming region 140 and a lattice-shaped partition region 150 that partitions the light receiving portion forming region 140. As shown in FIG. 3A, the light receiving portion forming region 140 is a region where the light receiving portion 105 made of a sensor element (for example, an image sensor element) and the electrode 106 are formed. In addition to the electrode 106 electrically connected to the light receiving portion 105, a test electrode (not shown) that is not electrically connected to the light receiving portion 105 is also provided in the light receiving portion forming region 140 in the same manner as the electrode 105. Is formed. Since at least two of the test electrodes need to be electrically connected by wiring, the respective electrodes are connected by wiring. This wiring can be easily formed by sputtering and photolithography techniques. The test electrode in which the wiring is thus formed has a cross-sectional structure as shown in FIG.

［第２工程］
次に、図３（Ｂ）のように、受光部１０５の位置する領域を避けて接続部１０２を形成する。そして、半導体ウエハ１０２上に接続部１０２を介して、保護部材１０１を接着する。接続部１０２はエポキシ樹脂等の接着樹脂からなり、半導体ウエハ１２０の全面に形成した後、フォトリソ等によりパターニングして受光部形成領域１４０を形成してもよく、印刷等によりパターニングしてもよい。なお、センサの種類（例えばＵＶセンサなど）によっては、受光部全面に形成したままでも良い。
また、接続部１０２は前記接着樹脂以外にも、接着フィルムにて形成してもよい。
一方、半導体ウエハ１２０に接着樹脂又はフィルムを形成する方法の他に、保護部材１０１の半導体ウエハ１２０と対向する面に、前述と同様にして樹脂や接着フィルムからなる接続部１０２を形成した後に、半導体ウエハ１２０に接着する方法も挙げられる。
これらの保護部材形成方法の中で、保護部材を貼り合わせる際の位置合わせ精度等の観点から、半導体ウエハ１２０に樹脂やフィルムを形成した後に、保護部材１０１を載置、接着する方法が好ましい。
このようにして保護部材１０１を形成することにより、受光部１０５、及び電極１０６は封止されることになる。 [Second step]
Next, as shown in FIG. 3B, the connection portion 102 is formed avoiding the region where the light receiving portion 105 is located. Then, the protective member 101 is bonded onto the semiconductor wafer 102 via the connection portion 102. The connection portion 102 is made of an adhesive resin such as an epoxy resin, and may be formed on the entire surface of the semiconductor wafer 120 and then patterned by photolithography or the like to form the light receiving portion formation region 140 or may be patterned by printing or the like. Depending on the type of sensor (for example, a UV sensor), it may be formed on the entire surface of the light receiving unit.
Further, the connecting portion 102 may be formed of an adhesive film other than the adhesive resin.
On the other hand, in addition to the method of forming the adhesive resin or film on the semiconductor wafer 120, after forming the connection portion 102 made of resin or adhesive film on the surface of the protective member 101 facing the semiconductor wafer 120 in the same manner as described above, A method of adhering to the semiconductor wafer 120 is also mentioned.
Among these protective member forming methods, the method of placing and bonding the protective member 101 after forming a resin or film on the semiconductor wafer 120 is preferable from the viewpoint of alignment accuracy when the protective member is bonded.
By forming the protective member 101 in this way, the light receiving portion 105 and the electrode 106 are sealed.

［第３工程］
そして、図３（Ｃ）のように、半導体ウエハ１２０の裏面を所定の厚さに削り、半導体ウエハ１２０を薄型化する。その後、図３（Ｄ）のように、半導体ウエハ１２０の表面側に形成された電極１０６の、半導体ウエハ１２０側の面が露出するように、ドライエッチング、ウエットエッチング、又はレーザーなどの加工方法により半導体ウエハ１２０を加工し、貫通孔１６０を形成する。その後、貫通孔１６０の側壁及び半導体ウエハ１２０の裏面上に図示しない保護膜を形成する。続いて、図３（Ｅ）のように、電極１０６の裏面から貫通孔１６０の側壁及び半導体ウエハ１２０の裏面上に延在する貫通配線１１１をスパッタ、又はメッキなどで形成する。電極１０６は、半導体ウエハ１２０の表面側に形成された図示しない配線によって、回路素子（不図示）もしくは受光部１０５に電気的に接続されているので、この時点で、貫通配線１１１は、回路素子（不図示）もしくは受光部１０５に電気的に接続される。
そして、図４（Ｆ）のように、半導体ウエハ１２０の貫通配線１１１形成面側にソルダーレジスト等の保護膜１１２を形成する。その後、貫通配線１１１の所定領域上に位置する保護膜１１２に図示しない開口部を形成する。次に、図４（Ｇ）のように、保護膜１１２に形成された図示しない開口部に配線１１１と電気的に接続するように外部端子１０４を設ける。 [Third step]
Then, as shown in FIG. 3C, the back surface of the semiconductor wafer 120 is cut to a predetermined thickness, so that the semiconductor wafer 120 is thinned. Thereafter, as shown in FIG. 3D, the electrode 106 formed on the front surface side of the semiconductor wafer 120 is exposed by a processing method such as dry etching, wet etching, or laser so that the surface on the semiconductor wafer 120 side is exposed. The semiconductor wafer 120 is processed to form the through hole 160. Thereafter, a protective film (not shown) is formed on the side wall of the through hole 160 and the back surface of the semiconductor wafer 120. Subsequently, as shown in FIG. 3E, the through wiring 111 extending from the back surface of the electrode 106 to the side wall of the through hole 160 and the back surface of the semiconductor wafer 120 is formed by sputtering or plating. Since the electrode 106 is electrically connected to a circuit element (not shown) or the light receiving unit 105 by a wiring (not shown) formed on the surface side of the semiconductor wafer 120, the through wiring 111 is connected to the circuit element at this time. (Not shown) or electrically connected to the light receiving unit 105.
Then, as shown in FIG. 4F, a protective film 112 such as a solder resist is formed on the surface of the semiconductor wafer 120 where the through wiring 111 is formed. Thereafter, an opening (not shown) is formed in the protective film 112 located on a predetermined region of the through wiring 111. Next, as illustrated in FIG. 4G, the external terminal 104 is provided so as to be electrically connected to the wiring 111 in an opening (not illustrated) formed in the protective film 112.

［第４工程］
最後に、図４（Ｈ）のように、図３（Ａ）で示した区画領域１５０に沿うように、保護部材１０１、接続部１０２、及び半導体ウエハ１２０を裁断して、半導体装置１００を製造することができる。 [Fourth step]
Finally, as shown in FIG. 4H, the protection member 101, the connection portion 102, and the semiconductor wafer 120 are cut along the partition region 150 shown in FIG. can do.

〔第２の実施形態〕
第２の実施形態における半導体装置の製造方法は、図２のように、第１工程において、テスト用電極２０８を４つの角部近傍領域に設けること以外は、第１の実施形態における半導体装置の製造方法と同様にして製造することができる。
本発明では、テスト用電極２０８の数が倍になったとしても、テスト用電極２０８を受光部に接続されている電極２０６と同時に形成することができるため、工程数が増加せずにテスト用電極を多数形成することが可能となる。 [Second Embodiment]
As shown in FIG. 2, the method of manufacturing the semiconductor device according to the second embodiment is similar to that of the semiconductor device according to the first embodiment except that the test electrodes 208 are provided in the vicinity of the four corners in the first step. It can be manufactured in the same manner as the manufacturing method.
In the present invention, even if the number of test electrodes 208 is doubled, the test electrodes 208 can be formed at the same time as the electrodes 206 connected to the light receiving portion, so that the number of steps does not increase and the number of steps is increased. A large number of electrodes can be formed.

＜半導体装置の検査方法＞ <Inspection method of semiconductor device>

〔第１の実施形態〕
本発明の第１の実施形態における半導体装置の検査方法は、前述の第１、及び第２の実施形態における半導体装置を検査する方法に関するものである。すなわち、半導体ウエハを裁断して得られた、保護部材が形成された後の最終製品としての半導体装置において、当該半導体装置が有する貫通配線の導通を検査することができる。
具体的には、半導体基板の受光部が形成されている面に、受光部と電気的に接続されていないテスト用電極を少なくとも２つ設け、それらを互いに電気的に接続させる。そして、これらのテスト用電極と電気的に接続した、前記半導体基板の受光部が形成された面と、それとは反対側の面と、を貫通する貫通配線を設ける。この貫通配線は、受光部形成面とは反対側の面に位置する外部電極と接続されているため、保護部材が形成された後であっても、例えばテスター等で導通の良否を検査することができる。 [First Embodiment]
The semiconductor device inspection method according to the first embodiment of the present invention relates to a method for inspecting the semiconductor device according to the first and second embodiments described above. That is, in a semiconductor device as a final product obtained by cutting the semiconductor wafer and after the protective member is formed, the continuity of the through wiring included in the semiconductor device can be inspected.
Specifically, at least two test electrodes that are not electrically connected to the light receiving part are provided on the surface of the semiconductor substrate where the light receiving part is formed, and these are electrically connected to each other. Then, a through-wiring that is electrically connected to these test electrodes and that penetrates the surface on which the light receiving portion of the semiconductor substrate is formed and the surface opposite to the surface is provided. Since this through wiring is connected to the external electrode located on the surface opposite to the light receiving portion forming surface, even after the protective member is formed, for example, a tester or the like is used to check the continuity. Can do.

また、前述の第２の実施形態における半導体装置を用いて貫通配線の導通を検査すると、仮に貫通配線に導通不良が発生した場合、個々の半導体装置のどの方向の貫通配線に不良が発生しているか否かを検査することができる。このとき、個片化前の半導体ウエハにおいて、不良が発生した半導体装置の周辺に位置していた半導体装置にも同様の不良が発生しているものと推測することができるため、検査の迅速化を図ることもできる。   Further, when the continuity of the through wiring is inspected using the semiconductor device in the second embodiment described above, if a continuity failure occurs in the through wiring, a defect occurs in the through wiring in any direction of the individual semiconductor device. Whether it is present or not. At this time, in the semiconductor wafer before singulation, it can be assumed that the same defect has occurred in the semiconductor device located around the semiconductor device in which the defect has occurred. Can also be planned.

〔第２の実施形態〕
本発明の第２の実施形態における半導体装置の検査方法は、保護部材を形成した後、裁断前の半導体ウエハの状態にて貫通配線の導通を検査することができる検査方法である。
具体的には、図６（Ａ）のように、受光部（不図示）が形成された複数の受光部形成領域３４０と、受光部形成領域３４０を区画する格子状の区画領域３５０を備えた半導体装置を準備する。そして、区画領域３５０のいずれかの箇所に、受光部（不図示）とは電気的に接続されていない少なくとも２つのテスト用電極３０８を形成し、それらを配線３３０にて接続する。これらのテスト用電極３０８は、受光部（不図示）と電気的に接続されている電極（不図示）の形成と同時に形成することができる。そして、半導体ウエハ３２０に、区画領域３５０に位置する接続部３０２を介して、半導体ウエハ３２０の全面を覆うように、光透過性の保護部材３０１を設ける。
その後、電極３０８と電気的に接続された貫通配線３１３を、電極３０８が形成された面とそれとは反対側の面とを貫通するように形成する。そして、電極３０８が形成された面とは反対側の面における貫通配線３１３の端部が露出するように保護膜３１２を形成する。 [Second Embodiment]
The semiconductor device inspection method according to the second embodiment of the present invention is an inspection method capable of inspecting the continuity of the through wiring in the state of the semiconductor wafer before cutting after forming the protective member.
Specifically, as shown in FIG. 6A, a plurality of light receiving portion forming regions 340 in which light receiving portions (not shown) are formed and a grid-like partition region 350 that partitions the light receiving portion forming region 340 are provided. A semiconductor device is prepared. Then, at least two test electrodes 308 that are not electrically connected to a light receiving portion (not shown) are formed in any part of the partition region 350, and these are connected by a wiring 330. These test electrodes 308 can be formed simultaneously with the formation of an electrode (not shown) electrically connected to a light receiving portion (not shown). Then, a light-transmissive protective member 301 is provided on the semiconductor wafer 320 so as to cover the entire surface of the semiconductor wafer 320 via the connection portion 302 located in the partition region 350.
After that, the through wiring 313 electrically connected to the electrode 308 is formed so as to penetrate the surface on which the electrode 308 is formed and the surface on the opposite side. Then, the protective film 312 is formed so that the end of the through wiring 313 on the surface opposite to the surface on which the electrode 308 is formed is exposed.

このようにして形成された貫通配線３１３の露出した前記端部は、外部端子３０４として機能させることにより、テスター等により貫通配線３１３の導通を検査することができる。すなわち、保護部材３０１を設けた後における半導体ウエハの状態にて貫通配線の導通を検査することができる。
貫通配線３１３は、受光部（不図示）に接続された貫通配線（不図示）と同時に形成するため、貫通配線３１３の導通を検査することにより、前記受光部（不図示）に接続された貫通配線の導通を検査したものとみなすことができる。また、後述するように、導通検査を終了した後に半導体ウエハ３２０を裁断するため、導通検査で不良が発生した半導体装置については、瞬時に選別、廃棄することもできる。 The exposed end portion of the through wiring 313 formed as described above can function as the external terminal 304, whereby the continuity of the through wiring 313 can be inspected by a tester or the like. That is, the continuity of the through wiring can be inspected in the state of the semiconductor wafer after the protection member 301 is provided.
Since the through wiring 313 is formed at the same time as the through wiring (not shown) connected to the light receiving portion (not shown), the through wiring connected to the light receiving portion (not shown) is checked by checking the conduction of the through wiring 313. It can be considered that the continuity of the wiring is inspected. Further, as will be described later, since the semiconductor wafer 320 is cut after the continuity test is completed, a semiconductor device in which a defect has occurred in the continuity test can be immediately selected and discarded.

そして、検査終了後、区画領域３４０に沿うようにダイシングソーにて裁断する。このようにして得られた半導体装置は、テスト用電極３０８、及び配線３３０が受光部形成領域３４０に存在しない、従来と同様の構成である。すなわち、半導体ウエハを裁断する工程で、テスト用電極３０８、及び配線３３０はともにダイシングと同時に除去されるため、最終製品中にこれらが残存することはない。   And after completion | finish of an inspection, it cuts with a dicing saw so that the division area | region 340 may be met. The semiconductor device thus obtained has a configuration similar to that of the prior art in which the test electrode 308 and the wiring 330 are not present in the light receiving portion formation region 340. That is, in the process of cutting the semiconductor wafer, both the test electrode 308 and the wiring 330 are removed at the same time as the dicing, so that they do not remain in the final product.

第２の実施形態における好ましい態様は、図６（Ｂ）のように、受光部形成領域３４０を区画する区画領域３５０が交差する交差点近傍領域に、テスト用電極３０８、及びテスト用電極３０８と接続する配線３３０を設けることが特徴である。
この領域は、４つの受光部形成領域３４０に囲まれているため、このテスト用電極と接続されている貫通配線の導通検査を行うことにより、４つの受光部形成領域３４０に形成された貫通配線を同時に検査したものとすることができる点で好ましい。 In a preferred mode of the second embodiment, as shown in FIG. 6B, the test electrode 308 and the test electrode 308 are connected to the vicinity of the intersection where the partition region 350 that partitions the light receiving portion formation region 340 intersects. A feature is that the wiring 330 is provided.
Since this region is surrounded by the four light receiving portion forming regions 340, through wirings formed in the four light receiving portion forming regions 340 are inspected by conducting a continuity test on the through wires connected to the test electrodes. Are preferable in that they can be simultaneously inspected.

第２の実施形態におけるより好ましい態様は、図６（Ａ）のように、半導体ウエハ３２０の中心を通過する２つの直行する線３６０、３７０と、半導体ウエハ３２０の外周縁部との接点近傍領域３８０、及び半導体ウエハの中心近傍領域３９０に少なくとも２つのテスト用電極３０８を設けることが特徴である。
図６（Ａ）では、テスト用電極３０８の形成位置である接点近傍領域３８０、及び中心近傍領域３９０が、図６（Ｂ）のように、４つの受光部形成領域３８０に囲まれた、区画領域３５０の交差点近傍領域であることを示している。このような位置にあると、５箇所の前記交差点近傍領域を構成する２０箇所の受光部形成領域３４０における貫通配線３１３を検査したものとみなすことができる。更には、半導体ウエハ３２０のどの位置に貫通配線の導通不良が発生しているかを認識することができるため、半導体ウエハ３２０の不良が発生する傾向を見極めることができる。 A more preferable aspect in the second embodiment is a region in the vicinity of the contact between two perpendicular lines 360 and 370 passing through the center of the semiconductor wafer 320 and the outer peripheral edge of the semiconductor wafer 320 as shown in FIG. 380 and at least two test electrodes 308 are provided in the central region 390 of the semiconductor wafer.
In FIG. 6A, the contact vicinity region 380 and the center vicinity region 390, which are the formation positions of the test electrodes 308, are surrounded by four light receiving portion formation regions 380 as shown in FIG. 6B. This indicates that the region 350 is near the intersection. If it exists in such a position, it can be considered that the penetration wiring 313 in the 20 light-receiving part formation area | regions 340 which comprise the said 5 intersection vicinity area | region was test | inspected. Furthermore, since it is possible to recognize at which position of the semiconductor wafer 320 the conduction failure of the through wiring has occurred, the tendency of the semiconductor wafer 320 to be defective can be determined.

また、特に好ましい態様としては、区画領域３５０のすべての交差点近傍領域にテスト用電極３０８を形成することが挙げられる。
この態様では、貫通配線の不良が発生した場合に、半導体ウエハ３２０中の不良が発生する傾向を精度よく見極めることができるため、その後に製造する半導体ウエハの不良を即時に解消することができる。すなわち、半導体装置の歩留まりを向上させることができる。
なお、この態様では、テスト用電極３０８を区画領域３５０の前記交差点近傍領域の数の２倍形成する必要があるため、製造時間の増加が懸念される。しかしながら、前述のように、テスト用電極３０８は、受光部に接続されている電極と同時に形成するため、電極３０８を接続する配線３３０を設けること以外、従来と同じ工程数にて製造することができるため、製造時間が大幅に増加することはない。 Moreover, as a particularly preferable aspect, it is possible to form the test electrodes 308 in all the intersection vicinity regions of the partition region 350.
In this aspect, when a defect of the through wiring occurs, the tendency of the defect in the semiconductor wafer 320 to be generated can be accurately determined, so that the defect of the semiconductor wafer to be manufactured thereafter can be resolved immediately. That is, the yield of semiconductor devices can be improved.
In this embodiment, since it is necessary to form the test electrodes 308 twice as many as the number of regions in the vicinity of the intersection of the partition region 350, there is a concern about an increase in manufacturing time. However, as described above, since the test electrode 308 is formed at the same time as the electrode connected to the light receiving portion, the test electrode 308 can be manufactured by the same number of steps as in the prior art except that the wiring 330 for connecting the electrode 308 is provided. As a result, manufacturing time does not increase significantly.

（Ａ）は、本発明における半導体装置の上面透視図であり、（Ｂ）は（Ａ）中のＸ−Ｘ’断面図であり、（Ｃ）は（Ａ）中のＹ−Ｙ’断面図であり。(A) is a top perspective view of the semiconductor device in the present invention, (B) is a cross-sectional view taken along line XX ′ in (A), and (C) is a cross-sectional view taken along line YY ′ in (A). It is. 本発明の第２の実施形態における半導体装置の上面透視図である。FIG. 5 is a top perspective view of a semiconductor device according to a second embodiment of the present invention. 本発明の第１の実施形態における半導体装置の、（Ａ）受光部及び電極を形成する工程から、（Ｅ）貫通配線を形成する工程までの工程断面図である。It is process sectional drawing of the semiconductor device in the 1st Embodiment of this invention from the process of (A) forming a light-receiving part and an electrode to the process of forming (E) penetration wiring. 本発明の第１の実施形態における半導体装置の、（Ｆ）保護膜を形成する工程から、（Ｈ）半導体ウエハを裁断する工程までの工程断面図である。It is process sectional drawing from the process of forming the (F) protective film of the semiconductor device in the 1st Embodiment of this invention to the process of cutting the (H) semiconductor wafer. 本発明の第１の実施形態における半導体装置の、図３（Ａ）の上面概略図である。FIG. 4 is a schematic top view of the semiconductor device in the first embodiment of the present invention shown in FIG. （Ａ）は、本発明の第２の実施形態における半導体装置の検査方法における、半導体ウエハの上面透視図であり、（Ｂ）は、区画領域の交差点近傍領域の部分拡大透視図であり、（Ｃ）は（Ｂ）中のＸ−Ｘ’断面図である。(A) is a top perspective view of a semiconductor wafer in a method for inspecting a semiconductor device according to a second embodiment of the present invention, and (B) is a partially enlarged perspective view of a region near an intersection of a partition region, C) is a sectional view taken along line XX ′ in FIG.

符号の説明Explanation of symbols

１００、２００ 半導体装置
１０１、３０１ 保護部材
１０２、３０２ 接続部
１０４、３０４ 外部端子
１０６、２０６ 電極
１０８、２０８、３０８ 電極（テスト用電極）
１１２、３１２ 保護膜
１１１、１１３、３１３ 貫通配線
１２０、３２０ 半導体基板（半導体ウエハ）
１３０、２３０、３３０ 配線
１４０、３４０ 受光部形成領域（表面）
１５０、３５０ 区画領域
１６０ 貫通孔
２５０ 角部近傍領域
３６０、３７０ 半導体ウエハの中心を通過する２つの直行する線
３８０ 半導体ウエハの中心を通過する２つの直行する線と半導体ウエハの外周縁部との接点近傍領域
３９０ 半導体ウエハの中心近傍領域 100, 200 Semiconductor device 101, 301 Protective member 102, 302 Connection portion 104, 304 External terminal 106, 206 Electrode 108, 208, 308 Electrode (Test electrode)
112, 312 Protective film 111, 113, 313 Through wiring 120, 320 Semiconductor substrate (semiconductor wafer)
130, 230, 330 Wiring 140, 340 Light-receiving portion formation region (surface)
150, 350 Partition region 160 Through hole 250 Near corner region 360, 370 Two perpendicular lines 380 passing through the center of the semiconductor wafer and two perpendicular lines passing through the center of the semiconductor wafer between the outer peripheral edge of the semiconductor wafer Near-contact region 390 Near-center region of semiconductor wafer

Claims (7)

受光部が形成された複数の受光部形成領域と、該受光部形成領域を区画する格子状の区画領域と、を有する半導体ウエハの該受光部形成領域に、該受光部と電気的に接続された受光部接続電極、及び該受光部と電気的に接続されてなく、少なくとも２つが互いに電気的に接続されたテスト用電極を同時に形成する第１工程と、
光透過性の保護部材を、前記受光部が封止されるように接続部を介して設ける第２工程と、
前記受光部接続電極及び前記テスト用電極が露出するように、前記半導体ウエハに前記受光部形成領域を有する面と前記受光部形成領域とは反対側の面を貫通する貫通孔を設け、該貫通孔に前記受光部接続電極と電気的に接続する受光部接続貫通配線及び前記テスト用電極と電気的に接続するテスト用貫通配線を同時に形成する第３工程と、
前記区画領域に沿うように、前記半導体ウエハ及び前記光透過性の保護部材を裁断する第４工程と、
をこの順に有することを特徴とする半導体装置の製造方法。 The light receiving portion is electrically connected to the light receiving portion forming region of the semiconductor wafer having a plurality of light receiving portion forming regions in which the light receiving portions are formed and a lattice-shaped partition region that partitions the light receiving portion forming region. A first step of simultaneously forming a light receiving part connection electrode and a test electrode that is not electrically connected to the light receiving part and at least two of which are electrically connected to each other;
A second step of providing a light-transmitting protective member via a connecting portion so that the light receiving portion is sealed;
The semiconductor wafer is provided with a through-hole penetrating the surface having the light receiving portion forming region and the surface opposite to the light receiving portion forming region so that the light receiving portion connecting electrode and the test electrode are exposed. a third step of forming the light receiving portion connecting electrode and electrically tested for through wiring electrically connected to the light receiving unit connected through wiring and the test electrode is connected to the hole at the same time,
A fourth step of cutting the semiconductor wafer and the light-transmissive protective member along the partition region;
In this order, a method for manufacturing a semiconductor device. 前記第１工程は、前記テスト用電極を、前記受光部接続電極よりも前記受光部形成領域の角部に近い領域に形成することを特徴とする請求項１に記載の半導体装置の製造方法。 The first step is a method of manufacturing a semiconductor device according to claim 1, characterized in that to form the test electrode, that is closer to the area in the corner portion of the light receiving part forming region than the light-receiving portion connecting electrode . 前記第３工程の後であって且つ前記第４工程の前、又は前記第４工程の後に、前記テスト用貫通配線が電気的に導通しているか否かを検査する検査工程を有することを特徴とする請求項１又は２に記載の半導体装置の製造方法。 It has an inspection process for inspecting whether or not the test through wiring is electrically conducted after the third process and before the fourth process or after the fourth process. A method for manufacturing a semiconductor device according to claim 1 or 2 . 受光部が形成された複数の受光部形成領域と、該受光部形成領域を区画する格子状の区画領域と、を有する半導体ウエハの該受光部形成領域に、該受光部と電気的に接続された受光部接続電極を形成すると同時に、前記区画領域に、前記受光部と電気的に接続されてなく、少なくとも２つが互いに電気的に接続されたテスト用電極を形成する第１工程と、
前記受光部が封止されるように、接続部を介して光透過性の保護部材を設ける第２工程と、
前記受光部接続電極及び前記テスト用電極が露出するように、前記半導体ウエハに前記区画領域を有する面と前記区画領域の反対側の面とを貫通する貫通孔を設け、該貫通孔に前記受光部接続電極と電気的に接続する受光部接続貫通配線及び前記テスト用電極と電気的に接続されたテスト用貫通配線を同時に形成する第３工程と、
前記テスト用貫通配線が電気的に導通しているか否かを検査する検査工程と、
前記区画領域に沿うように、前記半導体ウエハ及び前記光透過性の保護部材を裁断する第４工程と、
をこの順に有することを特徴とする半導体装置の製造方法。 A plurality of light receiving portions forms a region where the light receiving portion is formed, a lattice shape of divided areas defining the light receiving portion forming region, the light receiving portion formation region of a semiconductor wafer to have a, electrically photodetection unit A first step of forming a test electrode in which at least two of them are electrically connected to each other in the partition region, at the same time as forming the connected light receiving unit connection electrode ;
Wherein such light receiving portion is sealed, a second step of Ru formed light transparent protective member through the connecting portion,
The semiconductor wafer is provided with a through hole penetrating the surface having the partition region and the surface opposite to the partition region so that the light receiving portion connection electrode and the test electrode are exposed. A third step of simultaneously forming a light receiving part connection through-wiring electrically connected to the part connection electrode and a test through-wiring electrically connected to the test electrode ;
An inspection step of the test through wiring checks if electrically conductive,
A fourth step of cutting the semiconductor wafer and the light-transmissive protective member along the partition region;
In this order, a method for manufacturing a semiconductor device. 前記第１工程は、前記テスト用電極を、前記区画領域であって且つ４つの受光部形成領域に囲まれた領域に設けることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4 , wherein in the first step, the test electrode is provided in a region that is the partition region and is surrounded by four light receiving portion formation regions . 前記第１工程は、前記テスト用電極を、前記半導体ウエハの中心を通過する２本の直行する区画領域であって且つ４つの受光部形成領域に囲まれた領域のうち、前記半導体ウエハの外周縁部に最も近い領域、及び半導体ウエハの中心の領域に設けることを特徴とする請求項５に記載の半導体装置の製造方法。 The first step, the test electrode, among the region surrounded by the a segmented region and four light receiving part forming region of the two orthogonal to passing through the center of the semiconductor wafer, outside of the semiconductor wafer 6. The method of manufacturing a semiconductor device according to claim 5 , wherein the semiconductor device is provided in a region closest to the peripheral portion and a central region of the semiconductor wafer. 前記第１工程は、前記テスト用電極を、前記区画領域であって且つ４つの受光部形成領域に囲まれたすべての領域に設けることを特徴とする請求項５に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5 , wherein, in the first step, the test electrodes are provided in all the regions that are the partition regions and are surrounded by four light receiving portion formation regions. .
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