JP2015126187A - Semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package which can easily achieve downsizing for the size of an imaging part.SOLUTION: A semiconductor package of the present embodiment comprises: an imaging substrate; an imaging part provided on the imaging substrate; connection wiring which is electrically connected with the imaging part and has a connection terminal provided on the imaging substrate on the side opposite to the imaging part side; a circuit board provided on the imaging substrate on the side opposite to the imaging part side; a circuit part provided on the circuit board on a surface on the imaging substrate side; a circuit electrode which is provided between the imaging substrate and the circuit board and electrically connected with the circuit part and the connection terminal of the connection wiring; and a connection electrode which reaches the circuit electrode from a surface of the circuit board on the side opposite to the imaging substrate side and electrically connected with the circuit electrode. The circuit part, the circuit electrode and the connection electrode are included in an imaging region in planar view where the imaging part is provided.

Description

  The present invention relates to a semiconductor package.

  With increasing demands for downsizing and weight reduction of sensor chips equipped with image sensors and the like, the surface image sensor and the external terminals on the back surface are formed by through electrodes (TSV: Through Silicon Via) penetrating the front and back surfaces. A connected chip size package has been proposed (for example, Patent Document 1).

JP 2010-199422 A

  However, in the chip size package as described above, since the light receiving unit (imaging unit) and the electrode to which the through electrode is connected are formed on the same surface, the through electrode is formed outside the light receiving unit. . As a result, the size of the chip size package becomes larger than the size of the light receiving portion, and it is difficult to reduce the size of the chip size package with respect to the size of the light receiving portion.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor package that can be easily miniaturized with respect to the size of the imaging unit.

  The semiconductor package of the present invention is electrically connected to the imaging substrate, the imaging unit provided on the imaging substrate, and the imaging unit, and the connection terminal is provided on the side opposite to the imaging unit side of the imaging substrate. A connection wiring; a circuit board provided on a side opposite to the imaging part side of the imaging board; a circuit part provided on a surface of the circuit board on the imaging board side; the imaging board and the circuit board; A circuit electrode electrically connected to the circuit unit and the connection terminal of the connection wiring; and the circuit electrode from the surface opposite to the imaging substrate side of the circuit board. A connection electrode electrically connected to the circuit electrode, and the circuit unit, the circuit electrode, and the connection electrode are included in an imaging region in which the imaging unit is provided in a plan view. Features.

  According to the semiconductor package of the present invention, the circuit electrode is provided between the imaging substrate and the circuit substrate, and the circuit portion, the circuit electrode, and the connection electrode are included in the imaging region in plan view. As a result, the size of the semiconductor package in plan view can be made substantially the same as the size of the image pickup unit in plan view. Therefore, according to this embodiment, it is easy to reduce the size of the entire semiconductor package in plan view relative to the size of the imaging unit in plan view.

The connection electrode may be provided outside the circuit unit.
According to this configuration, since the connection electrode is provided outside the circuit portion, it is not necessary to provide a location where the connection electrode is formed inside the circuit portion, and the circuit portion can be easily formed.

A plurality of the connection electrodes are provided, and each of the connection electrodes is electrically connected to the connection electrodes, and further includes a plurality of external terminals provided on a surface opposite to the imaging substrate side of the circuit board. At least one of them may be provided on the outer edge side of the circuit board from the external terminal.
According to this configuration, it is easy to form the connection electrode outside the circuit unit.

A plurality of the connection electrodes are provided, and each of the connection electrodes is electrically connected to the plurality of connection electrodes, and further includes a plurality of external terminals provided on a surface opposite to the imaging substrate side of the circuit board. At least one of them may be provided on the outer edge side of the circuit board from the connection electrode.
According to this configuration, since the external terminal is provided on the outer edge side of the circuit board, it can be stably mounted when mounting the semiconductor package via the external terminal.

It is good also as a structure further provided with the sealing part provided surrounding the said imaging part.
According to this configuration, it is possible to reduce the influence of disturbance on the imaging unit.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor package which is easy to reduce in size with respect to the magnitude | size of an imaging part is provided.

It is a figure which shows the semiconductor package of this embodiment, Comprising: (A) is a top view, (B) is a bottom view. It is a figure which shows the semiconductor package of this embodiment, Comprising: It is II-II sectional drawing in FIG. It is sectional drawing which shows the procedure of the manufacturing method of the semiconductor package of this embodiment. It is sectional drawing which shows the procedure of the manufacturing method of the semiconductor package of this embodiment. It is a bottom view which shows an example of the other structure of the semiconductor package of this embodiment.

Hereinafter, a semiconductor package according to an embodiment of the present invention will be described with reference to the drawings.
The scope of the present invention is not limited to the following embodiment, and can be arbitrarily changed within the scope of the technical idea of the present invention. Moreover, in the following drawings, in order to make each structure easy to understand, the actual structure may be different from the scale, number, or the like in each structure.

(Semiconductor package)
1A, 1B, and 2 are views showing a semiconductor package 10 of the present embodiment. FIG. 1A is a plan view. FIG. 1B is a bottom view. 2 is a cross-sectional view taken along the line II-II in FIG.

  In the following description, an XYZ coordinate system is set, and the positional relationship of each member will be described with reference to this XYZ coordinate system. At this time, the stacking direction of the sensor unit 20 and the signal processing unit 40 (see FIG. 2) is orthogonal to the Z-axis direction and the Z-axis direction, and is parallel to one side of the outer periphery of the semiconductor package 10 in plan view (see FIG. 1). The direction (length direction in FIG. 1) is the X-axis direction, and the direction (width direction in FIG. 1) perpendicular to both the Z-axis direction and the X-axis direction is the Y-axis direction.

The semiconductor package 10 of the present embodiment is a chip package on which a backside illumination (BSI: Back Side Illumination) CMOS (Complementary Metal-Oxide Semiconductor) sensor is mounted.
As shown in FIG. 2, the semiconductor package 10 includes a sensor unit 20, a protective substrate 30, a signal processing unit 40, a wiring layer 43, and an external connection electrode unit 50.

  The sensor unit 20 detects light incident on the sensor unit 20 via the protective substrate 30. The sensor unit 20 includes an imaging substrate 21, an imaging unit 26, connection wiring 24, and a sealing unit 25.

The imaging substrate 21 is a substrate in which the imaging unit 26 is provided on the protective substrate 30 side (+ Z side). The imaging substrate 21 is made of a semiconductor material such as silicon.
The imaging unit 26 includes a photodiode 22 and a color filter 23. In the present embodiment, the imaging unit 26 is embedded in the imaging substrate 21 so that the surface of the color filter 23 is flush with the surface 21 a of the imaging substrate 21. That is, in the thickness direction (Z-axis direction) of the imaging substrate 21, the positions of the surface 21 a of the imaging substrate 21 and the surface of the color filter 23 are the same. The positions of the surface 21a of the imaging substrate 21 and the surface of the color filter 23 in the thickness direction (Z-axis direction) of the imaging substrate 21 may be different.

  In the present embodiment, as shown in FIGS. 1A and 2, an area where the imaging unit 26 is provided in a plan view (XY plane view) is an imaging area IA.

The photodiode 22 functions as a photodetector. When the photodiode 22 is irradiated with light, the photodiode 22 generates a current or a voltage corresponding to the intensity of the irradiated light.
The color filter 23 is provided on the protective substrate 30 side (+ Z side) of the photodiode 22. The color filter 23 is a filter that selectively transmits light of a specific wavelength. In the present embodiment, the color filter 23 selectively transmits a light having a red wavelength, a filter that selectively transmits a light having a blue wavelength, and a light having a green wavelength. Including filters.

  A connection wiring 24 connected to the photodiode 22 is provided on the wiring layer 43 side (−Z side) of the photodiode 22 of the imaging unit 26. The connection terminal 24 a of the connection wiring 24 is provided on the back surface 21 b of the imaging substrate 21 on the wiring layer 43 side.

  The sealing portion 25 is a frame-like member that is embedded in the outer edge of the imaging substrate 21. The sealing unit 25 is provided so as to surround the imaging unit 26. The sealing unit 25 has a property of blocking light, for example, and suppresses light from entering the photodiode 22 from the side surface. A material for forming the sealing portion 25 is, for example, aluminum.

As shown in FIG. 2, the protective substrate 30 is a transparent substrate attached to the surface 21 a of the imaging substrate 21 via an adhesive 31. The material of the protective substrate 30 is not particularly limited within the range having translucency, and for example, a glass plate or the like can be used.
The adhesive 31 that bonds the protective substrate 30 and the imaging substrate 21 is not particularly limited as long as it has translucency, and is, for example, a transparent resin.

  The signal processing unit 40 processes information detected by the sensor unit 20. The signal processing unit 40 includes a circuit board 41 and a logic circuit unit (circuit unit) 42.

  The circuit board 41 is a board provided on the back surface 21 b side of the imaging board 21 with the wiring layer 43 interposed therebetween. The circuit board 41 is formed of a semiconductor material such as silicon, like the imaging substrate 21. The circuit board 41 is formed with a through hole 50a described later.

  A logic circuit portion 42 is formed on the front surface 41 a (surface on the wiring layer 43 side) of the circuit board 41. The logic circuit unit 42 processes an electrical signal transmitted from the sensor unit 20, more specifically, the imaging unit 26.

  The wiring layer 43 is provided between the imaging substrate 21 and the circuit substrate 41. The wiring layer 43 includes an insulating portion 44, an imaging portion electrode (circuit electrode) 45, a stud bump 46, and an I / O (Input / Output) pad (circuit electrode) 47. That is, the imaging unit electrode 45 and the I / O pad 47 are provided between the imaging substrate 21 and the circuit board 41.

  The insulating part 44 is formed in a layer between the imaging substrate 21 and the circuit substrate 41. The insulating part 44 has electrical insulation. The material for forming the insulating portion 44 is not particularly limited as long as it has electrical insulation, and is, for example, BPSG (Bron Phosphorate Silicate Glass). An imaging unit electrode 45, a stud bump 46, and an I / O pad 47 are provided in the insulating unit 44.

  The imaging unit electrode 45 is an electrode for electrically connecting the imaging unit 26 (photodiode 22) and the logic circuit unit 42. The imaging unit electrode 45 is electrically connected to the logic circuit unit 42 through a wiring (not shown). An insulating portion is provided in a range excluding a predetermined connection portion, for example, a stud bump 46, between the imaging portion electrode 45 and the imaging substrate 21 and between the imaging portion electrode 45 and the circuit board 41. 44 is provided.

  A stud bump 46 is provided on the imaging substrate 21 side (+ Z side) of the imaging unit electrode 45. The stud bump 46 is electrically connected to the imaging unit electrode 45 and is provided at a position facing the connection terminal 24a so as to be exposed from the surface of the insulating unit 44 on the imaging substrate 21 side (+ Z side). The end of the stud bump 46 on the imaging substrate 21 side (+ Z side) is electrically connected to the connection terminal 24 a of the connection wiring 24 that is electrically connected to the imaging unit 26. That is, the imaging unit 26 and the logic circuit unit 42 are electrically connected by the connection wiring 24, the stud bump 46, and the imaging unit electrode 45.

  The I / O pad 47 is an electrode that is electrically connected to the logic circuit unit 42 by a wiring (not shown). In this embodiment, the I / O pad 47 is provided so as not to overlap the logic circuit unit 42 in a plan view (XY plane view). A through electrode 51 described later is electrically connected to the I / O pad 47. Within a range excluding a predetermined connection portion between the I / O pad 47 and the imaging substrate 21 and between the I / O pad 47 and the circuit substrate 41, for example, a connection portion with a through electrode 51 described later. Is provided with an insulating portion 44.

  In the present embodiment, a plurality of imaging unit electrodes 45 and I / O pads 47 are provided. Further, a plurality of stud bumps 46 are provided according to the number of imaging unit electrodes 45.

The external connection electrode unit 50 includes a through electrode (connection electrode) 51, an extraction electrode 52, and an external terminal 53. A plurality of external connection electrode portions 50 are provided according to the number of I / O pads 47.
As shown in FIGS. 1B and 2, the through electrode 51 is formed on the inner surface of the through hole 50 a formed in the circuit board 41 and a part of the back surface 41 b of the circuit board 41. The through electrode 51 is formed so as to be located outside the logic circuit portion 42. In the present embodiment, as shown in FIG. 1B, the through electrode 51 is formed so as not to overlap the logic circuit portion 42 in plan view (XY plane view).

  As shown in FIG. 2, the through hole 50 a penetrates the circuit board 41 in the thickness direction (Z-axis direction) and penetrates the insulating portion 44 between the circuit board 41 and the I / O pad 47. It is formed to reach the O pad 47. As shown in FIG. 1B, the through hole 50a has a circular shape in plan view (XY plane view). As shown in FIG. 2, the through hole 50 a has a tapered shape in which the inner diameter decreases from the back surface 41 b of the circuit board 41 toward the I / O pad 47.

  The through electrode 51 formed on the inner surface of the through hole 50 a reaches the I / O pad 47 from the back surface 41 b of the circuit board 41 and is electrically connected to the I / O pad 47.

As shown in FIGS. 1B and 2, the extraction electrode 52 is formed on the back surface 41 b of the circuit board 41 and is electrically connected to the through electrode 51. An external terminal 53 is electrically connected to the extraction electrode 52.
The external terminal 53 is a terminal connected to the three-dimensional wiring substrate or the like when the semiconductor package 10 is connected to the three-dimensional wiring substrate or the like, for example. The external terminal 53 is, for example, a metal bump. The external terminal 53 is electrically connected to the logic circuit unit 42 through the extraction electrode 52, the through electrode 51, and the I / O pad 47.

  In the present embodiment, the external terminal 53 is provided so as to be closer to the center side of the circuit board 41 than the through electrode 51 as shown in FIG. In other words, in the present embodiment, the through electrode 51 is provided on the outer edge side of the circuit board 41 with respect to the external terminal 53.

  In the present embodiment, as shown in FIG. 2, the connection wiring 24, the logic circuit unit 42, the imaging unit electrode 45, the stud bump 46, the I / O pad 47, the through electrode 51, the extraction electrode 52, and the external terminal 53 are It is included in the imaging area IA in plan view (XY plane view).

  The device on which the semiconductor package 10 of the present embodiment is mounted is not particularly limited, and is, for example, an endoscope.

(Semiconductor package manufacturing method)
3A to 3C and FIGS. 4A and 4B are cross-sectional views showing the procedure of the method for manufacturing the semiconductor package 10 of the present embodiment.
First, as shown in FIG. 3A, a plurality of imaging units 26, sealing units 25, and connection wirings 24 are formed on the wafer 121 (two in the drawing).
Next, as illustrated in FIG. 3B, a protective substrate 130 is attached to the imaging unit 26 side (+ Z side) of the wafer 121 via an adhesive 31.

Next, as shown in FIG. 3C, the side opposite to the imaging unit 26 side (−Z side) of the wafer 121 is polished to expose the connection terminal 24 a of the connection wiring 24.
Next, as shown in FIG. 4A, a plurality of logic circuit portions 42 are formed on the surface of the wafer 141. Then, wiring layers 43 are formed on the surface of the wafer 141 so as to correspond to the plurality of logic circuit portions 42, respectively.

  Next, the wafer 121 and the wiring layer 43 are bonded so that the stud bumps 46 of the wiring layer 43 and the connection terminals 24 a of the connection wiring 24 are electrically connected. As a bonding method of the wafer 121 and the wiring layer 43, for example, a method of bonding using a non-conductive resin (NCP) or a bonding method by low temperature anodic bonding can be selected.

Next, as shown in FIG. 4B, the external connection electrode portion 50 is formed on the wafer 141. The external connection electrode part 50 is formed corresponding to each logic circuit part 42. Thereby, a semiconductor package wafer 110 including a plurality of semiconductor packages is formed.
Next, the semiconductor package wafer 110 is cut by dicing at the position of the dotted line shown in FIG.
Thus, a plurality of semiconductor packages 10 are manufactured.

  According to the present embodiment, the wiring layer 43 is provided between the imaging board 21 and the circuit board 41. The wiring layer 43 includes a through electrode 51 and an I / O pad 47 that is electrically connected. Thus, even when the I / O pad 47 is arranged at a position included in the imaging area IA in plan view (XY plane view), the I / O pad 47 and the through electrode 51 are electrically connected. be able to.

  Therefore, according to this embodiment, as shown in FIGS. 1A, 1B, and 2, the semiconductor package can be configured such that each electrode or the like is included in the imaging region IA. As a result, according to the present embodiment, the size of the entire semiconductor package 10 in plan view and the size of the image pickup unit 26 in plan view can be made the same. On the other hand, it is easy to reduce the size of the entire semiconductor package 10 in plan view.

  For example, in a configuration in which the I / O pad is formed on the side where the imaging unit of the imaging substrate is provided, the smaller the size of the entire semiconductor package, the smaller the area where the I / O pad is formed with respect to the imaging region. The proportion increases. Therefore, it is difficult to reduce the size of the entire semiconductor package in plan view relative to the size of the imaging region in plan view as the semiconductor package is smaller. Therefore, the semiconductor package 10 of the present embodiment is particularly effective when mounted on a device including a small semiconductor package such as an endoscope.

  In addition, according to the present embodiment, since the imaging unit electrode 45 and the I / O pad 47 are both provided in the wiring layer 43, the imaging unit electrode 45 and the I / O pad 47 are collectively formed. It is possible. Thereby, according to this embodiment, it is easy to form the imaging unit electrode 45 and the I / O pad 47.

  Further, according to the present embodiment, since the through electrode 51 is formed outside the logic circuit unit 42, the through electrode 51 is formed in the logic circuit unit 42 when the logic circuit unit 42 is formed. It is not necessary to provide a portion to be provided, and the logic circuit portion 42 can be easily formed.

  Further, according to the present embodiment, the through electrode 51 is formed on the outer edge side of the circuit board 41 with respect to the external terminal 53. Thereby, according to this embodiment, it is easy to form the penetration electrode 51 so that it may become the outer side of the logic circuit part 42. FIG.

  Further, according to the present embodiment, the sealing unit 25 is provided around the imaging unit 26. Thereby, it is suppressed that a disturbance enters into the imaging part 26, and the precision of the sensor part 20 can be improved.

  In the present embodiment, the following configuration may be employed.

  In the embodiment described above, in each of the plurality of external connection electrode portions 50, the through electrode 51 is configured to be on the outer edge side of the circuit board 41 with respect to the external terminal 53. However, the configuration is not limited thereto. . In the present embodiment, for example, in a part of the external connection electrode portion 50, the through electrode 51 may be on the outer edge side of the circuit board 41 with respect to the external terminal 53.

  In the present embodiment, for example, a configuration like the semiconductor package 210 shown in FIG. 5 may be used. FIG. 5 is a bottom view showing a semiconductor package 210 which is an example of another configuration of the present embodiment. As shown in FIG. 5, the semiconductor package 210 is different from the semiconductor package 10 in that an external connection electrode unit 150 is provided.

  The external connection electrode portion 150 is different from the external connection electrode portion 50 of the semiconductor package 10 in that the external terminal 53 is provided on the outer edge side of the circuit board 41 with respect to the through electrode 51. According to such a configuration, since the external terminals 53 to be joined at the time of mounting are provided on the outer edge of the circuit board 41, it is easy to stably mount the semiconductor package.

  5 shows a configuration in which the external terminal 53 is located on the outer edge side of the circuit board 41 with respect to the through electrode 51 in any of the plurality of external connection electrode portions 150, but is not limited thereto. . In the present embodiment, in some of the plurality of external connection electrode portions 150, the external terminal 53 may be on the outer edge side of the circuit board 41 with respect to the through electrode 51.

  In the present embodiment, in a part of the external connection electrode part, the external terminal 53 is located on the outer edge side of the circuit board 41 with respect to the through electrode 51, and in at least a part of the other external connection electrode part, the through electrode 51 is The configuration may be such that it is on the outer edge side of the circuit board 41 with respect to the external terminal 53.

  In the embodiment described above, the imaging unit electrode 45 and the connection wiring 24 are connected via the stud bump 46, but the present invention is not limited to this. In the present embodiment, the method for connecting the imaging unit electrode 45 and the connection wiring 24 is not particularly limited. For example, the imaging unit electrode 45 and the connection wiring 24 may be connected by a plating bump. The electrode 45 may be formed so as to be exposed on the imaging substrate 21 side of the insulating portion 44, and the imaging portion electrode 45 and the connection wiring 24 may be directly connected.

  In the present embodiment, the configuration of the wiring layer 43 is not particularly limited as long as the imaging unit electrode 45 and the I / O pad 47 are provided between the imaging substrate 21 and the circuit board 41. In the present embodiment, for example, as a configuration of the wiring layer 43, an I / O pad 47 is formed on the circuit board 41 side (−Z side) of the insulating portion 44, and the imaging substrate 21 side (+ Z side) of the insulating portion 44. Alternatively, the imaging unit electrode 45 may be formed. In this case, for example, the I / O pad 47 is formed on the surface 41 a of the circuit board 41.

In the embodiment described above, the through electrode 51 is used as an electrode for connecting the external terminal 53 and the I / O pad 47 via the extraction electrode 52. However, the present invention is not limited to this. The electrode that connects the external terminal 53 and the I / O pad 47 is not particularly limited. In the present embodiment, for example, the size of the circuit board in plan view is smaller than the size of the imaging board in plan view, and the external terminals 53 are formed by electrodes formed from the back surface of the circuit board through the side surfaces. And the I / O pad 47 may be connected.
In the present embodiment, for example, the groove in a plan view (XY plane view) is semicircular and is open on the side surface of the circuit board 41 (a surface perpendicular to the back surface 41b of the circuit board 41). An electrode may be formed on the circuit board 41, and an electrode for connecting the external terminal 53 and the I / O pad 47 via the extraction electrode 52 may be formed inside the groove.

  In the present embodiment, the color filter 23 may be provided with a microlens on the protective substrate 30 side (+ Z side).

  In this embodiment, the I / O pad 47 may be provided so as to partially or entirely overlap with the logic circuit unit 42 in plan view (XY plane view).

  In the present embodiment, the sealing portion 25 may not be provided.

  DESCRIPTION OF SYMBOLS 10,210 ... Semiconductor package, 21 ... Imaging board, 24 ... Connection wiring, 24a ... Connection terminal, 25 ... Sealing part, 26 ... Imaging part, 41 ... Circuit board, 42 ... Logic circuit part (circuit part), 45 ... Imaging Part electrode (circuit electrode), 47 ... I / O pad (circuit electrode), 51 ... through electrode (connection electrode), 53 ... external terminal, IA ... imaging area

Claims (5)

An imaging substrate;
An imaging unit provided on the imaging substrate;
A connection wiring that is electrically connected to the imaging unit, and a connection terminal is provided on a side opposite to the imaging unit side of the imaging substrate;
A circuit board provided on the side opposite to the imaging unit side of the imaging board;
A circuit unit provided on a surface of the circuit board on the imaging substrate side;
A circuit electrode provided between the imaging substrate and the circuit board and electrically connected to the circuit portion and the connection terminal of the connection wiring;
A connection electrode that reaches the circuit electrode from the surface opposite to the imaging substrate side of the circuit board and is electrically connected to the circuit electrode;
With
The semiconductor package, wherein the circuit unit, the circuit electrode, and the connection electrode are included in an imaging region in which the imaging unit is provided in a plan view.     The semiconductor package according to claim 1, wherein the connection electrode is provided outside the circuit unit. A plurality of the connection electrodes are provided,
A plurality of external terminals electrically connected to the plurality of connection electrodes, respectively, provided on a surface opposite to the imaging substrate side of the circuit board;
The semiconductor package according to claim 1, wherein at least one of the connection electrodes is provided on an outer edge side of the circuit board with respect to the external terminal. A plurality of the connection electrodes are provided,
A plurality of external terminals electrically connected to the plurality of connection electrodes, respectively, provided on a surface opposite to the imaging substrate side of the circuit board;
4. The semiconductor package according to claim 1, wherein at least one of the external terminals is provided on an outer edge side of the circuit board with respect to the connection electrode. 5.     5. The semiconductor package according to claim 1, further comprising a sealing part provided to surround the imaging part. 6.

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