JP3882521B2 - Mounting method of semiconductor device - Google Patents

Mounting method of semiconductor device Download PDF

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Publication number
JP3882521B2
JP3882521B2 JP2001096869A JP2001096869A JP3882521B2 JP 3882521 B2 JP3882521 B2 JP 3882521B2 JP 2001096869 A JP2001096869 A JP 2001096869A JP 2001096869 A JP2001096869 A JP 2001096869A JP 3882521 B2 JP3882521 B2 JP 3882521B2
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Japan
Prior art keywords
substrate
semiconductor chip
mounting
electrode
side electrode
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Expired - Fee Related
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JP2001096869A
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Japanese (ja)
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JP2002299372A (en
Inventor
敏 中島
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Seiko Epson Corp
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Seiko Epson Corp
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Publication of JP3882521B2 publication Critical patent/JP3882521B2/en
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の実装方法に係り、特に実装時のボンディング荷重を低下させつつ、電機的な接続を確実に行わせるための技術に関する。
【０００２】
【従来の技術】
従来より基板上に半導体チップを実装するための技術が各種知られている。
例えば、実装技術として、ワイヤーボンディング方式やフリップチップボンディング方式などが挙げられる。
ワイヤーボンディング方式によれば、図１３に示すように、基板１００上に半導体チップ１０１を接着剤等で固定し、半導体チップ１０１の電極と基板１００上の電極１０２とを導電ワイヤ１０３などを用いて空中配線接続をしている。
フリップチップボンディング方式によれば、図１４に示すように、半導体チップ２０１上に形成された導電性の電極（あるいは突起電極）２０２と基板上の電極との位置あわせを行い、合金接合や導電性粒子、導電性接着剤２０３などを用いた機械的接触により接続している。
【０００３】
【発明が解決しようとする課題】
ワイヤーボンディング方式においては、図１３に示すように、半導体チップ１０１を基板１００上に搭載し、ワイヤーボンディング後に、機械的強度を持たせるために導電ワイヤを含む半導体チップ１０１をモールド剤１０４を塗布して埋設するように構成していた。この結果、モジュール１０５全体としての厚みが増加してしまうという不具合があった。
また、半導体チップ１０１を高周波回路として用いる場合には、ワイヤ長さが長くなりすぎ、高周波回路特性的に好ましくないという問題点があった。
フリップチップボンディング方式によれば、半導体チップ２０１の電極２０２および基板上の電極は、双方とも平面上に配置されているため、図１５に矢印で示すように、温度変化などに起因して生じる平面方向の材料伸縮を起こし、半導体チップ材料と基板材料との線膨張係数の違いにより電極接合部にせん断応力が働いて、電極接合部に亀裂が生じ、導通不良を起こす可能性があった。
【０００４】
また、多機能化を図るべく半導体チップサイズが大きくなり、さらに電極数が増加すると、半導体チップを基板の電極に実装する際のボンディング加重が大きくなり、半導体チップの能動面に応力が係り、半導体チップの特性を変化させる原因ともなっていた。
また、半導体チップの実装時には、基板に応力がかかるため、先に実装された半導体チップの電極部に亀裂を与えることになっていた。
また、ワイヤーボンディングと同様に基板上に半導体チップを搭載するためモジュールとしての厚みを増加させてしまうという問題点があった。
一方、半導体チップを大容量化、多機能化し、多くの入出力端子を半導体チップから基板上に接続する半導体チップの実装方法おいて、多くの入出力端子を突起電極として半導体チップ上に配置するには、電極の面積を縮小し、配置ピッチを微細化する必要があるため、機械的強度が十分に得られるほど突起電極の接続部の面積を確保することはできず、平面電極を形成しなければならないという問題点があった。
【０００５】
また、微少な電極を形成するために高度な技術レベルが要求されるという問題点があった。さらに微細化、多ピン化されるとともに、サイズが大型化した半導体チップの平面電極を基板上の電極に対し平面方向同士で実装するには、非常に大きなボンディング加重が必要となり、半導体チップあるいは基板に不要な応力を印加することとなってしまうという問題点があった。そこで、本発明の目的は、半導体チップの実装時のボンディング荷重を低減することができる実装方法を提供することにある。
【００１２】
【課題を解決するための手段】
上記課題を解決するため、半導体装置の実装面にほぼ垂直な側面に溝状に形成された側面電極を有する半導体装置を基板上に実装する半導体装置の実装方法において、基板側に前記半導体装置を収容する収容凹部を設け、前記収容凹部内の内層配線パターンと基板表面の表層配線パターンとを前記側面電極に対応する位置に対応づけて導電性ワイヤで接続し、前記基板に垂直に前記半導体装置を前記収容凹部内に所定の圧力で押し込むことにより前記導電性ワイヤと前記側面電極を電気的に接続させる、ことを特徴としている。
【００１３】
【発明の実施の形態】
次に本発明の好適な実施の形態について図面を参照して説明する。
［１］半導体チップの製造
まず、半導体チップの製造工程について説明する。
［１．１］ＬＳＩ形成工程
まず、Ｓｉ製のウェハに通常と同様の工程でＬＳＩを形成する。
ＬＳＩの形成工程は、洗浄工程、拡散工程、薄膜形成工程、パターニング工程を含む。
まず、洗浄工程は、ウェハを清浄な状態とすべく、洗浄を行う。
拡散工程は、ｐｎ接合工程や不純物プロファイル制御のために行われる。
薄膜形成工程は、シリコン窒化膜、多結晶シリコン、表面電極を含むアルミニウム電極等を形成する。
パターニング工程は、露光工程およびエッチング工程を含んでいる。露光工程は、シリコン基板上に塗布されたレジストを露光、現像して所定のレジストパターンを形成する。エッチング工程は、露光工程におけるレジストパターンをマスクとして下地膜をエッチングし、パターンを形成することとなる。
以下、洗浄工程、拡散工程、薄膜形成工程、パターニング工程繰り返して複数のＬＳＩをウェハ上に形成する。
【００１４】
［１．２］穿孔工程
図１にＬＳＩが形成されたウェハの外観斜視図を示す。
次に、複数のＬＳＩ１が形成されたウェハ２において、図２に示すように、ＬＳＩ１の周辺部分に形成された電極（表面電極）３近傍の領域であって各電極に対応する位置であって、仮想的に設けたダイシングラインＤＬに沿って側面電極形成用孔４を穿孔して形成する。
側面電極形成用孔の穿孔後、図３（ａ）に示すように、ＬＳＩおよび側面電極形成用孔の絶縁コーティング５を行う。
【００１５】
［１．３］メッキ工程
次に図３（ｂ）に示すように、表面電極の全部または一部の絶縁コーティングをレーザ加工などにより除去する。
そして、図３（ｃ）に示すように、一般的な電極用のメッキ材料６を用いて表面電極および側面電極形成用孔内にメッキ処理を施し、両者を導通状態とする。
次に表面電極および側面電極形成用孔にポリイミドコーティングなどの所定のコーティング処理を施す。
【００１６】
［１．４］ダイシング工程
次にウェハ２を切り離して半導体チップにすべくダイシングを行う。
この場合において、側面電極形成用孔４の中心点を通る直線（図２にダイシングラインＤＬとして表示）に沿ってウェハ２のダイシングを行い、半導体チップ２０（図４参照）を得る。
これにより、側面電極形成用孔４は、２等分され、側面電極１０となる。
図４に側面電極の外観斜視図を示す。
図４に示すように、側面電極１０は、竹を半分に割ったような形状となっている。
なお、得られる半導体チップ２０の厚さを低減する必要があれば、ダイシング前にウェハ２のＬＳＩ形成面に対向する面（半導体チップの裏面；実装面）２０Ａに機械的研磨あるいは化学的研磨を施すことにより厚さを低減することが可能である。
なお、ハーフダイシング状態であれば、ダイシング後に面２０Ａに機械的研磨あるいは化学的研磨を施すことにより厚さを低減することも可能である。
【００１７】
［２］半導体チップの基板への実装
次に半導体チップの基板への実装について各基板毎に説明する。
［２．１］フレキシブル基板の場合
まず、最初に実装対象の基板がフレキシブル基板の場合について説明する。
図５（ａ）、（ｂ）に示すように、半導体チップ２０の実装先がフレキシブル基板３０である場合には、フレキシブル基板３０の配線パターン３１を半導体チップ２０の側面電極１０に対応する位置に配置したオーバーハングパターンとする。配線パターン３１の材料としては、銅（Ｃｕ）、ニッケル（Ｎｉ）、金（Ａｕ）などが用いられる。
そして、半導体チップ２０を吸着などの方法により支持したツールＴＬにより半導体チップ２０の位置合わせを行いながら、フレキシブル基板３０に垂直な方向（図５（ａ）中、矢印で示す。）から所定の圧力で加圧しながら実装する。
【００１８】
この場合に、半導体チップ２０の側面電極１０と、フレキシブル基板３０の配線パターン（オーバーハングパターン）３１とは図６に示すように接触状態となり、導通することとなる。
また、図７（ａ）に示すように、穿孔時に半導体チップの実装面側の側面電極の形状がテーパー形状となるように側面電極形成用孔４を形成すれば、図７（ｂ）に示すように、側面電極１０の実装面側はテーパー形状となり、図８に示すように、より確実に半導体チップ２０の側面電極１０と、フレキシブル基板３０の配線パターン３１（オーバーハングパターン）と、が電気的に接続状態となる。
このようなテーパー形状の側面電極形成用孔４を形成するためには、ＬＳＩ形成面側から所定の出力のレーザ光で穿孔を行えばよい。
さらに配線パターン（オーバーハングパターン）３１を弾性の高い材料で形成し、半導体チップ２０の実装による配線パターン（オーバーハングパターン）３１の変形に伴う反発力により電気的接続の確実性を向上させることも可能である。
さらにまた、あらかじめ配線パターン（オーバハングパターン）３１に半田メッキを施しておき、側面電極１０と半田付けを行って電気的接続を確保するように構成することも可能である。
【００１９】
［２．２］セラミック基板に貫通スルーホールを形成する場合
次に実装対象の基板がセラミック基板であり、このセラミック基板に貫通スルーホールを形成する場合について図９を参照して説明する。
図９に示すように、グリーン状態（焼成前）の多層セラミック基板４０の最表層となる表層基板４１の形成時に、次層につながる貫通スルーホール４２を形成し、この貫通スルーホール４２の半導体チップ２０配置側の半分を抜き落とすことにより、基板側側面電極４３を形成する。
その後、半導体チップ実装用凹部４４に相当する部分を打ち抜いた表層基板４１を含む他の層を構成する基板４５と張り合わせ、焼成して多層セラミック基板４０とする。
そして、図９に示すように、半導体チップ２０の側面電極１０と基板側側面電極４３との間を導電粒子入りの異方性導電接着剤４６を介して電気的に接続する。
この結果、半導体チップ２０と表層基板４１の次に積層されている基板４５との間には、異方性導電接着剤４６を入れる必要がないので、実装時のボンディング荷重を低減させることができ、半導体チップ２０に不要な応力を受けることがないので、半導体チップ２０の特性の変化を抑制し、実装時の破損を避けることができる。
すなわち、半導体実装時に導電粒子入りの異方性導電接着剤４６を側面方向に押し出しながら、異方性導電接着剤４６と基板側配線または異方性導電接着剤４６と基板表面との間に形成された気泡を押し出す必要がないので、半兆体チップ２０に大荷重が印加されることがないので、半導体チップ２０の特性の変化を抑制し、実装時の破損を避けることができるのである。
【００２０】
［２．３］リジット基板に貫通スルーホールを形成する場合
次に実装対象の基板がリジット基板であり、このリジット基板に貫通スルーホールを形成する場合について図１０を参照して説明する。
まず、図１０に示すように、多層リジット基板５０の全層あるいは所定の層まで貫通する貫通スルーホール５１を形成して、機械的切削加工により半導体チップ実装用凹部５２を形成するに際し、貫通スルーホール５１を深さ方向の半分程度まで、かつ、貫通スルーホール５１の半導体チップ２０配置側の半分を削り落とす。
これにより、貫通スルーホール５１は、基板側側面電極５３を形成することとなる。
そして、図１０に示すように、半導体チップ２０の側面電極１０と基板側側面電極５３との間を導電粒子入りの異方性導電接着剤５４を介して接続する。
この結果、［２．２］項において説明したセラミック基板の場合と同様に半導体チップ２０と半導体チップが対向する基板面５０Ａとの間には、異方性導電接着剤５４を入れる必要がない。
従って、実装時のボンディング荷重を低減させることができ、半導体チップ２０に不要な応力をかけることがないので、半導体チップ２０の特性の変化を抑制し、破損を防止することができる。
【００２１】
［２．４］基板に内層スルーホール（非貫通スルーホール）を形成する場合
続いて実装対象の基板がセラミック基板あるいはリジット基板であり、この基板に内層スルーホール形成する場合について図１１を参照して説明する。
まず、多層セラミック基板あるいは多層リジット基板である多層基板６０の表層基板から所定の内層基板まで内層スルーホール６１を形成し、表層基板と内層基板との間を電気的に接続する。
そして、セラミック基板の場合は、半導体チップ実装用凹部６２に相当する部分を打ち抜いた基板を含む各層を構成する基板を張り合わせ、焼成して多層セラミック基板とする。また、リジット基板の場合は、機械的切削加工により半導体チップ実装用凹部６２を形成する。
この場合に、内層スルーホール６１の半導体チップ２０配置側の半分を削り落とすことにより基板側側面電極６３を形成する。
そして、図１１に示すように、半導体チップ２０の側面電極２０と内層スルーホールを利用して形成された基板側側面電極６３との間を導電粒子入りの異方性導電接着剤６４を介して接続する。
【００２２】
この結果、［２．２］項および［２．３］項において説明したセラミック基板あるいはリジット基板の場合と同様に半導体チップ２０と半導体チップ２０が対向する基板面６５との間には、異方性導電接着剤６４を入れる必要がない。
従って、実装時のボンディング荷重を低減させることができ、半導体チップ２０に不要な応力がかかることがないので、半導体チップ２０の特性の変化を抑制し、破損を防止することができる。
【００２３】
また、導電粒子入りの異方性導電接着剤５４を介して接続する方法以外の方法としては、図１２に示すように、表層配線パターン７１と内層配線パターン７２とをワイヤボンディング装置によりワイヤ７３で接続し、半導体チップ２０を実装する際にワイヤ７３を半導体チップ側の側面電極１０と内層配線パターン７２（基板）との間に挟み込む。
これにより、半導体チップ２０の側面電極１０と、ワイヤ７３とは図１２に示すように接触状態となり、導通することとなる。
図１２においては、ワイヤ７３を表層配線パターン７１側に最初に接続し、その後、内層配線パターン７２側に接続する場合を図示しているが、ワイヤ７３を内層配線パターン７２側に最初に接続するように構成することも可能である。
さらに、上記各構成において、半導体チップ２０と半導体チップ２０が対向する基板７２との間には、必要に応じて、エポキシ系接着剤などを入れるようにしてもかまわない。
【００２４】
［３］実施形態の効果
以上の説明のように、本実施形態によれば、従来の実装方法と比較して実装時のボンディング荷重を低減することができ、平面方向のせん断応力を半導体チップに対して与えることがないので、半導体チップの特性の変化を抑制し、破損を防止することができる。
また、半導体チップ側の側面電極と基板側の側面電極とは、温度変化などに伴う半導体チップあるいは基板の変形（平面方向の変形）の影響を受けにくく、接続部に亀裂等が発生しにくく、接続信頼性を向上することができる。
すなわち、従来は、電極に対して直行する方向にせん断応力がかかることになっていたのに対し、本実施形態によれば、せん断応力に平行する形で半導体チップの電極と基板電極とが接続されており、弾性を有することとなって半導体チップあるいは基板の変形の影響を受けにくくなっているのである。
さらに半導体チップを含むモジュールの厚みを低減することが可能となる。
以上の説明においては、基板の一方の面に半導体チップを実装する場合について述べたが、基板実装時のボンディング荷重が低いため、基板の両面に実装することも可能となっている。
【００２５】
【発明の効果】
本発明によれば、実装時のボンディング荷重を低減することができ、平面方向のせん断応力を半導体チップに対して与えることがないので、半導体チップの特性の変化を抑制し、破損を防止することができる。
また、半導体装置の電極と基板電極との間の接続を確実に行え、接続信頼性を向上することができる。
【図面の簡単な説明】
【図１】 ＬＳＩが形成されたウェハの外観斜視である。
【図２】 側面電極形成用孔の穿孔についての説明図である。
【図３】 側面電極の導通をとるための半導体装置の製造方法の説明図である。
【図４】 側面電極の外観斜視図である。
【図５】 配線パターンをオーバーハングパターンとした場合の実装説明図である。
【図６】 側面電極と配線パターン（オーバーハングパターン）との接続状態の説明図である。
【図７】 実装面側がテーパー形状となっている側面電極の説明図である。
【図８】 側面電極の実装面側はテーパー形状とした場合の実装説明図である。
【図９】セラミック基板に貫通スルーホールを形成する場合の実装説明図である。
【図１０】 リジット基板に貫通スルーホールを形成する場合の実装説明図である。
【図１１】 基板に内層スルーホール（非貫通スルーホール）を形成する場合の実装説明図である。
【図１２】 導電性ワイヤを用いて実装を行う場合の実装説明図である。
【図１３】 従来のワイヤボンディング方式を説明するための図である。
【図１４】 従来のフリップチップボンディング方式を説明するための図である。
【図１５】 従来のフリップチップボンディング方式における問題点を説明する図である。
【符号の説明】
１…ＬＳＩ
２…ウェハ
３…表面電極
４…側面電極形成用孔
５…絶縁コーティング
６…メッキ
１０…側面電極
２０…半導体チップ（半導体装置）
３０…フレキシブル基板
３１…配線パターン（オーバーハングパターン）
４０…多層セラミック基板
４１…表層基板
４２…貫通スルーホール
４３…基板側側面電極
４４…半導体チップ実装用凹部
４５…基板
４６…異方性導電接着剤
５０…多層リジット基板
５０Ａ…基板面
５１…貫通スルーホール
５２…半導体チップ実装用凹部
５３…基板側側面電極
５４…異方性導電接着剤
６０…多層基板
６１…内層スルーホール
６２…半導体チップ実装用凹部
６３…基板側側面電極
６４…異方性導電接着剤
７１…表層配線パターン
７２…内層配線パターン
７３…ワイヤ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for mounting a semiconductor device, and more particularly to a technique for ensuring electrical connection while reducing a bonding load during mounting.
[0002]
[Prior art]
Conventionally, various techniques for mounting a semiconductor chip on a substrate are known.
For example, as a mounting technique, a wire bonding method, a flip chip bonding method, or the like can be given.
According to the wire bonding method, as shown in FIG. 13, the semiconductor chip 101 is fixed on the substrate 100 with an adhesive or the like, and the electrode of the semiconductor chip 101 and the electrode 102 on the substrate 100 are connected using a conductive wire 103 or the like. There is an aerial wiring connection.
According to the flip chip bonding method, as shown in FIG. 14, the conductive electrode (or protruding electrode) 202 formed on the semiconductor chip 201 is aligned with the electrode on the substrate, and alloy bonding or conductive property is achieved. Connection is made by mechanical contact using particles, conductive adhesive 203 or the like.
[0003]
[Problems to be solved by the invention]
In the wire bonding method, as shown in FIG. 13, a semiconductor chip 101 is mounted on a substrate 100, and after wire bonding, a semiconductor chip 101 including a conductive wire is applied with a molding agent 104 to give mechanical strength. It was configured to be buried. As a result, there is a problem that the thickness of the module 105 as a whole increases.
Further, when the semiconductor chip 101 is used as a high frequency circuit, there is a problem that the wire length becomes too long, which is not preferable in terms of high frequency circuit characteristics.
According to the flip chip bonding method, the electrode 202 of the semiconductor chip 201 and the electrode on the substrate are both arranged on a plane, so that a plane generated due to a temperature change or the like as indicated by an arrow in FIG. The material expands and contracts in the direction, and shear stress acts on the electrode joint due to the difference in coefficient of linear expansion between the semiconductor chip material and the substrate material, which may cause cracks in the electrode joint and cause poor conduction.
[0004]
In addition, when the semiconductor chip size is increased to increase the number of functions and the number of electrodes is further increased, the bonding load when the semiconductor chip is mounted on the electrode of the substrate is increased, the stress is applied to the active surface of the semiconductor chip, and the semiconductor It was also a cause of changing the characteristics of the chip.
Moreover, since stress is applied to the substrate when the semiconductor chip is mounted, the electrode portion of the previously mounted semiconductor chip is cracked.
Moreover, since the semiconductor chip is mounted on the substrate as in the case of wire bonding, there is a problem that the thickness of the module is increased.
On the other hand, in a semiconductor chip mounting method in which a semiconductor chip is increased in capacity and multifunction and many input / output terminals are connected to the substrate from the semiconductor chip, many input / output terminals are arranged as protruding electrodes on the semiconductor chip. Therefore, it is necessary to reduce the area of the electrode and reduce the arrangement pitch, so that the area of the connecting portion of the protruding electrode cannot be secured so that sufficient mechanical strength is obtained, and a planar electrode is formed. There was a problem of having to.
[0005]
In addition, there is a problem that a high technical level is required to form a minute electrode. Furthermore, in order to mount a planar electrode of a semiconductor chip, which has been further miniaturized and increased in number of pins, and whose size has been increased in a planar direction with respect to an electrode on a substrate, a very large bonding load is required. There is a problem in that unnecessary stress is applied to the substrate. Therefore, an object of the present invention is to provide a mounting method capable of reducing a bonding load when mounting a semiconductor chip.
[0012]
[Means for Solving the Problems]
In order to solve the above problems, in a semiconductor device mounting method in which a semiconductor device having a side electrode formed in a groove shape on a side surface substantially perpendicular to the mounting surface of the semiconductor device is mounted on a substrate, the semiconductor device is placed on the substrate side A housing recess is provided, the inner layer wiring pattern in the housing recess and the surface layer wiring pattern on the substrate surface are connected by a conductive wire in association with a position corresponding to the side electrode, and the semiconductor device is perpendicular to the substrate. The conductive wire and the side electrode are electrically connected by pushing the wire into the housing recess with a predetermined pressure.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Next, preferred embodiments of the present invention will be described with reference to the drawings.
[1] Manufacturing of Semiconductor Chip First, the manufacturing process of the semiconductor chip will be described.
[1.1] LSI Formation Step First, an LSI is formed on a Si wafer by the same steps as usual.
The LSI formation process includes a cleaning process, a diffusion process, a thin film formation process, and a patterning process.
First, in the cleaning step, cleaning is performed so that the wafer is in a clean state.
The diffusion process is performed for the pn junction process and impurity profile control.
In the thin film forming step, a silicon nitride film, polycrystalline silicon, an aluminum electrode including a surface electrode, and the like are formed.
The patterning process includes an exposure process and an etching process. In the exposure step, the resist applied on the silicon substrate is exposed and developed to form a predetermined resist pattern. In the etching process, the base film is etched using the resist pattern in the exposure process as a mask to form a pattern.
Thereafter, a plurality of LSIs are formed on the wafer by repeating the cleaning process, the diffusion process, the thin film forming process, and the patterning process.
[0014]
[1.2] Drilling Process FIG. 1 is an external perspective view of a wafer on which an LSI is formed.
Next, in the wafer 2 on which a plurality of LSIs 1 are formed, as shown in FIG. 2, the region in the vicinity of the electrode (surface electrode) 3 formed in the peripheral part of the LSI 1 is a position corresponding to each electrode. The side electrode forming holes 4 are formed by drilling along the virtually provided dicing lines DL.
After drilling the side electrode forming holes, as shown in FIG. 3A, an insulating coating 5 for the LSI and the side electrode forming holes is applied.
[0015]
[1.3] Plating step Next, as shown in FIG. 3B, the whole or part of the insulating coating on the surface electrode is removed by laser processing or the like.
And as shown in FIG.3 (c), the plating process is performed in the hole for surface electrode and side electrode formation using the plating material 6 for general electrodes, and both are made into a conduction state.
Next, a predetermined coating process such as polyimide coating is applied to the surface electrode and side electrode forming holes.
[0016]
[1.4] Dicing Step Next, dicing is performed to separate the wafer 2 into semiconductor chips.
In this case, the wafer 2 is diced along a straight line (shown as a dicing line DL in FIG. 2) passing through the center point of the side electrode forming hole 4 to obtain the semiconductor chip 20 (see FIG. 4).
Thereby, the side electrode forming hole 4 is divided into two equal parts to form the side electrode 10.
FIG. 4 shows an external perspective view of the side electrode.
As shown in FIG. 4, the side electrode 10 has a shape like bamboo divided in half.
If it is necessary to reduce the thickness of the obtained semiconductor chip 20, mechanical polishing or chemical polishing is performed on the surface (back surface of the semiconductor chip; mounting surface) 20A facing the LSI formation surface of the wafer 2 before dicing. By applying, the thickness can be reduced.
In the half dicing state, the thickness can be reduced by performing mechanical polishing or chemical polishing on the surface 20A after dicing.
[0017]
[2] Mounting of Semiconductor Chip on Substrate Next, mounting of the semiconductor chip on the substrate will be described for each substrate.
[2.1] In the case of a flexible substrate First, the case where the substrate to be mounted is a flexible substrate will be described first.
As shown in FIGS. 5A and 5B, when the mounting destination of the semiconductor chip 20 is the flexible substrate 30, the wiring pattern 31 of the flexible substrate 30 is placed at a position corresponding to the side electrode 10 of the semiconductor chip 20. The arranged overhang pattern is used. As a material of the wiring pattern 31, copper (Cu), nickel (Ni), gold (Au), or the like is used.
Then, while aligning the semiconductor chip 20 with the tool TL that supports the semiconductor chip 20 by suction or the like, a predetermined pressure is applied from a direction perpendicular to the flexible substrate 30 (indicated by an arrow in FIG. 5A). Mount while applying pressure.
[0018]
In this case, the side electrode 10 of the semiconductor chip 20 and the wiring pattern (overhang pattern) 31 of the flexible substrate 30 are in contact with each other as shown in FIG.
Further, as shown in FIG. 7A, if the side electrode forming hole 4 is formed so that the shape of the side electrode on the mounting surface side of the semiconductor chip becomes a tapered shape when drilling, the side electrode forming hole 4 is shown in FIG. Thus, the mounting surface side of the side electrode 10 has a tapered shape, and as shown in FIG. 8, the side electrode 10 of the semiconductor chip 20 and the wiring pattern 31 (overhang pattern) of the flexible substrate 30 are more reliably electrically connected. Connection state.
In order to form such a tapered side electrode forming hole 4, it is only necessary to perform perforation with a laser beam having a predetermined output from the LSI forming surface side.
Further, the wiring pattern (overhang pattern) 31 is formed of a highly elastic material, and the reliability of electrical connection can be improved by the repulsive force accompanying the deformation of the wiring pattern (overhang pattern) 31 due to the mounting of the semiconductor chip 20. Is possible.
Furthermore, the wiring pattern (overhang pattern) 31 may be pre-soldered and soldered to the side electrode 10 to ensure electrical connection.
[0019]
[2.2] Forming a Through-Through Hole in a Ceramic Substrate Next, a case where a substrate to be mounted is a ceramic substrate and a through-through hole is formed in the ceramic substrate will be described with reference to FIG.
As shown in FIG. 9, when forming the surface layer substrate 41 which is the outermost surface layer of the multilayer ceramic substrate 40 in the green state (before firing), a through-through hole 42 connected to the next layer is formed, and the semiconductor chip of the through-through hole 42 is formed. The substrate side surface electrode 43 is formed by removing half of the 20 arrangement side.
After that, the multilayer ceramic substrate 40 is formed by laminating and baking the substrate 45 constituting other layers including the surface layer substrate 41 in which a portion corresponding to the semiconductor chip mounting recess 44 is punched.
Then, as shown in FIG. 9, the side surface electrode 10 of the semiconductor chip 20 and the substrate side surface electrode 43 are electrically connected via an anisotropic conductive adhesive 46 containing conductive particles.
As a result, since it is not necessary to put the anisotropic conductive adhesive 46 between the semiconductor chip 20 and the substrate 45 stacked next to the surface layer substrate 41, the bonding load at the time of mounting can be reduced. Since the semiconductor chip 20 is not subjected to unnecessary stress, changes in the characteristics of the semiconductor chip 20 can be suppressed and damage during mounting can be avoided.
That is, it is formed between the anisotropic conductive adhesive 46 and the substrate-side wiring or the anisotropic conductive adhesive 46 and the substrate surface while extruding the anisotropic conductive adhesive 46 containing conductive particles in the lateral direction during semiconductor mounting. Since it is not necessary to push out the generated bubbles, a large load is not applied to the semi-trunk chip 20, so that a change in characteristics of the semiconductor chip 20 can be suppressed and damage during mounting can be avoided.
[0020]
[2.3] Forming a Through-Through Hole in a Rigid Substrate Next, a case where a substrate to be mounted is a rigid substrate and a through-through hole is formed in the rigid substrate will be described with reference to FIG.
First, as shown in FIG. 10, through through holes 51 that penetrate all layers or a predetermined layer of the multilayer rigid substrate 50 are formed, and when the semiconductor chip mounting recess 52 is formed by mechanical cutting, the through through holes are formed. The hole 51 is cut to about half in the depth direction, and the half of the through-through hole 51 on the side where the semiconductor chip 20 is disposed is scraped off.
As a result, the through-hole 51 forms the substrate side electrode 53.
Then, as shown in FIG. 10, the side electrode 10 of the semiconductor chip 20 and the substrate side electrode 53 are connected via an anisotropic conductive adhesive 54 containing conductive particles.
As a result, as in the case of the ceramic substrate described in the section [2.2], it is not necessary to put the anisotropic conductive adhesive 54 between the semiconductor chip 20 and the substrate surface 50A facing the semiconductor chip.
Therefore, the bonding load at the time of mounting can be reduced, and unnecessary stress is not applied to the semiconductor chip 20, so that the change in characteristics of the semiconductor chip 20 can be suppressed and the breakage can be prevented.
[0021]
[2.4] Forming an inner layer through hole (non-through hole) in a substrate Next, a substrate to be mounted is a ceramic substrate or a rigid substrate, and the case of forming an inner layer through hole in this substrate is described with reference to FIG. I will explain.
First, an inner layer through hole 61 is formed from the surface layer substrate of the multilayer substrate 60 which is a multilayer ceramic substrate or a multilayer rigid substrate to a predetermined inner layer substrate, and the surface layer substrate and the inner layer substrate are electrically connected.
In the case of a ceramic substrate, the substrates constituting the respective layers including the substrate obtained by punching out the portion corresponding to the semiconductor chip mounting recess 62 are bonded and fired to obtain a multilayer ceramic substrate. In the case of a rigid substrate, the semiconductor chip mounting recess 62 is formed by mechanical cutting.
In this case, the substrate side surface electrode 63 is formed by scraping off half of the inner layer through hole 61 on the side where the semiconductor chip 20 is disposed.
Then, as shown in FIG. 11, between the side surface electrode 20 of the semiconductor chip 20 and the substrate side surface electrode 63 formed using the inner layer through hole, an anisotropic conductive adhesive 64 containing conductive particles is interposed. Connecting.
[0022]
As a result, as in the case of the ceramic substrate or the rigid substrate described in the items [2.2] and [2.3], there is an anisotropic difference between the semiconductor chip 20 and the substrate surface 65 facing the semiconductor chip 20. There is no need to insert the conductive conductive adhesive 64.
Therefore, the bonding load at the time of mounting can be reduced, and unnecessary stress is not applied to the semiconductor chip 20, so that the change in the characteristics of the semiconductor chip 20 can be suppressed and the breakage can be prevented.
[0023]
Further, as a method other than the method of connecting via the anisotropic conductive adhesive 54 containing conductive particles, as shown in FIG. 12, a surface layer wiring pattern 71 and an inner layer wiring pattern 72 are connected with a wire 73 by a wire bonding apparatus. When connecting and mounting the semiconductor chip 20, the wire 73 is sandwiched between the side electrode 10 on the semiconductor chip side and the inner layer wiring pattern 72 (substrate).
As a result, the side surface electrode 10 of the semiconductor chip 20 and the wire 73 are brought into contact with each other as shown in FIG.
In FIG. 12, the wire 73 is first connected to the surface wiring pattern 71 side and then connected to the inner wiring pattern 72 side. However, the wire 73 is first connected to the inner wiring pattern 72 side. It is also possible to configure as described above.
Furthermore, in each of the above configurations, an epoxy adhesive or the like may be inserted between the semiconductor chip 20 and the substrate 72 facing the semiconductor chip 20 as necessary.
[0024]
[3] Effects of Embodiment As described above, according to the present embodiment, the bonding load during mounting can be reduced as compared with the conventional mounting method, and the shear stress in the planar direction is applied to the semiconductor chip. Therefore, the change in the characteristics of the semiconductor chip can be suppressed and the breakage can be prevented.
In addition, the side electrode on the semiconductor chip side and the side electrode on the substrate side are not easily affected by deformation (deformation in the plane direction) of the semiconductor chip or the substrate due to temperature change, etc. Connection reliability can be improved.
That is, conventionally, shear stress is applied in a direction perpendicular to the electrode, but according to the present embodiment, the electrode of the semiconductor chip and the substrate electrode are connected in parallel to the shear stress. Therefore, it has elasticity and is hardly affected by the deformation of the semiconductor chip or the substrate.
Furthermore, the thickness of the module including the semiconductor chip can be reduced.
In the above description, the case where the semiconductor chip is mounted on one surface of the substrate is described. However, since the bonding load at the time of mounting the substrate is low, it can be mounted on both surfaces of the substrate.
[0025]
【The invention's effect】
According to the present invention, the bonding load at the time of mounting can be reduced, and since no shear stress in the planar direction is applied to the semiconductor chip, the change in the characteristics of the semiconductor chip is suppressed and the breakage is prevented. Can do.
Further, the connection between the electrode of the semiconductor device and the substrate electrode can be reliably performed, and the connection reliability can be improved.
[Brief description of the drawings]
FIG. 1 is an external perspective view of a wafer on which an LSI is formed.
FIG. 2 is an explanatory view of perforation of a side electrode forming hole.
FIG. 3 is an explanatory diagram of a method for manufacturing a semiconductor device for conducting conduction of a side electrode.
FIG. 4 is an external perspective view of a side electrode.
FIG. 5 is an explanatory diagram of mounting when the wiring pattern is an overhang pattern.
FIG. 6 is an explanatory diagram of a connection state between a side electrode and a wiring pattern (overhang pattern).
FIG. 7 is an explanatory diagram of a side electrode whose mounting surface side is tapered.
FIG. 8 is a mounting explanatory diagram when the mounting surface side of the side electrode is tapered.
FIG. 9 is a mounting explanatory diagram in the case where through-holes are formed in a ceramic substrate.
FIG. 10 is an explanatory diagram of mounting when a through-hole is formed in a rigid substrate.
FIG. 11 is a mounting explanatory diagram in the case where an inner layer through hole (non-through hole) is formed in a substrate.
FIG. 12 is a mounting explanatory diagram when mounting is performed using a conductive wire.
FIG. 13 is a diagram for explaining a conventional wire bonding method.
FIG. 14 is a diagram for explaining a conventional flip chip bonding method.
FIG. 15 is a diagram illustrating a problem in a conventional flip chip bonding method.
[Explanation of symbols]
1 ... LSI
2 ... wafer 3 ... surface electrode 4 ... side electrode forming hole 5 ... insulating coating 6 ... plating 10 ... side electrode 20 ... semiconductor chip (semiconductor device)
30 ... Flexible substrate 31 ... Wiring pattern (overhang pattern)
40 ... multilayer ceramic substrate 41 ... surface layer substrate 42 ... through-hole 43 ... substrate side electrode 44 ... semiconductor chip mounting recess 45 ... substrate 46 ... anisotropic conductive adhesive 50 ... multilayer rigid substrate 50A ... substrate surface 51 ... through Through hole 52 ... Semiconductor chip mounting recess 53 ... Substrate side electrode 54 ... Anisotropic conductive adhesive 60 ... Multilayer substrate 61 ... Inner layer through hole 62 ... Semiconductor chip mounting recess 63 ... Substrate side electrode 64 ... Anisotropic Conductive adhesive 71 ... surface layer wiring pattern 72 ... inner layer wiring pattern 73 ... wire

Claims (1)

半導体装置の実装面にほぼ垂直な側面に溝状に形成された側面電極を有する半導体装置を基板上に実装する半導体装置の実装方法において、
基板側に前記半導体装置を収容する収容凹部を設け、
前記収容凹部内の内層配線パターンと基板表面の表層配線パターンとを前記側面電極に対応する位置に対応づけて導電性ワイヤで接続し、
前記基板に垂直に前記半導体装置を前記収容凹部内に所定の圧力で押し込むことにより前記導電性ワイヤと前記側面電極を電気的に接続させる、
ことを特徴とする半導体装置の実装方法。In a semiconductor device mounting method for mounting a semiconductor device having a side electrode formed in a groove shape on a side surface substantially perpendicular to a mounting surface of the semiconductor device on a substrate,
An accommodation recess for accommodating the semiconductor device is provided on the substrate side,
The inner layer wiring pattern in the housing recess and the surface layer wiring pattern on the substrate surface are connected by a conductive wire in association with the position corresponding to the side electrode,
Electrically connecting the conductive wire and the side electrode by pushing the semiconductor device perpendicularly to the substrate into the housing recess with a predetermined pressure;
A method for mounting a semiconductor device.
JP2001096869A 2001-03-29 2001-03-29 Mounting method of semiconductor device Expired - Fee Related JP3882521B2 (en)

Priority Applications (1)

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JP2001096869A JP3882521B2 (en) 2001-03-29 2001-03-29 Mounting method of semiconductor device

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JP2001096869A JP3882521B2 (en) 2001-03-29 2001-03-29 Mounting method of semiconductor device

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JP3882521B2 true JP3882521B2 (en) 2007-02-21

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DE10308855A1 (en) * 2003-02-27 2004-09-16 Infineon Technologies Ag Semiconductor wafer for electronic components, with integrated circuits in lines and columns for semiconductor chips on wafer top surface with strip-shaped dividing regions between chip integrated circuits
JP4908936B2 (en) * 2005-06-30 2012-04-04 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP5106822B2 (en) * 2006-10-27 2012-12-26 三菱重工業株式会社 Semiconductor device, inspection device, and manufacturing method of semiconductor device
JP5206826B2 (en) 2011-03-04 2013-06-12 株式会社デンソー Region-divided substrate, semiconductor device using the same, and manufacturing method thereof
JP5588409B2 (en) * 2011-09-05 2014-09-10 株式会社東芝 Semiconductor device and manufacturing method thereof
JP2014137525A (en) * 2013-01-18 2014-07-28 Seiko Epson Corp Method for manufacturing substrate for electro-optic device, substrate for electro-optic device, electro-optic device and electronic apparatus
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