JP2002026069A - Mounting method for semiconductor element - Google Patents
Mounting method for semiconductor elementInfo
- Publication number
- JP2002026069A JP2002026069A JP2000199458A JP2000199458A JP2002026069A JP 2002026069 A JP2002026069 A JP 2002026069A JP 2000199458 A JP2000199458 A JP 2000199458A JP 2000199458 A JP2000199458 A JP 2000199458A JP 2002026069 A JP2002026069 A JP 2002026069A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- mounting
- semiconductor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Landscapes
- Drying Of Semiconductors (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子の電極
と回路基板の電極とを接合することによって、半導体素
子を回路基板に実装する半導体素子の実装方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor element on a circuit board by bonding an electrode of the semiconductor element to an electrode of a circuit board.
【０００２】[0002]
【従来の技術】半導体素子を回路基板に接合する方法と
しては、パッケージングされた半導体素子でなく裸の半
導体素子を用い、半導体素子の電極と回路基板の電極と
を半田や金等の金属接合により接合する方法、銀や銅等
の導電性ペーストにより接合する方法、熱可塑性または
熱硬化性の樹脂と導電粉末とからなる異方導電性の接着
シートやペーストを用いて接合する方法等が、高密度、
薄型、高信頼性、高生産性で実装できる方法として盛ん
に実施されている。2. Description of the Related Art As a method of joining a semiconductor element to a circuit board, a bare semiconductor element is used instead of a packaged semiconductor element, and an electrode of the semiconductor element and an electrode of the circuit board are joined to a metal such as solder or gold. Bonding method, a method of bonding with a conductive paste such as silver or copper, a method of bonding using an anisotropic conductive adhesive sheet or paste composed of a thermoplastic or thermosetting resin and conductive powder, and the like, High density,
It is being actively implemented as a method that can be mounted with low profile, high reliability, and high productivity.
【０００３】従来の半導体素子の実装方法について、図
７〜図９を参照しながら説明する。A conventional method for mounting a semiconductor device will be described with reference to FIGS.
【０００４】（従来例１）図７は従来例１における半導
体素子の実装方法を示す。(Conventional Example 1) FIG. 7 shows a method of mounting a semiconductor device in Conventional Example 1.
【０００５】図７において、１は半導体素子であり、２
は半導体素子１上に形成された電極、４は回路基板、５
は回路基板４上に形成された回路パターン（電極）であ
る。In FIG. 7, reference numeral 1 denotes a semiconductor element;
Is an electrode formed on the semiconductor element 1, 4 is a circuit board, 5
Is a circuit pattern (electrode) formed on the circuit board 4.
【０００６】半導体素子１の電極２と回路基板４の回路
パターン５とは、半田、金、銅等の金属３により接合さ
れている。The electrode 2 of the semiconductor element 1 and the circuit pattern 5 of the circuit board 4 are joined by a metal 3 such as solder, gold or copper.
【０００７】半導体素子１と回路基板４との接合面の隙
間には、前記接合後に耐湿性を向上させるためエポキシ
等の樹脂６が充填される。尚、樹脂６は求められる信頼
性の条件によっては充填しない場合もある。The gap between the joining surfaces of the semiconductor element 1 and the circuit board 4 is filled with a resin 6 such as epoxy to improve moisture resistance after the joining. The resin 6 may not be filled depending on the required reliability conditions.
【０００８】（従来例２）図８は従来例２における半導
体素子の実装方法を示す。(Conventional Example 2) FIG. 8 shows a method of mounting a semiconductor device in Conventional Example 2.
【０００９】従来例１と半導体素子１、電極２、回路基
板４、回路パターン５の構成は同じである。The configurations of the semiconductor element 1, the electrode 2, the circuit board 4, and the circuit pattern 5 are the same as those of the conventional example 1.
【００１０】半導体素子１の電極２上には、外部電極端
子７として、ワイヤボンディング法を用いてＡｕ、Ａ
ｌ、Ｃｕ、半田等のボールバンプやメッキ法によるバン
プが形成されている。On the electrode 2 of the semiconductor element 1, Au, A is used as an external electrode terminal 7 by using a wire bonding method.
Ball bumps such as l, Cu, solder and the like and bumps formed by plating are formed.
【００１１】外部電極端子７と回路基板４の回路パター
ン５とは、Ａｇ、Ａｕ、半田等の導電性ペースト８を介
在して接合されている。The external electrode terminals 7 and the circuit pattern 5 of the circuit board 4 are joined via a conductive paste 8 such as Ag, Au, solder or the like.
【００１２】半導体素子１と回路基板４との接合面の隙
間には、従来例１と同様に、前記接合後に耐湿性を向上
させるためのエポキシ等の樹脂６が充填される。尚、樹
脂６は求められる信頼性の条件によっては充填しない場
合もある。A gap between the bonding surfaces of the semiconductor element 1 and the circuit board 4 is filled with a resin 6 such as epoxy to improve moisture resistance after the bonding, as in the first conventional example. The resin 6 may not be filled depending on the required reliability conditions.
【００１３】（従来例３）図９は従来例３における半導
体素子の実装方法を示す。(Conventional Example 3) FIG. 9 shows a mounting method of a semiconductor device in Conventional Example 3.
【００１４】従来例１、２と半導体素子１、電極２、回
路基板４、回路パターン５の構成は同じである。The structures of the semiconductor element 1, the electrode 2, the circuit board 4, and the circuit pattern 5 are the same as those of the conventional examples 1 and 2.
【００１５】半導体素子１の電極２上には従来例２と同
様に、外部電極端子７として、ワイヤボンディング法を
用いてＡｕ、Ａｌ、Ｃｕ、半田等のボールバンプやメッ
キ法によるバンプが形成されている。As in the second conventional example, ball bumps made of Au, Al, Cu, solder or the like or bumps formed by plating are formed on the electrodes 2 of the semiconductor element 1 as the external electrode terminals 7 by using a wire bonding method. ing.
【００１６】外部電極端子７と回路基板４の回路パター
ン５とは、熱可塑性または熱硬化性の樹脂１０と、Ａ
ｕ、Ｎｉ、Ｃｕ等の導電粉末９とからなる異方導電性の
接着シートやペーストを用いて接合することにより、半
導体素子１の電極２と回路基板４の回路パターン５とを
電気的に接続している。The external electrode terminals 7 and the circuit pattern 5 of the circuit board 4 are made of a thermoplastic or thermosetting resin 10 and A
The electrodes 2 of the semiconductor element 1 and the circuit patterns 5 of the circuit board 4 are electrically connected by bonding using an anisotropic conductive adhesive sheet or paste made of conductive powder 9 of u, Ni, Cu, or the like. are doing.
【００１７】[0017]
【発明が解決しようとする課題】しかし上記従来例１〜
３の半導体素子の実装方法においては、図１０に示すよ
うに、ガラスエポキシ樹脂材、セラミック等で形成され
た回路基板４と、Ｓｉ、ＧａＡｓ等により形成された半
導体素子１の線膨張係数が異なるため、熱ストレスが加
わった場合、従来例１では金属３（従来例２、３では外
部電極端子７）で形成された接合部１３に応力が集中し
て亀裂１１が発生し、電気的にオープンするという問題
があった。However, the above conventional examples 1 to
In the semiconductor element mounting method of No. 3, as shown in FIG. 10, the circuit board 4 formed of a glass epoxy resin material, ceramic, or the like, and the semiconductor element 1 formed of Si, GaAs, or the like have different linear expansion coefficients. Therefore, when a thermal stress is applied, in the conventional example 1, the stress is concentrated on the joint 13 formed of the metal 3 (the external electrode terminal 7 in the conventional examples 2 and 3), and the crack 11 is generated, and the electrical opening is caused. There was a problem of doing.
【００１８】また、熱ストレスでは無く、図１１に示す
ように単純な曲げ応力Ａが加わった場合においても、回
路基板４と半導体素子１の弾性率の違いから同様の問題
が生じる。そしてそれらの問題を解決するために図１１
に示すように、半導体素子１の厚みＴを薄くしている。
具体的には５０μｍ厚位にし、弾性率の差を小さくして
実装するという方法も行われていた。しかし、その場合
においては半導体素子１の厚みＴが薄いために生産工程
上、半導体素子１の取扱いが難しくなり、半導体素子１
が割れたり欠けたりするという問題が頻繁に生じてい
た。Even when a simple bending stress A is applied as shown in FIG. 11 instead of a thermal stress, a similar problem arises due to a difference in the elastic modulus between the circuit board 4 and the semiconductor element 1. Then, in order to solve those problems, FIG.
As shown in the figure, the thickness T of the semiconductor element 1 is reduced.
Specifically, a method of mounting the semiconductor device with a thickness of about 50 μm and reducing the difference in elastic modulus has been performed. However, in this case, since the thickness T of the semiconductor element 1 is small, it is difficult to handle the semiconductor element 1 in a production process.
The problem of cracking or chipping frequently occurred.
【００１９】本発明は前記問題点を解決し、実装後の曲
げに対して半導体素子を追従できるようにすることで、
半導体素子を高密度、高生産性で回路基板に実装するこ
とを可能にする半導体素子の実装方法を提供することを
目的とするものである。The present invention solves the above-mentioned problems and enables the semiconductor element to follow the bending after mounting.
It is an object of the present invention to provide a method for mounting a semiconductor element, which enables a semiconductor element to be mounted on a circuit board with high density and high productivity.
【００２０】[0020]
【課題を解決するための手段】上記目的を達成するため
の本発明は、半導体素子の電極と回路基板の電極とを接
合することによって、半導体素子を回路基板に実装する
半導体素子の実装方法において、電極のある面とは反対
側の面である背面に切込み溝を設けた半導体素子を、回
路基板に実装することを特徴とする。According to the present invention, there is provided a method for mounting a semiconductor element on a circuit board by joining an electrode of the semiconductor element and an electrode of a circuit board. A semiconductor element having a cut groove on the back surface opposite to the surface on which electrodes are provided is mounted on a circuit board.
【００２１】本発明によれば、半導体素子の背面に切込
み溝を設けているので、曲げに対して半導体素子が追従
することが可能となり、熱ストレスや曲げストレスに対
して許容範囲が広がる。また、半導体素子の切込み溝以
外の部分は厚みがあるため、欠けや割れ等の心配が無
く、取扱いが容易となる。According to the present invention, since the cut groove is provided on the back surface of the semiconductor element, the semiconductor element can follow the bending, and the allowable range for the thermal stress and the bending stress is widened. Further, since the portions other than the cut grooves of the semiconductor element are thick, there is no fear of chipping or cracking, and the handling becomes easy.
【００２２】上記発明において、半導体素子の背面に切
込み溝を設ける方法を、ダイシングソーを用いて半導体
ウエハをダイシングして半導体チップに分割する工程に
おいて、ダイシングソーによるハーフカットによって行
ったり、フォトレジストまたは金属箔膜をパターニング
してマスクとし、フッ素原子を含む反応性ガスを使用し
たドライエッチング法により行ったり、フォトレジスト
をマスクとし、化学的エッチング法により行ったりする
と好適である。In the above invention, the method of forming the notch groove on the back surface of the semiconductor element is performed by dicing a semiconductor wafer using a dicing saw to divide it into semiconductor chips by half-cutting with a dicing saw, or using a photoresist or a photoresist. It is preferable that the metal foil film is patterned and used as a mask by a dry etching method using a reactive gas containing a fluorine atom, or that the photoresist is used as a mask and a chemical etching method be used.
【００２３】[0023]
【発明の実施の形態】以下、添付図面を参照して本発明
の一実施形態について説明する。尚、従来例の図７〜図
１１の構成と同一部分には同一符号を付して説明を省略
する。また以下の実施形態は本発明の具現化した一例で
あって、本発明の技術範囲を限定するものではない。An embodiment of the present invention will be described below with reference to the accompanying drawings. The same reference numerals are given to the same portions as those in the conventional example shown in FIGS. The following embodiments are embodied examples of the present invention, and do not limit the technical scope of the present invention.
【００２４】図１において、半導体素子１上には電極２
が形成され、回路基板４上には回路パターン（電極）５
が形成され、後述するように、半導体素子１の電極２と
回路基板４の回路パターン５とを接合することによっ
て、半導体素子１は回路基板４に実装される。半導体素
子１の電極２のある面とは反対側の面である背面１ａに
は、切込み溝１４が形成されている。切込み溝１４は例
えば、半導体素子１の厚みＴが４００μｍの場合、幅Ｂ
は１００μｍ、深さＨは３５０μｍに形成する。尚、切
込み溝１４のサイズは前記サイズに限定されるものでは
ない。In FIG. 1, an electrode 2 is provided on a semiconductor element 1.
Are formed, and a circuit pattern (electrode) 5 is formed on the circuit board 4.
Is formed, and the semiconductor element 1 is mounted on the circuit board 4 by joining the electrode 2 of the semiconductor element 1 and the circuit pattern 5 of the circuit board 4 as described later. A cut groove 14 is formed on the back surface 1a of the semiconductor element 1 opposite to the surface on which the electrode 2 is located. For example, when the thickness T of the semiconductor element 1 is 400 μm,
Is 100 μm and the depth H is 350 μm. In addition, the size of the cut groove 14 is not limited to the above size.
【００２５】また図２と図３は、半導体素子１の背面１
ａに切込み溝１４が設けられた状態を示す斜視図であ
る。図２は矩形状の半導体素子１の縦横の辺に沿ってそ
れぞれ平行に切込み溝１４を形成したものであり、図３
は半導体素子１の縦横の辺に斜めに互いが平行になるよ
うに切込み溝１４を形成したものである。尚、切込み溝
１４は、図２や図３の形状に限定されるものではない。FIGS. 2 and 3 show the back surface 1 of the semiconductor device 1.
It is a perspective view showing the state where cut groove 14 was provided in a. FIG. 2 shows cutout grooves 14 formed in parallel along the vertical and horizontal sides of the rectangular semiconductor element 1.
In the figure, cut grooves 14 are formed obliquely on the vertical and horizontal sides of the semiconductor element 1 so as to be parallel to each other. Note that the cut groove 14 is not limited to the shapes shown in FIGS.
【００２６】切込み溝１４を設けた半導体素子１は、そ
の電極２と回路基板４の回路パターン５とが、半田、
金、銅等の金属３により電気的に接合される。この接合
は、電極２上に形成したワイヤボンディング法によるＡ
ｕ、Ａｌ、Ｃｕ、半田等のボールバンプやメッキ法によ
るバンプを介して、熱可塑性または熱硬化性の樹脂とＡ
ｕ、Ｎｉ、Ｃｕ等の導電粉末とからなる異方導電性の接
着シートを用いる等、従来例で説明した他の接合方法を
用いても良い。The semiconductor element 1 provided with the cut groove 14 has a structure in which the electrode 2 and the circuit pattern 5 of the circuit board 4 are soldered.
It is electrically joined by a metal 3 such as gold or copper. This bonding is performed by the wire bonding method formed on the electrode 2.
u, Al, Cu, solder, etc., through a ball bump or a plating bump to form a thermoplastic or thermosetting resin with A
Other joining methods described in the conventional example may be used, such as using an anisotropic conductive adhesive sheet made of a conductive powder such as u, Ni, or Cu.
【００２７】切込み溝１４の形成は、図４に示すよう
に、半導体素子１が半導体ウエハ１７の状態で、図４
（ａ）に示すように、ダイシングソー１５を用いて未切
断部１ｂを残して切除するハーフカットにより行うと好
適である。図４（ｂ）はそのハーフカット工程の斜視図
を示したものである。As shown in FIG. 4, the notches 14 are formed when the semiconductor element 1 is in the state of a semiconductor wafer 17 as shown in FIG.
As shown in (a), it is preferable to carry out half cutting using a dicing saw 15 so as to leave the uncut portion 1b. FIG. 4B is a perspective view of the half cutting process.
【００２８】このように切込み溝１４を形成した後、図
５に示すようにダイシングソー１５を用いてフルダイシ
ングして、半導体ウエハ１７を個片の半導体チップ１６
の状態に分割する。ただし、先に半導体チップ１６にフ
ルダイシングしてから、それぞれ分割された半導体チッ
プ１６の背面に切込み溝１４を形成しても良い。After the cut grooves 14 are formed in this manner, the semiconductor wafer 17 is subjected to full dicing using a dicing saw 15 as shown in FIG.
Divided into states. However, after the semiconductor chip 16 is first fully diced, the cut groove 14 may be formed on the back surface of each divided semiconductor chip 16.
【００２９】また、切込み溝１４は、フォトレジストま
たは金属箔膜をパターニングしてマスクとし、フッ素原
子を含む反応性ガスを使用したドライエッチング法によ
り行うもしくは、フォトレジストをマスクとし、化学的
エッチング法により行うことにより形成しても良い。The cut groove 14 is formed by patterning a photoresist or a metal foil film as a mask, and is performed by a dry etching method using a reactive gas containing fluorine atoms, or a chemical etching method using a photoresist as a mask. May be formed.
【００３０】この実施形態によれば、半導体素子１の背
面１ａに切込み溝１４を設けているので、回路基板４に
半導体素子１を実装後、図６に示すように、曲げに対し
て半導体素子１が追従することが可能となり、熱ストレ
スや曲げストレスに対して許容範囲が広がる。その結
果、接合部１３に対する応力集中が緩和され、亀裂等の
発生しない高品質な実装が行える。また、半導体素子１
の切込み溝１４以外の部分は厚みがあるため、欠けや割
れ等の心配が無く、取扱いが容易に行える。According to this embodiment, since the cut groove 14 is provided on the back surface 1a of the semiconductor element 1, after the semiconductor element 1 is mounted on the circuit board 4, as shown in FIG. 1 can follow, and the allowable range for thermal stress and bending stress is widened. As a result, stress concentration on the joint 13 is reduced, and high-quality mounting without cracks or the like can be performed. In addition, the semiconductor element 1
Since the portion other than the cut groove 14 is thick, there is no fear of chipping or cracking, and the handling can be easily performed.
【００３１】[0031]
【発明の効果】以上の説明の通り本発明によれば、背面
に切込み溝を設けた半導体素子を用いて回路基板への実
装を行っているので、実装後においての熱や外力に起因
する曲げに対して半導体素子が追従することが可能とな
り、熱ストレスや曲げストレスに対して許容範囲が広が
る。また、半導体素子の切込み溝以外の部分は厚みがあ
るため、欠けや割れ等の心配が無く、ハンドリングが容
易に行える。その結果、半導体素子を高密度、高生産
性、低コストで実装することを可能にする半導体素子の
実装方法を提供することが可能になる。As described above, according to the present invention, since a semiconductor element having a cut groove on the back surface is used for mounting on a circuit board, bending caused by heat or external force after mounting is performed. The semiconductor element can follow this, and the allowable range for thermal stress and bending stress is widened. Further, since the portions other than the cut grooves of the semiconductor element are thick, there is no fear of chipping or cracking, and handling can be easily performed. As a result, it is possible to provide a method for mounting a semiconductor element, which enables high-density, high-productivity, and low-cost mounting of the semiconductor element.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の実施形態に係る半導体素子と回路基板
との実装後の断面図。FIG. 1 is a cross-sectional view after mounting a semiconductor element and a circuit board according to an embodiment of the present invention.
【図２】本発明の実施形態に係る半導体素子の１例を示
す斜視図。FIG. 2 is a perspective view showing an example of a semiconductor device according to an embodiment of the present invention.
【図３】本発明の実施形態に係る半導体素子の別な例を
示す斜視図。FIG. 3 is a perspective view showing another example of the semiconductor device according to the embodiment of the present invention.
【図４】本発明の実施形態に係る半導体素子の製造プロ
セスを示し、（ａ）はハーフカット工程を示す断面図、
（ｂ）は斜視図。FIG. 4 shows a manufacturing process of the semiconductor device according to the embodiment of the present invention, wherein (a) is a cross-sectional view showing a half-cut step,
(B) is a perspective view.
【図５】本発明の実施形態に係る半導体素子の製造プロ
セスのフルカット工程を示す断面図。FIG. 5 is a cross-sectional view showing a full-cut step of a manufacturing process of the semiconductor device according to the embodiment of the present invention.
【図６】本発明の実施形態に係る半導体素子の実装後
に、回路基板の曲げに対して追従している状態を示す断
面図。FIG. 6 is a cross-sectional view showing a state in which the semiconductor device according to the embodiment of the present invention follows the bending of the circuit board after mounting.
【図７】従来の半導体素子の実装方法を示す断面図。FIG. 7 is a sectional view showing a conventional method for mounting a semiconductor element.
【図８】従来の半導体素子の実装方法を示す断面図。FIG. 8 is a cross-sectional view showing a conventional method for mounting a semiconductor element.
【図９】従来の半導体素子の実装方法を示す断面図。FIG. 9 is a cross-sectional view showing a conventional method for mounting a semiconductor element.
【図１０】従来の半導体素子の実装後の問題点を示す断
面図。FIG. 10 is a sectional view showing a problem after mounting a conventional semiconductor element.
【図１１】従来の厚みが薄い半導体素子を実装した状態
を示す断面図。FIG. 11 is a sectional view showing a state where a conventional thin semiconductor element is mounted.
１ 半導体素子 １ａ 背面 ２ 半導体素子の電極 ４ 回路基板 ５ 回路パターン（回路基板の電極） １４ 切込み溝 １５ ダイシングソー １６ 半導体チップ １７ 半導体ウエハ DESCRIPTION OF SYMBOLS 1 Semiconductor element 1a Back surface 2 Electrode of semiconductor element 4 Circuit board 5 Circuit pattern (electrode of circuit board) 14 Cut groove 15 Dicing saw 16 Semiconductor chip 17 Semiconductor wafer
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F004 AA16 DA00 DA01 DA02 DA03 DA15 DA16 DA17 DA18 DA19 DA20 DB01 EB08 5F044 KK02 KK04 LL09 QQ01 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F004 AA16 DA00 DA01 DA02 DA03 DA15 DA16 DA17 DA18 DA19 DA20 DB01 EB08 5F044 KK02 KK04 LL09 QQ01
Claims (4)
接合することによって、半導体素子を回路基板に実装す
る半導体素子の実装方法において、電極のある面とは反
対側の面である背面に切込み溝を設けた半導体素子を、
回路基板に実装することを特徴とする半導体素子の実装
方法。In a semiconductor element mounting method for mounting a semiconductor element on a circuit board by bonding an electrode of the semiconductor element and an electrode of a circuit board, a method of mounting the semiconductor element on a back surface opposite to a surface on which an electrode is provided. A semiconductor element with a cut groove
A method for mounting a semiconductor element, wherein the method is mounted on a circuit board.
法は、ダイシングソーを用いて半導体ウエハをダイシン
グして半導体チップに分割する工程において、ダイシン
グソーによるハーフカットによって行う請求項１記載の
半導体素子の実装方法。2. The method according to claim 1, wherein the step of forming the notch on the back surface of the semiconductor element is performed by half-cutting with a dicing saw in the step of dicing the semiconductor wafer into semiconductor chips using a dicing saw. How to implement.
法は、フォトレジストまたは金属箔膜をパターニングし
てマスクとし、フッ素原子を含む反応性ガスを使用した
ドライエッチング法により行う請求項１記載の半導体素
子の実装方法。3. The method according to claim 1, wherein the groove is provided on the back surface of the semiconductor element by a dry etching method using a reactive gas containing a fluorine atom by patterning a photoresist or a metal foil film as a mask. How to mount a semiconductor device.
法は、フォトレジストをマスクとし、化学的エッチング
法により行う請求項１記載の半導体素子の実装方法。4. The method for mounting a semiconductor device according to claim 1, wherein the method of providing the cut groove on the back surface of the semiconductor device is performed by a chemical etching method using a photoresist as a mask.
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| JP2000199458A JP2002026069A (en) | 2000-06-30 | 2000-06-30 | Mounting method for semiconductor element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000199458A JP2002026069A (en) | 2000-06-30 | 2000-06-30 | Mounting method for semiconductor element |
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| Publication Number | Publication Date |
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| JP2002026069A5 JP2002026069A5 (en) | 2005-07-07 |
Family
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|---|---|---|---|
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| JP2005150221A (en) * | 2003-11-12 | 2005-06-09 | Seiko Epson Corp | Semiconductor device, semiconductor wafer, and its manufacturing method |
| JP2006073843A (en) * | 2004-09-03 | 2006-03-16 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| JP2008083579A (en) * | 2006-09-28 | 2008-04-10 | Fuji Xerox Co Ltd | Image display medium |
| JP2013211496A (en) * | 2012-03-30 | 2013-10-10 | National Institute Of Advanced Industrial & Technology | Silicon carbide semiconductor element manufacturing method |
| KR20140079499A (en) * | 2011-10-21 | 2014-06-26 | 코닌클리케 필립스 엔.브이. | Low warpage wafer bonding through use of slotted substrates |
| US20180011232A1 (en) * | 2016-07-11 | 2018-01-11 | Hamamatsu Photonics K.K. | Fabry-perot interference filter and light-detecting device |
| JP2018010037A (en) * | 2016-07-11 | 2018-01-18 | 浜松ホトニクス株式会社 | Fabry-perot interference filter and photodetection device |
| JP2018010038A (en) * | 2016-07-11 | 2018-01-18 | 浜松ホトニクス株式会社 | Fabry-perot interference filter and photodetection device |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005150221A (en) * | 2003-11-12 | 2005-06-09 | Seiko Epson Corp | Semiconductor device, semiconductor wafer, and its manufacturing method |
| JP2006073843A (en) * | 2004-09-03 | 2006-03-16 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| JP2008083579A (en) * | 2006-09-28 | 2008-04-10 | Fuji Xerox Co Ltd | Image display medium |
| KR20140079499A (en) * | 2011-10-21 | 2014-06-26 | 코닌클리케 필립스 엔.브이. | Low warpage wafer bonding through use of slotted substrates |
| KR102020001B1 (en) | 2011-10-21 | 2019-09-09 | 루미리즈 홀딩 비.브이. | Low warpage wafer bonding through use of slotted substrates |
| JP2013211496A (en) * | 2012-03-30 | 2013-10-10 | National Institute Of Advanced Industrial & Technology | Silicon carbide semiconductor element manufacturing method |
| US9728606B2 (en) | 2012-03-30 | 2017-08-08 | Fuji Electric Co., Ltd. | Silicon carbide semiconductor element and fabrication method thereof |
| US20180011232A1 (en) * | 2016-07-11 | 2018-01-11 | Hamamatsu Photonics K.K. | Fabry-perot interference filter and light-detecting device |
| JP2018010037A (en) * | 2016-07-11 | 2018-01-18 | 浜松ホトニクス株式会社 | Fabry-perot interference filter and photodetection device |
| JP2018010038A (en) * | 2016-07-11 | 2018-01-18 | 浜松ホトニクス株式会社 | Fabry-perot interference filter and photodetection device |
| US11054560B2 (en) | 2016-07-11 | 2021-07-06 | Hamamatsu Photonics K.K | Fabry-Perot interference filter and light-detecting device |
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