JPH02240942A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the stiffness of a semiconductor device and to relax the concentration of stress occurring in a part of connection by forming a plurality of grooves on the reverse side at a prescribed interval. CONSTITUTION:A silicon large-scale integrated circuit 1 as a semiconductor device is shaped in a rectangular plate and has a construction wherein a plurality of half-gable-shaped grooves 1a are cut on the reverse side thereof. These grooves 1a are formed in parallel and at a prescribed interval in the direction intersecting the longitudinal direction of an Si chip 1 perpendicularly, while projecting electrodes 4 are formed on the surface of the Si chip 1. On the surface of a circuit board 2, on the other side, leads 3 are provided in projection at positions corresponding to the projecting electrodes 4 when the Si chip 1 is bonded by a facedown method. These leads 3 are formed in the shape of a thin film by using a composite conductive material such as ITO(Indium-Tin- Oxide). According to this constitution, it is possible to reduce the stiffness of the semiconductor device and to relax reliably the concentration of stress occurring in a part of connection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device bonded by a face-down method.

[Conventional technology]

When bonding a semiconductor device onto a circuit board using a face-down method, known bonding methods include a flip chip method and a beam lead method. These bonding methods are explained below.

The flip-chip method is a method in which solder bumps are formed in advance on the electrode portions of a semiconductor chip, and are soldered face-down to the conductor portions of a pre-soldered circuit board. In addition, in the beam lead method, fine beam-shaped leads of Au (gold) are formed on the electrodes of the semiconductor chip at the wafer stage of the semiconductor manufacturing process, and then these are connected face down to the Au conductors on the circuit board. This is a method of thermal compression bonding by aligning with the pattern.

In semiconductor devices such as those described above, when the ambient temperature changes, the thermal expansion coefficients of the circuit board and the semiconductor device differ, causing stress concentration at the connections, which is the main cause of connection failures and deterioration of reliability. ing. Therefore, conventional measures have been taken to address these problems as shown below.

(1) Use a circuit board made of a material with a small difference in thermal expansion coefficient from that of the semiconductor device.

(2) Provide a means to alleviate stress concentration occurring at the connection portion.

(3) Reinforce the joints where stress concentration occurs with resin, etc.

Here, the above (2) will be explained as follows.

As shown in FIG. 5, the electrode portion 1 on the surface of the Si chip 11
4 and the leads 13 protruding from the surface of the circuit board 12...
- and are connected by stress concentration relaxation leads 16... As a result, even if the ambient temperature changes, the Si chip 1
1 and the circuit board 12, the stress concentration relieving leads 16, which are the connecting portions between the circuit board 12 and the circuit board 12, alleviate stress concentration, making it possible to prevent connection failures and deterioration of reliability.

[Problems to be Solved by the Invention] However, the conventional mounting structure described above has various problems as shown below.

That is, in (1) above, the stress concentration occurring at the connection part can be reliably reduced, but the material of the circuit board to be used is limited;
As a result, versatility is lost and costs increase.

Moreover, in the above (2), when the number of terminals of a semiconductor device increases and the terminal arrangement becomes fine pitch, it becomes practically difficult to provide the leads 16, and the cost becomes extremely high. This tendency becomes more noticeable as semiconductor devices become larger.

On the other hand, although the above method (3) can be implemented most easily, it does not essentially solve the problem, and selection of the resin is extremely difficult.

[Means to solve the problem]

In order to solve the above-mentioned Lmlu, the semiconductor device according to the present invention is a semiconductor device bonded onto a circuit board by a face-down method, and is characterized in that a plurality of grooves are formed on the back surface at predetermined intervals. .

[For production]

With the above configuration, after the semiconductor device is bonded to the circuit board using the face-down method, even if the ambient temperature changes and the semiconductor device and the circuit board expand according to their respective thermal expansion coefficients and cause distortion, The plurality of grooves formed at the predetermined intervals described above can reduce the rigidity of the semiconductor device and reliably alleviate the stress concentration that occurs at the connection part, thereby reducing connection failures and improving reliability. You can definitely measure it.

〔Example〕

An embodiment of the present invention will be described below based on FIGS. 1 and 2.

As shown in FIG. 1, a silicon large-scale integrated circuit (hereinafter referred to as a Si chip) 1 as a semiconductor device has a rectangular plate shape, and a plurality of semi-gable grooves 1a...
The structure is engraved with .

These grooves 1a... are formed on the Si chip 1 as shown in FIG.
They are formed parallel to each other at predetermined intervals in a direction perpendicular to the longitudinal direction of the. The shape of the Si chip 1 in this example is a rectangle with a long side of 10 nn and a short side of 6 m, and a thickness of 0.53 on, and protruding electrodes 4 are formed on the surface.

On the other hand, when the Si chip l is bonded face-down to the surface of the circuit board 2, the leads 3 and
. . . are provided in a protruding manner at positions corresponding to the protruding electrodes 4 . This lead 3... is made of ITO (Indiu
It is formed into a thin film using a composite conductive material such as m-Tin-Oxide.

Further, although the circuit board 2 is made of common soda glass material in this embodiment, it is also possible to use materials other than glass such as ceramic or glass epoxy.

Protruding electrodes 4 protruding from the surface of the Si chip 1
...and the leads 3 protruding from the circuit board 2...
is bonded with a conductive resin paste (not shown). As the bonding agent, in addition to the conductive resin paste, an anisotropic conductive film and a UV hardening phase resin can also be used. In addition, the curing of the conductive resin paste is 10
This is done by heating to 0-150°C.

In the above configuration, when bonding the Si chip 1 onto the circuit board 2 in a face-down manner, the protruding electrodes 4 of the Si chip 1 and the leads 3 of the circuit board 2...
are bonded using conductive resin paste.

In such a semiconductor device, when the ambient temperature changes, the circuit board 2 made of soda glass thermally expands based on its coefficient of linear expansion (approximately 8 x 10-', /''C); The Si chip l has a coefficient of linear expansion (approximately 2°4
In other words, when the ambient temperature changes, distortion occurs between the Si chip 1 and the circuit board 2 due to a very large difference in coefficient of thermal expansion. Accordingly, the lead 3... and the protruding electrode 4...
Stress concentration occurs at the connection with the However, in this embodiment, the rigidity of the Si chip 1 is reduced by the semi-gabled grooves 1a, so that the stress concentration occurring at the connection portion is significantly relaxed and reduced.

In order to confirm the above characteristics, the connection state of the connection portion was evaluated by measuring the contact resistance value after the conductive resin paste was cured. As a result, when there is no groove 1a, the contact resistance value tends to increase as the distance from the center of the Si chip increases. On the other hand, in the case of the Si chip 1 of this example, that is, when the grooves 1a... are formed on the back surface, this tendency is greatly reduced, and the contact resistance value is determined by the distance from the center of the Si chip. It was found that the stress concentration (related to

By the way, in this embodiment, a case is explained in which a Si chip is bonded face-down to a circuit board as a semiconductor device, but the bonding method is not limited to Si chips, and other group 4 semiconductors and compound semiconductors (3 -5 group and 2-6 group compound semiconductors, etc.), and the shape, depth, pitch, etc. of the grooves formed on the back surface of the Si chip 1 are also limited to those shown in this example. It's not something you can do. It is also applicable to mounting flat displays such as liquid crystal displays.

Note that the shape of the grooves 1a can be formed depending on the shape of the Si chip. For example, as shown in FIG. 3, in the case of a Si chip 21 having a nearly square plate shape, grooves 21a are formed in a grid pattern at predetermined intervals. Furthermore, as shown in FIG. 4, in the case of a long and thin plate-shaped Si chip 31 with a high aspect ratio,
1a... are formed parallel to each other at predetermined intervals in a direction perpendicular to the longitudinal direction.

〔Effect of the invention〕

As described above, the semiconductor device according to the present invention is a semiconductor device bonded onto a circuit board by a face-down method, and has a configuration in which a plurality of grooves are formed at predetermined intervals on the back surface.

As a result, the plurality of grooves formed on the back surface reduce the rigidity of the semiconductor device, and stress concentration occurring at the connection portion can be reliably alleviated. This also brings about effects such as reducing connection failures and improving reliability.

[Brief explanation of drawings]

1 and 2 show an embodiment of the present invention. FIG. 1 is a front view showing a state in which a Si chip is bonded onto a circuit board in a face-down manner, and FIG. FIG. 3 is a plan view showing the formation state of a groove in a nearly square Si chip, and FIG. 4 is a plan view showing another example. FIG. 5 is a plan view showing the formation of grooves in a Si chip with a large aspect ratio that is in the form of an elongated plate. FIG. FIG. 3 is a front view showing a state in which bonding is performed on the top. 1, 21, 31 are Si chips (semiconductor devices), 2 is a circuit board, 3... is a lead, 4... is a wiring electrode la.
...21a...31a... are grooves. Patent applicant Sharp Tomizu Tomizu Yoizu Tomizu Co., Ltd.

Claims (1)

[Claims] 1. A semiconductor device bonded onto a circuit board by a face-down method, characterized in that a plurality of grooves are formed at predetermined intervals on the back surface.