JPH06310626A - Semiconductor chip and semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the heat radiation efficiency and stabilize the semiconductor chip operation by forming recessed and projected parts on the rear face of a semiconductor chip board, arranging it within a package, and cooling it directly with a refrigerant. CONSTITUTION:A semiconductor chip 1 is contained in a package consisting of a base 4 and a cap 6. The semiconductor chip 1 is provided with a plurality of grooves 1e on the rear surface opposite to the main surface of a board 1a for forming elements, thereby increasing contact area between a refrigerant and the chip 1. An inlet 6a and an outlet 6b are formed on the upper surface of the cap 6 of the semiconductor package and they are connected with a cooling piping 8. In the piping 8, a florinate is sealed as a cooling medium and it is circulated therein by a pump. When the fluorinent cooled by the external cooling apparatus is made to flow into the package, the heat generating from the chip 1 is effectively absorbed thereby and the chip 1 is cooled. Therefore, the heat radiation effect can be improved, resulting in high density packaging.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip and a semiconductor integrated circuit device, and in particular, it is effective when applied to a semiconductor chip and a semiconductor integrated circuit device which generate a large amount of heat by mounting high-speed elements at high density. It is about technology.

[0002]

2. Description of the Related Art Semiconductor integrated circuit devices such as large-scale computers and supercomputers that perform arithmetic processing are mainly composed of high-speed bipolar transistors. In this type of integrated circuit device, the power consumption of the semiconductor chip tends to increase as the operating speed of the high-speed bipolar transistor increases, and the amount of heat generated from the semiconductor chip tends to increase.

When the temperature of the semiconductor chip rises, not only the operating characteristics of the bipolar transistor are changed, but also the wiring connecting the semiconductor chips is broken, which may cause fatal damage to the semiconductor chip. It is also conceivable that the temperature rise of the semiconductor chip causes thermal runaway and the device is destroyed. Therefore, in this type of semiconductor integrated circuit device, cooling of the semiconductor chip is indispensable.

As a cooling technique for this purpose, a heat dissipating member is provided on the cap of the package in which the semiconductor chip is sealed, or a heat transfer member is brought into contact with each of the semiconductor chips mounted on the substrate to form a semiconductor chip. A general method is to conduct heat to a water-cooling jacket attached to the upper surface of the cap of the sealed package, and circulate the cooling water in the water-cooling jacket for cooling.

However, in this method, since cooling is performed via the heat transfer member and the upper surface of the package, sufficient heat dissipation efficiency cannot be obtained due to the thermal resistance of the heat transfer member and the cap. Therefore, a technique has been proposed in which a cooling medium is circulated inside the package to directly exchange heat between the semiconductor chip and the cooling medium, thereby eliminating the thermal resistance and improving the heat radiation efficiency. (Japanese Patent Application No. 2-244432
issue)

[0006]

However, in the prior art, it is expected that the heat dissipation capability will be insufficient when the semiconductor integrated circuit devices with large power consumption in the future are mounted at high density. Therefore, there is a need for a cooling method with improved heat dissipation efficiency.

An object of the present invention is to provide a technique for ensuring stable operation of the semiconductor chip and enabling high-density mounting by providing a cooling technique with improved heat dissipation efficiency of the semiconductor chip. is there.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

A semiconductor package is mounted in a face-down manner, and unevenness is formed on the back surface of the substrate of a semiconductor chip which is directly cooled by a cooling medium introduced into the package. A semiconductor chip is attached by a face-down method, and irregularities are formed on the back surface of the substrate of the semiconductor chip of the semiconductor integrated circuit device in which the semiconductor chip is directly cooled by the cooling medium introduced into the package.

As a method for forming irregularities on the back surface of the substrate, for example, a method of partially etching is used.

[0012]

According to the above-described means, the surface area of the back surface of the semiconductor chip where heat is dissipated is increased, which increases the contact area between the cooling medium and the semiconductor chip, so that the heat dissipation efficiency is improved and high density mounting is performed. Stable operation is possible even with a semiconductor chip.

The structure of the present invention will be described below together with embodiments. In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and repeated description thereof will be omitted.

[0014]

EXAMPLE A semiconductor integrated circuit device of this example has a chip forming surface of a semiconductor chip and a base mounting surface facing each other.
A so-called face-down bonding method is used to mount a plurality of semiconductor chips on a base of a semiconductor package, and the base and a cap are welded by solder to form a package.

FIG. 1 is a vertical cross-sectional view showing a schematic structure of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a partial vertical cross-sectional view showing a portion A in FIG. 1 in an enlarged manner. . 3 to 6 are views for explaining a process of forming irregularities on a semiconductor chip mounted on the semiconductor integrated circuit device.

In the figure, 1 is a semiconductor chip. The semiconductor chip 1 has a plurality of semiconductor elements 1b formed on the element formation surface which is the main surface of a semiconductor substrate 1a made of single crystal silicon, and these semiconductor elements 1b constitute a predetermined circuit system. Above the element formation surface of the semiconductor substrate 1a (below in the figure), a plurality of wiring layers for connecting between the semiconductor elements 1a or between the circuits formed by the semiconductor elements 1a and an insulating layer for separating these wiring layers are provided. The multilayer wiring 1c is formed by alternately laminating. Aluminum or an aluminum alloy is used for the wiring layer, and silicon oxide or the like is used for the insulating layer. A bonding pad 1d of the semiconductor chip 1 is provided on the surface of the multilayer wiring 1c, that is, the surface of the final protective film of the uppermost layer (the lowermost layer in the figure) of the multilayer wiring.

In the semiconductor chip 1 of the present embodiment, a plurality of grooves 1e are provided on the back surface (upper surface in the figure) opposite to the main surface of the substrate 1a which is the element forming surface to form irregularities. Groove 1e
Are formed by etching using a photolithography technique at the wafer stage. The method will be briefly described with reference to FIGS.

First, the substrate 2 of the semiconductor wafer 2 in a dry state
The resist 3 is uniformly coated on the back surface of the side a opposite to the element formation surface using a spin coater, and prebaked in a baking oven to increase the adhesiveness between the resist 3 and the substrate 2a. The wafer in this state is shown in FIG.

Next, by using a photomask having a predetermined pattern formed thereon, the resist 3 is exposed to a predetermined pattern, and only the resist 3 which has been made soluble by exposure is dissolved and removed in a developing solution. Development, substrate 2
a The resist 3 on the back surface is formed in a predetermined pattern. The wafer in this state is shown in FIG.

Next, post-baking is performed to improve the adhesion between the resist 3 and the substrate 2a and the chemical resistance of the resist 3, and then the wafer 2 is dipped in an etching solution to remove the portion not covered with the resist 3. The groove 1e is formed by melting. The wafer in this state is shown in FIG.

After the etching, the wafer 2 is washed and dried to remove the remaining resist 3. The wafer 2 in this state is shown in FIG.

The wafer 2 is diced to separate the semiconductor chips 1, and each semiconductor chip 1 is housed in a package consisting of a base and a cap. .

In FIG. 1, reference numeral 4 is a base made of ceramic which is the base of the package. A multilayer wiring (not shown) is formed inside the base 4 of the package, a bonding pad 4a arranged corresponding to the bonding pad 1d of the semiconductor chip is provided on the upper surface of the base 4, and a printed board (not shown) is provided on the lower surface. Bonding pads 4b for connecting to (not shown) are provided. The bonding pad 4a provided on the upper surface of the base 4 and the bonding pad 4b provided on the lower surface are electrically connected by the multilayer wiring inside the base 4.

The semiconductor chip 1 and the base 4 are the base 4
The bonding pad 4a and the bonding pad 1d of the semiconductor chip 1 are aligned and thermocompression-bonded to electrically and mechanically connect via the solder electrode 5. Therefore, the bonding pads 1d and 4a have
A material having high wettability with the solder electrode 5 used when mounting the semiconductor chip on the base is used.

In the figure, 6 is a cap made of ceramics, which is mounted on the semiconductor chip 1 after the base 4 is mounted.
And the base 4 are joined by solder 7 to form a semiconductor package.

On the upper surface of the cap 6 of the semiconductor package,
An inlet 6a and an outlet 6b connected to the cooling pipe 8 are provided. The cooling pipe 8 communicates a cooler (not shown) provided outside with the package. Fluorinert, which is a chemically stable liquid, is used as the cooling medium, and the cooling pipe 8 is provided with a pump (not shown) for circulating the Fluorinert.

For cooling the semiconductor chip 1, the fluorinate cooled by the cooler is introduced through the cooling pipe 8 into the inlet port 6.
When flowing into the package from a, flowing inside the package, and passing through the back surface of the substrate 1a of the semiconductor chip 1, the heat generated by the operation of the element 1b formed on the semiconductor chip 1 is absorbed, and the heat flows out from the outlet 6b. Is done by doing. The outflowing Fluorinert is carried to the cooler by the cooling pipe 8, cooled again, and circulated again by the pump.

Further, in this embodiment, the unevenness is formed on the back surface of the substrate 2a by the etching process using the lithographic technique. However, as the method of forming the unevenness, other means exemplified below can be used. .

(A) A metal having a high heat transfer coefficient is partially deposited to form unevenness on the back surface of the semiconductor chip substrate.

(B) By attaching metal particles with an adhesive agent containing a ceramic or the like, unevenness is formed on the back surface of the substrate of the semiconductor chip.

(C) Asperities are formed on the back surface of the substrate of the semiconductor chip by performing mechanical grinding by back grinding using a coarse grindstone.

(D) A laser with weakened output partially melts the back surface of the substrate of the semiconductor chip to form irregularities.

The inventions made by the present inventors are as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, although Fluorinert was used as the cooling medium in the above-mentioned embodiments, other liquids or gases such as pure water can be applied to the present invention as the cooling medium, and the liquid is introduced and cooled by the vaporization phenomenon. It is also possible to discharge as.

Regarding the shape of the groove, it is also possible to adopt a triangular, semi-circular or other groove in addition to the rectangular shape used in this embodiment.

[0036]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) Since the surface of the back surface of the semiconductor chip is made uneven, the surface area of the back surface is increased and the contact area between the cooling medium and the semiconductor chip is increased, so that the heat dissipation efficiency is improved.

(2) Due to the effect (1), the semiconductor chip can be prevented from being overheated, so that stable operation of the semiconductor chip and the semiconductor integrated circuit device can be guaranteed.

(3) Due to the effect (1), the heat dissipation capability is improved, so that the semiconductor chip and the semiconductor integrated circuit device can be mounted at a higher density.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a schematic configuration of an embodiment of the present invention,

FIG. 2 is a partial cross-sectional view showing an enlarged portion A in FIG.

FIG. 3 is an explanatory view showing a process of forming unevenness on a wafer,

FIG. 4 is an explanatory view showing a process of forming unevenness on a wafer,

FIG. 5 is an explanatory view showing a process of forming unevenness on a wafer,

FIG. 6 is an explanatory diagram showing a process of forming irregularities on a wafer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 1a ... Substrate, 1b ... Element, 1c ... Multilayer wiring, 1d, 4a, 4b ... Bonding pad, 1e
... Grooves (unevenness), 2 ... Wafer, 3 ... Resist, 4 ... Base, 5 ... Solder electrode, 6 ... Cap, 6a ... Inlet, 6
b ... Outflow port, 7 ... Solder, 8 ... Cooling pipe.

Claims (3)

[Claims] 1. A semiconductor chip mounted on a semiconductor package by a face-down method and directly cooled by a cooling medium introduced into the semiconductor package, wherein a semiconductor substrate has irregularities formed on its back surface. Chips. 2. A semiconductor integrated circuit device in which a cooling medium is introduced into a semiconductor package to directly cool a semiconductor chip mounted on the semiconductor package by a face-down method, wherein irregularities are formed on the back surface of the substrate of the semiconductor chip. Semiconductor integrated circuit device. 3. The unevenness is formed on the back surface of the substrate of the semiconductor chip by etching.
The semiconductor chip according to claim 1 or the semiconductor integrated circuit device according to claim 2.