JP5090625B2 - 半導体デバイスを形成する方法およびシステム - Google Patents
半導体デバイスを形成する方法およびシステム Download PDFInfo
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
方法およびシステムは、簡単で、安価で、既存の技術に容易に適合されることが可能であるべきである。本発明は、これらのニーズに対処する。
好ましくは、クロスポイントメモリアレイは、半導体層がその間にあるように配列された、直交する2層の組の平行に離間した導体を含む。2つの導体の組は、行電極のそれぞれが、列電極のそれぞれを、正確に1つの場所において交差するように重ねられる行電極および列電極を形成する。
〔1〕 半導体デバイスを形成する方法であって、
基板(415)に3次元(3D)パターン(405)を形成すること、および、
前記半導体デバイスの所望の特性に従って、前記基板(415)上に少なくとも1つの材料(410)を堆積させることを含む半導体デバイスを形成する方法。
〔2〕 前記3Dパターン(405)を形成することは、
前記基板(415)上に材料の層(410)を堆積させること、
前記材料の層(410)内に3Dパターン(405)をインプリントすること、および、
前記3Dパターン(405)を前記基板(415)に転写することをさらに含む〔1〕に記載の半導体デバイスを形成する方法。
〔3〕 前記半導体デバイスは、クロスポイントメモリアレイ(600)を備える〔1〕に記載の半導体デバイスを形成する方法。
〔4〕 前記半導体デバイスは、トランジスタ、抵抗器、コンデンサ、ダイオード、ヒューズ、およびアンチヒューズのうちの少なくとも1つである〔2〕に記載の半導体デバイスを形成する方法。
〔5〕 3Dパターン(405)を前記材料の層(410)内にインプリントすることは、前記3Dパターン(405)を作製するのに3Dスタンピングツールを利用することをさらに含む〔2〕に記載の半導体デバイスを形成する方法。
〔6〕 半導体デバイスを形成するシステムであって、
3次元であるパターン(405)を基板(415)に形成する手段と、
前記半導体デバイスの所望の特性に従って、基板(415)上に少なくとも1つの半導体材料を堆積させる手段とを備える半導体デバイスを形成するシステム。
〔7〕 前記半導体デバイスは、クロスポイントメモリアレイ(600)を備える〔6〕に記載の半導体デバイスを形成するシステム。
〔8〕 前記3Dパターン(405)を形成する前記手段は、
前記基板(415)上に材料の層(410)を堆積させる手段と、
前記材料の層(410)内に3Dパターン(405)をインプリントする手段と、
前記3Dパターン(405)を前記基板(415)に転写する手段とをさらに備える〔6〕に記載の半導体デバイスを形成するシステム。
〔9〕 前記基板(415)上に少なくとも1つの半導体材料を堆積させる前記手段は、
2組の導体を、該2組の導体の間に半導体層(630)がある状態で堆積させて、行電極(610)のそれぞれが、列電極(620)のそれぞれを、正確に1つの場所において交差するように重ねられる前記行電極(610)、および列電極(620)を形成する手段とをさらに備える〔7〕に記載の半導体デバイスを形成するシステム。
〔10〕前記半導体デバイスは、トランジスタ、抵抗器、コンデンサ、ダイオード、ヒューズ、およびアンチヒューズのうちの少なくとも1つである〔7〕に記載の半導体デバイスを形成するシステム。
320 ドクターブレード
330 液体化合物
340 剥離(release)ドラム
405 3Dパターン
410 材料の層
415,715 基板
420 第1の露出部分
425 第2の露出部分
610 行電極
620 列電極
630 半導体層
720 第1金属層
720’ 第1金属層の残りの部分
730 第1平坦化ポリマー
730’ 第1平坦化ポリマーの残りの部分
740 第2金属層
740’ 第2金属層の残りの部分
750 第2平坦化ポリマー
750’ 第2平坦化ポリマーの残りの部分
Claims (3)
- 半導体デバイスを形成する方法であって、
基板に3次元(3D)パターンを形成する工程と、前記半導体デバイスは、3次元(3D)パターンを形成した前記基板にクロスポイントメモリアレイを形成するプロセスを備え、
前記3Dパターンを形成することは、
前記基板上に材料の層を堆積させる工程と、
前記材料の層内に3Dパターンをインプリントする工程と、
前記3Dパターンを基板エッチング工程によって前記基板に転写する工程とからなり、
前記基板エッチング工程は、3Dパターンがインプリントされた材料の層の一部をエッチングして基板の第1の部分を露出させる工程と、該基板の露出部分を選択的にエッチングする工程と、次に材料の層の別の部分を除去して基板の第2の部分を露出させる工程と、該基板の露出部分を選択的にエッチングする工程と、材料の層の残りの部分を除去する工程とからなり、
前記クロスポイントメモリアレイは、
前記3Dパターンがパターニングされた基板上に第1金属層を堆積させる工程(701)と、
第1平坦化ポリマーを前記第1金属層に塗布する工程(702)と、
反応性イオンエッチング(RIE)プロセスによって
前記第1平坦化ポリマーの一部を除去して第1金属層の一部を露出させ、それによってエッチングは、第1金属層に関して選択性を有する工程(703)と、
前記第1金属層の露出した一部をエッチングするために、前記第1平坦化ポリマーをエッチングマスクとして利用する工程(704)と、
前記第1金属層の残りの部分まで前記基板を選択的にエッチングする工程(705)と、
前記第1平坦化ポリマーの残りの部分を除去して前記第1金属層の残りの部分を露出させる工程(706)と、
第2金属層を前記第1金属層の残りの部分を含む基板上に堆積させる工程(707)と、
第2平坦化ポリマーを前記第2金属層の表面に塗布する工程(708)と、
反応性イオンエッチング(RIE)プロセスによって
前記第2平坦化ポリマーの一部を除去し、それによって、前記第2金属層の一部を露出させ、エッチングは、第2金属層に関して選択性を有する工程(709)と、
前記第2金属層の一部をエッチングするために、前記第2平坦化ポリマーをエッチングマスクとして利用する工程(710)と、
前記第2平坦化ポリマーの残りの部分を除去して前記一部の第1金属層の上に第2金属層を形成して行電極および列電極を形成する工程(711)と、
からなる半導体デバイスを形成する方法。 - 前記クロスポイントメモリアレイは、電極の行と列の間の複数の層により形成された複数のダイオードとアンチヒューズとから構成され、各ダイオードは前記行と列の交差のそれぞれにおいてヒューズと直列になっていることを特徴とする請求項1に記載の半導体デバイスを形成する方法。
- 3Dパターンを前記材料の層内にインプリントすることは、前記3Dパターンを作製するのに3Dスタンピングツールを利用することをさらに含む請求項1に記載の半導体デバイスを形成する方法。
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US10/769,127 US8148251B2 (en) | 2004-01-30 | 2004-01-30 | Forming a semiconductor device |
US10/769127 | 2004-01-30 |
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JP (1) | JP5090625B2 (ja) |
CN (1) | CN100405542C (ja) |
GB (1) | GB2411289B (ja) |
TW (1) | TWI386973B (ja) |
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US7195950B2 (en) * | 2004-07-21 | 2007-03-27 | Hewlett-Packard Development Company, L.P. | Forming a plurality of thin-film devices |
FR2890229B1 (fr) * | 2005-08-31 | 2007-11-09 | St Microelectronics Sa | Procede de formation d'un condensateur variable |
SG134178A1 (en) * | 2006-01-09 | 2007-08-29 | Agency Science Tech & Res | Microstructure formation technique |
US8049110B2 (en) * | 2008-10-01 | 2011-11-01 | Hewlett-Packard Development Company, L.P. | Microelectronic device |
US9034233B2 (en) * | 2010-11-30 | 2015-05-19 | Infineon Technologies Ag | Method of processing a substrate |
US20120305892A1 (en) * | 2010-12-08 | 2012-12-06 | Martin Thornton | Electronic device, method of manufacturing a device and apparatus for manufacturing a device |
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US6861365B2 (en) | 2002-06-28 | 2005-03-01 | Hewlett-Packard Development Company, L.P. | Method and system for forming a semiconductor device |
US6900881B2 (en) | 2002-07-11 | 2005-05-31 | Molecular Imprints, Inc. | Step and repeat imprint lithography systems |
JP3821069B2 (ja) * | 2002-08-01 | 2006-09-13 | 株式会社日立製作所 | 転写パターンによる構造体の形成方法 |
US7147790B2 (en) * | 2002-11-27 | 2006-12-12 | Komag, Inc. | Perpendicular magnetic discrete track recording disk |
GB0229191D0 (en) * | 2002-12-14 | 2003-01-22 | Plastic Logic Ltd | Embossing of polymer devices |
EP1806958A4 (en) * | 2004-10-29 | 2008-12-31 | Murata Manufacturing Co | CERAMIC MULTILAYER SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME |
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2004
- 2004-01-30 US US10/769,127 patent/US8148251B2/en not_active Expired - Fee Related
- 2004-07-27 TW TW093122384A patent/TWI386973B/zh not_active IP Right Cessation
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2005
- 2005-01-27 GB GB0501735A patent/GB2411289B/en not_active Expired - Fee Related
- 2005-01-28 CN CNB200510006706XA patent/CN100405542C/zh not_active Expired - Fee Related
- 2005-01-28 JP JP2005020698A patent/JP5090625B2/ja not_active Expired - Fee Related
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US20050170639A1 (en) | 2005-08-04 |
GB2411289B (en) | 2008-02-13 |
GB2411289A (en) | 2005-08-24 |
JP2005217417A (ja) | 2005-08-11 |
GB0501735D0 (en) | 2005-03-02 |
TW200525598A (en) | 2005-08-01 |
CN1649088A (zh) | 2005-08-03 |
CN100405542C (zh) | 2008-07-23 |
TWI386973B (zh) | 2013-02-21 |
US8148251B2 (en) | 2012-04-03 |
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