JP5043862B2 - 半導体構造およびその製造方法(相補型金属酸化膜半導体) - Google Patents
半導体構造およびその製造方法(相補型金属酸化膜半導体) Download PDFInfo
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/8232—Field-effect technology
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Description
A. Shimizu等の「LocalMechanical-Stress Control (LMC): A New Technique for CMOS-PerformanceEnhancement」、2001年、IEEE IEDM Tech.Digest、433〜436ページ Shinya Ito等の「MechanicalStress Effect of Etch-Stop Nitride and its Impact on Deep Submicron TransistorDesign」、2000年、IEEE IEDM Tech.Digest、247〜250ページ F. Ootsuka等の「A HighlyDense, High-Performance 130 nm Node CMOS Technology for Large ScaleSystem-on-a-Chip Applications」、2000年、IEEE IEDM Tech. Digest、575〜578ページ
Claims (6)
- 半導体構造であって、
(110)面を有する半導体基板と、
前記半導体基板上に配置され、<100>チャネル方向に沿って歪みチャネルをそれぞれが有する、少なくとも1つのnFETおよび少なくとも1つのpFETと、
を含み、
前記歪みチャネルの各々が、単一の引張応力を有するライナ、圧縮応力を有する浅いトレンチ分離(STI)領域、およびソース/ドレイン領域における引張応力を有する埋め込みウェルを含むことによって生じる、半導体構造。 - 前記半導体基板がバルク半導体材料または半導体オンインシュレータ(SOI)である、請求項1に記載の半導体構造。
- 前記半導体基板が緩和されているかまたは二軸歪みを有する、請求項1に記載の半導体構造。
- 半導体構造であって、
(110)面を有する半導体基板と、
前記半導体基板上に配置され、<100>チャネル方向に沿って歪みチャネルをそれぞれが有する、少なくとも1つのnFETおよび少なくとも1つのpFETであって、前記歪みチャネルが、前記少なくとも1つのnFETおよび前記少なくとも1つのpFETを覆う単一の引張応力を有するライナによって生じる、少なくとも1つのnFETおよび少なくとも1つのpFETと、
を含み、
前記少なくとも1つのnFETおよび前記少なくとも1つのpFETの各ソース/ドレイン領域内に配置された引張応力を有する埋め込みウェルを更に含む、半導体構造。 - 半導体構造であって、
(110)面を有する半導体基板と、
前記半導体基板上に配置され、<100>チャネル方向に沿って歪みチャネルをそれぞれが有する、少なくとも1つのnFETおよび少なくとも1つのpFETであって、前記歪みチャネルが、前記少なくとも1つのnFETおよび前記少なくとも1つのpFETを覆う単一の引張応力を有するライナによって生じる、少なくとも1つのnFETおよび少なくとも1つのpFETと、
を含み、
前記少なくとも1つのnFETと前記少なくとも1つのpFETとの間の圧縮応力を有するSTI領域、および、前記少なくとも1つのnFETおよび前記少なくとも1つのpFETの各ソース/ドレイン領域内に配置された引張応力を有する埋め込みウェルを更に含む、半導体構造。 - 半導体構造を形成する方法であって、
(110)面を有する半導体基板に配置された少なくとも1つのnFETおよび少なくとも1つのpFETを形成するステップを含み、前記少なくとも1つのnFETおよび前記少なくとも1つのpFETが双方とも<100>チャネル方向に沿って歪みチャネルを有し、
前記歪みチャネルの各々が、単一の引張応力を有するライナ、圧縮応力を有する浅いトレンチ分離(STI)領域、および引張応力を有する埋め込みウェルを含むことによって生じる、方法。
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US11/327,256 | 2006-01-06 | ||
US11/327,256 US20070158739A1 (en) | 2006-01-06 | 2006-01-06 | Higher performance CMOS on (110) wafers |
PCT/EP2006/069909 WO2007077125A1 (en) | 2006-01-06 | 2006-12-19 | Complementary metal oxide semiconductor |
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JP2009522795A JP2009522795A (ja) | 2009-06-11 |
JP5043862B2 true JP5043862B2 (ja) | 2012-10-10 |
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US (2) | US20070158739A1 (ja) |
EP (1) | EP1974377B1 (ja) |
JP (1) | JP5043862B2 (ja) |
CN (1) | CN101326631B (ja) |
TW (1) | TW200737417A (ja) |
WO (1) | WO2007077125A1 (ja) |
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US20070158739A1 (en) * | 2006-01-06 | 2007-07-12 | International Business Machines Corporation | Higher performance CMOS on (110) wafers |
US7485515B2 (en) * | 2006-04-17 | 2009-02-03 | United Microelectronics Corp. | Method of manufacturing metal oxide semiconductor |
US7829407B2 (en) * | 2006-11-20 | 2010-11-09 | International Business Machines Corporation | Method of fabricating a stressed MOSFET by bending SOI region |
US8236638B2 (en) * | 2007-04-18 | 2012-08-07 | Freescale Semiconductor, Inc. | Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner |
US20080290414A1 (en) * | 2007-05-24 | 2008-11-27 | Texas Instruments Incorporated | Integrating strain engineering to maximize system-on-a-chip performance |
JP2009076731A (ja) * | 2007-09-21 | 2009-04-09 | Renesas Technology Corp | 半導体装置およびその製造方法 |
DE102007046849B4 (de) * | 2007-09-29 | 2014-11-06 | Advanced Micro Devices, Inc. | Verfahren zur Herstellung von Gateelektrodenstrukturen mit großem ε nach der Transistorherstellung |
US20090142891A1 (en) * | 2007-11-30 | 2009-06-04 | International Business Machines Corporation | Maskless stress memorization technique for cmos devices |
US9842929B1 (en) | 2016-06-09 | 2017-12-12 | International Business Machines Corporation | Strained silicon complementary metal oxide semiconductor including a silicon containing tensile N-type fin field effect transistor and silicon containing compressive P-type fin field effect transistor formed using a dual relaxed substrate |
WO2018004607A1 (en) * | 2016-06-30 | 2018-01-04 | Intel Corporation | Co-integration of gan and self-aligned thin body group iv transistors |
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US6483171B1 (en) * | 1999-08-13 | 2002-11-19 | Micron Technology, Inc. | Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same |
US7001837B2 (en) * | 2003-01-17 | 2006-02-21 | Advanced Micro Devices, Inc. | Semiconductor with tensile strained substrate and method of making the same |
US7303949B2 (en) * | 2003-10-20 | 2007-12-04 | International Business Machines Corporation | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture |
US7319258B2 (en) * | 2003-10-31 | 2008-01-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip with<100>-oriented transistors |
US7057216B2 (en) * | 2003-10-31 | 2006-06-06 | International Business Machines Corporation | High mobility heterojunction complementary field effect transistors and methods thereof |
CN100539151C (zh) * | 2003-12-25 | 2009-09-09 | 富士通微电子株式会社 | 半导体装置及半导体集成电路装置 |
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US7803670B2 (en) * | 2006-07-20 | 2010-09-28 | Freescale Semiconductor, Inc. | Twisted dual-substrate orientation (DSO) substrates |
-
2006
- 2006-01-06 US US11/327,256 patent/US20070158739A1/en not_active Abandoned
- 2006-12-19 WO PCT/EP2006/069909 patent/WO2007077125A1/en active Application Filing
- 2006-12-19 CN CN200680046295XA patent/CN101326631B/zh not_active Expired - Fee Related
- 2006-12-19 EP EP06841454A patent/EP1974377B1/en not_active Not-in-force
- 2006-12-19 JP JP2008548965A patent/JP5043862B2/ja not_active Expired - Fee Related
-
2007
- 2007-01-03 TW TW096100240A patent/TW200737417A/zh unknown
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2008
- 2008-05-16 US US12/122,227 patent/US7968946B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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TW200737417A (en) | 2007-10-01 |
US20070158739A1 (en) | 2007-07-12 |
EP1974377A1 (en) | 2008-10-01 |
CN101326631A (zh) | 2008-12-17 |
JP2009522795A (ja) | 2009-06-11 |
US20080217691A1 (en) | 2008-09-11 |
WO2007077125A1 (en) | 2007-07-12 |
US7968946B2 (en) | 2011-06-28 |
EP1974377B1 (en) | 2012-09-12 |
CN101326631B (zh) | 2011-03-30 |
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