WO2018004607A1

WO2018004607A1 - Co-integration of gan and self-aligned thin body group iv transistors

Info

Publication number: WO2018004607A1
Application number: PCT/US2016/040443
Authority: WO
Inventors: Sansaptak DASGUPTA; Han Wui Then; Marko Radosavljevic; Sanaz K. GARDNER; Pavel M. AGABABOV
Original assignee: Intel Corporation
Priority date: 2016-06-30
Filing date: 2016-06-30
Publication date: 2018-01-04
Also published as: TWI749010B; TW201810612A

Abstract

Techniques are disclosed for forming integrated circuits configured with co-integrated group III-N transistors and group IV transistors. The diverse transistors can be formed in a neighboring fashion or otherwise adjacent to one another on a common substrate. The substrate is a semiconductor-on-insulator configuration. According to an embodiment, structural features of neighboring III-N transistors are used to define structural features of an intervening group IV transistor. So, for example, features of the III-N transistor structures are initially used as a mask to pattern the intervening group IV transistor structure and subsequently are later used as part of the III-N transistor structures, in some cases. In other cases, the III-N transistor structures are sacrificial in nature, in that they are removed after formation of the IV transistor feature. The self-aligned co-location techniques can be used to significantly reduce integration processing needed to form mixed transistor technology (e.g., silicon-containing transistors between GaN transistors).

Description

CO-INTEGRATION OF GAN AND SELF- ALIGNED THIN BODY GROUP IV TRANSISTORS

BACKGROUND

[0001] In the fields of wireless communication and power management, various components can be implemented using semiconductor devices such as transistors. For example, in radio frequency (RF) communication, the RF front end, which is a generic term for the circuitry between an antenna and a digital baseband system, may include multiple transistor-based components, such as switches and power amplifiers. Due, in part, to their large bandgap and high mobility, gallium nitride (GaN) and other group III-N semiconductor materials are suited to integrated circuits for applications such as high-frequency and high-power. In contrast, silicon and other group IV semiconductor materials are suited to integrated circuits for applications such as low-power.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 is a cross-sectional view of an integrated circuit structure configured with co- integrated group III-V NMOS transistors and group IV PMOS transistors on a common substrate, in accordance with an embodiment of the present disclosure.

[0003] Figure Γ is a cross-sectional view of an integrated circuit structure configured with co- integrated group III-V NMOS transistors and group IV PMOS transistors on a common substrate, in accordance with another embodiment of the present disclosure.

[0004] Figures 2 through 10 illustrate an example process for preparing an integrated circuit structure configured with co-integrated group III-V NMOS transistors and group IV PMOS transistors on a common substrate, in accordance with an embodiment of the present disclosure.

[0005] Figure 1 1 is an example computing system implemented with one or more of the integrated circuit structures as disclosed herein, in accordance with some embodiments of the present disclosure.

[0006] These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

[0007] Techniques are disclosed for forming integrated circuits configured with co-integrated group III-V transistors and group IV transistors. The diverse transistors can be formed in a neighboring fashion or otherwise adjacent to one another on a common substrate. The substrate is a semiconductor-on-insulator configuration (e.g., silicon-on-insulator). According to an embodiment, structural features of neighboring III-V transistors are used during the fabrication process to define structural features of an intervening group IV transistor. So, features of the III- V transistor structures are initially used as a mask to pattern the intervening group IV transistor structure and subsequently are later used as part of the III-V transistor structures, in some embodiments. In other embodiments, the III-V transistor structures initially used as a mask to pattern the intervening group IV transistor structure are sacrificial in nature, in that they are removed sometime after formation of the group IV transistor feature. The co-location self- aligned techniques can be used to significantly reduce integration processing needed to form mixed transistor technology on a common substrate, as will be appreciated.

General Overview

[0008] Currently, GaN PMOS has low performance. As such, silicon PMOS is a more suitable choice to implement CMOS operations in conjunction with GaN NMOS. However, co- integration of III-N material based devices (such as GaN NMOS transistors) with a silicon substrate is a significant challenge due to dissimilar properties of the GaN and silicon. For instance, GaN has a large lattice mismatch with silicon. In particular, the lattice mismatch between a GaN material and a silicon wafer along <111> crystallographic orientation is about 17%. Such a large lattice mismatch typically results in high defect densities in the III-N material grown on the silicon. In addition, a larger coefficient of thermal expansion mismatch also exists. For example, the mismatch in thermal expansion coefficient between GaN and silicon is about 116%, and this typically results in surface cracks on the III-N material grown on silicon. These defects significantly reduce the mobility of carriers (e.g., electrons, holes, or both) in the III-N materials and can also result in poor yield and reliability issues. To this end, existing techniques do not provide an efficient pathway for co-integration of both group III-N transistors with group IV transistors in CMOS circuits. In some cases, co-integration is handled by using two distinct substrates and forming processes that are carried out independently, and then a subsequent bonding process joins the separately formed substrates. There is a need, therefore, for integration schemes that enable co-integration of group III-N and group IV components on a common substrate for applications such as RF front ends, voltage regulator circuits, and other applications having a need for diverse material systems integration.

[0009] Thus, techniques are disclosed for forming integrated circuits configured with co- integrated group III-V transistors and group IV transistors. The diverse transistors can be formed in a neighboring fashion or otherwise adjacent to one another on a common substrate. The substrate is a semiconductor-on-insulator configuration, according to some embodiments. The substrate may be, for example, a relatively thin silicon layer on a buried oxide which is in turn provided on a silicon handle wafer or other suitable silicon platform. Either the top semiconductor layer on the insulator or the underlying semiconductor layer (e.g., handle wafer) can be used in forming either of the group III-V and the group IV transistors. So, for instance, both transistor types can be formed using the top semiconductor layer, or the III-V transistor can be formed using the bottom semiconductor layer and the IV transistor can be formed using the top semiconductor layer. An example integrated circuit configured in accordance with an embodiment has group III-N transistors configured for high power and/or high frequency (e.g., RF amplifier, RF switch, RF filter) and group IV transistors configured for relatively lower power applications (e.g., memory cells, logic), although many applications can benefit from the techniques as will be appreciated. The group III-N transistors can be, for example, n-type metal oxide semiconductor (NMOS) and the group IV transistors can be p-type metal oxide semiconductor (PMOS), thereby providing a complementary metal oxide semiconductor (CMOS) integrated circuit.

[0010] According to an embodiment, structural features of neighboring III-N (or III-V) transistors are used during the fabrication process to define structural features of an intervening group IV transistor. In one such example case, GaN lateral epitaxial overgrowth techniques are used to provide GaN islands in which a GaN transistor channel can be formed. These islands have well-controlled dimensions, depending on the growth process used as well as other factors such as the orientation of the underlying crystalline surface upon with the GaN is to be grown. In any case, the spacing between the neighboring GaN islands can be tightly controlled (e.g., in the range of 100 nm or smaller, even down to 10 nm or less). Thus, two neighboring GaN islands can be spaced from one another as desired to define, for instance, the gate length of the group IV transistor to be formed therebetween. The so-spaced islands are then effectively used as a mask to etch the group IV transistor gate trench. Note that the trench self-aligns to the neighboring GaN islands without any further masking or alignment processes. So, the GaN islands are initially used as a mask to pattern the intervening group IV transistor structure and subsequently can be later used as part of the III-N transistor structures, in some embodiments. In other embodiments, the GaN Islands are sacrificial in nature, in that they are removed sometime after formation of the group IV transistor feature. Numerous other example embodiments will be apparent.

[0011] As will be further appreciated in light of this disclosure, self-aligned co-location techniques as provided herein can be used to significantly reduce integration processing needed to form mixed transistor technology on a common substrate. Also, in some embodiments, the dimensions of the group IV transistor structures, particularly the gate length, can be made extremely small (e.g., 10 nm or smaller), which is very difficult to consistently produce across a given substrate using current processes and techniques. In contrast, the GaN overgrowth that forms the islands is highly predictable and controllable. Thus, patterning steps are reduced, as is the need for masks and additional alignment and planarization steps, which greatly simplifies the overall process, reduces cost and processing time.

[0012] As used herein, group IV semiconductor materials include, for example, silicon, germanium, carbon, tin, lead and alloys thereof such as silicon germanium (SiGe), silicon carbide (SiC), and germanium-tin (Ge-Sn), to name a few examples. In addition, group III-N semiconductor material (or III-N material or simply III-N) includes a compound of one or more group III elements (e.g., aluminum, gallium, indium, boron, thallium), with nitrogen. Accordingly, III-N material as used herein includes, but is not limited to, gallium nitride (GaN), indium nitride (InN), aluminum nitride (AIN), aluminum indium nitride (AlInN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN), to name a few examples of III-N materials. In a more inclusive manner, note that a group III-V material, as used herein, includes at least one group III element (e.g., aluminum, gallium, indium, boron, thallium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium nitride (GaN), gallium arsenide (GaAs), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs), to name some examples. Numerous group IV and III-V material systems can be used in various embodiments of the present disclosure.

[0013] Use of the techniques and structures provided herein may be detectable in cross- sections of an integrated circuit using tools such as scanning electron microscopy (SEM) or transmission electron microscopy (TEM) that can show the various layers and structure of the device. Other methods, such as composition mapping, x-ray crystallography or diffraction (XRD), secondary ion mass spectrometry (SIMS), time-of-flight SIMS (ToF-SFMS), atom probe imaging, local electrode atom probe (LEAP) techniques, 3D tomography, high resolution physical or chemical analysis, to name some suitable example analytical tools. In some embodiments, for instance, a SEM may indicate neighboring group IV structures and III-V structures (e.g., such as silicon PMOS and GaN NMOS) in a cross-section with each group IV structure having two neighboring group III-V structures so that the group IV structures and III-V structures alternate, and, further, that each group IV structure has a thin metal gate including adjacent gate spacers, with both the metal gate and the spacers positioned over a gate dielectric layer. Gate length may be, for example, 50 nm or less, or 40 nm or less, or 30 nm or less, or 20 nm or less, or 15 nm or less, or 10 nm or less, or 8. 5 nm or less, or 7 nm or less. Numerous configurations and variations will be apparent in light of this disclosure.

Architecture and Methodology

[0014] Figure 1 is a cross-sectional view of an integrated circuit structure configured with co- integrated group III-V NMOS transistors and group IV PMOS transistors on a common substrate, in accordance with an embodiment of the present disclosure. Note that the structure is shown in a cross-sectional view taken along an orthogonal -to-gate direction, as are the corresponding structures shown in Figures 2 - 10. As shown, integrated circuit 100 comprises a semiconductor-on-insulator (SOI) substrate having formed thereon a plurality of group IV transistors (101A, 101B) and a plurality of III-N transistors (102A, 102B). As can further be seen, transistor 101A is between transistors 102A and 102B, and transistor 101B is between transistors 102B and 102C. Although four transistors are shown, any number of transistors can be used in any number of alternating patterns, as will be appreciated. Further note that dummy transistor bodies may also be used (e.g., features of one or more dummy group III-V transistors can be used to form an intervening group IV transistor). To this end, the techniques provided herein can be implemented with both functional and dummified (non-functional) transistor configurations.

[0015] In the particular example embodiment shown in Figure 1, transistor 101A is a silicon (Si) transistor (e.g., PMOS), which is positioned between GaN transistors 102A and 102B (e.g., MOS). Likewise, transistor 101B is a Si transistor (e.g., PMOS) positioned between GaN transistors 102B and 102C (e.g., NMOS). As further shown, GaN transistor 102B is also between Si transistors 101 A and 101B. While, in certain embodiments, GaN transistors alternate with Si transistors, other configurations can also be implemented as will be appreciated in light of this disclosure. For example, in other embodiments, the integrated circuit structure 100 may comprise a plurality of groupings of first transistors between adjacent second transistors, such as InGaN transistors alternating with SiGe transistors, or AlGaN transistors alternating with Ge transistors, to name a few further example configurations.

[0016] The substrate can have any number of semiconductor-on-insulator (SOI) configurations, and may be implemented, for example, using a pre-fabricated SOI substrate or a bulk substrate having insulator and semiconductor layers formed thereon. In this example case, the SOI substrate includes a thin layer of Si on an insulator (e.g., silicon dioxide or other silicon- compatible insulator) which is in turn provided on a Si handle substrate (e.g., bulk silicon substrate). In other embodiments, the substrate may be configured differently. For instance, the SOI substrate may have a thin semiconductor layer of SiGe on a silicon dioxide layer on a bulk silicon wafer or substrate, wherein the Ge concentration of the SiGe layer can vary from around, for instance, 5% to 40%. In other such embodiments having a higher concentration of Ge (40% to 90%)), the substrate may include a graded buffer layer between the insulator layer and uppermost layer of SiGe that gradually increases the Ge concentration from a level compatible with the insulator layer to a target Ge level. In still other cases, note that the target level of Ge may be 100%> so as to provide a SOI substrate configuration of Ge/graded Ge-Si buffer/Si- compatible insulator/Si substrate. In still other cases, the SOI substrate configuration may be Ge/Ge-compatible insulator/Ge substrate. In a more general sense, the SOI substrate can be comprises any combination of group IV materials, such as Si, Ge, SiGe, or SiC. As will be further appreciated in light of this disclosure, the substrate may have a specific surface crystalline orientation, which can be described by a Miller Index. For example, the substrate may be have a <100>, <110>, or <111>, crystalline orientation, depending on the specific material used.

[0017] Generally, in the specific embodiment shown in Figure 1, the group III-N transistors 102A-C each include a source S, drain D, and gate G, along with a GaN channel layer and a polarization layer P for inducing a two-dimensional electron gas (2DEG) in the channel. Further note that the GaN channel layer is grown directly on the underlying silicon substrate in this example case. Each of the source S, drain D, and gate G may include a multilayer structure, including source/drain region materials, work function tuning materials, resistance reducing materials, and metal contact materials. In addition, gate spacers are provided to isolate the gate G from the source S and drain D. The group IV transistors 101 A-B also each include a source S, drain D, and gate G. Source and drain contacts C are provided, which may include a multilayer structure, including work function tuning materials, resistance reducing materials, and metal contact materials. A silicon (Si) channel region is provided between the source S and drain D and underneath the gate G. A gate dielectric GD is provided between the underlying Si channel and the gate G. Further note in this example embodiment that the gate dielectric GD is provided under both gate G and the corresponding adjacent gate spacers. Thus, in some embodiments, an integrated circuit is disclosed comprising a first transistor, such as a group IV transistor, and a second transistor, such as a III-N transistor (or other III-V transistor), and the first transistor comprises a gate and adjacent gate spacers, each positioned over, and, in some embodiments, on a gate dielectric layer.

[0018] As will be further appreciated, the gate of the transistor 101 can be centrally located between neighboring transistors 102 in a self-aligned fashion, as further shown in Figure 1. In some such embodiments, the distance between two neighboring group IV transistors 102 can be set to a nominal distance of X (e.g., in the range of 50 nm to 500 nm). Given the controlled growth rate of the III-N material used during formation of transistors 102, as will be further explained in turn, the distance Y from each of the neighboring transistors 102 is also controllable. So, the III-N material can be overgrown a specific distance Y and then used as a mask to form features of the transistors 101. Thus, it further follows that the distance W, which corresponds to gate length of transistor 101, is also controllable. So, for instance, the gate center of transistor 101 is at one-half the distance X from either neighboring transistor 102, and Y equals one-half the distance X minus 0.5W. These spatial relationships can be consistently repeated across the entire substrate given the self-aligning nature of the fabrication process, such that the gate center of the transistor 101 is approximately one-half the distance X from either neighboring transistor 102. Note that the gate center need not be precisely located at one-half the distance X from the neighboring transistor 102, but rather may be within a reasonable tolerance of that location. For example, the gate center may be within 10% of that location, or 7.5% of that location, or 5% of that location, or 3% of that location, or 2% of that location, or 1% of that location, or 0.5% of that location. In some specific example embodiments, the gate center is located at one-half the distance X from the neighboring transistor 102, +/- 3 nm, or +/- 2 nm, or +/- 1 nm. Further note that the tolerance may be asymmetric, such as +2/-1 nm. Without the self-aligning co-location techniques provided herein, such gate location consistency across a given wafer and in the context of a mixed transistor integrated circuit on a common substrate is very difficult to achieve.

[0019] Figure Γ shows another example embodiment similar to the embodiment shown in Figure 1, with one alteration. In particular, integrated circuit 100' includes all of the features of integrated circuit 100, but further includes a nucleation layer between the substrate and the GaN channel layer. The nucleation layer can be used to assist in starting the growth of GaN for transistors 102. In one such embodiment, for instance, the nucleation layer may include, for example, aluminum nitride (A1N) layer, or other suitable starter material. In still other embodiments, this layer may be further configured with buffering qualities in addition to nucleation.

[0020] Figures 2 through 9 illustrate a methodology for forming an example integrated circuit according to various embodiments of the present disclosure, along with the various resulting structures thereof. As can be seen, substrate 200 of the integrated circuit has a semiconductor- on-insulator structure (SOI) configuration, which generally includes a handle substrate or wafer 205, an insulator layer 210, and a semiconductor layer 215. In one specific example embodiment, substrate 200 comprises a bulk silicon substrate 205, silicon dioxide layer 210 (sometimes also referred to as a buried oxide layer or BOX layer), and a thin silicon layer 215. SOI 200 can be prefabricated or prepared. For example, a bulk silicon wafer, may be treated with an oxygen ion implantation process to form an implanted layer of oxygen and subsequently annealed to form a buried oxide layer separating a thin top silicon layer from a thicker bottom bulk silicon layer. For this process, the thin silicon layer 215 and the silicon substrate 205 would have the same crystalline orientation. Thus, in a specific embodiment, silicon substrate 205 and thin silicon layer 215 have the same crystalline orientation, such as, for example, a <100> orientation. In another example embodiment, a bulk silicon wafer is surface oxidized and treated with a hydrogen ion implantation process through the oxidized surface to form an imbedded hydrogen layer. A handle substrate, such as a second silicon substrate, can be attached to the oxidized surface, and the composite structure heated to cause exfoliation along the hydrogen layer, leaving a thin silicon layer 215 and oxide layer 210 attached to the handle silicon substrate 205. In this process, the silicon substrate (handle) 205 can have a different crystalline orientation than the top thin silicon layer 215, which can be utilized differently in various component building processes, such as those described herein. For example, in a specific embodiment, silicon substrate 205 has one crystalline orientation, such as a <111> orientation, while thin silicon layer 215 has a second different crystalline orientation, such as a <100> orientation. As will be appreciated, insulating layer 210 can be an oxide or nitride layer disposed between the thin silicon layer 215 and silicon substrate 205. In still other embodiments, each of the layers 210, 215, 220, and 230 can be provided with blanket deposition processes to form the multilayer stack. In addition, note that semiconductor layer 215 need not be limited to silicon, but can be other group IV semiconductors as well, such as Ge, SiGe, and SiC. In any such embodiments, insulator layer 210 has a thickness in the range of, for example, 10 nm to 2 microns (e.g., 200 nm to 1 micron), or any other suitable thickness. As will be appreciated in light of this disclosure, the thickness of the insulator layer 210 can be used to electrically isolate transistors formed in semiconductor layer 215 from the underlying substrate 205. Such isolation is helpful, for instance, in reducing sub-channel (or sub-fin) leakage. The thickness of the semiconductor layer 215 can also vary from one embodiment to the next, but in some cases is in the range of 5 nm to 500 nm (e.g., 10 nm to 200 nm). The thickness of the semiconductor layer 215 can be set based on the transistor device configuration being formed therein, and particularly based on the desired channel layer thickness and possibly the source/drain region thickness.

[0021] As further shown in Figure 2, a dielectric layer 220 is also provided over semiconductor layer 215 of SOI 200, and, furthermore shallow trench isolation (STI) layer 230 is provided over dielectric layer 220. In some embodiments, either or both of this layers 220 and 230 may include multiple material layers or a stacked configuration. In addition, one or more intervening layers may also be provided in some embodiments, as will be appreciated in light of this disclosure. The dielectric layer 220 can have any suitable dielectric constant, but in some embodiments is a high-k dielectric material, such as that suitable for a high-k gate dielectric of a group IV transistor configuration. In general, a high-k dielectric material includes material having a dielectric constant greater than that of silicon dioxide (a k-value greater than 3.9). Example high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, tantalum silicon oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, silicon oxide, lead scandium tantalum oxide, and lead zinc niobate, to name some examples. In some embodiments, an annealing process may be carried out on the dielectric layer 220 to improve its quality. The thickness of the dielectric layer 220 can vary from one embodiment to the next, but in some cases is in the range of 1 nm to 20 nm (e.g., 5 nm to 10 nm), depending on the end use or target application.

[0022] The STI layer 230 may include any suitable insulator or isolation materials, such oxides (e.g., silicon dioxide or aluminum oxide) and/or nitrides (e.g., silicon nitride or silicon oxynitride), to name a few examples. In some embodiments, STI layer 230 may include multiple material layers or a stacked configuration. The STI layer 230 can have any suitable dielectric constant, but in some embodiments is a low-k dielectric material, such as that suitable for providing electric isolation between neighboring transistors. In general, a low-k dielectric material includes material having a dielectric constant less than that of silicon dioxide (k of less than 3.9. Example low-k dielectric materials include, for instance, porous silicon dioxide, porous silicon nitride, carbon or fluorine doped silicon dioxide, porous carbon doped silicon dioxide, spin-on polymeric dielectrics, to name some examples. The thickness of the STI layer 230 can vary from one embodiment to the next, but in some cases is in the range of 50 nm to 2 microns (e.g., 200 nm to 1 micron), depending on the end use or target application and as will be appreciated.

[0023] As will be further appreciated in light of this disclosure, each of these layers 205, 210, 215, 220, and 230 can be used to form various features and components of the integrated circuit 100, as will be described in turn. Further note that, in some embodiments, each of these layers 210, 215, 220, and 230 can be sequentially provided over substrate 205 in a blanket fashion using standard processing, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), oxidation, and implantation processes, to name a few examples. One the multilayer structure of Figure 2 is formed, the methodology can continue to form the various devices. Note that in some embodiments, the structure can be completed in advance or otherwise acquired for subsequent use with respect to the methods shown in Figures 3 through 10.

[0024] Figure 3 shows the resulting structure after trenches have been formed for group III-V transistor growth, according to an embodiment. As can be seen in this example case, portions of STI layer 230, dielectric layer 220, semiconductor layer 215, and insulator layer 210 are removed thereby forming trench 335 over and exposing the underlying substrate 205. In one such case, the substrate 205 can have a crystal orientation of 111 with respect to the trench direction. Such a 111 orientation is well-suited for growth of III-N materials such as GaN. In other embodiments, trench 335 may land on a different layer of the structure, such as semiconductor layer 215, which may also provide a specific orientation suitable for growth of transistor materials. Although a number of etch schemes can be used to form trenches, one embodiment employs a combination of wet and/or dry etch processes. For example, if the STI layer 230 is silicon nitride and the dielectric layer 220 is silicon dioxide, a wet etch process including hot phosphoric acid can be used to etch through the STI layer 230 to expose the underlying dielectric layer 220. This wet etch can then be followed by a dilute hydrofluoric (HF) acid or trimix acid dip to pattern etch the dielectric layer 220, thereby exposing the underlying semiconductor layer 215. If trenches 335 are to land on the lower substrate 205, then further etching can be used to remove the semiconductor layer 215 and insulator layer 210. The etchant for this layer can be selected, for instance, based on it selectivity to crystal orientation, thereby providing an anisotropic etch. For instance, if the semiconductor layer 215 is silicon and the trench is oriented in the 100 crystal direction, then an etchant such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) can be used to etch that layer 215 in the 100 crystal direction much faster than it will in the 111 direction. Other such selective or so- called anisotropic etch schemes can be used as well, depending on factors such as the composition of layer 215 and the orientation of the trench 335 with respect to the crystal orientation. Directional dry etching can also be used. Dimensions of trench 335 can vary from one embodiment to the next, but in some cases, each trench 335 has a cross-sectional opening in the range of 50 nm to about 50 μιη.

[0025] After forming of trenches 335, the methodology continues with filling the trenches with III-V material from which the group III-V transistors of the circuit result are formed. Example embodiments are illustrated in Figure 4 A, Figure 4B, and Figure 4C. As can be seen, the structures of this example embodiment generally include a III-V semiconductor body 440, a III- V polarization layer 445 for inducing a 2DEG in a channel of the semiconductor body 440, and an overgrowth of III-V semiconductor material 450 (450A, 450B, or 450C, in respective embodiments illustrated in Figures 4A-C). Other embodiments may include other layers, as there are many configurations of group III-V transistors, and any such configurations can be implemented accordance with an embodiment of the present disclosure, as will be appreciated. For instance, and as previously explained with reference to Figure Γ, the first layer formed in trenches 335 may optionally be a nucleation layer of, for example, A1N layer having a thickness in the range of about 10 nm to 400 nm (e.g., ~ 50 nm). In one example embodiment, the III-V semiconductor body 440 is a III-N material such as GaN or InGaN, which are particularly well- suited to high power applications due, in part, to their wide bandgap, high critical breakdown electric field, and high electron saturation. The polarization layer 445 can be, for example, A1N, AlInN, AlGaN, or AlInGaN. The overgrowth of III-V semiconductor material 445 can be GaN, for example, or other III-V material that can be overgrown in a predictable or otherwise consistent fashion, as will be appreciated in light of this disclosure. As will be further appreciated in light of this disclosure, given such a predictable overgrowth pattern, the distance W between overgrowth regions of neighboring group III-V transistors can be reliably determined. Further note that the overgrowth of III-V semiconductor material can have different shapes [0026] Formation of the III-N features 440, 445, and 450 (and any other layers, such as a nucleation layer) may be performed using any number of deposition techniques, including, for example, metal-organic chemical vapor deposition (MOCVD), molecular-beam epitaxy (MBE) chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD). As discussed above, GaN has a large lattice mismatch with Si and a large mismatch in coefficient of thermal expansion, typically resulting in high defect densities in GaN material grown on Si. Therefore, in some embodiments, high quality GaN on Si is grown using lateral epitaxial overgrowth (LEO) conditions. Such LEO processing may include, for example, growing a GaN body 440 on Si substrate 205 within a patterned trench 335 and subsequently allowing material to overgrow the trench 335, forming lateral overgrowth regions 450A, 450B, or 450C. In this way, defects that may be present within the grown material are able to bend or are otherwise reduced as material forms over the STI layer 230, leaving the remainder of the GaN material 440 suitable for transistor channel use.

[0027] In one example process flow, growth of the III-V semiconductor body 440, such as GaN, can be interrupted or modified to form the polarization layer 445. For example, in some such example embodiments, a GaN body 440 is grown to just below the surface of the STI layer 230, after which the deposition process parameters are modified to transition from growing GaN to growing polarization layer 445 material. After the relatively thin polarization layer 445 is formed, the deposition process parameters can once again be modified to transition from growing the polarization layer 445 to growing GaN thereby allowing for continued lateral epitaxial overgrowth of GaN 450. The polarization layer 445 may include any suitable materials, such as one or more III-V materials, and more specifically in some embodiments, one or more III-N materials, for example. In some embodiments having a GaN body 440, polarization layer 445 includes aluminum, such that the layer includes at least one of AIN, AlGaN, InAlN, and InAlGaN. The polarization layer 445 effectively increases carrier mobility in the transistor channel region in the GaN body 440 to induce a 2DEG. In such cases, polarization layer 445 generally includes material having a higher bandgap than the material of the III-N body 440 to form the 2DEG. For example, in some embodiments, the semiconductor body 440 is GaN and the polarization layer 445 is AIN and/or AlGaN. In some embodiments, polarization layer 445 may have a multilayer structure including multiple III-V materials, wherein one of the layers in the multilayer structure may be present to further increase carrier mobility in the transistor channel region and/or to improve compatibility (e.g., density of interface traps) between the polarization layer 445 and overlying layers. In some embodiments, polarization layer 445 may or may not include grading (e.g., increasing and/or decreasing) the content of one or more materials in at least a portion of the layer. Note that the thickness of the polarization layer 445 may also vary from one embodiment to the next, and may be, for example, in the range of 1 nm to 20 nm (e.g., 5 nm to 10 nm).

[0028] Conditions for overgrowth of III-V semiconductor material 450 can be used to vary the properties of the resulting epitaxially grown structure. In some embodiments, faceting of the III- V overgrowth region, or cap, is controlled by, for example, the V/III ratio for depositing the material and on the growth temperature and pressure. In general, increasing the V/III ratio favors rectangular facet formation, such as cap 450B shown in Figure 4B and cap 450C shown in Figure 4C, as does increasing deposition temperatures and decreasing pressures. Also in general, lower V/III ratios, lower temperatures, and higher pressures favor triangular facet formation, such as cap 450A shown in Figure 4A. In addition, the orientation of trench 335 used for III-V body 440 growth can lead to different facets for the resulting overgrowth regions 450A-C. In one specific embodiment, for example, for a <100> Si substrate 205 and GaN 450, a trench 335 orientation along the <110> direction favors triangular facets (Figure 4A). In another example embodiment, for a <100> Si substrate 205 and GaN 450, trench 335 orientation along the <100> direction favors rectangular facets (Figure 4B or 4C). In another example embodiment, for a <111> Si substrate 205 and GaN 450, trench 335 orientation along the <112> direction favors triangular facets (Figure 4A).

[0029] As will be appreciated in light of the present disclosure, lateral epitaxial overgrowth techniques can be used to form III-V transistor features that can be used to precisely determine various features, such as the gate length, Lg, of a transistor positioned in between those III-V transistors. For example, as shown in Figures 4A-C, formation of lateral overgrowth regions 450A, 450B, and 450C on STI layer 230 results in formation of gap 460 of width W between neighboring caps. Lateral overgrowth can be continued as needed, increasing the size of the caps 450 and thereby correspondingly reducing the width of the gap 460 in between, until a specified or targeted gap width is achieved. Overgrowth can then be stopped, such as by ending the supply of reagents needed for continued growth, or otherwise adjusting the process to halt growth, such as by reducing temperature or increasing pressure beyond given growth thresholds. In this way, the width of the gap can be controlled in a relatively precise manner and, in some embodiments of the present disclosure, extremely small gaps 460 can be consistently produced by controlling the process conditions of lateral epitaxial overgrowth. For example, gaps having a width of less than about 100 nm, such as less than about 75 nm, or less than about 50 nm, or less than 25 nm, or less than 15 nm, or less than 10 nm (e.g., 1 nm to 9 nm gaps) can be achieved using the methods described herein.

[0030] The gap 460 can then be used to form the gate of an intervening transistor, such as a Si PMOS or other group IV transistor. Thus, the gate of a first transistor, such as a Si transistor, if positioned, and, in some embodiments, centrally positioned, between adjacent second transistors, being substantially equidistant between the second transistors. After formation of the gate, the III-V overgrowth regions 450 can be removed, and the underlying body 440 and polarization layer 445 can be used to form III-V transistors, such as GaN MOS transistors. Thus, in effect, the lateral epitaxial overgrowth regions 450 are used as a temporary mask in forming the gate or other features of a transistor positioned therebetween. The resulting integrated circuit comprises a first material system device between two second material system neighboring devices, and the second neighboring devices effectively define the position and dimensions of at least one feature of the first device.

[0031] Further details of an example embodiment are illustrated in Figures 5-7. As shown in Figure 5, neighboring caps 450 are lateral epitaxial overgrowth regions formed on polarization layer 445 over III-V semiconductor body 440 and extend over STI layer 230, forming a gap having a width W. While caps 450A are shown, the same methodology can be used for caps 450B and 450C, as will be appreciated in light of this disclosure. So, reference to the caps or regions 450A, 450B, or 450C going forward will simply be caps or regions 450. The exposed portion of STI layer 230 can be removed by various etching processes to form gate trench 570, which, in this embodiment is a cavity in STI layer 230 exposing a portion of dielectric layer 220. Thus, in some embodiments, etching occurs through the STI layer and stops at the dielectric layer 220. Any number of etching processes can be used to selectively remove the STI layer 230 without removing the dielectric layer 220 or regions 450, including various selective wet or dry isotropic etches (providing anisotropic or directional etching through the STI layer). During etching, the III-V caps 450 remain or otherwise have an etch rate that is substantially less than the etch rate of the STI 230 material, for the given etch chemistry. As such, the lateral epitaxial overgrowth regions essentially act as a mask for forming the gate feature. For example, according to an embodiment, if the STI layer 230 is silicon nitride, the overgrowth region 450 is GaN, and the dielectric layer 220 is silicon dioxide or a high-k dielectric such as hafnium oxide, a wet etch process including hot phosphoric acid can be used to etch STI layer 230, exposing the underlying dielectric layer 220, with relatively minimal removal of the GaN regions 450 and dielectric layer 220. [0032] As further shown in Figure 5, note the spatial relationship of the trench 570 with respect to the neighboring III-V semiconductor bodies 440. In particular, the inward-facing edge of each neighboring III-V semiconductor body 440 defines a distance of X between those edges. Each overgrowth region 450 extends a distance of Y from the edge of its corresponding body 440. Presuming a predictable growth pattern of the neighboring overgrowth regions 450, such distance Y is also predictable, as is the width W. It further follows that the center of trench 570 will be at a distance of X/2 from either edge of the neighboring overgrowth regions 450. As previously explained, a reasonable tolerance can be allowed for to the actual center of the trench 570 with respect to the neighboring overgrowth regions 450, depending on factors such as the value of X (the greater the value of X, the greater the tolerance allowed). For instance, in some cases, the center of trench 570 (as seen in cross-section) may deviate from the location of X/2 by up to 10% of X/2 in either direction, while other embodiments have a tighter tolerance of 5% or less, or 2.5% or less. As will be appreciated in light of this disclosure, such consistent trench placement, particularly for relatively narrow trenches 570 (e.g., <20 nm), is very difficult using standard processes.

[0033] As shown in the example embodiment illustrated in Figure 6, the trench 570 formed in the STI layer 230 can be filled with a metal to form gate 680 between neighboring caps 450. Any suitable gate metal deposition processes can be used (e.g., CVD, PVD, MBE), which can then be followed by various etching, polishing, planarization, and clean processes, in some embodiments. The gate 680 may be, for example, polycrystalline silicon, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), ruthenium (Ru), nickel (Ni), palladium (Pd), platinum (Pt), and titanium nitride (TiN), to name a few examples. In this example embodiment, note that caps 450 define the gate length, Lg, of gate 680 formed in STI layer 230. Thus, as described herein, the extent to which the caps 450 extend over the STI layer 230 can be controlled as needed to provide a gap having a width required for a targeted Lg value of a gate for an intervening transistor, according to some embodiments.

[0034] As shown in Figure 7, once the trench-based feature has been formed (a transistor gate, in the example embodiment shown), the process may continue with removing the overgrowth regions 450, in accordance with an embodiment. The overgrowth regions 450 can be removed using any number of suitable processes such as, for example, planarization followed by polishing, or an etch selective to the region 450 material. Various intervening processes may also be included. In still other embodiments, note that the overgrowth regions 450 may not be removed, or may be only partially removed or otherwise further shaped and tailored for subsequent use in a III-V device.

[0035] After removal of the overgrowth regions 450, various further features and/or layers can be provided, according to some embodiments. For example, as shown in Figure 8A, directional etching of STI layer 230 and of dielectric layer 220 can be used to form or otherwise shape gate spacers 891 alongside gate 680 as well as remaining STI material 892 alongside polarization layer 445 and III-V body 440. Note that 891 and 892 can be the same material as STI 230. Any number of etching processes can be used, such as, for example, dry etching in CF₄, CF₄/0₂/Ar, Cl₂/0₂, or HBr/CF₃, which are particularly useful for highly directional etch removal of the STI layer, providing, in some embodiments, parallel or nearly parallel sidewall and gate spacers. In addition, etching of the polarization layer 445 and GaN body 440 (or other suitable III-V body 440) is avoided in some embodiments. Masking can be used to facilitate the selectivity of the spacer etch process, as needed.

[0036] The depth of the spacer etch can vary from one embodiment to the next, depending on the source/drain configuration. In the example case shown in Figure 8A, the etch stops on the semiconductor layer 215. In such case, the methodology may further include ion implantation to dope the layer 215 to form source and drain regions to either side the gate 680. For example, in one such embodiment, where layer 215 is silicon, the exposed portion of layer 215 can be p- doped (e.g., boron, gallium, aluminum) by implantation. In the example case shown in Figure 8B, the etch stops continues through the semiconductor layer 215 (e.g., using standard anisotropic or directional etching) and lands on the underlying insulator layer 210. In such cases, the methodology may further include epitaxial regrowth of the source and drain regions. For example, epitaxial silicon or SiGe or germanium can be grown in the source drain regions, or some other replacement source/drain material. In such embodiments, note that the replacement S/D material can be grown, for instance, from the sidewalls of the exposed semiconductor layer 215 (e.g., silicon or SiGe may grow from Si layer 215, or germanium or SiGe may grow from Ge layer 215, according to some embodiments). Doping of the epitaxial material can be done in situ (during deposition) or afterward by implantation. The source/drain regions may include additional layers in some embodiments, such as graded buffer layers to transition to a desired concentration of a given component (concentration of a semiconductor material such as germanium, or a dopant concentration) and/or contact resistance reducing layers and/or work function tuning layers.

[0037] Thus, according to some embodiments, STI layer 230 can be used to provide gate spacers 891 and sidewall spacers 892, and dielectric layer 220 is used to provide gate dielectric layer 220. Note how the gate dielectric 220 is underneath the gate spacers 891. In a typical group IV transistor configuration, the gate dielectric material is not under the gate spacer, but rather is between the gate spacer only. Thus, a tell-tale indicator of a structure formed in accordance with some embodiments of the present disclosure is a gate spacer over a gate dielectric, which may further be in combination with a gate that is centrally located between two neighboring transistors, which may further be in combination with a gate that is relatively narrow.

[0038] Continuing with the methodology, once the gate spacers 891 are formed, along with the resulting source/drain trenches to a desired depth as previously explained, the source/drain regions and contacts can be formed, according to an embodiment. In an example embodiment illustrated in Figure 9, source/drain regions 995 (further labelled S and D) are provided on or above the insulator layer 210 either by implant doping of the semiconductor layer 215 on the insulator layer 210 (as explained with respect to Figure 8 A), or by epitaxial growth of replacement source/drain material on or above the insulator layer 210 (as explained with respect to Figure 8B). Other embodiments may employ other source/drain regions 995 forming techniques, as will be appreciated. As will be further appreciated, source/drain regions 995 may include any number of materials (e.g., silicon, germanium, SiGe) and doping schemes (e.g., undoped, n-type doped, or p-type doped). For example, in an embodiment where the structure comprises a silicon layer 215 on an oxide layer 210 and the transistor device is configured to be a PMOS device, source/drain regions 995 may include, for instance, boron doped Si or SiGe. In another example embodiment, where the transistor device is configured to be an NMOS device, source/drain regions 995 may include, for instance, phosphorus doped Si. Doping concentrations can be set as desired (e.g., doping amounts of around 2E20 per cubic cm). As previously explained, the S/D regions 995 may have a multi-layer structure including multiple material layers. For instance, in some embodiments, a passivation material may be deposited prior to the deposition of the primary S/D material to assist with the quality of the interface between the S/D material and the material of the layer beneath. Further, in some embodiments, a contact- improving material may be formed on the top of the S/D regions to assist with making contact to S/D contacts, described below, for example. In some embodiments, the S/D regions may include grading (e.g., increasing and/or decreasing) the content of one or more materials in at least a portion of the regions.

[0039] As can be further seen in Figure 9, the methodology continues with providing S/D contacts 996 are provided over the S/D regions 995 and may include any suitable material, such as a conductive metal or alloy (e.g., aluminum, tungsten, silver, nickel-platinum, or nickel- aluminum). In some embodiments, S/D contacts 996 may include a resistance reducing metal and a contact plug metal, or just a contact plug, depending on the end use or target application. Example contact resistance reducing metals may include silver, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys. The contact plug metal may include, for instance, aluminum, silver, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy can be used, depending on the end use or target application. In some embodiments, additional layers may be present in the S/D contacts region, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired. In some embodiments, metallization of the S/D contacts 996 may be carried out, for example, using a silicidation or germanidation process (e.g., generally, deposition of contact metal onto silicon or germanium containing S/D regions 995 followed by annealing). Numerous S/D configurations will be apparent in light of this disclosure.

[0040] As can be seen in Figure 10, once the group IV transistor formation is completed, the methodology continues with forming additional features of the group III-V transistors, according to an embodiment. For instance, in the example case shown, source/drain regions 1097 (also labeled S and D) are provided adjacent the 2DEG channel induced in the III-V body 440 by polarization layer 445. In addition, a gate 1099 is provided over the channel. S/D regions 1097, in some embodiments, can be formed using any suitable techniques, as will be apparent in light of the present disclosure. For example, in some embodiments, S/D regions 1097 may be formed by any combination of optional patterning/masking/lithography/etching with depositing, growing, and regrowing the S/D region 1097 material(s), which may then be followed by a planarization and/or polish process, for instance. Note that although S/D regions 1097 are shown as one continuous portion in Figure 10, in some embodiments, the S/D regions 1097 may include multiple portions, such as S/D material adjacent to the channel region (which is the top portion of III-V layer 440) and S/D contacts above the S/D material. However, in some embodiments, the first layer of an interconnect layer above depicted device layer may be considered S/D contacts for S/D regions 1097. Regardless of the configuration, in some embodiments, the S/D material (which will be in at least a portion of the S/D region 1097) may include any suitable material, such as III-V material, III-N material, and/or any other suitable material(s), as will be apparent in light of this disclosure. In addition, in some embodiments, the S/D region 1097 material may be doped in an n-type or p-type manner, for example, using any suitable doping techniques. In an example embodiment, S/D regions 1097 may include indium and nitrogen (e.g., InN or InGaN) and may be doped in an n-type manner (e.g., doped with Si, Se, and/or Te, with doping amounts of around 2E20 per cubic cm). In some embodiments, one or both of the S/D regions 1097 may have a multilayer structure including multiple materials. In some embodiments, one or both of the S/D regions 140 may or may not include grading (e.g., increasing and/or decreasing) the content of one or more materials in at least a portion of one or both of the regions. Further note that the source-gate spacing may be different than the drain- gate spacing, in some embodiments, depending on the desired breakdown voltage of the III-V device.

[0041] As previously explained, in some embodiments, S/D regions 1097 may include S/D contacts. In some such embodiments, S/D contacts may include any suitable material, such as a conductive metal or alloy (e.g., aluminum, tungsten, silver, nickel-platinum, or nickel- aluminum). In some embodiments, S/D contacts may include a resistance reducing metal and a contact plug metal, or just a contact plug, depending on the end use or target application. Example contact resistance reducing metals include silver, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys. The contact plug metal may include, for instance, aluminum, silver, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy can be used, depending on the end use or target application. In some embodiments, additional layers may be present in the S/D contact regions 1097, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired. Note that, in some embodiments, gate stack processing may be performed prior to the formation of S/D regions 1097, while in other embodiments, gate stack processing may be performed after the formation of S/D regions 1097, for example. The gate stack can be tailored as desired.

Example System

[0042] Figure 11 illustrates a computing system 1000 implemented with integrated circuit structures or devices as disclosed herein, in accordance with an example embodiment. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

[0043] Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices configured in accordance with an example embodiment (e.g., mixed III-V and IV transistors on a common substrate, having self-aligned qualities). In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

[0044] The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. In some embodiments, communication chip 1006 may include one or more mixed transistor structures on a common substrate as variously described herein.

[0045] The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0046] The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices as variously described herein. As will be appreciated in light of this disclosure, note that multi- standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In one example embodiment, the processor 1004 and communication chips 1006 are integrated into a single chip or chip set, such as a system-on-chip (as generally indicated by a dashed line around those components). In one such case, logic circuitry of the processor 1004 can be implemented, for example, in silicon or SiGe, and the RF circuitry of the communication chips 1006 can be implemented in GaN, and the logic for RF and mixed signal processing can be implemented in GaN NMOS and silicon PMOS, using the various mixed transistor techniques provided herein. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

[0047] In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices configured as variously described herein.

Further Example Embodiments

[0048] The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

[0049] Example 1 is an integrated circuit, comprising: a semiconductor-on-insulator substrate including a buried insulator layer disposed between upper and lower semiconductor layers of group IV material; and a first transistor between two adjacent second transistors, wherein the first transistor has a channel region included in the upper semiconductor layer, and each of the second transistors comprises a group III-N semiconductor structure that either is on the upper semiconductor layer, or alternatively, passes through the upper semiconductor layer and the buried insulator layer and is on the lower semiconductor layer.

[0050] Example 2 includes the subject matter of Example 1, wherein the III-N semiconductor structure for each second transistor is in a trench having a bottom on the upper semiconductor layer.

[0051] Example 3 includes the subject matter of Example 1, wherein the III-N semiconductor structure for each second transistor is in a trench that passes through the upper semiconductor layer and the buried insulator layer, and has a bottom on the lower semiconductor layer.

[0052] Example 4 includes the subject matter of Example 3, wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to the trench direction, and the crystal orientation for the lower semiconductor layer is the same as the crystal orientation of the upper semiconductor layer.

[0053] Example 5 includes the subject matter of Example 3, wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to the trench direction, and the crystal orientation for the lower semiconductor layer is different from the crystal orientation of the upper semiconductor layer.

[0054] Example 6 includes the subject matter of any of the preceding Examples, wherein the first transistor has a gate that is centrally positioned between the second transistors, such that the second transistors are separated by a distance X, and the center of the gate is at a location between the second transistors, and the location is within one-half the distance of X, plus or minus 1 nm.

[0055] Example 7 includes the subject matter of Example 6, wherein the configuration of a first transistor between two adjacent second transistors is repeated a plurality of times, and the corresponding gate location for each such configuration is within one-half the corresponding distance of X, plus or minus 1 nm. In other Examples, this tolerance may be larger (e.g., +/-5 nm) or smaller (+/-0.5 nm), depending on factors such as the distance between opposing sides of the second transistors.

[0056] Example 8 includes the subject matter of any of the preceding Examples, wherein first transistor has a gate that is substantially equidistant between the second transistors. So, for instance, a centroid of the gate structure is located on an imaginary vertical line that is substantially equidistant between the second transistors. The location of the imaginary vertical line need not be precisely equidistant, but rather be within a tolerance thereof, such as within X nm of the location, where X is 10% of the total distance between opposing edges of the second transistors, where X is 5% of the total distance between opposing edges of the second transistors, or where X is 2.5% of the total distance between opposing edges of the second transistors, or where X is 1% of the total distance between opposing edges of the second transistors. Further note that the respective edge points at which the distance between the opposing edges is measured are in a common horizontal plane, and can be at any locations along those opposing edges.

[0057] Example 9 includes the subject matter of any of the preceding Examples, wherein the lower and upper semiconductor layers are silicon.

[0058] Example 10 includes the subject matter of any of Examples 1 through 8, wherein the upper semiconductor layer is silicon, germanium, or silicon germanium (SiGe), and the lower semiconductor layer is silicon, germanium, or silicon germanium (SiGe).

[0059] Example 11 includes the subject matter of Example 10, wherein the upper semiconductor layer is different from the lower semiconductor layer.

[0060] Example 12 includes the subject matter of any of the preceding Examples, wherein the first transistor further comprises: a gate dielectric over the channel; a gate metal over the gate dielectric; source and drain regions to either side of the channel; and a gate spacer between the gate and the source region, and a gate spacer between the gate and the drain region, wherein the gate dielectric is between the channel region and the gate spacers.

[0061] Example 13 includes the subject matter of any of the preceding Examples, wherein the first transistor comprises a gate metal and adjacent gate spacers over a high-k gate dielectric layer.

[0062] Example 14 includes the subject matter of any of the preceding Examples, wherein the first transistor is a PMOS transistor and the second transistors are MOS transistors.

[0063] Example 15 includes the subject matter of any of the preceding Examples, wherein the III-N semiconductor structure comprises GaN.

[0064] Example 16 includes the subject matter of any of the preceding Examples, wherein the III-N semiconductor structure comprises a nucleation layer and a channel layer.

[0065] Example 17 includes the subject matter of Example 16, wherein the nucleation layer comprises aluminum nitride (A1N) and the channel layer comprises GaN.

[0066] Example 18 includes the subject matter of any of the preceding Examples, wherein the first transistor comprises has a gate length of 20 nm or less. [0067] Example 19 includes the subject matter of any of the preceding Examples, wherein the first transistor comprises has a gate length of 10 nm or less.

[0068] Example 20 includes the subject matter of any of the preceding Examples, wherein at least one of the second transistors comprises a polarization layer within or over the III-N semiconductor structure.

[0069] Example 21 includes the subject matter of Example 20, wherein the polarization layer includes aluminum and nitrogen.

[0070] Example 22 is a system-on-chip (SOC) comprising the integrated circuit of any of Examples 1 through 21.

[0071] Example 23 is a radio frequency (RF) circuit comprising the integrated circuit of any of Examples 1 through 21.

[0072] Example 24 is a mobile computing system comprising the integrated circuit of any of Examples 1 through 21.

[0073] Example 25 is an integrated circuit, comprising: a silicon-on-insulator substrate including a buried insulator layer disposed between upper and lower silicon layers; and a first transistor between two adjacent second transistors. The first transistor includes: a channel region included in the upper silicon layer; a high-k gate dielectric over the channel region; a gate metal over the gate dielectric; source and drain regions to either side of the channel region; and a gate spacer between the gate and the source region, and a gate spacer between the gate and the drain region, wherein the gate dielectric is between the channel region and the gate spacers. The second transistors each includes: a gallium nitride (GaN) body having a channel region, the GaN body being one of on the upper silicon layer, or passing through the upper silicon layer and the buried insulator layer and being on the lower silicon layer; a polarization layer over the GaN body; and source and drain regions to either side of the channel region.

[0074] Example 26 includes the subject matter of Example 25, wherein the III-N semiconductor for each second transistor is in a trench having a bottom on the upper silicon layer.

[0075] Example 27 includes the subject matter of Example 25, wherein the III-N semiconductor for each second transistor is in a trench that passes through the upper silicon layer and the buried insulator layer, and has a bottom on the lower silicon layer.

[0076] Example 28 includes the subject matter of Example 27, wherein each of the lower and upper silicon layers has a crystal orientation with respect to the trench direction, and the crystal orientation for the lower silicon layer is the same as the crystal orientation of the upper silicon layer.

[0077] Example 29 includes the subject matter of Example 27, wherein each of the lower and upper silicon layers has a crystal orientation with respect to the trench direction, and the crystal orientation for the lower silicon layer is different from the crystal orientation of the upper silicon layer.

[0078] Example 30 includes the subject matter of any of Examples 25 through 29, wherein the first transistor gate is centrally positioned between the second transistors, such that the GaN bodies of the second transistors are separated by a distance X, and the center of the first transistor gate is at a location between the second transistors, and the location is within one-half the distance of X, plus or minus 1 nm. Other tolerances will be appreciated.

[0079] Example 31 includes the subject matter of Example 30, wherein the configuration of a first transistor between two adjacent second transistors is repeated a plurality of times, and the corresponding first transistor gate location for each such configuration is within one-half the corresponding distance of X, plus or minus 1 nm.

[0080] Example 32 includes the subject matter of any of Examples 25 through 31, wherein first transistor gate is substantially equidistant between the GaN bodies of the second transistors.

[0081] Example 33 includes the subject matter of any of Examples 25 through 32, wherein the source and drain regions of the first transistor are silicon, germanium, or silicon germanium (SiGe).

[0082] Example 34 includes the subject matter of any of Examples 25 through 33, wherein the first transistor is a PMOS transistor and the second transistors are NMOS transistors.

[0083] Example 35 includes the subject matter of any of Examples 25 through 34, wherein the first transistor comprises has a gate length of 20 nm or less.

[0084] Example 36 includes the subject matter of any of Examples 25 through 35, wherein the first transistor comprises has a gate length of 10 nm or less.

[0085] Example 37 includes the subject matter of any of Examples 25 through 36, wherein the polarization layer includes aluminum and nitrogen.

[0086] Example 38 includes a system-on-chip (SOC) comprising the integrated circuit of any of Examples 25 through 37.

[0087] Example 39 includes a radio frequency (RF) comprising the integrated circuit of any of Examples 25 through 37. [0088] Example 40 includes a mobile computing system comprising the integrated circuit of any of Examples 25 through 37.

[0089] Example 41 is a method of forming an integrated circuit, the method comprising: depositing a blanket layer of high-k gate dielectric material on a semiconductor-on-insulator substrate, the substrate including a buried insulator layer disposed between upper and lower semiconductor layers of group IV material; depositing a blanket layer of isolation material on the gate dielectric material; forming trenches by etching through the isolation and gate dielectric materials; selectively growing a group III-N semiconductor from the trenches so as to form lateral epitaxial overgrowth regions on the isolation material, thereby defining a gap having a width W between lateral epitaxial overgrowth regions of neighboring trenches; and forming a circuit feature between the lateral epitaxial overgrowth regions and in the isolation material, using the lateral epitaxial overgrowth regions as a mask.

[0090] Example 42 includes the subject matter of Example 41, wherein forming trenches by etching through the isolation and gate dielectric materials further includes etching through the upper semiconductor layer and the buried insulator layer to expose the lower semiconductor layer.

[0091] Example 43 includes the subject matter of Example 41 or 42, wherein selectively growing a group III-N semiconductor from the trenches includes growing a gallium nitride (GaN) body, followed by a polarization layer, followed by more GaN so as to form the lateral epitaxial overgrowth regions.

[0092] Example 44 includes the subject matter of Example 41 or 42, wherein selectively growing a group III-N semiconductor from the trenches includes growing an aluminum nitride (A1N) nucleation layer, followed by growing a gallium nitride (GaN) body, followed by a polarization layer, followed by growing more GaN so as to form the lateral epitaxial overgrowth regions.

[0093] Example 45 includes the subject matter of any of Examples 41 through 44, wherein forming a circuit feature between the lateral epitaxial overgrowth regions, using the lateral epitaxial overgrowth regions as a mask, includes forming a transistor gate, the method further comprising: forming a first transistor including the gate; and forming second transistors including the group III-N semiconductor.

[0094] Example 46 includes the subject matter of Example 45, wherein the first transistor is a PMOS group IV transistor having its channel in the upper semiconductor layer, and the second transistors are each NMOS group III-V transistors. [0095] Example 47 includes the subject matter of Example 45, wherein the first transistor is a PMOS transistor having its channel in the upper semiconductor layer, and the second transistors are each NMOS GaN transistors, wherein the upper semiconductor layer is silicon, germanium, or silicon germanium (SiGe).

[0096] Example 48 includes the subject matter of any of Examples 41 through 47, wherein the trenches are further etched so that they pass through the upper semiconductor layer and the buried insulator layer, each trench having a bottom on the lower semiconductor layer, and wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to the direction of the trenches, and the crystal orientation for the lower semiconductor layer is the same as the crystal orientation of the upper semiconductor layer.

[0097] Example 49 includes the subject matter of any of Examples 41 through 47, wherein the trenches are further etched so that they pass through the upper semiconductor layer and the buried insulator layer, each trench having a bottom on the lower semiconductor layer, and wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to the direction of the trenches, and the crystal orientation for the lower semiconductor layer is different from the crystal orientation of the upper semiconductor layer.

[0098] Example 50 includes the subject matter of any of Examples 41 through 49, and further includes removing the lateral epitaxial overgrowth regions after the circuit feature is formed. Note, however, that in other Examples the lateral epitaxial overgrowth regions may be left in the final integrated circuit structure.

[0099] The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of this disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS What is claimed is:

1. An integrated circuit, comprising:

a semiconductor-on-insulator substrate including a buried insulator layer disposed between upper and lower semiconductor layers of group IV material; and a first transistor between two adjacent second transistors, wherein the first transistor has a channel region included in the upper semiconductor layer, and each of the second transistors comprises a group III-N semiconductor structure that either:

is on the upper semiconductor layer; or

passes through the upper semiconductor layer and the buried insulator layer and is on the lower semiconductor layer.

2. The integrated circuit of claim 1, wherein the III-N semiconductor structure for each second transistor is in a trench having a bottom on the upper semiconductor layer.

3. The integrated circuit of claim 1, wherein the III-N semiconductor structure for each second transistor is in a trench that passes through the upper semiconductor layer and the buried insulator layer, and has a bottom on the lower semiconductor layer.

4. The integrated circuit of claim 3, wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to the trench direction, and the crystal orientation for the lower semiconductor layer is the same as the crystal orientation of the upper semiconductor layer.

5. The integrated circuit of claim 3, wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to the trench direction, and the crystal orientation for the lower semiconductor layer is different from the crystal orientation of the upper semiconductor layer.

6. The integrated circuit of claim 1, wherein the first transistor has a gate that is centrally positioned between the second transistors, such that the second transistors are separated by a distance X, and the center of the gate is at a location between the second transistors, and the location is within one-half the distance of X, plus or minus 1 nm.

7. The integrated circuit of claim 6, wherein the configuration of a first transistor between two adjacent second transistors is repeated a plurality of times, and the corresponding gate location for each such configuration is within one-half the corresponding distance of X, plus or minus 1 nm.

8. The integrated circuit of claim 1, wherein the upper semiconductor layer is silicon, germanium, or silicon germanium (SiGe), and the lower semiconductor layer is silicon, germanium, or silicon germanium (SiGe).

9. The integrated circuit of claim 1, wherein the first transistor further comprises: a gate dielectric over the channel;

a gate metal over the gate dielectric;

source and drain regions to either side of the channel; and

a gate spacer between the gate and the source region, and a gate spacer between the gate and the drain region, wherein the gate dielectric is between the channel region and the gate spacers.

10. The integrated circuit of claim 1, wherein the III-N semiconductor structure comprises a nucleation layer and a channel layer.

11. The transistor of claim 1, wherein at least one of the second transistors comprises a polarization layer within or over the III-N semiconductor structure, and wherein the polarization layer includes aluminum and nitrogen.

12. A system-on-chip comprising the integrated circuit of any of claims 1 through 11.

13. A radio frequency (RF) circuit comprising the integrated circuit of any of claims 1 through 11.

14. A mobile computing system comprising the integrated circuit of any of claims 1 through 11.

15. An integrated circuit, comprising:

a silicon-on-insulator substrate including a buried insulator layer disposed between upper and lower silicon layers; and

a first transistor between two adjacent second transistors; wherein the first transistor is a PMOS transistor and includes:

a channel region included in the upper silicon layer;

a high-k gate dielectric over the channel region;

a gate metal over the gate dielectric;

source and drain regions to either side of the channel region; and

a gate spacer between the gate and the source region, and a gate spacer between the gate and the drain region, wherein the gate dielectric is between the channel region and the gate spacers; and

wherein the second transistors each is an MOS transistor and includes:

a gallium nitride (GaN) body having a channel region, the GaN body being one of on the upper silicon layer, or passing through the upper silicon layer and the buried insulator layer and being on the lower silicon layer;

a polarization layer over the GaN body; and

source and drain regions to either side of the channel region.

16. The integrated circuit of claim 15, wherein the III-N semiconductor for each second transistor is in a trench that passes through the upper silicon layer and the buried insulator layer, and has a bottom on the lower silicon layer.

17. The integrated circuit of claim 15, wherein the first transistor gate is centrally positioned between the second transistors, such that the GaN bodies of the second transistors are separated by a distance X, and the center of the first transistor gate is at a location between the second transistors, and the location is within one-half the distance of X, plus or minus 1 nm.

18. The integrated circuit of claim 17, wherein the configuration of a first transistor between two adjacent second transistors is repeated a plurality of times, and the corresponding first transistor gate location for each such configuration is within one-half the corresponding distance of X, plus or minus 1 nm.

19. The integrated circuit of claim 15, wherein the source and drain regions of the first transistor are silicon, germanium, or silicon germanium (SiGe).

A system-on-chip comprising the integrated circuit of any of claims 15 through

21. A method of forming an integrated circuit, the method comprising: depositing a blanket layer of high-k gate dielectric material on a semiconductor-on- insulator substrate, the substrate including a buried insulator layer disposed between upper and lower semiconductor layers of group IV material; depositing a blanket layer of isolation material on the gate dielectric material;

forming trenches by etching through the isolation and gate dielectric materials;

selectively growing a group III-N semiconductor from the trenches so as to form lateral epitaxial overgrowth regions on the isolation material, thereby defining a gap having a width W between lateral epitaxial overgrowth regions of neighboring trenches; and

forming a circuit feature between the lateral epitaxial overgrowth regions and in the isolation material, using the lateral epitaxial overgrowth regions as a mask.

22. The method of claim 21, wherein forming trenches by etching through the isolation and gate dielectric materials further includes etching through the upper semiconductor layer and the buried insulator layer to expose the lower semiconductor layer.

23. The method of claim 21, wherein selectively growing a group III-N semiconductor from the trenches includes growing a gallium nitride (GaN) body, followed by a polarization layer, followed by more GaN so as to form the lateral epitaxial overgrowth regions.

24. The method of claim 21, wherein selectively growing a group III-N semiconductor from the trenches includes growing an aluminum nitride (A1N) nucleation layer, followed by growing a gallium nitride (GaN) body, followed by a polarization layer, followed by growing more GaN so as to form the lateral epitaxial overgrowth regions.

25. The method of any of claims 21 through 24, further comprising removing the lateral epitaxial overgrowth regions after the circuit feature is formed.