TW201810612A - Co-integration of GaN and self-aligned thin body group IV transistors - Google Patents

Abstract

Techniques are disclosed for forming integrated circuits configured with co-integrated group III-N transistors and group IV transistors. The diverse transistors can be formed in a neighboring fashion or otherwise adjacent to one another on a common substrate. The substrate is a semiconductor-on-insulator configuration. According to an embodiment, structural features of neighboring III-N transistors are used to define structural features of an intervening group IV transistor. So, for example, features of the III-N transistor structures are initially used as a mask to pattern the intervening group IV transistor structure and subsequently are later used as part of the III-N transistor structures, in some cases. In other cases, the III-N transistor structures are sacrificial in nature, in that they are removed after formation of the IV transistor feature. The self-aligned co-location techniques can be used to significantly reduce integration processing needed to form mixed transistor technology (e.g., silicon-containing transistors between GaN transistors).

Description

Co-integration technology of gallium nitride and self-aligned thin body group IV transistors

The present disclosure relates to a co-integration technique for gallium nitride and self-aligned thin body Group IV transistors.

BACKGROUND OF THE INVENTION In the field of wireless communication and power management, various components can be implemented using semiconductor devices such as transistors. For example, in radio frequency (RF) communications, the RF front end can include a plurality of transistor-based components, such as switches and power amplifiers, which are generic terms for circuits between antennas and digital baseband systems. In part due to its large band gap and high mobility, gallium nitride (GaN) and other Group III-N semiconductor materials are suitable for use in integrated circuits such as high frequency and high power applications. In contrast, germanium and other Group IV semiconductor materials are suitable for use in integrated circuits such as low power applications.

In one aspect of the present disclosure, an integrated circuit is specifically provided, comprising: a semiconductor-on-insulator substrate comprising an embedded insulator layer sandwiched between an upper portion and a lower semiconductor layer of a Group IV material; And a first transistor between two adjacent second transistors, wherein the first transistor has a channel region included in the upper semiconductor layer, and the second transistors comprise a third group A semiconductor structure which is one of the following: on or over the upper semiconductor layer and the buried insulator layer.

The detailed description of the preferred embodiment discloses techniques for forming an integrated circuit that is assembled using a co-integrated III-V transistor and a Group IV transistor. Different transistors may be formed adjacent to each other on a common substrate in an adjacent manner or otherwise. The substrate is a semiconductor-on-insulator configuration (eg, on-insulator). According to an embodiment, structural features of adjacent III-V transistors are used during the fabrication process to define structural features of the intervening Group IV transistors. Thus, in some embodiments, the features of the III-V transistor structure are initially used as a mask for patterning intervening Group IV transistor structures, which are then later used as part of the III-V transistor structure. In other embodiments, the III-V transistor structure originally used as a mask for patterning intervening Group IV transistor structures is erosive in nature because of its formation after formation of a Group IV transistor feature. Removed from time. It will be appreciated that co-located self-alignment techniques can be used to significantly reduce the integration process required to form hybrid transistor technology on a common substrate. General overview

Currently, GaN PMOS has low performance. Therefore, 矽 PMOS is a more suitable choice for CMOS operation in combination with GaN NMOS. However, due to the different properties of GaN and germanium, co-integration of III-N material-based devices, such as GaN NMOS transistors, with germanium substrates is a significant problem. For example, GaN has a larger lattice mismatch with germanium. Specifically, the lattice mismatch between the GaN material oriented along the <111> crystal and the germanium wafer is about 17%. This larger lattice mismatch typically results in a higher defect density in the III-N material grown on the crucible. In addition, there is also a large thermal expansion coefficient mismatch. For example, the mismatch in thermal expansion coefficient between GaN and germanium is about 116%, and this typically results in surface cracks on the III-N material grown on the crucible. These defects significantly reduce the mobility of carriers (eg, electrons, holes, or both) in the III-N material and can also cause poor yield and reliability issues. To this end, the prior art does not provide an efficient way of co-integration of Group III-N transistors with Group IV transistors in CMOS circuits. In some cases, co-integration is processed by using two different substrates and independently performing the formation process, and then the subsequent bonding process connects the separately formed substrates. Therefore, for applications such as RF front ends, voltage regulator circuits, and other applications requiring different material system integration, there is a need for an integrated solution that enables Group III-N and Group IV components to be co-integrated on a common substrate.

Techniques for forming integrated circuits using co-integration of Group III-V transistors and Group IV transistors are disclosed. Different transistors may be formed adjacent to each other on a common substrate in an adjacent manner or otherwise. According to some embodiments, the substrate is a semiconductor-on-insulator configuration. The substrate can be, for example, a relatively thin layer of tantalum oxide that is in turn provided on a tantalum processing wafer or other suitable crucible platform. A top semiconductor layer or an underlying semiconductor layer (eg, a handle wafer) on the insulator can be used to form any of the Group III-V and Group IV transistors. Thus, for example, two types of transistors can be formed using a top semiconductor layer, or a III-V transistor can be formed using a bottom semiconductor layer and an IV transistor can be formed using a top semiconductor layer. An exemplary integrated circuit assembled in accordance with an embodiment has a Group III-N transistor for high power and/or high frequency (eg, RF amplifier, RF switch, RF filter) and for relatively high Low power applications (eg, memory components, logic) are used to assemble Group IV transistors, although it should be appreciated that many applications may benefit from such techniques. The Group III-N transistor can be, for example, an n-type metal oxide semiconductor (NMOS) and the Group IV transistor can be a p-type metal oxide semiconductor (PMOS) to provide a complementary metal oxide semiconductor (CMOS) integrated circuit. .

According to an embodiment, structural features of adjacent III-N (or III-V) transistors are used during the fabrication process to define structural features of the intervening Group IV transistors. In one such exemplary case, a GaN lateral epitaxial growth technique is used to provide GaN islands in which GaN transistor channels can be formed. These islands have a well-controlled size depending on the growth process used and other factors such as the orientation of the crystal surface on which GaN grows. In any case, the spacing between adjacent GaN islands can be tightly controlled (eg, in the range of 100 nm or less, even up to 10 nm or less). Thus, two adjacent GaN islands can be spaced apart from one another in accordance with the need to define, for example, the gate length of the Group IV transistor to be formed therebetween. The islands thus spaced apart in this manner are in fact used as a mask for etching the Group IV transistor gate trenches. Note that the trenches are self-aligned to adjacent GaN islands without any further masking or alignment processes. Thus, in some embodiments, the GaN island is initially used as a mask for patterning intervening of the Group IV transistor structure, which is then later used as part of the III-N transistor structure. In other embodiments, the GaN island is degrading in nature because it is removed some time after the formation of the Group IV transistor features. Many other exemplary embodiments are obvious.

As further appreciated in light of the present disclosure, the self-aligned co-location techniques as provided herein can be used to significantly reduce the integration process required to form hybrid transistor technology on a common substrate. Also, in some embodiments, the size of the Group IV transistor structure, particularly the gate length, can be made extremely small (e.g., 10 nm or less) such that it is difficult to consistent on a given substrate using current processes and techniques. Generated. In contrast, the island-forming GaN growth system is highly predictable and controllable. As a result, the patterning step is reduced, and the need for masking and additional alignment and planarization steps is reduced, greatly simplifying the overall process, reducing cost and processing time.

As used herein, Group IV semiconductor materials include, for example, germanium, antimony, carbon, tin, lead, and alloys thereof such as germanium (SiGe), tantalum carbide (SiC), and germanium-tin (Ge-Sn), to name a few. . Additionally, the Group III-N semiconductor material (or III-N material or simply III-N) includes a compound of one or more Group III elements (eg, aluminum, gallium, indium, boron, ruthenium) and nitrogen. Thus, III-N materials as used herein include, but are not limited to, gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), aluminum indium nitride (AlInN), aluminum gallium nitride (AlGaN). Indium gallium nitride (InGaN) and aluminum indium gallium nitride (AlInGaN), just to name a few examples of III-N materials. In a more inclusive manner, it is noted that the Group III-V materials as used herein include at least one Group III element (eg, aluminum, gallium, indium, boron, antimony) and at least one Group V element (eg, nitrogen, Phosphorus, arsenic, antimony, antimony, such as gallium nitride (GaN), gallium arsenide (GaAs), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs), to name a few. Many of the Group IV and III-V material systems can be used in various embodiments of the present disclosure.

The techniques and structures provided herein can be detected in a cross section of an integrated circuit using tools such as scanning electron microscopy (SEM) or transmission electron microscopy (TEM), which can show the device. Various layers and structures. Other methods such as composition mapping, x-ray crystallography or diffraction (XRD), secondary ion mass spectrometry (SIMS), time-of-flight SIMS (ToF-SIMS), atom probe imaging, local electrode atom probe (LEAP) technology , 3D tomography, high-resolution physics or chemical analysis, just to name a few examples of analytical tools. In some embodiments, for example, the SEM can indicate adjacent Group IV structures and III-V structures (eg, 矽PMOS and GaN NMOS) in cross-section, where each Group IV structure has two adjacent III- a V-group structure such that the Group IV structure and the III-V structure alternate, and further, each of the Group IV structures has a thin metal gate including adjacent gate spacers, wherein the metal gates and spacers are both positioned On the gate dielectric layer. The gate length can be, for example, 50 nm or less, or 40 nm or less, or 30 nm or less, or 20 nm or less, or 15 nm or less, or 10 nm or less, or 8.5 nm. Or smaller, or 7 nm or less. Many configurations and variations are apparent from the present disclosure. Architecture and method

1 is a cross-sectional view of an integrated circuit structure assembled using a co-integrated III-V NMOS transistor and a Group IV PMOS transistor on a common substrate in accordance with an embodiment of the present disclosure. Note that the structure is shown in a cross-sectional view taken along the direction perpendicular to the gate, as is the corresponding structure shown in Figures 2-10. As shown, the integrated circuit 100 includes a semiconductor-on-insulator (SOI) substrate having a plurality of Group IV transistors (101A, 101B) and a plurality of III-N transistors (102A, 102B) formed thereon. As can be further found, the transistor 101A is between the transistors 102A and 102B, and the transistor 101B is between the transistors 102B and 102C. Although four transistors are shown, it should be understood that many transistors can be used in many alternating modes. In addition, it should be noted that a dummy transistor body can also be used (eg, features of one or more dummy III-V transistors can be used to form an intervening Group IV transistor). To this end, the techniques provided herein can be implemented using functional and dummy (non-functional) transistor configurations.

In the particular exemplary embodiment illustrated in FIG. 1, transistor 101A is a germanium (Si) transistor (eg, a PMOS) positioned between GaN transistors 102A and 102B (eg, an NMOS). Likewise, transistor 101B is a Si transistor (eg, PMOS) that is positioned between GaN transistors 102B and 102C (eg, NMOS). As further shown, GaN transistor 102B is also between Si transistors 101A and 101B. Although in some embodiments, the GaN transistor alternates with the Si transistor, other configurations are possible, as will be appreciated in light of the present disclosure. For example, in other embodiments, integrated circuit structure 100 can include multiple groups of first transistors between adjacent second transistors, such as InGaN transistors alternating with SiGe transistors, or with Ge AlGaN transistors with alternating transistors, just to name a few other exemplary configurations.

The substrate can have many semiconductor-on-insulator (SOI) configurations and can be implemented, for example, using a pre-formed SOI substrate or a monolithic substrate having insulators and semiconductor layers formed thereon. In this exemplary case, the SOI substrate includes a thin layer of Si on an insulator (eg, cerium oxide or other germanium-compatible insulator), which in turn is provided on a Si-treated substrate (eg, a monolithic substrate). In other embodiments, the substrates can be assembled in different ways. For example, the SOI substrate can have a thin SiGe semiconductor layer on the monolithic germanium wafer or the ceria layer on the substrate, wherein the Ge concentration of the SiGe layer can vary from about 5% to about 40%. In other such embodiments having a higher concentration of Ge (40% to 90%), the substrate may include a graded buffer layer between the insulator layer and the top SiGe layer that is compatible with the Ge concentration from the insulator layer The level is gradually increased to the target Ge level. In other cases, it is noted that the target level of Ge can be 100% to provide an SOI substrate configuration for a Ge/graded Ge-Si buffer/Si-compatible insulator/Si substrate. In other cases, the SOI substrate configuration can be a Ge/Ge-compatible insulator/Ge substrate. In a more general sense, the SOI substrate can comprise any combination of Group IV materials such as Si, Ge, SiGe or SiC. As further appreciated in light of the present disclosure, the substrate can have a particular surface crystal orientation that can be described by the Miller Index. For example, the substrate can have a <100>, <110> or <111> crystal orientation, depending on the particular material used.

In general, in the embodiment shown in FIG. 1, the III-N transistors 102A-C each include a source S, a drain D, and a gate G, and the GaN channel layer and the second of the induced channels. Polarized layer P of the Dimensional Electron Gas (2DEG). Furthermore, it should be noted that in this exemplary case, the GaN channel layer is grown directly on the underlying germanium substrate. Each of the source S, the drain D, and the gate G may include a multilayer structure including a source/drain region material, a work function adjusting material, a resistance reducing material, and a metal contact material. In addition, a gate spacer is provided to separate the gate G from the source S and the drain D. The Group IV transistors 101A-B also each include a source S, a drain D, and a gate G. A source and a drain contact C are provided, and the contacts may include a multilayer structure including a work function adjusting material, a resistance reducing material, and a metal contact material. A 矽 (Si) channel region is provided between the source S and the drain D and below the gate G. A gate dielectric GD is provided between the underlying Si channel and the gate G. Also note that in this exemplary embodiment, the gate dielectric GD is provided below the gate G and the corresponding adjacent gate spacer. Thus, in some embodiments, an integrated circuit comprising a first transistor such as a Group IV transistor, and a second transistor such as a III-N transistor (or other III-V transistor) is disclosed, and A transistor includes a gate and adjacent gate spacers, each positioned over the gate dielectric layer and, in some embodiments, on the gate dielectric layer.

As further understood, the gate transistor 101 can be centered between adjacent transistors 102 in a self-aligned manner, as further illustrated in FIG. In some such embodiments, the distance between two adjacent Group IV transistors 102 can be set to a nominal distance of X (eg, in the range of 50 nm to 500 nm). Given the controlled growth rate of the III-N material used during the formation of the transistor 102, as further explained, the distance Y from each of the adjacent transistors 102 can also be controlled. Thus, the III-N material can be grown a specific distance Y and then used as a mask to form features of the transistor 101. It is further concluded that the distance W corresponding to the gate length of the transistor 101 can also be controlled. Thus, for example, the gate center of transistor 101 is at half the distance X from any adjacent transistor 102, and Y is equal to one half of distance X minus 0.5W. Given the self-aligning properties of the fabrication process, such spatial relationships can be consistently repeated throughout the substrate such that the gate center of transistor 101 is about half the distance X from any adjacent transistor 102. At the office. Note that the gate center is not necessarily accurately positioned at half the distance X from the adjacent transistor 102, but may actually be within a reasonable tolerance of this position. For example, the gate center can be 10% of the location, or 7.5% of the location, or 5% of the location, or 3% of the location, or 2% of the location, or 1% of the location, Or within 0.5% of this location. In some specific exemplary embodiments, the gate center is positioned at half the distance X from the adjacent transistor 102, +/- 3 nm, or +/- 2 nm, or +/- 1 nm. Also note that the tolerance can be asymmetrical, such as +2/-1 nm. In the absence of the self-aligned co-location technique provided herein, this gate position uniformity is difficult to achieve in the case of a hybrid electromorphic bulk circuit on a given wafer and on a common substrate.

Figure 1 'shows another exemplary embodiment having a variation similar to the embodiment shown in Figure 1. Specifically, the integrated circuit 100' includes all of the features of the integrated circuit 100, but further includes a nucleation layer between the substrate and the GaN channel layer. A nucleation layer can be used to assist in the initiation of growth of the GaN transistor 102. In one such embodiment, for example, the nucleation layer can comprise, for example, an aluminum nitride (AlN) layer, or other suitable starting material. In other embodiments, this layer may be further formulated to have buffering properties in addition to nucleation.

2 through 9 illustrate a method of forming an exemplary integrated circuit in accordance with various embodiments of the present invention, along with various resulting structures. As can be seen, the substrate 200 of the integrated circuit has a semiconductor-on-insulator (SOI) configuration that generally includes a handle substrate or wafer 205, an insulator layer 210, and a semiconductor layer 215. In one particular exemplary embodiment, substrate 200 includes an integral germanium substrate 205, a hafnium oxide layer 210 (sometimes also referred to as an embedding oxide layer or BOX layer), and a thin germanium layer 215. The SOI 200 can be pre-formed or prepared. For example, the monolithic wafer can be processed using an oxygen ion implantation process to form an implanted oxygen layer and subsequently annealed to form an embedded oxide layer that integrates the thin top layer with the thicker bottom Separation of the layer. For this process, the thin layer 215 and the germanium substrate 205 have the same crystal orientation. Thus, in a particular embodiment, the germanium substrate 205 and the thin germanium layer 215 have the same crystal orientation, such as, for example, <100> orientation. In another exemplary embodiment, the monolithic wafer is surface oxidized and processed through an oxidized surface with a hydrogen ion implantation process to form an intercalating hydrogen layer. A processing substrate, such as a second germanium substrate, can be attached to the oxidized surface and the composite structure is heated to cause stripping along the hydrogen layer, leaving a thin tantalum layer 215 and an oxide layer 210 that are attached to the processing germanium substrate 205. In this process, the tantalum substrate (process) 205 can have a different crystal orientation than the top thin layer 215 so that it can be utilized in various ways during various component construction processes, such as the component construction processes described herein. For example, in a particular embodiment, the germanium substrate 205 has a crystal orientation, such as a <111> orientation, while the thin germanium layer 215 has a second, different crystal orientation, such as a <100> orientation. As can be appreciated, the insulating layer 210 can be an oxide or nitride layer disposed between the thin layer 215 and the germanium substrate 205. In other embodiments, each of layers 210, 215, 220, and 230 can be provided using a blanket deposition process to form a multilayer stack. In addition, it is noted that the semiconductor layer 215 is not necessarily limited to germanium, but may be other group IV semiconductors such as Ge, SiGe, and SiC. In any such embodiment, the insulator layer 210 has a thickness, for example, in the range of 10 nm to 2 microns (eg, 200 nm to 1 micron), or any other suitable thickness. As is apparent in light of the present disclosure, the thickness of the insulator layer 210 can be used to electrically separate the transistor formed in the semiconductor layer 215 from the underlying substrate 205. This isolation is useful, for example, in reducing sub-channel (or sub-flap) leakage. The thickness of the semiconductor layer 215 can also vary between various embodiments, but in some cases is in the range of 5 nm to 500 nm (eg, 10 nm to 200 nm). The thickness of the semiconductor layer 215 can be set based on the configuration of the transistor device formed therein, particularly based on the desired channel layer thickness and possible source/drain region thickness.

As further shown in FIG. 2, dielectric layer 220 is also provided over semiconductor layer 215 of SOI 200, and shallow trench isolation (STI) layer 230 is provided over dielectric layer 220. In some embodiments, one or both of layers 220 and 230 can include multiple material layers or stacked configurations. Additionally, one or more intervening layers may also be provided in some embodiments, as will be appreciated in light of this disclosure. Dielectric layer 220 can have any suitable dielectric constant, but in some embodiments is a high-k dielectric material, such as a high-k gate dielectric suitable for a Group IV transistor configuration. Dielectric material. Typically, high-k dielectric materials include materials having a dielectric constant greater than the dielectric constant of cerium oxide (a k-value greater than 3.9). Exemplary high-k dielectric materials include, for example, cerium oxide, cerium oxide, cerium oxide, cerium oxide, zirconia, zirconia cerium, cerium oxide, cerium oxide, titanium oxide, titanium cerium oxide, titanium cerium oxide, oxidation. Niobium, niobium oxide, aluminum oxide, antimony oxide, lead oxide antimony and lead and zinc antimonate, to name a few. In some embodiments, an annealing process can be performed on the dielectric layer 220 to improve its quality. The thickness of the dielectric layer 220 can vary from embodiment to embodiment, but in some cases from 1 nm to 20 nm (eg, 5 nm to 10 nm), depending on the end use or target application.

STI layer 230 can comprise any suitable insulator or isolation material, such as an oxide (eg, ceria or alumina) and/or a nitride (eg, tantalum nitride or hafnium oxynitride), to name a few. In some embodiments, STI layer 230 can include multiple material layers or stacked configurations. STI layer 230 can have any suitable dielectric constant, but in some embodiments is a low-k dielectric material, such as a low-k dielectric material suitable for providing electrical isolation between adjacent transistors. Typically, low-k dielectric materials include materials having a dielectric constant (less than 3.9 k) that is less than the dielectric constant of ceria. Exemplary low-k dielectric materials include, for example, porous ceria, porous tantalum nitride, carbon or fluorine doped ceria, porous carbon doped ceria, spin-on polymer dielectric, to name a few example. The thickness STI layer 230 can vary between various embodiments, but in some cases is in the range of 50 nm to 2 microns (eg, 200 nm to 1 micron), depending on the end use or target application and as understood.

As further appreciated in light of this disclosure, each of these layers 205, 210, 215, 220, and 230 can be used to form various features and components of integrated circuit 100, as described in turn. It is further noted that in some embodiments, each of the layers 210, 215, 220, and 230 can be provided sequentially on the substrate 205 in a blanket manner using standard processing, such as chemical vapor deposition (CVD). ), atomic layer deposition (ALD), physical vapor deposition (PVD), oxidation, and implantation processes, to name a few. After forming a multilayer structure of Figure 2, the method can continue to form various devices. Note that in some embodiments, the structure may be pre-finished or otherwise obtained for subsequent use with respect to the methods illustrated in Figures 3-10.

Figure 3 illustrates the resulting structure after forming a trench for the growth of a Group III-V transistor, in accordance with an embodiment. As can be seen in this exemplary case, portions of STI layer 230, dielectric layer 220, semiconductor layer 215, and insulator layer 210 are removed, thereby forming trenches 335 on underlying substrate 205 and exposing underlying substrate 205. In one such case, the substrate 205 can have a crystal orientation 111 relative to the direction of the trench. This 111 orientation is well suited for the growth of III-N materials such as GaN. In other embodiments, the trenches 335 may terminate on different layers of the structure, such as the semiconductor layer 215, thereby also providing a particular orientation suitable for growing the transistor material. While various etching schemes can be used to form the trenches, one embodiment uses a combination of wet and/or dry etching processes. For example, if the STI layer 230 is tantalum nitride and the dielectric layer 220 is germanium dioxide, a wet etch process including hot phosphoric acid can be used to etch through the STI layer 230 to expose the underlying dielectric layer 220. Then, a dilute hydrofluoric (HF) acid or a ternary mixed gas acid immersion may be performed after this wet etching to pattern the etch dielectric layer 220, thereby exposing the underlying semiconductor layer 215. If the trench 335 terminates on the lower substrate 205, further etching can be used to remove the semiconductor layer 215 and the insulator layer 210. The etchant of this layer can be selected, for example, based on its selectivity for crystal orientation to provide an anisotropic etch. For example, if the semiconductor layer 215 is tied and the trench is oriented in the 100 crystal orientation, an etchant such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) can be used much faster than in the 111 direction. This layer 215 is etched in the 100 crystal direction. Other such selective or so-called anisotropic etching schemes may also be used, depending on factors such as the composition of layer 215 and the orientation of trench 335 relative to crystal orientation. Directional dry etching can also be used. The size of the trench 335 can vary between various embodiments, but in some cases, each trench 335 has a cross-sectional opening in the range of 50 nm to about 50 μm.

After forming the trench 335, the method continues to fill the trench with the III-V material, resulting in the formation of a circuit III-V transistor. An exemplary embodiment is illustrated in Figures 4A, 4B, and 4C. As can be seen, the structure of this exemplary embodiment generally includes a III-V semiconductor body 440, a III-V polarization layer 445 that induces 2DEG in the channel of the semiconductor body 440, and a growth of the III-V semiconductor material 450 (450A). , 450B or 450C, in the respective embodiment shown in Figures 4A-C). Other embodiments may include other layers because of the many configurations of the III-V family of transistors, and any such configuration may be practiced in accordance with embodiments of the present disclosure, as appreciated. For example, and as previously explained with reference to FIG. 1 ', the first layer formed in trench 335 can be selectively a nucleation layer, for example, having a range of about 10 nm to 400 nm (eg, ~50 nm). AlN layer of thickness. In an exemplary embodiment, the III-V semiconductor body 440 is a III-N material such as GaN or InGaN, which are particularly well suited for high power applications, due in part to their wider bandwidth, High critical breakdown electric field and high electron saturation. The polarization layer 445 can be, for example, AlN, AlInN, AlGaN, or AlInGaN. The grown III-V semiconductor material 445 can be GaN, for example, or other III-V materials that can be predicted or otherwise grown in a consistent manner, as understood in light of the present disclosure. As further understood in light of the present disclosure, given this predictable growth pattern, the distance W between the growth regions of adjacent III-V transistors can be reliably determined. It is further noted that the grown III-V semiconductor material can have different shapes.

The formation of III-N features 440, 445, and 450 (and any other layers, such as nucleation layers) can be performed using a number of deposition techniques including, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy. (MBE) chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD). As discussed above, GaN has a large lattice mismatch with Si and a large mismatch in thermal expansion coefficient, typically resulting in higher defect densities in GaN materials grown on Si. Thus, in some embodiments, high quality GaN on Si is grown using lateral epitaxial growth (LEO) conditions. This LEO process can include, for example, growing the GaN body 440 on the Si substrate 205 within the patterned trench 335, then allowing the material to fill the trench 335, thereby forming a lateral growth region 450A, 450B or 450C. In this manner, when a material is formed on the STI layer 230, defects that may be present in the growth material can be bent or otherwise reduced, leaving the remainder of the GaN material 440 suitable for use with the transistor channel.

In an exemplary process flow, growth of the III-V semiconductor body 440, such as GaN, can be interrupted or modified to form a polarized layer 445. For example, in some such exemplary embodiments, GaN body 440 is just grown below the surface of STI layer 230 and then the deposition process parameters are modified to transition from growing GaN to growing polarization layer 445 material. After forming the relatively thin polarized layer 445, the deposition process parameters can be modified again to transition from the grown polarization layer 445 to the grown GaN, allowing for continued lateral epitaxial growth of the GaN 450. Polarization layer 445 can comprise any suitable material, such as one or more III-V materials, and more specifically, in some embodiments, such as one or more III-N materials. In some embodiments having a GaN body 440, the polarizing layer 445 includes aluminum such that the layer includes at least one of AlN, AlGaN, InAlN, and InAlGaN. The polarizing layer 445 effectively increases the carrier mobility in the transistor channel region in the GaN body 440 to induce 2DEG. In such cases, the polarizing layer 445 generally includes a material having a higher band gap than the material of the III-N body 440 to form a 2DEG. For example, in some embodiments, semiconductor body 440 is GaN and polarized layer 445 is AlN and/or AlGaN. In some embodiments, the polarizing layer 445 can have a multilayer structure comprising a plurality of III-V materials, wherein one of the layers can exist to further increase carrier mobility and/or improved poles in the transistor channel region. The compatibility between the layer 445 and the overlying layer (eg, the density of interface traps). In some embodiments, the polarizing layer 445 may or may not include grading (eg, increasing and/or decreasing) the content of one or more materials in at least a portion of the layer. Note that the thickness of the polarizing layer 445 can also vary between various embodiments and can range, for example, from 1 nm to 20 nm (eg, 5 nm to 10 nm).

The conditions for growing the III-V semiconductor material 450 can be used to modify the properties of the resulting epitaxial growth structure. In some embodiments, the facets or caps of the III-V growth region are controlled by, for example, a V/III ratio for deposition material and growth temperature and pressure. In general, increasing the V/III ratio facilitates the formation of a rectangular end face, such as the cover 450B shown in FIG. 4B and the cover 450C shown in FIG. 4C, as well as increasing the deposition temperature and lowering the pressure. Again, generally, a lower V/III ratio, lower temperature, and higher pressure facilitate triangular end face formation, such as cover 450A shown in Figure 4A. Additionally, the orientation of the trenches 335 for the growth of the III-V body 440 can result in different end faces of the resulting growth regions 450A-C. In one embodiment, for example, for <100> Si substrate 205 and GaN 450, the trench 335 along the <110> direction is oriented to favor the triangular end face (Fig. 4A). In another exemplary embodiment, for the <100> Si substrate 205 and the GaN 450, the trenches 335 along the <100> direction are oriented to favor the rectangular end faces (Fig. 4B or 4C). In another exemplary embodiment, for the <111> Si substrate 205 and the GaN 450, the trenches 335 along the <112> direction are oriented to favor the triangular end faces (Fig. 4A).

As is apparent in light of the present disclosure, lateral epitaxial growth techniques can be used to form III-V transistor features that can be used to accurately determine various features of a transistor positioned between its III-V transistors, such as a gate. Length, Lg. For example, as shown in Figures 4A-C, forming lateral growth regions 450A, 450B, and 450C on STI layer 230 results in the formation of a gap 460 having a width W between adjacent covers. Lateral growth can continue as needed, increasing the size of the cover 450, thereby correspondingly reducing the width of the gap 460 therebetween until a specified or target gap width is achieved. Growth can then be stopped, such as by ending the supply of reagents required for continued growth, or otherwise adjusting the process to stop growth, such as by decreasing the temperature or increasing the pressure beyond a given growth threshold. In this manner, the width of the gap can be controlled in a relatively precise manner, and in some embodiments of the present disclosure, the minimal gap 460 can be consistently produced by controlling the processing conditions of lateral epitaxial growth. For example, a method described herein can be used to achieve a gap having a width of less than about 100 nm, such as less than about 75 nm, or less than about 50 nm, or less than 25 nm, or less than 15 nm, or less than 10 nm (eg, , 1 nm to 9 nm gap).

The gap 460 can then be used to form an interposer transistor, such as a gate of a Si PMOS or other Group IV transistor. Thus, if a first transistor, such as a gate of a Si transistor, is positioned between adjacent second transistors, and in some embodiments is centered, the gate is substantially between the second transistors Isometric. After the gate is formed, the III-V growth region 450 can be removed, and the underlying body 440 and the polarization layer 445 can be used to form a III-V transistor, such as a GaN NMOS transistor. Thus, in fact, the lateral epitaxial growth region 450 acts as a temporary mask in the process of forming the gate or other features of the transistor positioned therebetween. The resulting integrated circuit includes a first material system device between two adjacent devices of the second material system, and the second adjacent device in fact defines the location and size of at least one feature of the first device.

Further details of the exemplary embodiments are illustrated in Figures 5-7. As shown in FIG. 5, adjacent cover 450 is a lateral epitaxial growth region formed on polarizing layer 445 on III-V semiconductor body 440 and extends over STI layer 230 to form a gap having a width W. Although cover 450A is shown, the same method can be used for covers 450B and 450C, as will be appreciated in light of this disclosure. Therefore, the following reference to the cover or region 450A, 450B or 450C is simply referred to as a cover or region 450. The exposed portion of the STI layer 230 can be removed by various etching processes to form a gate trench 570, which in this embodiment exposes a cavity in the STI layer 230 of a portion of the dielectric layer 220. Thus, in some embodiments, etching occurs across the STI layer and stops at the dielectric layer 220. A number of etching processes can be used to selectively remove the STI layer 230 without removing the dielectric layer 220 or region 450, including various selective wet or dry isotropic etches (providing anisotropic or directional etch through the STI layer) . During etching, the III-V cap 450 maintains or otherwise has an etch rate that is substantially less than the etch rate of the STI 230 material for a given etch chemistry. Thus, the lateral epitaxial growth region acts essentially as a mask that forms the gate features. For example, according to an embodiment, if the STI layer 230 is tantalum nitride, the growth region 450 is GaN, and the dielectric layer 220 is ruthenium dioxide or a high-k dielectric such as ruthenium oxide, including hot phosphoric acid. The wet etch process can be used to etch STI layer 230, expose underlying dielectric layer 220, and remove GaN region 450 and dielectric layer 220 relatively minimally.

As further shown in FIG. 5, attention is paid to the spatial relationship of the trenches 570 relative to the adjacent III-V semiconductor body 440. In particular, the inwardly facing edges of each adjacent III-V semiconductor body 440 define a distance X between their edges. Each growth zone 450 extends a distance Y from the edge of its corresponding body 440. Assuming a predictable growth pattern of adjacent growth regions 450, this distance Y is also predictable, as is the width W. It is further concluded that the center of the trench 570 is at a distance of X/2 from either edge of the adjacent growth region 450. As previously explained, for the actual center of the trench 570 relative to the adjacent growth region 450, a reasonable tolerance may be tolerated, depending on factors such as the value of X (the larger the value X, the greater the tolerance allowed). For example, in some cases, the center of the channel 570 (as seen in cross-section) may deviate from the position of X/2 by as much as 10% of X/2 in either direction, while other embodiments have 5% or less. , or a tighter tolerance of 2.5% or less. As understood in light of the present disclosure, this uniform trench layout, particularly for relatively narrow trenches 570 (eg, < 20 nm), is difficult to achieve using standard processes.

As shown in the exemplary embodiment illustrated in FIG. 6, trenches 570 formed in STI layer 230 may be filled with metal to form gate 680 between adjacent caps 450. In some embodiments, any suitable gate metal deposition process (eg, CVD, PVD, MBE) can be used, and then various etching, polishing, planarization, and cleaning processes can be performed. Gate 680 can be, for example, polysilicon, or various suitable metals or metal alloys such as aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), ruthenium (Ru), nickel (Ni), palladium (Pd) ), platinum (Pt) and titanium nitride (TiN), to name a few. In this exemplary embodiment, it is noted that the cover 450 defines the gate length, Lg, of the gate 680 formed in the STI layer 230. Thus, in accordance with some embodiments, as described herein, the extent to which the cover 450 extends over the STI layer 230 can be controlled as needed to provide a gap having the width required to intervene the target Lg value of the gate of the transistor.

According to an embodiment, as shown in FIG. 7, once a trench-based feature (a transistor gate, in the illustrated exemplary embodiment) is formed, the process may continue to remove the growth region 450. Growth region 450 can be removed using a number of suitable processes, such as, for example, planarization followed by polishing, or selective etching of region 450 material. Various interventional procedures can also be included. In other embodiments, it is noted that the growth zone 450 may not be removed, or may only be partially removed or otherwise further shaped and customized for subsequent use in a III-V device.

According to some embodiments, various other features and/or layers may be provided after the growth region 450 is removed. For example, as shown in FIG. 8A, directional etching of STI layer 230 and dielectric layer 220 can be used to form or otherwise form gate spacers 891 alongside gate 680 and to polarized layers 445 and III-V bodies. The remaining STI material 892 next to 440. Note that 891 and 892 can be the same material as STI 230. Many etching processes can be used, such as dry etching in CF ₄ , CF ₄ /O ₂ /Ar, Cl ₂ /O ₂ or HBr/CF ₃ , which are especially suitable for highly directional etch removal of STI layers, thereby Parallel or nearly parallel sidewalls and gate spacers are provided in some embodiments. Additionally, in some embodiments, etching of polarized layer 445 and GaN body 440 (or other suitable III-V body 440) is avoided. The mask can be used to promote the selectivity of the spacer etch process as needed.

The depth of the spacer etch can vary between various embodiments depending on the source/drain configuration. In the exemplary case illustrated in FIG. 8A, the etch terminates at the semiconductor layer 215. In this case, the method can further include ion implantation to dope layer 215 to form source and drain regions on either side of gate 680. For example, in one such embodiment in which layer 215 is defective, the exposed portion of layer 215 can be p-doped (eg, boron, gallium, aluminum) by implantation. In the exemplary case illustrated in FIG. 8B, the etch stop continues through the semiconductor layer 215 (eg, using standard anisotropic or directional etch) and terminates in the underlying insulator layer 210. In such cases, the method can further include epitaxial regrowth of the source and drain regions. For example, epitaxial germanium or SiGe or germanium, or some other alternative source/drain material, can be grown in the source drain region. In such embodiments, it is noted that alternative S/D materials may be grown, for example, from sidewalls of exposed semiconductor layer 215 (eg, germanium or SiGe may be grown from Si layer 215, or germanium or SiGe may be from Ge layer 215, in accordance with some embodiments). Growing). The doped epitaxial material can be performed in situ (during deposition) or later by implantation. In some embodiments, the source/drain regions may include additional layers, such as a graded buffer layer that transitions to a desired concentration of a given component (such as the concentration of semiconductor material of germanium, or dopant concentration) and/or Or contact the resistance reduction layer and / or the work function adjustment layer.

Thus, in accordance with some embodiments, STI layer 230 can be used to provide gate spacers 891 and sidewall spacers 892, and dielectric layer 220 is used to provide gate dielectric layer 220. Note how the gate dielectric 220 is positioned below the gate spacer 891. In a typical Group IV transistor configuration, the gate dielectric material is not under the gate spacer, but is actually only between the gate spacers. Thus, an illustrative indicator of a structure formed in accordance with some embodiments of the present disclosure is a gate dielectric gate spacer that can further be centered with a gate between two adjacent transistors. In combination, it can be further combined with a relatively narrow gate.

Continuing with the method, according to an embodiment, the source/drain regions and contacts can be formed once the gate spacers 891 are formed along with the previously obtained source/drain trenches that achieve the desired depth. In the exemplary embodiment illustrated in FIG. 9, source/drain regions 995 (further labeled S and D) are provided on or over insulator layer 210 by providing insulator layer 210 thereon. The semiconductor layer 215 is implant doped (as explained with respect to FIG. 8A), or epitaxial growth of the alternative source/drain material on or above the insulator layer 210 (as explained with respect to FIG. 8B). Other embodiments may use other source/drain regions 995 to form the technique, as appreciated. As further understood, the source/drain regions 995 can include a number of materials (eg, germanium, germanium, SiGe) and doping schemes (eg, undoped, n-doped, or p-doped). For example, in an embodiment where the structure includes a germanium layer 215 on the oxide layer 210 and the transistor device is assembled into a PMOS device, the source/drain regions 995 can include, for example, boron doped Si or SiGe. In another exemplary embodiment in which the transistor device is assembled into an NMOS device, the source/drain region 995 can include, for example, phosphorus doped Si. The doping concentration can be set as desired (for example, a doping amount of about 2E20 per cubic centimeter). As previously explained, the S/D region 995 can have a multilayer structure that includes multiple layers of material. For example, in some embodiments, a passivation material may be deposited to aid in the quality of the interface between the S/D material and the underlying layer material prior to deposition of the primary S/D material. Moreover, in some embodiments, a contact improving material can be formed on top of the S/D region to facilitate, for example, contact with the S/D contact, as described below. In some embodiments, the S/D region can include grading (eg, increasing and/or decreasing) the content of one or more of the materials in at least a portion of the regions.

As further found in FIG. 9, the method continues to provide S/D contacts 996 on S/D region 995 and may comprise any suitable material, such as a conductive metal or alloy (eg, aluminum, tungsten, silver, nickel-platinum). Or nickel-aluminum). In some embodiments, the S/D contact 996 can include a resistance reducing metal and a contact plug metal, or only a contact plug, depending on the end use or target application. Exemplary contact resistance reducing metals can include silver, nickel, aluminum, titanium, gold, gold-bismuth, nickel-platinum or nickel aluminum, and/or other such electrical resistance reducing metals or alloys. The contact plug metal can include, for example, aluminum, silver, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitable conductive contact metal or alloy can be used, depending on the end use or intended application. In some embodiments, additional layers may be present in the S/D contact region, such as an adhesion layer (eg, titanium nitride) and/or a liner or barrier layer (eg, tantalum nitride), if desired. In some embodiments, metallization of the S/D contact 996 can be performed, for example, using a deuteration or deuteration process (eg, generally, depositing a contact metal on the S/D region 995 containing germanium or germanium, Followed by annealing). In view of this disclosure, many S/D configurations are readily apparent.

As can be seen in Figure 10, in accordance with an embodiment, once the formation of the Group IV transistor is complete, the method continues to form additional features of the Group III-V transistor. For example, in the illustrated exemplary case, source/drain regions 1097 (also labeled S and D) are provided adjacent to the 2DEG channel induced by polarization layer 445 in III-V body 440. Additionally, gate 1099 is provided on the channel. In some embodiments, S/D region 1097 can be formed using any suitable technique, as will be apparent from the present disclosure. For example, in some embodiments, the S/D region 1097 can be formed by any combination of optional patterning/masking/lithography/etching and deposition, growth, and regrowth of the long S/D region 1097 material, A planarization and/or polishing process can then be performed, for example. Note that although in FIG. 10, S/D region 1097 is shown as a contiguous portion, in some embodiments, S/D region 1097 can include multiple portions, such as with a channel region (which is the top of III-V layer 440) Partially adjacent S/D material and S/D contacts above the S/D material. However, in some embodiments, the first layer of the interconnect layer above the depicted device layer can be considered an S/D contact of the S/D region 1097. Regardless of the configuration, in some embodiments, the S/D material (which is in at least a portion of the S/D region 1097) can comprise any suitable material, such as a III-V material, a III-N material, and/or any other. Suitable materials are apparent as they are apparent from the present disclosure. Additionally, in some embodiments, the S/D region 1097 material can be doped, for example, in an n-type or p-type manner using any suitable doping technique. In an exemplary embodiment, the S/D region 1097 may include indium and nitrogen (eg, InN or InGaN) and may be doped in an n-type manner (eg, using Si, Se, and/or Te, at about 2E20 per cubic centimeter) Doping amount to doping). In some embodiments, one or both of the S/D regions 1097 can have a multilayer structure comprising a plurality of materials. In some embodiments, one or both of the S/D regions 140 may or may not include grading (eg, incrementing) the content of one or more of the materials in one or both of the regions. And / or decrement). Further in some embodiments, it is noted that the source-gate spacing can be different than the drain-gate spacing, depending on the desired breakdown voltage of the III-V device.

As previously explained, in some embodiments, the S/D region 1097 can include S/D contacts. In some such embodiments, the S/D contacts can comprise any suitable material, such as a conductive metal or alloy (eg, aluminum, tungsten, silver, nickel-platinum, or nickel-aluminum). In some embodiments, the S/D contacts may include a resistance reducing metal and a contact plug metal, or only a contact plug, depending on the end use or target application. Exemplary contact resistance reducing metals include silver, nickel, aluminum, titanium, gold, gold-bismuth, nickel-platinum or nickel aluminum, and/or other such electrical resistance reducing metals or alloys. The contact plug metal can include, for example, aluminum, silver, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitable conductive contact metal or alloy can be used, depending on the end use or intended application. In some embodiments, additional layers may be present in the S/D contact region 1097, such as an adhesion layer (eg, titanium nitride) and/or a liner or barrier layer (eg, tantalum nitride), if desired. Note that in some embodiments, the gate stacking process can be performed prior to forming the S/D regions 1097, while in other embodiments, the gate stacking process can be performed, for example, after forming the S/D regions 1097. The gate stack can be customized as needed. Exemplary system

FIG. 11 illustrates an computing system 1000 implemented with an integrated circuit structure or apparatus as disclosed herein, in accordance with an exemplary embodiment. As can be seen, the computing system 1000 houses the motherboard 1002. The motherboard 1002 can include a plurality of components including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As can be appreciated, the motherboard 1002 can be, for example, any printed circuit board, regardless of the motherboard, the daughterboard mounted on the motherboard, or the only board of the system 1000, and the like.

Depending on the application of the computing device, computing device 1000 can include one or more other components that may or may not be physically and electrically coupled to motherboard 1002. Such other components may include, but are not limited to, electrical memory (eg, DRAM), non-electrical memory (eg, ROM), graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, Display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera and large capacity Storage device (such as a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), etc.). Any of the components included in computing system 1000 can include one or more integrated circuit structures or devices in accordance with an exemplary embodiment (eg, mixed III-V and IV transistors on a common substrate) , which has a self-aligning property). In some embodiments, multiple functions may be integrated into one or more of the wafers (eg, note that communication chip 1006 may be part of processor 1004 or otherwise integrated into processor 1004).

The communication chip 1006 is capable of wireless communication for data transfer to and from the computing device 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through the use of modulated electromagnetic radiation via non-solid media. The term does not imply that the associated device does not contain any leads, but in some embodiments the associated devices may not contain any leads. The communication chip 1006 can implement any wireless standard or protocol in a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives of each of these, and any other wireless protocols designated as 3G, 4G, 5G, and others. The computing device 1000 can include a plurality of communication chips 1006. For example, the first communication chip 1006 can be dedicated to a shorter range of wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 1006 can be dedicated to a longer range of wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX. , LTE, Ev-DO, etc. In some embodiments, the communication wafer 1006 can include one or more hybrid transistor structures on a common substrate, as described individually herein.

The processor 1004 of the computing device 1000 includes an integrated circuit die package within the processor 1004. In some embodiments, the integrated circuit die of the processor includes an on-board circuit implemented with one or more integrated circuit structures or devices as described individually herein. The term "processor" may refer to any device that processes, for example, electronic data from a register and/or memory to transform the electronic data into other electronic material that can be stored in a register and/or memory or Part of the device.

The communication chip 1006 also includes integrated circuit dies that are packaged within the communication chip 1006. In accordance with some such exemplary embodiments, an integrated circuit die of a communication chip includes one or more integrated circuit structures or devices as individually described herein. As understood in light of this disclosure, it is noted that multi-standard wireless capabilities can be directly integrated into processor 1004 (eg, where the functionality of any of the wafers 1006 is integrated into processor 1004, rather than having a separate communication chip). Also note that processor 1004 can be a chipset having this wireless capability. In one exemplary embodiment, processor 1004 and communication chip 1006 are integrated into a single wafer or wafer set, such as a system single wafer (as indicated generally by dashed lines surrounding their components). In one such case, using the various hybrid transistor techniques provided herein, the logic of processor 1004 can be implemented, for example, in germanium or SiGe, and the RF circuitry of communication chip 1006 can be implemented in GaN and used for RF and The logic of mixed signal processing can be implemented in GaN NMOS and 矽 PMOS. In summary, a number of processors 1004 and/or communication chips 1006 can be used. Likewise, any one wafer or wafer set can have multiple functions integrated therein.

In various implementations, the computing system 1000 can be a laptop, a portable Internet device, a notebook computer, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer. , server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or processing data or using one of the individual descriptions as described herein Or any other electronic device that has a plurality of integrated circuit structures or devices. Other exemplary embodiments

The following examples are directed to other embodiments, many of which are well known.

Example 1 is an integrated circuit comprising: a semiconductor-on-insulator substrate comprising an embedded insulator layer disposed between the upper portion and the lower semiconductor layer of the Group IV material; and two adjacent second transistors a first transistor, wherein the first transistor has a channel region included in the upper semiconductor layer, and each of the second transistors includes a III-N semiconductor structure, The semiconductor structure is on the upper semiconductor layer, or alternatively, through the upper semiconductor layer and the buried insulator layer and on the lower semiconductor layer.

Example 2 includes the subject matter of Example 1, wherein the III-N semiconductor structure of each of the second transistors is in a trench having a bottom on the upper semiconductor layer.

Example 3 includes the subject matter of Example 1, wherein the III-N semiconductor structure of each of the second transistors is in a trench, the trench passes through the upper semiconductor layer and the buried insulator layer, and has a lower semiconductor One of the bottoms of the layer.

Example 4 includes the subject matter of Example 3, wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to one of the trench directions, and the crystal orientation of the lower semiconductor layer is the same as the crystal orientation of the upper semiconductor layer .

Example 5 includes the subject matter of Example 3, wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to one of the trench directions, and a crystal orientation of the lower semiconductor layer is different from a crystal orientation of the upper semiconductor layer .

Example 6 includes the subject matter of any of the preceding examples, wherein the first transistor has a gate centered between the second transistors such that the second transistors are separated by a distance X, and the center of the gate is at a position between the second transistors, and the position is plus or minus 1 nm within one-half of the distance of X.

Example 7 includes the subject matter of Example 6, wherein the configuration of one of the first transistors between two adjacent second transistors is repeated a plurality of times, and the corresponding gate position of each of the configurations is one-half of the corresponding distance of X Add or subtract 1 nm. In other examples, this tolerance may be greater (eg, +/- 5 nm) or less (+/- 0.5 nm) depending on factors such as the distance between opposite sides of the second transistor.

Example 8 includes the subject matter of any of the preceding examples, wherein the first transistor has a gate that is substantially equidistant between the second transistors. Thus, for example, the center of mass of the gate structure is positioned on an imaginary vertical line that is substantially equidistant between the second transistors. The position of the imaginary vertical line is not necessarily exactly equidistant, but the truth is within its tolerance, such as within X nm of the position, where 10% of the total distance between the opposite edges of the X-system second transistor , wherein 5% of the total distance between opposite edges of the X-system second transistor, or 2.5% of the total distance between opposite edges of the X-system second transistor, or the opposite of the X-type second transistor 1% of the total distance between the edges. Also note that the respective edge points of the distance between the opposite edges are measured in a common horizontal plane and may be anywhere along their opposite edges.

Example 9 includes the subject matter of any of the preceding examples, wherein the lower and upper semiconductor layers are germanium.

Example 10 includes the subject matter of any of Examples 1-8, wherein the upper semiconductor layer is germanium, germanium or germanium (SiGe) and the lower semiconductor layer is germanium, germanium or germanium (SiGe).

Example 11 includes the subject matter of Example 10, wherein the upper semiconductor layer is different from the lower semiconductor layer.

Embodiment 12 includes the subject matter of any of the preceding examples, wherein the first transistor further comprises: a gate dielectric on the channel; a gate metal on the gate dielectric; a source and a drain region on either side of the channel; and a gate spacer between the gate and the source region, and a gate spacer between the gate and the drain region Wherein the gate dielectric is between the channel region and the gate spacers.

Example 13 includes the subject matter of any of the preceding examples, wherein the first transistor comprises a gate metal and an adjacent gate spacer on a high-k gate dielectric layer.

Example 14 includes the subject matter of any of the preceding examples, wherein the first electro-crystalline system is a PMOS transistor and the second electro-crystalline system is an NMOS transistor.

Example 15 includes the subject matter of any of the preceding examples, wherein the III-N semiconductor structure comprises GaN.

Example 16 includes the subject matter of any of the preceding examples, wherein the III-N semiconductor structure comprises a nucleation layer and a channel layer.

Example 17 includes the subject matter of Example 16, wherein the nucleation layer comprises aluminum nitride (AlN) and the channel layer comprises GaN.

Example 18 includes the subject matter of any of the preceding examples, wherein the first transistor comprises a gate length of one of 20 nm or less.

Example 19 includes the subject matter of any of the preceding examples, wherein the first transistor comprises a gate length of 10 nm or less.

Example 20 includes the subject matter of any of the preceding examples, wherein at least one of the second transistors comprises a polarized layer within the III-N semiconductor structure or over the III-N semiconductor structure.

Example 21 includes the subject matter of Example 20, wherein the polarizing layer comprises aluminum and nitrogen.

Example 22 is a system single wafer (SOC) comprising the integrated circuit of any of Examples 1-21.

Example 23 is a radio frequency (RF) circuit comprising the integrated circuit of any of Examples 1-21.

Example 24 is a mobile computing system comprising the integrated circuit of any of Examples 1-21.

Example 25 is an integrated circuit comprising: an insulator upper substrate comprising an embedded insulator layer disposed between the upper and lower germanium layers; and one of two adjacent second transistors The first transistor. The first transistor includes: a channel region included in the upper germanium layer; a high-k gate dielectric on the channel region; a gate metal on the gate dielectric; a source and a drain region on either side of the channel region; and a gate spacer between the gate and the source region, and a gate between the gate and the drain region a spacer, wherein the gate dielectric is between the channel region and the gate spacers. Each of the second transistors includes: a gallium nitride (GaN) body having a channel region, wherein the GaN host system is one of: on the upper layer, or through the upper layer and Embedding an insulator layer and on the lower germanium layer; a polarizing layer on the GaN body; and source and drain regions on either side of the channel region.

Example 26 includes the subject matter of Example 25, wherein the III-N semiconductor of each second transistor is in a trench having a bottom on one of the upper germanium layers.

Example 27 includes the subject matter of Example 25, wherein the III-N semiconductor of each second transistor is in a trench that passes through the upper germanium layer and the buried insulator layer and has a lower germanium layer On one of the bottoms.

Example 28 includes the subject matter of Example 27, wherein each of the lower and upper ruthenium layers has a crystal orientation relative to one of the channel directions, and the crystal orientation of the lower ruthenium layer is the same as the crystal orientation of the upper ruthenium layer .

Example 29 includes the subject matter of Example 27, wherein each of the lower and upper ruthenium layers has a crystal orientation relative to one of the channel directions, and the crystal orientation of the lower ruthenium layer is different from the crystal orientation of the upper ruthenium layer .

Example 30 includes the subject matter of any one of examples 25 to 29, wherein the first transistor gate is centrally positioned between the second transistors such that the GaN bodies of the second transistors are separated by a distance X And the center of the first transistor gate is at a position between the second transistors, and the position is plus or minus 1 nm within one-half of the distance of X. Other tolerances should be understood.

Example 31 includes the subject matter of Example 30, wherein the configuration of one of the first transistors between two adjacent second transistors is repeated a plurality of times, and the corresponding first transistor gate position of each of the configurations is at X One or a half of the corresponding distance plus or minus 1 nm.

Example 32 includes the subject matter of any of Examples 25 to 31, wherein the first transistor gate is substantially equidistant between the GaN bodies of the second transistors.

Example 33 includes the subject matter of any one of Examples 25 to 32, wherein the source and drain regions of the first transistor are germanium, germanium or germanium (SiGe).

Example 34 includes the subject matter of any one of Examples 25 to 33, wherein the first electro-crystalline system is a PMOS transistor and the second electro-crystalline system is an NMOS transistor.

Example 35 includes the subject matter of any one of Examples 25 to 34, wherein the first transistor comprises one of gate lengths of 20 nm or less.

Example 36 includes the subject matter of any one of Examples 25 to 35, wherein the first transistor comprises a gate length of 10 nm or less.

Example 37 includes the subject matter of any one of Examples 25 to 36, wherein the polarizing layer comprises aluminum and nitrogen.

Example 38 includes a system single wafer (SOC) comprising the integrated circuit of any of examples 25-37.

Example 39 includes a radio frequency (RF) circuit comprising the integrated circuit of any of examples 25-37.

The example 40 includes a mobile computing system that includes the integrated circuits of any of the examples 25 through 37.

Example 41 is a method of forming an integrated circuit, the method comprising: depositing a cap layer of a high-k gate dielectric material on a semiconductor-on-insulator substrate, the substrate comprising a portion disposed on the material of the group IV material a buried insulator layer between the lower semiconductor layers; depositing a cover layer of the isolation material on the gate dielectric material; forming a trench by etching through the isolation and gate dielectric materials; The trenches selectively grow a Group III-N semiconductor to form a lateral epitaxial growth region on the isolation material to define a gap having a width W between lateral epitaxial growth regions of adjacent trenches And using the lateral epitaxial growth regions as a mask to form a circuit feature between the lateral epitaxial growth regions and in the isolation material.

Example 42 includes the subject matter of Example 41, wherein forming the trench by etching through the isolation and gate dielectric materials further comprises etching through the upper semiconductor layer and the buried insulator layer to expose the lower semiconductor layer.

Example 43 includes the subject matter of Example 41 or 42, wherein selectively growing a Group III-N semiconductor from the trenches comprises growing a gallium nitride (GaN) body followed by a polarized layer, followed by Multiple GaN is formed to form the lateral epitaxial growth regions.

Example 44 includes the subject matter of Example 41 or 42, wherein selectively growing a Group III-N semiconductor from the trenches comprises growing an aluminum nitride (AlN) nucleation layer followed by growth of a gallium nitride (GaN) The body, followed by a polarized layer, is followed by growing more GaN to form the lateral epitaxial growth regions.

Example 45 includes the subject matter of any one of examples 41 to 44, wherein using the lateral epitaxial growth regions as a mask to form a circuit feature between the lateral epitaxial growth regions comprises forming a transistor gate The method further includes: forming a first transistor including the gate; and forming a second transistor including the Group III-N semiconductor.

Example 46 includes the subject matter of Example 45, wherein the first electro-crystalline system is a PMOS Group IV transistor, the transistor having its channel in the upper semiconductor layer, and the second transistors are each NMOS III-V Family transistor.

Example 47 includes the subject matter of Example 45, wherein the first electro-crystalline system is a PMOS transistor having a channel in the upper semiconductor layer, and the second transistors are each an NMOS GaN transistor, wherein the upper semiconductor Layer system 矽, 锗 or 矽锗 (SiGe).

Example 48 includes the subject matter of any one of Examples 41 to 47, wherein the trenches are further etched such that they pass through the upper semiconductor layer and the buried insulator layer, each trench having a lower semiconductor layer a bottom portion, and wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to a direction of the trench, and a crystal orientation of the lower semiconductor layer is the same as a crystal orientation of the upper semiconductor layer.

Example 49 includes the subject matter of any one of Examples 41 to 47, wherein the trenches are further etched such that they pass through the upper semiconductor layer and the buried insulator layer, each trench having a lower semiconductor layer a bottom portion, and wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to a direction of the trench, and a crystal orientation of the lower semiconductor layer is different from a crystal orientation of the upper semiconductor layer.

Example 50 includes the subject matter of any of Examples 41 to 49, and further comprising removing the lateral epitaxial growth regions after forming the circuit features. However, it should be noted that in other examples, the lateral epitaxial growth regions may remain in the final integrated circuit structure.

The foregoing description of the exemplary embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to the precise form disclosed. Many modifications and variations are possible in light of the present disclosure. The scope of the disclosure is not limited by the details of the disclosure, but rather is limited by the scope of the accompanying patent application. The presently-filed application, which claims the priority of the present application, may claim the disclosed subject matter in various ways, and may generally include any collection of one or more limitations as disclosed individually or separately herein.

100‧‧‧ integrated circuit

100'‧‧‧ integrated circuit

101‧‧‧gate transistor

101A, 101B‧‧‧Group IV transistor

102‧‧‧Optoelectronics

102A, 102B, 102C‧‧‧III-N transistor

200‧‧‧Substrate

205‧‧‧Processing substrate or wafer

210‧‧‧Insulator layer

215‧‧‧Semiconductor layer

220‧‧‧ dielectric layer

230‧‧‧STI layer

335‧‧‧Ditch

440‧‧‧III-V semiconductor body

445‧‧‧III-V polarization layer

450, 450A, 450B, 450C‧‧‧III-V semiconductor materials

460‧‧‧ gap

570‧‧‧Ganjigou

680, 1099, G‧‧ ‧ gate

891‧‧‧ gate spacer

892‧‧‧ sidewall spacers

995, 1097‧‧‧ source/bungee area

996‧‧‧S/D contacts

1000‧‧‧ computing system

1002‧‧ Motherboard

1004‧‧‧ processor

1006‧‧‧Communication chip

C‧‧‧Contact

D‧‧‧汲

GD‧‧‧ gate dielectric

P‧‧‧ Polarization layer

S‧‧‧ source

SOI‧‧‧Semiconductor semiconductor structure

W, Y‧‧‧ distance

X‧‧‧ nominal distance

1 is a cross-sectional view of an integrated circuit structure assembled using a co-integrated III-V NMOS transistor and a Group IV PMOS transistor on a common substrate in accordance with an embodiment of the present disclosure.

1 ′ is a cross-sectional view of an integrated circuit structure assembled using a co-integrated III-V NMOS transistor and a Group IV PMOS transistor on a common substrate in accordance with another embodiment of the present disclosure.

2 to 10 illustrate an example of an integrated circuit structure for fabricating a co-integrated III-V NMOS transistor and a Group IV PMOS transistor on a common substrate in accordance with an embodiment of the present disclosure. Sexual process.

11 is an exemplary computing system implemented with one or more of the integrated circuit structures as disclosed herein in accordance with some embodiments of the present disclosure.

These and other features of the present invention will be better understood from the following detailed description. In the figures, each identical or nearly identical component that is illustrated in the various figures can be represented by the like. For the sake of clarity, not every component is labeled in every figure. In addition, the drawings are not necessarily to scale unless the For example, while some figures generally indicate straight lines, right angles, and smooth surfaces, the actual implementation of the disclosed technology may have less than perfect straight and right angles, given the real world limitations of the manufacturing process, and some features may have Surface topology or otherwise not smooth. In summary, the drawings are provided merely to illustrate exemplary structures.

Claims (25)

An integrated circuit comprising: a semiconductor-on-insulator substrate comprising an embedded insulator layer sandwiched between an upper portion and a lower semiconductor layer of a Group IV material; and between two adjacent second transistors a first transistor, wherein the first transistor has a channel region included in the upper semiconductor layer, and the second transistors comprise a Group III-N semiconductor structure, the Group III-N semiconductor The structure is one of the following: on the upper semiconductor layer, or through the upper semiconductor layer and the buried insulator layer and on the lower semiconductor layer. The integrated circuit of claim 1, wherein the III-N semiconductor structure for each of the second transistors is in a trench having a bottom on the upper semiconductor layer. The integrated circuit of claim 1, wherein the III-N semiconductor structure for each of the second transistors is in a trench, the trench passes through the upper semiconductor layer and the buried insulator layer, and has One of the bottoms of the lower semiconductor layer. The integrated circuit of claim 3, wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to one of the trench directions, and a crystal orientation with respect to the lower semiconductor layer and the upper semiconductor layer The crystal orientation is the same. The integrated circuit of claim 3, wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to one of the trench directions, and a crystal orientation with respect to the lower semiconductor layer is different from the upper semiconductor layer Crystal orientation. The integrated circuit of claim 1, wherein the first transistor has a gate, and the gate is centrally disposed between the second transistors such that the second transistors are separated by a distance X And the center of the gate is at a position between the second transistors, and the position is within one or a half of the distance of X plus or minus 1 nm. The integrated circuit of claim 6, wherein the configuration of the first transistor between the two adjacent second transistors is repeated a plurality of times, and the corresponding gate position for each of the configurations is at X One or more of the corresponding distances plus or minus 1 nm. The integrated circuit of claim 1, wherein the upper semiconductor layer is germanium, germanium or germanium (SiGe), and the lower semiconductor layer is germanium, germanium or germanium (SiGe). The integrated circuit of claim 1, wherein the first transistor further comprises: a gate dielectric on the channel; a gate metal on the gate dielectric; a source and a drain region of the side; and a gate spacer between the gate and the source region, and a gate spacer between the gate and the drain region, wherein the gate A polar dielectric is between the channel region and the gate spacers. The integrated circuit of claim 1, wherein the III-N semiconductor structure comprises a nucleation layer and a channel layer. The transistor of claim 1, wherein at least one of the second transistors comprises a polarizing layer within the III-N semiconductor structure or on the III-N semiconductor structure, and wherein the polarizing layer Includes aluminum and nitrogen. A system single chip comprising the integrated circuit of any one of claims 1 to 11. A radio frequency (RF) circuit comprising the integrated circuit of any one of claims 1 to 11. An action computing system comprising the integrated circuit of any one of claims 1 to 11. An integrated circuit comprising: an insulator upper substrate comprising an embedded insulator layer sandwiched between the upper and lower germanium layers; and a first transistor between the two adjacent second transistors Wherein the first electro-crystalline system is a PMOS transistor and includes: a channel region included in the upper germanium layer; a high-k gate dielectric on the channel region; and the gate dielectric a gate metal; a source and a drain region on each side of the channel region; and a gate spacer between the gate and the source region, and the gate and the gate a gate spacer between the pole regions, wherein the gate dielectric is between the channel region and the gate spacers; and wherein the second transistors are each an NMOS transistor and includes: a gallium nitride (GaN) body of one of the channel regions, the GaN main system: on the upper layer, or through the upper layer and the buried insulator layer and in the lower layer a polarizing layer on the GaN body; and on each side of the channel region And drain regions. The integrated circuit of claim 15, wherein the III-N semiconductor of each of the second transistors is in a trench, the trench passes through the upper germanium layer and the buried insulator layer, and has a lower layer One of the bottoms of the layer. The integrated circuit of claim 15, wherein the first transistor gate is centrally disposed between the second transistors such that the GaN bodies of the second transistors are separated by a distance X, and The center of the first transistor gate is at a position between the second transistors, and the position is within one or a half of the distance of X plus or minus 1 nm. The integrated circuit of claim 17, wherein the configuration of the first transistor between the two adjacent second transistors is repeated a plurality of times, and the corresponding first transistor gate for each of the configurations The position is within one or a half of the corresponding distance of X plus or minus 1 nm. The integrated circuit of claim 15, wherein the source and drain regions of the first transistor are 矽, 锗 or 矽锗 (SiGe). A system single chip comprising the integrated circuit of any one of claims 15 to 19. A method of forming an integrated circuit, the method comprising: depositing a cap layer of a high-k gate dielectric material on a semiconductor-on-insulator substrate, the substrate comprising an upper semiconductor layer and a lower semiconductor layer a buried insulator layer therebetween; depositing a cover layer of the isolation material on the gate dielectric material; forming a trench by etching through the isolation and gate dielectric materials; Selectively growing a Group III-N semiconductor to form a lateral epitaxial growth region on the isolation material, thereby defining a gap having a width W between the lateral epitaxial growth regions of adjacent trenches; and using The lateral epitaxial growth regions act as a mask between the lateral epitaxial growth regions and form a circuit feature in the isolation material. The method of claim 21, wherein forming the trench by etching through the isolation and gate dielectric materials further comprises etching through the upper semiconductor layer and the buried insulator layer to expose the lower semiconductor layer. The method of claim 21, wherein selectively growing a Group III-N semiconductor from the trenches comprises growing a gallium nitride (GaN) body followed by a polarization layer followed by more GaN These lateral epitaxial growth regions are formed. The method of claim 21, wherein selectively growing a Group III-N semiconductor from the trenches comprises growing an aluminum nitride (AlN) nucleation layer followed by growing a gallium nitride (GaN) body, This is followed by a polarization layer followed by growth of more GaN to form the lateral epitaxial growth regions. The method of any one of claims 21 to 24, further comprising removing the lateral epitaxial growth regions after forming the circuit features.