JP5010104B2 - Mtcmos装置及びその制御方法 - Google Patents
Mtcmos装置及びその制御方法 Download PDFInfo
- Publication number
- JP5010104B2 JP5010104B2 JP2005017129A JP2005017129A JP5010104B2 JP 5010104 B2 JP5010104 B2 JP 5010104B2 JP 2005017129 A JP2005017129 A JP 2005017129A JP 2005017129 A JP2005017129 A JP 2005017129A JP 5010104 B2 JP5010104 B2 JP 5010104B2
- Authority
- JP
- Japan
- Prior art keywords
- logic state
- control signal
- signal
- control
- mtcmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
- F16B—DEVICES FOR FASTENING OR SECURING CONSTRUCTIONAL ELEMENTS OR MACHINE PARTS TOGETHER, e.g. NAILS, BOLTS, CIRCLIPS, CLAMPS, CLIPS OR WEDGES; JOINTS OR JOINTING
- F16B11/00—Connecting constructional elements or machine parts by sticking or pressing them together, e.g. cold pressure welding
- F16B11/006—Connecting constructional elements or machine parts by sticking or pressing them together, e.g. cold pressure welding by gluing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
- F16B—DEVICES FOR FASTENING OR SECURING CONSTRUCTIONAL ELEMENTS OR MACHINE PARTS TOGETHER, e.g. NAILS, BOLTS, CIRCLIPS, CLAMPS, CLIPS OR WEDGES; JOINTS OR JOINTING
- F16B37/00—Nuts or like thread-engaging members
- F16B37/04—Devices for fastening nuts to surfaces, e.g. sheets, plates
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Mechanical Engineering (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040005598A KR100574967B1 (ko) | 2004-01-29 | 2004-01-29 | Mtcmos용 제어회로 |
| KR2004-005598 | 2004-01-29 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005218099A JP2005218099A (ja) | 2005-08-11 |
| JP2005218099A5 JP2005218099A5 (enExample) | 2008-02-14 |
| JP5010104B2 true JP5010104B2 (ja) | 2012-08-29 |
Family
ID=34806011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005017129A Expired - Fee Related JP5010104B2 (ja) | 2004-01-29 | 2005-01-25 | Mtcmos装置及びその制御方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7215155B2 (enExample) |
| JP (1) | JP5010104B2 (enExample) |
| KR (1) | KR100574967B1 (enExample) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101045295B1 (ko) | 2004-04-29 | 2011-06-29 | 삼성전자주식회사 | Mtcmos 플립-플롭, 그를 포함하는 mtcmos회로, 및 그 생성 방법 |
| KR100564634B1 (ko) * | 2004-10-08 | 2006-03-28 | 삼성전자주식회사 | 단락전류 방지회로를 구비한 mtcmos 회로 시스템 |
| JP2008522258A (ja) * | 2004-11-30 | 2008-06-26 | フリースケール セミコンダクター インコーポレイテッド | 選択的なパワー・ゲーティングを用いて電力消費を低減する装置及び方法 |
| US20060273391A1 (en) * | 2005-06-01 | 2006-12-07 | Diaz Carlos H | CMOS devices for low power integrated circuits |
| US7391232B1 (en) * | 2007-10-30 | 2008-06-24 | International Business Machines Corporation | Method and apparatus for extending lifetime reliability of digital logic devices through reversal of aging mechanisms |
| US7391233B1 (en) * | 2007-10-30 | 2008-06-24 | International Business Machines Corporation | Method and apparatus for extending lifetime reliability of digital logic devices through removal of aging mechanisms |
| KR101477512B1 (ko) * | 2008-03-18 | 2014-12-31 | 삼성전자주식회사 | 액티브 클럭 쉴딩 구조의 회로 및 이를 포함하는 반도체집적 회로 |
| KR101003153B1 (ko) * | 2009-05-15 | 2010-12-21 | 주식회사 하이닉스반도체 | 전압 안정화 회로 및 이를 이용한 반도체 메모리 장치 |
| US8026741B2 (en) * | 2009-07-31 | 2011-09-27 | Apple Inc. | CMOS circuitry with mixed transistor parameters |
| US7977972B2 (en) | 2009-08-07 | 2011-07-12 | The Board Of Trustees Of The University Of Arkansas | Ultra-low power multi-threshold asynchronous circuit design |
| US8736332B2 (en) * | 2009-12-17 | 2014-05-27 | Lsi Corporation | Leakage current reduction in a sequential circuit |
| US8390331B2 (en) * | 2009-12-29 | 2013-03-05 | Nxp B.V. | Flexible CMOS library architecture for leakage power and variability reduction |
| US8738940B2 (en) | 2011-09-06 | 2014-05-27 | Lsi Corporation | Power controller for SoC power gating applications |
| US8669800B2 (en) * | 2012-02-24 | 2014-03-11 | International Business Machines Corporation | Implementing power saving self powering down latch structure |
| US9094013B2 (en) | 2013-05-24 | 2015-07-28 | The Board Of Trustees Of The University Of Arkansas | Single component sleep-convention logic (SCL) modules |
| US9287858B1 (en) | 2014-09-03 | 2016-03-15 | Texas Instruments Incorporated | Low leakage shadow latch-based multi-threshold CMOS sequential circuit |
| US10367514B2 (en) | 2015-01-24 | 2019-07-30 | Circuit Seed, Llc | Passive phased injection locked circuit |
| EP3329598A4 (en) | 2015-07-29 | 2019-07-31 | Circuit Seed, LLC | COMPLEMENTARY POWER FIELD EFFECT TRANSISTOR DEVICES AND AMPLIFIERS |
| WO2017019973A1 (en) * | 2015-07-30 | 2017-02-02 | Circuit Seed, Llc | Multi-stage and feed forward compensated complementary current field effect transistor amplifiers |
| US10476457B2 (en) | 2015-07-30 | 2019-11-12 | Circuit Seed, Llc | Low noise trans-impedance amplifiers based on complementary current field-effect transistor devices |
| CN108140614A (zh) | 2015-07-30 | 2018-06-08 | 电路种子有限责任公司 | 基于互补电流场效应晶体管装置的参考产生器和电流源晶体管 |
| US10283506B2 (en) | 2015-12-14 | 2019-05-07 | Circuit Seed, Llc | Super-saturation current field effect transistor and trans-impedance MOS device |
| KR102420005B1 (ko) * | 2017-12-21 | 2022-07-12 | 에스케이하이닉스 주식회사 | 파워 게이팅 제어 회로 |
| US11271566B2 (en) * | 2018-12-14 | 2022-03-08 | Integrated Device Technology, Inc. | Digital logic compatible inputs in compound semiconductor circuits |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW334532B (en) | 1996-07-05 | 1998-06-21 | Matsushita Electric Industrial Co Ltd | The inspection system of semiconductor IC and the method of generation |
| TW365007B (en) | 1996-12-27 | 1999-07-21 | Matsushita Electric Industrial Co Ltd | Driving method of semiconductor integrated circuit and the semiconductor integrated circuit |
| JP3856892B2 (ja) * | 1997-03-03 | 2006-12-13 | 日本電信電話株式会社 | 自己同期型パイプラインデータパス回路および非同期信号制御回路 |
| JPH10261946A (ja) * | 1997-03-19 | 1998-09-29 | Mitsubishi Electric Corp | 半導体集積回路 |
| JPH11112297A (ja) * | 1997-10-06 | 1999-04-23 | Nec Corp | ラッチ回路及びこのラッチ回路を有する半導体集積回路 |
| WO1999066640A1 (en) | 1998-06-18 | 1999-12-23 | Hitachi, Ltd. | Semiconductor integrated circuit |
| JP3878431B2 (ja) * | 2000-06-16 | 2007-02-07 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
| JP3727838B2 (ja) * | 2000-09-27 | 2005-12-21 | 株式会社東芝 | 半導体集積回路 |
| JP3864248B2 (ja) * | 2001-12-17 | 2006-12-27 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 半導体装置 |
| JP3986393B2 (ja) * | 2002-08-27 | 2007-10-03 | 富士通株式会社 | 不揮発性データ記憶回路を有する集積回路装置 |
-
2004
- 2004-01-29 KR KR1020040005598A patent/KR100574967B1/ko not_active Expired - Fee Related
- 2004-11-23 US US10/996,084 patent/US7215155B2/en not_active Expired - Lifetime
-
2005
- 2005-01-25 JP JP2005017129A patent/JP5010104B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20050168242A1 (en) | 2005-08-04 |
| KR20050077921A (ko) | 2005-08-04 |
| JP2005218099A (ja) | 2005-08-11 |
| US7215155B2 (en) | 2007-05-08 |
| KR100574967B1 (ko) | 2006-04-28 |
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