JP4982809B2 - Coaxial via connection structure - Google Patents

Coaxial via connection structure Download PDF

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JP4982809B2
JP4982809B2 JP2008517842A JP2008517842A JP4982809B2 JP 4982809 B2 JP4982809 B2 JP 4982809B2 JP 2008517842 A JP2008517842 A JP 2008517842A JP 2008517842 A JP2008517842 A JP 2008517842A JP 4982809 B2 JP4982809 B2 JP 4982809B2
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coaxial
line
connection structure
shield electrode
layer
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JPWO2007138895A1 (en
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昌宏 青柳
博 仲川
克弥 菊地
時彦 横島
泰弘 山地
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National Institute of Advanced Industrial Science and Technology AIST
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0222Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00Auxiliary devices
    • H01P1/04Fixed joints
    • H01P1/045Coaxial joints
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P11/00Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09718Clearance holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809Coaxial layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
    • H05K2203/0733Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Waveguides (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Description

本発明は、各種実装構造体、特に多層同軸配線に有用な同軸型ビア接続構造及びその製造方法に関するものである。   The present invention relates to a coaxial via connection structure useful for various mounting structures, particularly multilayer coaxial wiring, and a method for manufacturing the same.

電子機器の高速化および高周波化に伴い、機器内の配線について、その信号伝送特性の向上が求められている。半導体デバイスパッケージ、プリント回路基板、フレキシブル回路基板などの実装構造体における配線については、特性インピーダンスを一定にするために、通常、ストリップ線路、マイクロストリップ線路、平面導波路線路などの伝送線路構造が用いられている。   With the increase in speed and frequency of electronic devices, improvement in signal transmission characteristics is required for the wiring in the devices. For wiring in mounting structures such as semiconductor device packages, printed circuit boards, and flexible circuit boards, transmission line structures such as strip lines, microstrip lines, and planar waveguide lines are usually used to make the characteristic impedance constant. It has been.

特に、伝送線路構造の中でも同軸線路は、最も優れた信号伝送特性を有するため、ケーブルとして広く用いられており、また実装構造体においては、たとえば、下記非特許文献1に開示された同軸線路構造や、下記特許文献1に開示されたプリント回路基板内に同軸線路構造を実現する製造技術が知られている。下記特許文献2には、シリコン半導体デバイス用多層配線プロセスとしての、多層微細配線構造の製造方法も開示されている。
R.C. Landis, "Buried Coaxial Conductors for High-Speed Interconnections", IEEE Trans. Components, Hybrids, and Manufacturing Tech., Vol.CHMT-10; No.2, pp. 204-208, 1987 特開2003−249731号公報 特開2003−309121号公報
In particular, among transmission line structures, a coaxial line has the most excellent signal transmission characteristics and is therefore widely used as a cable. In a mounting structure, for example, the coaxial line structure disclosed in Non-Patent Document 1 below is used. In addition, a manufacturing technique for realizing a coaxial line structure in a printed circuit board disclosed in Patent Document 1 below is known. Patent Document 2 listed below also discloses a method for manufacturing a multilayer fine wiring structure as a multilayer wiring process for silicon semiconductor devices.
RC Landis, "Buried Coaxial Conductors for High-Speed Interconnections", IEEE Trans. Components, Hybrids, and Manufacturing Tech., Vol.CHMT-10; No.2, pp. 204-208, 1987 JP 2003-249731 A JP 2003-309121 A

しかしながら、非特許文献1および特許文献1に記載の技術は、平面的な配線を実現するものであって、多層配線に必要なビア接続構造を考慮していない。また、プリント回路技術を用いる場合、最小の線幅は10から20ミクロン程度となり、これより微細な配線を実現するには、異なる製造プロセスを用いる必要がある。これに対し、特許文献2は、シリコン半導体デバイス用多層配線プロセスを用いて多層配線に展開できる同軸線路構造を提案してはいるものの、実装構造体内で配線を10ミクロン以下まで微細化することはやはり難しい。   However, the techniques described in Non-Patent Document 1 and Patent Document 1 realize planar wiring and do not consider a via connection structure necessary for multilayer wiring. Also, when using printed circuit technology, the minimum line width is about 10 to 20 microns, and different manufacturing processes must be used to realize finer wiring. On the other hand, Patent Document 2 proposes a coaxial line structure that can be developed into a multi-layer wiring by using a multi-layer wiring process for silicon semiconductor devices, but it is not possible to miniaturize the wiring to 10 microns or less in the mounting structure. After all it is difficult.

そこで、以上のとおりの事情に鑑み、本発明は、同軸線路構造を多層化する際に必要な同軸線路対応の同軸型ビア接続構造およびこれを用いた多層同軸配線を提供し、さらに、その製造プロセスにシリコン半導体デバイス用多層配線プロセスを用いて、最小の線幅を10ミクロン以下から1ミクロン程度(つまり配線用金属材料の表皮深さと同じ程度)までに微細化することが可能な製造方法を提供することを課題としている。   Accordingly, in view of the circumstances as described above, the present invention provides a coaxial via connection structure corresponding to a coaxial line and a multilayer coaxial wiring using the coaxial line structure, which are necessary when multilayering the coaxial line structure, and further manufacturing the same. A manufacturing method capable of reducing the minimum line width from 10 microns or less to about 1 micron (that is, the same as the skin depth of the metal material for wiring) by using a multilayer wiring process for silicon semiconductor devices in the process. The issue is to provide.

上記目的を達成するために、本発明の同軸型ビア接続構造は、互いに異なる高さに位置し且つ交わる方向に延びる上下層の同軸線路をビア接続するためのものであり、上下層の同軸線路に対応する高さを持つシールド電極壁と、シールド電極壁において下層の同軸線路に対応する位置にある下層接続開口部と、シールド電極壁において上層の同軸線路に対応する位置にある上層接続開口部と、シールド電極壁内において下層接続開口部および上層接続開口部の間を結ぶ信号線とを有しており、上下層の同軸線路が交差する位置に配置されて、下層接続開口部に位置する下層の同軸線路と上層接続開口部に位置する上層の同軸線路とを信号線で接続することを特徴とする。   In order to achieve the above object, the coaxial via connection structure of the present invention is for via-connecting upper and lower coaxial lines located at different heights and extending in intersecting directions. A shield electrode wall having a height corresponding to, a lower layer connection opening at a position corresponding to the lower coaxial line in the shield electrode wall, and an upper layer connection opening at a position corresponding to the upper coaxial line in the shield electrode wall And a signal line that connects between the lower layer connection opening and the upper layer connection opening in the shield electrode wall, and is disposed at a position where the upper and lower coaxial lines intersect and is positioned at the lower layer connection opening. The lower-layer coaxial line and the upper-layer coaxial line located in the upper-layer connection opening are connected by a signal line.

信号線は、下層接続開口部からシールド電極壁内に延びた下層線部と、上層接続開口部からシールド電極壁内に延びた上層線部と、下層線部および上層線部を結ぶ線部とを有している。また、信号線は、その一端が下層接続開口部にて下層の同軸線路と結線し、他端が上層接続開口部にて上層の同軸線路と結線する。   The signal line includes a lower layer line portion extending from the lower layer connection opening into the shield electrode wall, an upper layer line portion extending from the upper layer connection opening into the shield electrode wall, and a line portion connecting the lower layer line portion and the upper layer line portion. have. One end of the signal line is connected to the lower coaxial line at the lower layer connection opening, and the other end is connected to the upper coaxial line at the upper layer connection opening.

シールド電極壁及び信号線は金属であり、信号線は、10μm以下の線幅である。また、多層同軸配線は、前記同軸型ビア接続構造を用いる。   The shield electrode wall and the signal line are metal, and the signal line has a line width of 10 μm or less. The multilayer coaxial wiring uses the coaxial via connection structure.

そしてさらに、本発明の同軸型ビア接続構造の製造方法は、
基板上にグランド金属層を堆積させ、該グランド金属層上に絶縁層を塗布し、該絶縁層に、同軸型ビア接続構造のシールド電極壁の下層部分のうちの下半分(V1)および下層の同軸線路のシールド電極壁のうちの下半分(LL1)に相当する溝パターンを形成し、該溝パターンに金属を充填して、前記下半分(V1)および前記下半分(LL1)を形成する工程と、
同軸ビア接続構造中の信号線を構成する下層線部および同軸ビア接続構造が接続する下層の同軸線路の信号線に対応するパターンを形成し、配線金属層を堆積させた後、該パターン上の配線金属層を除去して、前記下層線部および前記信号線を形成する工程と、
絶縁層をさらに塗布し、該絶縁層に、同軸ビア接続構造のシールド電極壁の下層部分のうちの上半分(V2)、下層の同軸線路のシールド電極壁のうちの上半分(LL2)、および同軸ビア接続構造中の信号線を構成する線部の下半分(C1)に相当する溝および穴パターンを形成し、該溝および穴パターンに金属を充填して、前記上半分(V2)、前記上半分(LL2)、および前記下半分(C1)を形成する工程と、
下層の同軸線路のシールド電極の上面部分(LL3)および上層の同軸線路のシールド電極の下面部分(UL1)となるグランド層用パターンを形成し、グランド金属層を堆積させた後、該グランド層用パターン上のグランド金属層を除去して、前記上面部分(LL3)および前記下面部分(UL1)を形成する工程と、
絶縁層をさらに塗布し、該絶縁層に、同軸ビア接続構造のシールド電極壁の上層部分のうちの下半分(V3)、上層の同軸線路のシールド電極壁のうちの下半分(UL2)、および同軸ビア接続構造中の信号線を構成する線部の上半分(C2)に相当する絶縁層の溝および穴パターンを形成し、該溝および穴パターンに金属を充填して、前記下半分(V3)、前記下半分(UL2)、および前記上半分(C2)を形成する工程と、
同軸ビア接続構造中の信号線を構成する上層線部および同軸ビア接続構造が接続する上層の同軸線路の信号線に対応するパターンを形成し、配線金属層を堆積させた後、該パターン上の配線金属層を除去して、前記上層線部および前記信号線を形成する工程と、
絶縁層をさらに塗布し、同軸ビア接続構造のシールド電極壁の上層部分のうちの上半分(V4)および上層の同軸線路のシールド電極壁のうちの上半分(UL3)に相当する絶縁層の溝パターンを形成し、該溝パターンに金属を充填して、前記上半分(V4)および前記上半分(UL3)を形成する工程と、
上層の同軸線路のシールド電極の上面部分(UL4)となるグランド層用パターンを形成し、グランド金属層を堆積させた後、該グランド層用パターン上のグランド金属層を除去する工程と、
を含むことを特徴とする。
And furthermore, the manufacturing method of the coaxial via connection structure of the present invention,
A ground metal layer is deposited on the substrate, an insulating layer is applied on the ground metal layer, and the lower half (V1) and the lower layer of the lower layer portion of the shield electrode wall of the coaxial via connection structure are applied to the insulating layer. Forming a groove pattern corresponding to the lower half (LL1) of the shield electrode wall of the coaxial line and filling the groove pattern with metal to form the lower half (V1) and the lower half (LL1) When,
After forming a pattern corresponding to the signal line of the lower layer line portion constituting the signal line in the coaxial via connection structure and the lower layer coaxial line to which the coaxial via connection structure is connected, and depositing the wiring metal layer, Removing the wiring metal layer and forming the lower line portion and the signal line;
An insulating layer is further applied to the upper half (V2) of the lower layer portion of the shield electrode wall of the coaxial via connection structure, an upper half (LL2) of the lower shield electrode wall of the coaxial line, and A groove and a hole pattern corresponding to the lower half (C1) of the line portion constituting the signal line in the coaxial via connection structure are formed, and the groove and the hole pattern are filled with metal, and the upper half (V2), Forming an upper half (LL2) and the lower half (C1);
After forming a ground layer pattern to be the upper surface portion (LL3) of the shield electrode of the lower coaxial line and the lower surface portion (UL1) of the shield electrode of the upper coaxial line, and depositing a ground metal layer, the ground layer Removing the ground metal layer on the pattern to form the upper surface portion (LL3) and the lower surface portion (UL1);
An insulating layer is further applied to the insulating layer, the lower half (V3) of the upper layer portion of the shield electrode wall of the coaxial via connection structure, the lower half (UL2) of the shield electrode wall of the upper coaxial line, and A groove and a hole pattern of an insulating layer corresponding to the upper half (C2) of the line portion constituting the signal line in the coaxial via connection structure are formed, and the groove and the hole pattern are filled with metal, and the lower half (V3 ), Forming the lower half (UL2) and the upper half (C2);
A pattern corresponding to an upper layer line portion constituting a signal line in the coaxial via connection structure and a signal line of an upper coaxial line to which the coaxial via connection structure is connected is formed, and after a wiring metal layer is deposited, Removing the wiring metal layer to form the upper layer line portion and the signal line;
An insulating layer is further applied, and the groove of the insulating layer corresponding to the upper half (V4) of the upper layer portion of the shield electrode wall of the coaxial via connection structure and the upper half (UL3) of the shield electrode wall of the upper coaxial line Forming a pattern and filling the groove pattern with metal to form the upper half (V4) and the upper half (UL3);
Forming a ground layer pattern to be the upper surface portion (UL4) of the shield electrode of the upper coaxial line, depositing a ground metal layer, and then removing the ground metal layer on the ground layer pattern;
It is characterized by including.

上記のとおりの特徴を有する本発明によれば、同軸線路構造を多層化する際に必要な同軸線路対応の同軸型ビア接続構造およびこれを用いた多層同軸配線を提供でき、また、その製造プロセスにシリコン半導体デバイス用多層配線プロセスを用いることにより、最小の線幅を10ミクロン以下から1ミクロン程度(配線用金属材料の表皮深さと同じ程度)までに微細化することが可能となる。   According to the present invention having the features as described above, it is possible to provide a coaxial via connection structure corresponding to a coaxial line necessary for multilayering the coaxial line structure, and a multilayer coaxial wiring using the same, and a manufacturing process thereof Further, by using a multilayer wiring process for silicon semiconductor devices, the minimum line width can be miniaturized from 10 microns or less to about 1 micron (same as the skin depth of the wiring metal material).

本発明の同軸型ビア接続構造の一実施形態を示した斜視図。The perspective view which showed one Embodiment of the coaxial type via | veer connection structure of this invention. 本発明の同軸型ビア接続構造の一実施形態を示した斜視図。The perspective view which showed one Embodiment of the coaxial type via | veer connection structure of this invention. 多層同軸配線における図1Aの同軸型ビア接続構造およびその周辺を例示した透過斜視図。1B is a transparent perspective view illustrating the coaxial via connection structure of FIG. 1A and its periphery in a multilayer coaxial wiring. FIG. 多層同配線における図1Aの同軸型ビア接続構造およびその周辺を例示した透過斜視図。Coaxial via connection structure and transparent perspective view illustrating the periphery thereof in FIG. 1A in the multilayer coaxial wiring. 多層同軸配線における本発明の同軸型ビア接続構造の配置について説明するための図。The figure for demonstrating arrangement | positioning of the coaxial via | veer connection structure of this invention in a multilayer coaxial wiring. 本発明の同軸型ビア接続構造による同軸線路の接続方向について説明するための図。The figure for demonstrating the connection direction of the coaxial line by the coaxial via | veer connection structure of this invention. 本発明の同軸型ビア接続構造による同軸線路の接続方向について説明するための別の図。The another figure for demonstrating the connection direction of the coaxial line by the coaxial via | veer connection structure of this invention. 本発明の多層同軸配線の製造方法の一実施形態について説明するためのフローチャート。The flowchart for demonstrating one Embodiment of the manufacturing method of the multilayer coaxial wiring of this invention. 図5Aに続くフローチャート。The flowchart following FIG. 5A. 図5Bに続くフローチャート。The flowchart following FIG. 5B. 図5Cに続くフローチャート。The flowchart following FIG. 5C. 図5A−図5Dの各ステップにて形成される部位ついて説明するための図。The figure for demonstrating the site | part formed in each step of FIG. 5A-FIG. 5D. 図5A−図5Dの各ステップにて形成される部位ついて説明するための図。The figure for demonstrating the site | part formed in each step of FIG. 5A-FIG. 5D. 図5A−図5Dの各ステップにて形成される部位ついて説明するための図。The figure for demonstrating the site | part formed in each step of FIG. 5A-FIG. 5D. 本発明の同軸型ビア接続構造の別の一実施形態を示した斜視図。The perspective view which showed another one Embodiment of the coaxial via | veer connection structure of this invention. 本発明の同軸型ビア接続構造の別の一実施形態を示した斜視図。The perspective view which showed another one Embodiment of the coaxial via | veer connection structure of this invention. 本発明の同軸型ビア接続構造の参考例を示した斜視図。The perspective view which showed the reference example of the coaxial via | veer connection structure of this invention.

符号の説明Explanation of symbols

1 同軸型ビア接続構造
11 シールド電極壁
12a 下層接続開口部
12b 上層接続開口部
13 信号線
131 下層水平線部
132 上層水平線部
133 垂直線部
14 絶縁層
2a,2a’,2a” 同軸線路
2b 同軸線路
21a,21b 信号線
30 基板
31 グランド金属層
32 感光性絶縁層
33 フォトマスク
331 パターン
34 溝パターン
35 金属
36 レジストパターン
37 配線金属層
38 感光性絶縁層
39 フォトマスク
391 パターン
40 溝および穴パターン
41 金属
42 レジストパターン
43 グランド金属層
44 感光性絶縁層
45 フォトマスク
451 パターン
46 溝および穴パターン
47 金属
48 レジストパターン
49 配線金属層
50 感光性絶縁層
51 フォトマスク
511 パターン
52 溝パターン
53 金属
54 レジストパターン
55 グランド金属層
DESCRIPTION OF SYMBOLS 1 Coaxial via connection structure 11 Shield electrode wall 12a Lower layer connection opening 12b Upper layer connection opening 13 Signal line 131 Lower layer horizontal line part 132 Upper layer horizontal line part 133 Vertical line part 14 Insulating layer 2a, 2a ', 2a "Coaxial line 2b Coaxial line 21a, 21b Signal line 30 Substrate 31 Ground metal layer 32 Photosensitive insulating layer 33 Photomask 331 Pattern 34 Groove pattern 35 Metal 36 Resist pattern 37 Wiring metal layer 38 Photosensitive insulating layer 39 Photomask 391 Pattern 40 Groove and hole pattern 41 Metal 42 resist pattern 43 ground metal layer 44 photosensitive insulating layer 45 photomask 451 pattern 46 groove and hole pattern 47 metal 48 resist pattern 49 wiring metal layer 50 photosensitive insulating layer 51 photomask 511 pattern 52 groove pattern Down 53 metal 54 resist pattern 55 ground metal layer

[第一の実施形態]
図1Aおよび図1Bは、各々、本発明の同軸型ビア接続構造の一実施形態を示した図であり、図2Aおよび図2Bは、各々、多層同軸配線構造における同軸型ビア接続構造とその周辺を示した図であり、図3は、多層同軸配線構造における同軸型ビア接続構造の配置例を示した図である。
[First embodiment]
1A and 1B are diagrams showing an embodiment of the coaxial via connection structure of the present invention, respectively. FIGS. 2A and 2B are coaxial via connection structures in a multilayer coaxial wiring structure and their surroundings, respectively. FIG. 3 is a diagram showing an arrangement example of the coaxial via connection structure in the multilayer coaxial wiring structure.

本実施形態の同軸型ビア接続構造1は、互いに異なる高さに位置し且つ交わる方向に延びる2本の同軸線路2a,2b(図2A,図2B,図3参照)が交差する位置に配置されて、それら同軸線路2a,2bをビア接続するものである。より具体的には、同軸型ビア接続構造1は、上下に異なる高さに位置する2本の同軸線路2a,2bを接続するために必要な高さ、つまり上下層の同軸線路2a,2bに届く高さを持つ角柱形状のシールド電極壁11と、シールド電極壁11の一側面において下層の同軸線路2aの高さ位置に形成された下層接続開口部12aと、シールド電極壁11の他の一側面において上層の同軸線路2bの高さ位置に形成された上層接続開口部12bと、シールド電極壁11内において下層接続開口部12aおよび上層接続開口部12bの間を結ぶように形成された1本の信号線13とを有している。   The coaxial via connection structure 1 of the present embodiment is disposed at a position where two coaxial lines 2a and 2b (see FIGS. 2A, 2B, and 3) that are located at different heights and extend in intersecting directions intersect each other. The coaxial lines 2a and 2b are connected via vias. More specifically, the coaxial via connection structure 1 has a height required to connect two coaxial lines 2a and 2b located at different heights in the vertical direction, that is, the coaxial lines 2a and 2b in the upper and lower layers. A shield electrode wall 11 having a prismatic shape having a reachable height, a lower layer connection opening 12a formed at one side of the shield electrode wall 11 at the height position of the lower coaxial line 2a, and another one of the shield electrode wall 11 An upper layer connection opening 12b formed at the height of the upper coaxial line 2b on the side surface and one line formed to connect the lower layer connection opening 12a and the upper layer connection opening 12b in the shield electrode wall 11 Signal line 13.

シールド電極壁11で囲まれた内部は絶縁層14となっており、信号線13の周囲を取り囲んでいる。言い換えると、信号線13の周囲を絶縁層14で取り囲み、絶縁層14の外側をシールド電極壁11で覆うことで、同軸型のビア構造を形成している。   The inside surrounded by the shield electrode wall 11 is an insulating layer 14 and surrounds the periphery of the signal line 13. In other words, the coaxial line via structure is formed by surrounding the signal line 13 with the insulating layer 14 and covering the outside of the insulating layer 14 with the shield electrode wall 11.

信号線13は、下層接続開口部12aからシールド電極壁11内に水平方向に延びた下層水平線部131と、上層接続開口部12bからシールド電極壁11内に水平方向に延びた上層水平線部132と、下層水平線部131の内端および上層水平線部132の内端を結ぶ垂直方向に延びた垂直線部133とを有しており、それらが一本となって下層接続開口部12aおよび上層接続開口部12bの間に延びた信号線13を構成している。   The signal line 13 includes a lower layer horizontal line part 131 extending in the horizontal direction from the lower layer connection opening 12a into the shield electrode wall 11, and an upper layer horizontal line part 132 extending in the horizontal direction from the upper layer connection opening 12b to the shield electrode wall 11. And a vertical line portion 133 extending in the vertical direction connecting the inner end of the lower layer horizontal line portion 131 and the inner end of the upper layer horizontal line portion 132, and these lower layer connection openings 12 a and the upper layer connection openings A signal line 13 extending between the portions 12b is formed.

本実施形態での信号線13を構成する線分はそれぞれ水平方向、垂直方向に延びたものとしているが、下層の同軸線路2aおよび上層の同軸線路2bを接続する信号線13が構成されればよいので、特に水平、垂直に限定されるわけではなく、斜め方向に延びているもの、曲がり角が直角ではなくカーブしているものなど、様々な形状を採用可能である。   The line segments constituting the signal line 13 in this embodiment are assumed to extend in the horizontal direction and the vertical direction, respectively, but if the signal line 13 connecting the lower coaxial line 2a and the upper coaxial line 2b is configured. Since it is good, it is not particularly limited to horizontal and vertical, and various shapes such as those extending in an oblique direction and those having a curved corner instead of a right angle can be adopted.

そして、下層接続開口部12aにて下層水平線部131の接続端が下層の同軸線路2aと結線し、上層接続開口部12bにて上層水平線部132の接続端が上層の同軸線路2bと結線することで、同軸線路2a,2bを的確にビア接続できる。   The connection end of the lower horizontal line portion 131 is connected to the lower coaxial line 2a at the lower layer connection opening 12a, and the connection end of the upper horizontal line portion 132 is connected to the upper coaxial line 2b at the upper layer connection opening 12b. Thus, the coaxial lines 2a and 2b can be accurately via-connected.

たとえば図3に例示したように、図面中で縦方向に走る下層の同軸線路2a’と図面中で横方向に走る上層の同軸線路2bが交差する点P1に、図1A,図2Aの同軸ビア配線構造1を配置し、同じ同軸線路2bと下層の別の同軸線路2a”が交差する点P2に、図1B,図2Bの同軸ビア配線構造1を配置することで、交差点P1にて同軸線路2a’から90度左に曲がって同軸線路2bへ繋がり、さらに交差点P2にて同軸線路2bから90度右に曲がって同軸線路2a”へ繋がって、A点とB点が接続されることとなる。   For example, as illustrated in FIG. 3, the coaxial via shown in FIGS. 1A and 2A is formed at a point P1 where the lower coaxial line 2a 'running in the vertical direction in the drawing intersects with the upper coaxial line 2b running in the horizontal direction in the drawing. The wiring structure 1 is arranged, and the coaxial via wiring structure 1 shown in FIGS. 1B and 2B is arranged at a point P2 where the same coaxial line 2b and another lower coaxial line 2a ″ intersect, so that the coaxial line at the intersection P1. Turn 90 degrees to the left from 2a ′ and connect to the coaxial line 2b. Further, turn 90 degrees to the right from the coaxial line 2b and connect to the coaxial line 2a ″ at the intersection P2, and the points A and B are connected. .

すなわち、本発明の同軸ビア接続構造1によれば、多層同軸配線構造にて単に上下層の同軸線路2a(2a’,2a”),2bを接続できるだけではなく、上下異なる層に位置し且つ直交する方向に延びる同軸線路2a,2bを3次元方向に接続できる。   That is, according to the coaxial via connection structure 1 of the present invention, not only can the upper and lower coaxial lines 2a (2a ', 2a ") and 2b be connected in the multilayer coaxial wiring structure, but they are located in different layers and orthogonal to each other. The coaxial lines 2a and 2b extending in the direction to be connected can be connected in a three-dimensional direction.

図4Aおよび図4Bは、各々、上下2本の同軸線路2a,2bについて、本発明の同軸型ビア接続構造1を使って接続を行う際に取りうる8種類の接続形態を示した図であり、図4Aは、図1Aの同軸型ビア接続構造1の向きを変えることで、下層の同軸線路2aから90度左に曲がって上層の同軸線路2bに接続する4種類、図4Bは、図1Bの同軸型ビア接続構造1の向きを変えることで、下層の同軸線路2aから90度右に曲がって上層の同軸線路2bに接続する4種類を示している。これらの図から分かるように、同軸型ビア接続構造1は、図1Aおよび図1Bの2種類の構造に集約され、この2種類について設計、試作、特性評価などを行えば、それぞれ4種類の接続形態、つまり全部で8種類の接続形態を実現することができる。   4A and 4B are diagrams showing eight types of connection modes that can be taken when connecting the upper and lower coaxial lines 2a and 2b using the coaxial via connection structure 1 of the present invention. 4A shows four types of connecting to the upper coaxial line 2b by turning 90 degrees to the left from the lower coaxial line 2a by changing the direction of the coaxial via connection structure 1 in FIG. 1A. By changing the direction of the coaxial via connection structure 1, four types are shown that turn 90 degrees to the right from the lower coaxial line 2 a and connect to the upper coaxial line 2 b. As can be seen from these figures, the coaxial via connection structure 1 is aggregated into two types of structures shown in FIGS. 1A and 1B, and if these two types are designed, prototyped, and evaluated for characteristics, four types of connections are made. The form, that is, eight kinds of connection forms in total can be realized.

[第二の実施形態]
図5A−図5Dは、各々、上述した本発明の同軸型ビア接続構造1を用いた多層同軸配線の製造方法の一例について説明するためのフローチャートであり、接続対象である上下層の同軸線路2a,2bを同軸型ビア接続構造1と同時に形成する場合のものである。以下、図中のステップ番号の順番にプロセスの説明を行う。なお、図6A,Bおよび図7は、各ステップの説明で使用するV1、LL1、UL1等の記号を付した部位がどの部位に該当するかを示すものであり、図1および図2A,Bとともに適宜参照する。
[Second Embodiment]
FIGS. 5A to 5D are flowcharts for explaining an example of a method for manufacturing a multilayer coaxial wiring using the coaxial via connection structure 1 of the present invention described above, and upper and lower coaxial lines 2a to be connected. , 2b are formed simultaneously with the coaxial via connection structure 1. Hereinafter, the process will be described in the order of step numbers in the figure. 6A, 6B, and 7 show to which part the parts with symbols such as V1, LL1, and UL1 used in the description of each step correspond, and FIGS. Reference is made as appropriate.

<ステップS1>
シリコン、サファイア、石英、窒化シリコン、窒化アルミ、化合物半導体(ガリウム砒素GaAs、窒化ガリウムGaN、炭化ケイ素SiC、インジウムリンInPなど)、ダイアモンドなどの基板30上に金、銀、銅などのグランド金属層31を真空蒸着、スパッタ、CVD、メッキなどの方法で堆積する。このグランド金属層31は、同軸型ビア接続構造1が接続する下層の同軸線路2aのシールド電極壁のうちの下面部分をなすものである。
<Step S1>
Ground metal layer of gold, silver, copper, etc. on a substrate 30 such as silicon, sapphire, quartz, silicon nitride, aluminum nitride, compound semiconductor (gallium arsenide GaAs, gallium nitride GaN, silicon carbide SiC, indium phosphide InP, etc.), diamond, etc. 31 is deposited by a method such as vacuum evaporation, sputtering, CVD, or plating. The ground metal layer 31 forms a lower surface portion of the shield electrode wall of the lower coaxial line 2a to which the coaxial via connection structure 1 is connected.

<ステップS2>
ポリイミド、ベンゾシクロブテンBCB、ポリアミド、ポリオキサゾールなどの樹脂にジアゾ感光剤を添加した感光性絶縁層32を塗布し、UV光等を照射して同軸型ビア接続構造1のシールド電極壁11の一部(V1)(図6A,B参照)および下層の同軸線路2a(図2参照)のシールド電極壁の一部(LL1)(図2A,B、図7参照)に対応するパターン331を含むフォトマスク33を用いて露光する。ポリイミドとしては、ブロック共重合ポリイミドが望ましい。
<Step S2>
One of the shield electrode walls 11 of the coaxial via connection structure 1 is applied by applying a photosensitive insulating layer 32 in which a diazo photosensitizer is added to a resin such as polyimide, benzocyclobutene BCB, polyamide, or polyoxazole, and irradiating UV light or the like. Photo including pattern 331 corresponding to part (V1) (see FIGS. 6A and 6B) and part of shield electrode wall (LL1) (see FIGS. 2A, 2B and 7) of lower coaxial line 2a (see FIG. 2) Exposure is performed using a mask 33. As the polyimide, block copolymerized polyimide is desirable.

ここでの一部(V1)とは、同軸ビア接続構造1の下層部分のうちの下半分に相当する部位であって、下層接続開口部12aの下半分の形状に相当する開口部を有している。また、一部(LL1)とは、同軸ビア接続構造1に接続される下層の同軸線路2aのうちの下半分に相当する部位である。   The part (V1) here is a portion corresponding to the lower half of the lower layer portion of the coaxial via connection structure 1, and has an opening corresponding to the shape of the lower half of the lower layer connection opening 12a. ing. The part (LL1) is a portion corresponding to the lower half of the lower coaxial line 2a connected to the coaxial via connection structure 1.

<ステップS3>
露光された感光性絶縁層32を現像し、同軸ビア接続構造1のシールド電極壁11の上記一部(V1)に相当する絶縁層14(図1参照)の溝パターン34を形成する。
<Step S3>
The exposed photosensitive insulating layer 32 is developed to form a groove pattern 34 of the insulating layer 14 (see FIG. 1) corresponding to the part (V1) of the shield electrode wall 11 of the coaxial via connection structure 1.

<ステップS4>
溝パターン34に対し、無電解あるいは電解メッキ法により金、銀、銅などの金属35の充填を行う。
<Step S4>
The groove pattern 34 is filled with a metal 35 such as gold, silver, or copper by electroless or electrolytic plating.

これにより、同軸ビア接続構造1のシールド電極壁11の上記一部(V1)および下層の同軸線路2aのシールド電極壁の上記一部(LL1)が同時に形成される。なお上記一部(V1)の形成により、下層接続開口部12aの下半分が形成されることになる。   Thereby, the part (V1) of the shield electrode wall 11 of the coaxial via connection structure 1 and the part (LL1) of the shield electrode wall of the lower coaxial line 2a are formed simultaneously. By forming the part (V1), the lower half of the lower layer connection opening 12a is formed.

<ステップS5>
同軸ビア接続構造1中の信号線13を構成する下層水平線部131(図6A,B参照)および同軸ビア接続構造1が接続する下層の同軸線路2aの信号線21a(図2A,B、図7参照)に対応するレジストパターン36をUV等を用いたリソグラフィ工程により形成して、金、銀、銅などの配線金属層37を真空蒸着、スパッタ、CVD、メッキなどの方法で堆積する。その後、レジストパターン36上の配線金属層37を溶媒に浸潤させてリフトオフ法により除去する。これにより、同軸ビア接続構造1中の信号線13を構成する下層水平線部131と同軸ビア接続構造1が接続する下層の同軸線路2aの信号線21aが形成される。
<Step S5>
The lower horizontal line 131 (see FIGS. 6A and 6B) constituting the signal line 13 in the coaxial via connection structure 1 and the signal line 21a of the lower coaxial line 2a to which the coaxial via connection structure 1 is connected (FIGS. 2A, B, and 7). A resist pattern 36 corresponding to the reference) is formed by a lithography process using UV or the like, and a wiring metal layer 37 such as gold, silver, or copper is deposited by a method such as vacuum deposition, sputtering, CVD, or plating. Thereafter, the wiring metal layer 37 on the resist pattern 36 is infiltrated with a solvent and removed by a lift-off method. As a result, the signal line 21a of the lower coaxial line 2a connected to the lower horizontal line 131 constituting the signal line 13 in the coaxial via connection structure 1 and the coaxial via connection structure 1 is formed.

<ステップS6>
感光性絶縁層38をさらに塗布し、UV光等を照射して同軸ビア接続構造1のシールド電極壁11の他の一部(V2)(図6A,B参照)および下層の同軸線路2aのシールド電極壁の他の一部(LL2)(図2A,B、図7参照)および同軸ビア接続構造1中の信号線13を構成する垂直線部133の下半分(C1)(図6A,B、図7参照)に相当するパターン391を含むフォトマスク39を用いて露光する。ここでの一部(V2)とは、上記一部(V1)に続く、同軸ビア接続構造1の下層部分のうちの上半分に相当する部位であって、下層接続開口部12aの上半分の形状に相当する開口部を有している。また、一部(LL2)とは、上記一部(LL1)に続く、同軸ビア接続構造1に接続される下層の同軸線路2aのうちの上半分に相当する部位である。
<Step S6>
Further, a photosensitive insulating layer 38 is further applied and irradiated with UV light or the like to shield the other part (V2) (see FIGS. 6A and 6B) of the shield electrode wall 11 of the coaxial via connection structure 1 and the lower coaxial line 2a. The other half of the electrode wall (LL2) (see FIGS. 2A and 2B, FIG. 7) and the lower half (C1) of the vertical line portion 133 constituting the signal line 13 in the coaxial via connection structure 1 (FIGS. 6A, B, Exposure is performed using a photomask 39 including a pattern 391 corresponding to FIG. The part (V2) here is a part corresponding to the upper half of the lower layer part of the coaxial via connection structure 1 following the part (V1), and is the upper half of the lower layer connection opening 12a. An opening corresponding to the shape is provided. The part (LL2) is a part corresponding to the upper half of the lower-layer coaxial line 2a connected to the coaxial via connection structure 1 following the part (LL1).

<ステップS7>
露光された感光性絶縁層38を現像し、同軸ビア接続構造1のシールド電極壁11の上記一部(V2)、下層の同軸線路2aのシールド電極壁の上記一部(LL2)、および上記信号線13の垂直線部133の下半分(C1)に相当する絶縁層の溝および穴パターン40を形成する。
<Step S7>
The exposed photosensitive insulating layer 38 is developed, the part (V2) of the shield electrode wall 11 of the coaxial via connection structure 1, the part (LL2) of the shield electrode wall of the lower coaxial line 2a, and the signal An insulating layer groove and hole pattern 40 corresponding to the lower half (C1) of the vertical line portion 133 of the line 13 is formed.

<ステップS8>
溝および穴パターン40に対し、無電解あるいは電解メッキ法により金、銀、銅などの金属41の充填を行う。これにより、上記ステップS4にて形成された同軸ビア接続構造1のシールド電極壁11の一部(V1)および下層の同軸線路2aのシールド電極壁の一部(LL1)に続いて、さらに同軸ビア接続構造1のシールド電極壁11の上記一部(V2)、下層の同軸線路2aのシールド電極壁の上記一部(LL2)、および上記信号線13の垂直線部133の下半分(C1)が形成される。なお、上記一部(V1)の形成により、下層接続開口部12aの上半分が形成されることになる。
<Step S8>
The groove and hole pattern 40 is filled with a metal 41 such as gold, silver, or copper by electroless or electrolytic plating. Thereby, following the part (V1) of the shield electrode wall 11 of the coaxial via connection structure 1 and the part (LL1) of the shield electrode wall of the lower coaxial line 2a formed in the step S4, the coaxial via The part (V2) of the shield electrode wall 11 of the connection structure 1, the part (LL2) of the shield electrode wall of the lower coaxial line 2a, and the lower half (C1) of the vertical line part 133 of the signal line 13 It is formed. The upper half of the lower layer connection opening 12a is formed by the formation of the part (V1).

<ステップS9>
続いて、下層の同軸線路2aのシールド電極のさらに他の一部(LL3)(図2A,B、図7参照)および上層の同軸線路2bのシールド電極の一部(UL1)(図2A,B、図7参照)となる、同軸線路2a,2b共通のグランド層用のレジストパターン42をUV等を用いたリソグラフィ工程により形成して、金、銀、銅などグランド金属層43を真空蒸着、スパッタ、CVD、メッキなどの方法で堆積する。その後、レジストパターン42上のグランド金属層43を溶媒に浸潤させてリフトオフ法により除去する。ここでの一部(LL3)とは、同軸ビア接続構造1に接続される下層の同軸線路2aのうちの上面部分のグランド層に相当する部位であり、また、一部(UL1)とは、同軸ビア接続構造1に接続される上層の同軸線路2bのうちの下面部分のグランド層に相当する部位である。
<Step S9>
Subsequently, still another part (LL3) of the shield electrode of the lower coaxial line 2a (see FIGS. 2A and B, FIG. 7) and a part of the shield electrode (UL1) of the upper coaxial line 2b (FIG. 2A, B) A resist pattern 42 for the ground layer common to the coaxial lines 2a and 2b is formed by a lithography process using UV or the like, and a ground metal layer 43 such as gold, silver, or copper is vacuum-deposited and sputtered. It deposits by methods, such as CVD and plating. Thereafter, the ground metal layer 43 on the resist pattern 42 is infiltrated with a solvent and removed by a lift-off method. The part (LL3) here is a part corresponding to the ground layer of the upper surface portion of the lower coaxial line 2a connected to the coaxial via connection structure 1, and part (UL1) is This is a portion corresponding to the ground layer of the lower surface portion of the upper coaxial line 2 b connected to the coaxial via connection structure 1.

これにより、下層の同軸線路2aのシールド電極の上記一部(LL3)および上層の同軸線路2bのシールド電極の上記一部(UL1)が形成される。すなわち、この段階で、ほぼ同軸ビア接続構造1の下半分とこれに接続される下層の同軸線路2a、つまり多層同軸配線構造中の下層部分が作製されることになる。なお、上層の同軸線路2bの下面部分の形成は、下層の同軸線路2aの上面部分の形成と同時に行われるが、これはグランド層を同軸線路2a、2bに共通のものとしているためである。   Thereby, the part (LL3) of the shield electrode of the lower coaxial line 2a and the part (UL1) of the shield electrode of the upper coaxial line 2b are formed. That is, at this stage, the lower half of the coaxial via connection structure 1 and the lower coaxial line 2a connected thereto, that is, the lower layer portion in the multilayer coaxial wiring structure are produced. The lower surface portion of the upper coaxial line 2b is formed at the same time as the upper surface portion of the lower coaxial line 2a, because the ground layer is common to the coaxial lines 2a and 2b.

<ステップS10>
感光性絶縁層44を塗布し、UV光等を照射して同軸ビア接続構造1のシールド電極壁11のさらに他の一部(V3)(図6A,B参照)、上層の同軸線路2bのシールド電極壁の他の一部(UL2)(図2A,B、図7参照)、および同軸ビア接続構造1中の信号線13を構成する垂直線部133の上半分(C2)(図6A,B、図7参照)に対応するパターン451を含むフォトマスク45を用いて露光する。ここでの一部(V3)とは、上記一部(V2)に続く、同軸ビア接続構造1の上層部分のうちの下半分に相当する部位であって、上層接続開口部12bの下半分の形状に相当する開口部を有している。また、一部(UL2)とは、上記一部(UL1)に続く、同軸ビア接続構造1に接続される上層の同軸線路2bのうちの下半分に相当する部位である。
<Step S10>
A photosensitive insulating layer 44 is applied and irradiated with UV light or the like, and yet another part (V3) of the shield electrode wall 11 of the coaxial via connection structure 1 (see FIGS. 6A and 6B), the shield of the upper coaxial line 2b. The other half of the electrode wall (UL2) (see FIGS. 2A, B, and 7) and the upper half (C2) of the vertical line portion 133 that constitutes the signal line 13 in the coaxial via connection structure 1 (FIGS. 6A and B) And exposure is performed using a photomask 45 including a pattern 451 corresponding to FIG. The part (V3) here is a part corresponding to the lower half of the upper layer part of the coaxial via connection structure 1 following the part (V2), and is the lower half of the upper layer connection opening 12b. An opening corresponding to the shape is provided. The part (UL2) is a part corresponding to the lower half of the upper coaxial line 2b connected to the coaxial via connection structure 1 following the part (UL1).

<ステップS11>
露光された感光性絶縁層44を現像し、同軸ビア接続構造1のシールド電極壁11の上記一部(V3)、上層の同軸線路2bのシールド電極壁の上記一部(UL2)、および上記信号線13の垂直線部133の上半分(C2)に相当する絶縁層の溝および穴パターン46を形成する。
<Step S11>
The exposed photosensitive insulating layer 44 is developed, the part (V3) of the shield electrode wall 11 of the coaxial via connection structure 1, the part (UL2) of the shield electrode wall of the upper coaxial line 2b, and the signal An insulating layer groove and hole pattern 46 corresponding to the upper half (C2) of the vertical line portion 133 of the line 13 is formed.

<ステップS12>
溝および穴パターン46に対し、無電解あるいは電解メッキ法により金、銀、銅などの金属47の充填を行う。これにより、上記ステップS4,S8にて形成された同軸ビア接続構造1のシールド電極壁11の一部(V1)(V2)、S9にて形成された上層の同軸線路2bのシールド電極壁の一部(UL1)、およびS7にて形成された信号線13の垂直線部133の下半分(C1)に続いて、さらに同軸ビア接続構造1のシールド電極壁11の上記一部(V3)、上層の同軸線路2bのシールド電極壁の上記一部(UL2)、および上記信号線13の垂直線部133の上半分(C2)が形成される。なお、上記一部(V3)の形成により、上層層接続開口部12bの下半分が形成されることになる。
<Step S12>
The groove and hole pattern 46 is filled with a metal 47 such as gold, silver, or copper by electroless or electrolytic plating. Thereby, a part (V1) (V2) of the shield electrode wall 11 of the coaxial via connection structure 1 formed in steps S4 and S8, one of the shield electrode walls of the upper coaxial line 2b formed in S9. Next to the lower half (C1) of the vertical line portion 133 of the signal line 13 formed in the portion (UL1) and S7, the above part (V3) of the shield electrode wall 11 of the coaxial via connection structure 1, the upper layer The part (UL2) of the shield electrode wall of the coaxial line 2b and the upper half (C2) of the vertical line part 133 of the signal line 13 are formed. In addition, the lower half of the upper layer connection opening 12b is formed by forming the part (V3).

<ステップS13>
同軸ビア接続構造1中の信号線13を構成する上層水平線部132(図6A,B参照)および上層の同軸線路2bの信号線21b(図2A,B、図7参照)に対応するレジストパターン48をUV等を用いたリソグラフィ工程により形成して、金、銀、銅など配線金属層49を真空蒸着、スパッタ、CVD、メッキなどの方法で堆積する。その後、レジストパターン48上の配線金属層49を溶媒に浸潤させてリフトオフ法により除去する。これにより、同軸ビア接続構造1中の信号線13の上層水平線部132と同軸ビア接続構造1が接続する上層の同軸線路2bの信号線21bが形成される。
<Step S13>
Resist pattern 48 corresponding to the upper horizontal line 132 (see FIGS. 6A and 6B) constituting the signal line 13 in the coaxial via connection structure 1 and the signal line 21b (see FIGS. 2A, B and 7) of the upper coaxial line 2b. Is formed by a lithography process using UV or the like, and a wiring metal layer 49 such as gold, silver, or copper is deposited by a method such as vacuum evaporation, sputtering, CVD, or plating. Thereafter, the wiring metal layer 49 on the resist pattern 48 is infiltrated with a solvent and removed by a lift-off method. As a result, the signal line 21b of the upper coaxial line 2b connected to the upper horizontal line portion 132 of the signal line 13 in the coaxial via connection structure 1 and the coaxial via connection structure 1 is formed.

<ステップS14>
感光性絶縁層50を塗布し、UV光等を照射して同軸ビア接続構造1のシールド電極壁11のさらにまた別の一部(V4)(図6A,B参照)および上層の同軸線路2bのシールド電極壁のさらに他の一部(UL3)(図2A,B、図7参照)に対応するパターン511を含むフォトマスク51を用いて露光する。ここでの一部(V4)とは、上記一部(V3)に続く、同軸ビア接続構造1の上層部分のうちの上半分に相当する部位であって、上層接続開口部12bの上半分の形状に相当する開口部を有している。また、一部(UL3)とは、上記一部(UL2)に続く、同軸ビア接続構造1に接続される上層の同軸線路2bのうちの上半分に相当する部位である。
<Step S14>
A photosensitive insulating layer 50 is applied and irradiated with UV light or the like, yet another part (V4) (see FIGS. 6A and 6B) of the shield electrode wall 11 of the coaxial via connection structure 1 and the upper coaxial line 2b. It exposes using the photomask 51 containing the pattern 511 corresponding to other part (UL3) (refer FIG. 2A, B, FIG. 7) of a shield electrode wall. The part (V4) here is a part corresponding to the upper half of the upper layer part of the coaxial via connection structure 1 following the part (V3), and is the upper half of the upper layer connection opening 12b. An opening corresponding to the shape is provided. The part (UL3) is a part corresponding to the upper half of the upper coaxial line 2b connected to the coaxial via connection structure 1 following the part (UL2).

<ステップS15>
露光された感光性絶縁層50を現像し、同軸ビア接続構造1のシールド電極壁11の上記一部(V4)および上層の同軸線路2bのシールド電極壁の上記一部(UL3)に相当する絶縁層の溝パターン52を形成する。
<Step S15>
The exposed photosensitive insulating layer 50 is developed, and the insulation corresponding to the part (V4) of the shield electrode wall 11 of the coaxial via connection structure 1 and the part (UL3) of the shield electrode wall of the upper coaxial line 2b is developed. A layer groove pattern 52 is formed.

<ステップS16>
溝パターン52に対し、無電解あるいは電解メッキ法により金、銀、銅などの金属53の充填を行う。これにより、上記ステップS4,S8,S12にて形成された同軸ビア接続構造1のシールド電極壁11の一部(V1)(V2)(V3)およびS9,S12にて形成された上層の同軸線路2bのシールド電極壁の一部(UL1)(UL2)に続いて、さらに同軸ビア接続構造1のシールド電極壁11の上記一部(V4)および上層の同軸線路2bのシールド電極壁の上記一部(UL3)が形成される。なお、上記一部(V4)の形成により、上層層接続開口部12bの上半分が形成されることになる。
<Step S16>
The groove pattern 52 is filled with a metal 53 such as gold, silver, or copper by electroless or electrolytic plating. Thereby, a part (V1) (V2) (V3) of the shield electrode wall 11 of the coaxial via connection structure 1 formed in steps S4, S8 and S12 and the upper coaxial line formed in S9 and S12. Following the part (UL1) (UL2) of the shield electrode wall 2b, the part (V4) of the shield electrode wall 11 of the coaxial via connection structure 1 and the part of the shield electrode wall of the upper coaxial line 2b are further provided. (UL3) is formed. The upper half of the upper layer connection opening 12b is formed by the formation of the part (V4).

<ステップS17>
上層の同軸線路2bのシールド電極のさらにまた別の一部(UL4)となるグランド層用のレジストパターン54をUV等を用いたリソグラフィ工程により形成して、金、銀、銅などグランド金属層55を真空蒸着、スパッタ、CVD、メッキなどの方法で堆積する。その後、レジストパターン54上のグランド金属層55を溶媒に浸潤させてリフトオフ法により除去する。ここでの一部(UL4)とは、上層の同軸線路2bのうちの上面部分のグランド層に相当する部位である。すなわち、この段階で、ほぼ同軸ビア接続構造1の上半分とこれに接続される上層の同軸線路2b、つまり多層同軸配線構造中の上層部分が作製されることになる。
<Step S17>
A ground layer resist pattern 54 to be yet another part (UL4) of the shield electrode of the upper coaxial line 2b is formed by a lithography process using UV or the like, and a ground metal layer 55 such as gold, silver, or copper is formed. Is deposited by a method such as vacuum vapor deposition, sputtering, CVD, or plating. Thereafter, the ground metal layer 55 on the resist pattern 54 is infiltrated with a solvent and removed by a lift-off method. The part (UL4) here is a portion corresponding to the ground layer on the upper surface portion of the upper coaxial line 2b. That is, at this stage, the upper half of the coaxial via connection structure 1 and the upper coaxial line 2b connected thereto, that is, the upper layer portion in the multilayer coaxial wiring structure are produced.

<ステップS18>
以上により、上下層にて互いに直交する同軸線路2a,2b(図2A,B参照)を結ぶ同軸型ビア接続構造1を備えた多層同軸配線構造が完成する。この同軸型ビア接続構造1の信号線13は、10μm以下の線幅とすることができる。
<Step S18>
Thus, a multilayer coaxial wiring structure including the coaxial via connection structure 1 that connects the coaxial lines 2a and 2b (see FIGS. 2A and 2B) orthogonal to each other in the upper and lower layers is completed. The signal line 13 of the coaxial via connection structure 1 can have a line width of 10 μm or less.

<各処理のバリエーション>
以上の製造方法において、UVリソグラフィ工程については、レーザービーム、電子ビームによる直接描画リソグラフィ工程を代わりに適用ことができる。
<Variation of each treatment>
In the above manufacturing method, the direct lithography process using a laser beam or an electron beam can be applied instead of the UV lithography process.

ステップS3,S7,S11,S15における、絶縁層14の溝または穴パターン34,40,46,52の形成に関しては、感光剤を添加しない非感光性絶縁層を用いて、ドライエッチング、化学エッチングなどのエッチング加工により形成することも可能である。   Regarding the formation of the groove or hole pattern 34, 40, 46, 52 of the insulating layer 14 in steps S3, S7, S11, S15, dry etching, chemical etching, etc. using a non-photosensitive insulating layer to which no photosensitive agent is added. It is also possible to form by etching.

ステップS1で形成されるグランド金属層31は、基板30全面に形成されるベタ膜になっているが、下層同軸線路2a の巾と同じ溝状のレジストパターンを形成した後に金属膜を堆積し、リフトオフ法により、下層同軸線路2aと同じ巾の短冊形状とすることができる。   The ground metal layer 31 formed in step S1 is a solid film formed on the entire surface of the substrate 30, but after forming a groove-like resist pattern having the same width as the lower coaxial line 2a, a metal film is deposited, By the lift-off method, a strip shape having the same width as that of the lower coaxial line 2a can be formed.

<CADシステム>
以上のとおりの製造プロセスを実行する際には、たとえば、配線レイアウトCADシステムを用いて、同軸型ビア接続構造1をセルデータとして登録し、図3に例示したような同軸線路列を多層に配置したものを基本配列パターンとして、任意の同軸線路2a,2bの交点に同軸型ビア接続構造1のセルデータを配置することで、同軸型ビア接続構造1を介して同軸線路2a,2bを結ぶ同軸線路を形成することができる。なお、同軸型ビア接続構造1のセルデータを配置する際に、同軸線路のデータは、セルデータの外形に従って、切り取って削除し、同軸型ビア接続構造のセルデータに置き換える作業が必要な場合がある。
<CAD system>
When executing the manufacturing process as described above, for example, using the wiring layout CAD system, the coaxial via connection structure 1 is registered as cell data, and coaxial line arrays as illustrated in FIG. 3 are arranged in multiple layers. Coaxial connection between the coaxial lines 2a and 2b via the coaxial via connection structure 1 by arranging the cell data of the coaxial via connection structure 1 at the intersections of arbitrary coaxial lines 2a and 2b using the above as a basic arrangement pattern A track can be formed. When arranging the cell data of the coaxial via connection structure 1, the data of the coaxial line may need to be cut and deleted according to the outline of the cell data and replaced with the cell data of the coaxial via connection structure. is there.

[第三の実施形態]
上述した各実施形態では、2層の同軸線路列について説明したが、もちろん3層以上の同軸線路列についても、隣接した直交する同軸線路の交点に同軸型ビア接続構造1を配置することで、複雑な配線を形成することができる。この場合、同軸型ビア接続構造1は、複数層に対応した高さのシールド電極壁11、複数層に対応した数および位置の接続開口部12a,12b・・・、および複数層を結ぶ形状の信号線13を有し、そのセルデータをCADシステムにて所望の同軸線路列の交点に配置することで、同軸型ビア接続構造1を用いた多層同軸配線構造を実現できる。製造プロセスは、上記第二の実施形態における各ステップを繰り返せばよい。
[Third embodiment]
In each of the embodiments described above, two layers of coaxial line trains have been described. Of course, for coaxial line trains of three or more layers, the coaxial via connection structure 1 is disposed at the intersection of adjacent orthogonal coaxial lines. Complex wiring can be formed. In this case, the coaxial via connection structure 1 includes a shield electrode wall 11 having a height corresponding to a plurality of layers, connection openings 12a, 12b... A multilayer coaxial wiring structure using the coaxial via connection structure 1 can be realized by having the signal line 13 and arranging the cell data at the intersection of a desired coaxial line array in the CAD system. The manufacturing process should just repeat each step in said 2nd embodiment.

[第四の実施形態]
シールド電極壁11に設けられた下層接続開口部12aと上層接続開口部12bは、シールド電極壁11がなく絶縁層14が露出している部分であり、図1A,Bではシールド電極壁11の横幅よりも小さい幅の矩形状となっているが、多層同軸線路の接続が可能であればこれに限定されるものではなく、たとえば図8A,Bに例示したようにシールド電極壁11の横幅とほぼ同じ幅としてもよい。なお、図8A,Bでは、下層接続開口部12aのみを上記同幅形状とした形態を図示しているが、もちろん上層接続開口部12bも同幅形状にできる。
[Fourth embodiment]
The lower layer connection opening 12a and the upper layer connection opening 12b provided in the shield electrode wall 11 are portions where the insulating layer 14 is exposed without the shield electrode wall 11, and in FIGS. 1A and 1B, the width of the shield electrode wall 11 is shown. However, the present invention is not limited to this as long as a multi-layer coaxial line can be connected. For example, as illustrated in FIGS. 8A and 8B, the width of the shield electrode wall 11 is substantially the same. It is good also as the same width. 8A and 8B show a form in which only the lower layer connection opening 12a has the same width, the upper layer connection opening 12b can of course have the same width.

参考例1
同軸型ビア接続構造1のシールド電極壁11は、図1A,B−図2A,Bでは角柱状になっているが、多層同軸線路の接続が可能であればこれに限定されるものではなく、たとえば図9に例示したように円柱状のものであっても、他の柱形状であってもよい。
[ Reference Example 1 ]
The shield electrode wall 11 of the coaxial via connection structure 1 has a prismatic shape in FIGS. 1A and B-FIGS. 2A and B, but is not limited to this as long as a multilayer coaxial line can be connected. For example, as illustrated in FIG. 9, it may be a columnar shape or another column shape.

参考例2
本発明の同軸型ビア接続構造1を用いて、同軸配線をメアンダ状(ジグザグに曲がりくねった状態)に布線した多層同軸配線構造とすることで、従来技術より占有面積が大幅に縮小された遅延線構造を実現することができる。
以上、図示例に基づき説明したが、この発明は上述の例に限定されるものでなく、特許請求の範囲に記載の範囲内で当業者が容易に改変し得る他の構成をも含むものである。
[ Reference Example 2 ]
By using the coaxial via connection structure 1 of the present invention, a multilayer coaxial wiring structure in which the coaxial wiring is arranged in a meandering shape (a zigzag winding state), and the occupying area is significantly reduced compared to the prior art. A line structure can be realized.
While the present invention has been described based on the illustrated examples, the present invention is not limited to the above-described examples, and includes other configurations that can be easily modified by those skilled in the art within the scope of the claims.

Claims (4)

互いに異なる高さに位置し且つ交わる方向に延びる上下層の同軸線路をビア接続する多層同軸配線構造における同軸型ビア接続構造において、
上下層の同軸線路に対応する高さを持つ角柱形状のシールド電極壁と、
前記シールド電極壁において下層の同軸線路に対応する位置の一側面にある下層接続開口部と、
前記シールド電極壁において上層の同軸線路に対応する位置であって他の一側面にある上層接続開口部と、
前記シールド電極壁内において前記下層接続開口部および前記上層接続開口部の間を結ぶ信号線とを有しており、
前記シールド電極壁は上下層の同軸線路が交差する位置に配置されて、前記下層接続開口部に位置する下層の同軸線路と前記上層接続開口部に位置する上層の同軸線路とを前記信号線で接続するものであって、
前記信号線は、下層接続開口部からシールド電極壁内に延びた下層線部と、上層接続開口部からシールド電極壁内に延びた上層線部と、下層線部および上層線部を結ぶ線部とを有し、前記下層線部の一端が前記下層接続開口部にて下層の同軸線路と結線し、前記上層線部の一端が、上層接続開口部にて上層の同軸線路と結線することから成る多層同軸配線構造における同軸型ビア接続構造。
In the coaxial via connection structure in the multilayer coaxial wiring structure in which the upper and lower coaxial lines extending in the intersecting direction are located at different heights and via-connect,
A prismatic shield electrode wall having a height corresponding to the upper and lower coaxial lines;
A lower layer connection opening on one side surface of the shield electrode wall at a position corresponding to the lower layer coaxial line;
The upper layer connection opening on the other side surface at a position corresponding to the upper layer coaxial line in the shield electrode wall;
Has a signal line connecting between the lower connecting opening and the upper connection opening in the shield electrode wall,
The shield electrode wall is disposed at a position where the upper and lower coaxial lines intersect, and the lower coaxial line located in the lower layer connection opening and the upper coaxial line located in the upper layer connection opening are connected by the signal line. To connect ,
The signal line includes a lower layer line portion extending from the lower layer connection opening into the shield electrode wall, an upper layer line portion extending from the upper layer connection opening to the shield electrode wall, and a line portion connecting the lower layer line portion and the upper layer line portion. One end of the lower layer line portion is connected to the lower coaxial line at the lower layer connection opening, and one end of the upper layer line portion is connected to the upper coaxial line at the upper layer connection opening. A coaxial via connection structure in a multilayer coaxial wiring structure.
前記シールド電極壁は、金属である請求項1に記載の多層同軸配線構造における同軸型ビア接続構造。 The coaxial via connection structure in the multilayer coaxial wiring structure according to claim 1, wherein the shield electrode wall is made of metal. 前記信号線は、金属である請求項1に記載の多層同軸配線構造における同軸型ビア接続構造。2. The coaxial via connection structure in a multilayer coaxial wiring structure according to claim 1, wherein the signal line is a metal. 前記信号線は、10μm以下の線幅である請求項1に記載の多層同軸配線構造における同軸型ビア接続構造。 The coaxial via connection structure in the multilayer coaxial wiring structure according to claim 1, wherein the signal line has a line width of 10 μm or less.
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Citations (3)

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Publication number Priority date Publication date Assignee Title
JPS61239701A (en) * 1985-04-16 1986-10-25 Mitsubishi Electric Corp Triplet line type t branch
JPH04267586A (en) * 1991-02-22 1992-09-24 Nec Corp Coaxial wiring pattern and formation thereof
JP2004023037A (en) * 2002-06-20 2004-01-22 Daiwa Kogyo:Kk Multi-layer wiring substrate and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61239701A (en) * 1985-04-16 1986-10-25 Mitsubishi Electric Corp Triplet line type t branch
JPH04267586A (en) * 1991-02-22 1992-09-24 Nec Corp Coaxial wiring pattern and formation thereof
JP2004023037A (en) * 2002-06-20 2004-01-22 Daiwa Kogyo:Kk Multi-layer wiring substrate and its manufacturing method

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