JPS62286254A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form a through hole, whose size is larger than the width of a lower interconnection layer, stably, by forming the through hole, whose size is larger than the width of the lower interconnection layer, in an interlayer insulating film to a depth so that at least the upper surface of a resin pattern is exposed. CONSTITUTION:In forming a through hole 15 for a multilayer interconnection on a semiconductor substrate 11, the depth of the hole is set and controlled so that at least the upper surface of a resin pattern on a lower interconnection layer 13 is exposed, when the through hole 15 is formed in an interlayer insulating film 14. Thus, the through hole 15, whose size is larger than the width of the lower interconnection layer 13, can be formed stably. Therefore, tolerance with respect to the position deviation of the through hole becomes large. The implementation of miniaturization and high density of the lower interconnection layer and easy pattern designing can be accomplished.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Object of the Invention] (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device, and in particular, a through hole ( contact hole)
Concerning how to form.

(Prior art) In a semiconductor integrated circuit having a multilayer wiring structure, the second
As shown in the figure, an interlayer @ structure using through holes is adopted. That is, 2 is a semiconductor substrate (for example, a silicon substrate) on which a semiconductor element has already been formed, and 22 is an insulating group (for example, 5LO2B) formed on the substrate.
tL), 23 is a first layer (lower, "Δ) wiring made of a conductive film (for example, an aluminum film) formed by zeturning on the above-mentioned insulating film, and 24 is an interlayer insulating film (for example, S r
25 is a through hole formed on a predetermined portion of the first layer wiring/interface 723 in the interlayer insulating film; 26 is a conductive film deposited on the interlayer insulating film 24;
7 or 21 with turned aluminum film)
Cheeks (upper wi) Self line, upper N self through-ho/I
It is also deposited inside the z<b>25 (bottom and sidewalls) and is in contact with the first layer wiring 23 .

In the above structure, the portion of the first layer wiring 23 where the contact is to be formed is formed thicker than the line width of other wiring portions, and the through hole 25 is formed with dimensions smaller than this thick line width. The dimensional difference between the hole 25 and the area where the contact is to be formed is determined depending on the alignment error of photolithography in the through hole forming process and the lateral etching size of the interlayer insulating film 24, and is determined, for example, from 2 to 6 txn.
It is.

The reason why the contact formation area of the lower layer wiring is designed to be thicker is that, for example, the lower 11
Considering the case where the line width of the contact formation area of the j wiring 33 is reduced, if the formation position of the through hole 25 is shifted and a part of it is shifted from the contact formation area, the 5 insulation M22 and the substrate - This avoids problems such as Rm being etched and over-etched portions 37 occurring, which may destroy semiconductor elements previously formed on the substrate surface or short-circuit wiring due to impurity diffusion layers, etc. It's for a reason.

- In order to advance the miniaturization of wiring in multilayer structures, it is necessary to reduce the line width of lower layer wiring to 2 μm or less69, and accordingly, the dimensions of through holes must be adjusted to take into account misalignment in photolithography. Even if it is necessary to make the IRn about IRn, it is extremely difficult to form four turns of photoresist metal corresponding to a 1 μm through hole on the interlayer insulating film when a metal wiring with high reflectance is used as the lower layer wiring. This was difficult, and further miniaturization was currently impossible.

As mentioned above, the conventional manufacturing method in which a through hole with a size smaller than the width of the underlying wiring is formed in the first interlayer insulating film causes damage to elements in the board and short circuits in the wiring due to misalignment of the through hole. This problem not only occurs easily, but also makes it difficult to miniaturize and increase the density of the underlying wiring.

Therefore, as a method to solve this problem, as shown in FIG. When forming the hole 45, carefully etching the hole 45 in the depth direction of the M hole 24 is done. It is conceivable to form the through hole 45 in the. However, this method is extremely difficult to control when considering variations in the thickness of the interlayer insulating film 24, and it is difficult to use this method as a production process to stably form through holes.
Close to Noh.

(Problems to be Solved by the Invention) The present invention has been made in order to solve the above-mentioned problem that it is difficult to stably form through holes larger in size than the lower layer wiring. This enables the stable formation of the above-mentioned through-holes, miniaturization of lower layer wiring,
The present invention provides a method of manufacturing a semiconductor device that can achieve high density.

[Structure of the Invention] (Means for Solving Problems) When forming through holes for multilayer wiring on a semiconductor substrate, the present invention involves applying resin or a turn to at least a pre-formed portion of the through hole on the lower layer wiring. a step of forming an inorganic interlayer insulating film on the entire surface of the semiconductor substrate; and a step of forming a through hole with a dimension larger than the line width of the underlying wiring in the interlayer insulation R film using the resin. The present invention is characterized by comprising a step of opening the hole to a depth where at least the upper blade of the setan is exposed, and a step of removing the resin turn on the bottom surface of the through hole.

(Function) When opening a through hole in a film, controlling the depth to a point where at least the top surface of the resin pattern on the lower layer wiring is exposed will prevent variations in the interlayer insulation film, etc. It is easy to consider.

Therefore, even if the through-hole formation position 3S is slightly shifted, the problem of over-etching will not occur, and the bottom "i"
Arrangement d,') Increase the width of the planned contact formation area, and as it becomes inevitable, the values of Geto, Yumoki, and profit will be changed to fld, and the value of secret will be changed to 1.

(Example) Hereinafter, one implementation of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) to (d) show the cross-sectional structure of a semiconductor wafer at each stage of the process of forming a multilayer wiring trench for a semiconductor integrated circuit. That is, as shown in Figure 1 (,),
A first layer (lower layer) wiring film is formed on a semiconductor substrate (for example, a silicon substrate) 11 on which a semiconductor element is formed, via an insulating film (for example, an S10□ film) 12 with a film thickness of 0.4 μm. (For example, aluminum film) 13 with a film thickness of 1.0 μm
It forms more than it becomes. Next, a photoresist pattern 10 for forming a bag distribution pattern is formed on the wiring film 13. In this case, a photosensitive polyimide (for example, Tovi's product name UR-3100) is used as a photorenost with a film thickness of 1.
The film is coated to a thickness of 0 μm, and exposed and developed in the same manner as normal photolithography. Next, as shown in FIG. 1(b), using the polyimide pattern 10 as a mask, the first layer wiring film 13 is etched using an anisotropic etching method, such as a normal parallel plate type HIE (reactive ion etching) device. A first layer wiring pattern l3/ having a line width of 2 .mu.m is formed by anisotropic etching using the RIg method.

Next, an oxidized 71J pattern is formed by, for example, plasma αD (chemical vapor deposition) to form an insulating film between wiring layers, and then etch-packed and planarized by, for example, RIEi, to a film thickness of 2.5 μm. Inorganic interlayer insulating film 1
form 4.

Next, as shown in FIG. 1(e), a through-hole photoreceptor pattern 18 is placed on the interlayer insulating film 14 corresponding to the portion where the through hole is to be formed on the first layer wiring pattern IJ'. Formed by normal photolithography. In this case, the through hole of the photorenost pattern 18 is 2 turns no 1 dimension e (fc burr direction 30μ
m, 30 μm in the lateral direction) is larger than the line width of 2.0 μm of the first layer wiring pattern 13'.

Next, using the photoresist two-turn 18 as a mask, the interlayer insulating film 14 is anisotropically etched, for example, by RIE, to form a through hole 15. The depth of this etching shall be controlled so that the bottom of the through hole 15 is within the range of the film thickness (1.0 μm) of the above-mentioned imidonose turn 1O, and this etching depth is 4.
is from the surface of the interlayer insulating film I4 with a thickness of 2.5 μm to
The interlayer insulating film No. 4 and the first layer I gland i within a range of 1.5 μm.
It is only necessary to take into consideration the variations in the film thicknesses of the 4-turn l3' film and the polyimide setan 10, and to set it accordingly, and since it is easy to control, over-etching that reaches the substrate surface does not occur. As shown in FIG. 1(d), at the same time as the polyimide pattern 10 of the through-hole forming method is etched away, the photorenost center 718 is etched away by, for example, RIE using oxygen gas. In this case, the etching rate is greatly different between the pattern 10.18 made of the resin material and the inorganic interlayer insulating film 14, and the interlayer discontinuities and the unwanted glands 14 are not etched. After this, the second; - (upper layer) wiring pattern 1
6 by a normal forming method (for example, an aluminum film is formed on the entire surface of the interlayer t! edge film by sputtering method, etc., and then patterned)? Form from this.

According to the through hole forming method of the above embodiment, it is possible to stably form a through hole having a dimension larger than the lower layer twill width. Therefore, the contact portion can be realized without intentionally making the contact forming portion of the lower layer wiring thicker than other parts, making it easier to design the wiring pattern, and making it possible to miniaturize and increase the density of the wiring. In addition, since the polyimide layer remains on the upper surface of the lower layer wiring other than the contact formation area, hillocks (
It is possible to absorb and relax the stress generated between the protrusion) or the lower layer wiring and the interlayer insulating film, and it is possible to reduce the risk of short circuits occurring between the wiring layers.

Note that the interlayer insulating film 14 in the above embodiment is not limited to the 5i02 film, but may also be a 515N4 ('d silicon) film, etc., and is not limited to photosensitive polyimide. Other resins that can withstand temperature (epoxy AT resin, tetrafluoroethylene resin, etc.) may also be used.

Also, the previous 8 members 1. ′? Lower layer wiring - Zeturn 13 by self-line using Reimito 97 Inter 710 as a mask
If you have formed the polyimide pattern 10, you may separate it by leaving only the redundant portion for forming the through holes and removing the other portions by lithography. If we do this, the photolithography process described above will increase, but what about the lower part of the side wall of the through hole when forming the through hole? Since the polyimide/circle turns are not exposed, there is no possibility that the exposed polyimide pattern will cause any adverse effects in subsequent steps. Note that in the method of the present invention, any method may be employed, not only the self-line using the photosensitive polyimide pattern 10, but also the method of forming the pattern of the lower layer wiring that is the base of the through hole. In order to cover the OJ function, it is sufficient to form the lower layer wiring/t-turn before forming the interlayer insulating film, and form the resin 9-turn in the preliminary portion for forming the through-hole on this pattern.

Further, the method of the present invention is suitable for manufacturing semiconductor devices having a multilayer wiring structure of two or more layers, and is not limited to the process of forming through holes in the interlayer insulating film on the first layer (bottom layer 71) wiring. The present invention can also be applied to a process of forming a through hole in a non-interlayer insulating film on wiring in an intermediate layer, and can also be applied to a process of forming a through hole between arbitrary layers.

[Effects of the Invention] As described above, according to the method of manufacturing a semiconductor device of the present invention, a through hole having a dimension larger than the width of the lower layer wiring can be stably formed, so that the tolerance for misalignment of the through hole is improved. This makes it possible to achieve finer, higher-density lower-layer wiring and easier wiring pattern design. Incidentally, when the method of the present invention is applied to the formation of a multilayer wiring structure of a semiconductor device for AD conversion/DA conversion, for example, where an infinite number of wiring lines are formed in parallel, the chip area can be reduced to about 3.
Effects such as being able to reduce the number of wires and the time required for wiring/setan design were achieved.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are diagrams showing the development of semiconductor urchins and depressions at each stage of the multilayer wiring formation process of a semiconductor integrated circuit according to an embodiment of the semiconductor device manufacturing method of the present invention, Figure 2 shows the cross-sectional structure of multi-node wiring in a conventional semi-dedicated lateral circuit, and Figures 3 and 4 show the results obtained by implementing different multi-node wiring formation methods conventionally considered. The cross-sectional structure of the multilayer wiring and the cross-sectional structure of the semiconductor after through-hole formation? FIG. lO...Photosensitive polyimide pattern, 1...Semiconductor substrate, 12...Insulating film, 13...Lower wiring film, 1
3'... Lower layer wiring, 14... Interlayer insulating film, 15...
・Through hole, groove...upper layer wiring, 18...photorenost pattern.

Claims (5)

[Claims] (1) When forming through holes for multilayer wiring on a semiconductor substrate, there is a step of providing a resin pattern on at least the area where the through hole is planned to be formed on the lower layer wiring, and then an amorphous interlayer insulating film is formed on the entire surface of the semiconductor substrate. forming a through hole in the interlayer insulating film to a depth that exposes at least the top surface of the resin pattern; 1. A method for manufacturing a semiconductor device, comprising the step of removing a pattern. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the resin pattern is a photosensitive resin pattern formed on the entire surface of the lower wiring. (3) Before forming the interlayer insulating film, a photosensitive resin pattern is formed on the lower wiring film in correspondence with the wiring pattern, and the lower wiring film is etched using this resin pattern as a mask to remove the lower wiring. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising: forming a semiconductor device. (4) Before forming the interlayer insulating film, a photosensitive resin pattern is formed on the lower wiring film in correspondence with the wiring pattern, and the lower wiring film is etched using this resin pattern as a mask to remove the lower wiring. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a resin pattern, and then removing a portion of the resin pattern other than a portion where a through hole is to be formed. (5) In the step of opening the through hole, a photoresist pattern formed on the interlayer insulating film is used as a mask, and then the resin pattern on the bottom of the through hole is removed and the photoresist pattern is removed at the same time. A method for manufacturing a semiconductor device according to claim 1.