JP2006024831A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which expands the exposure margin in lithography, when forming a connection hole without causing a decline in productivity, and by which a yield is improved and further microfabrication is attained, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device includes an underlayer interconnection 3 provided on a substrate, a second interlayer dielectric 5 covering the underlayer interconnection 3, a via 7 in which the inside of the connection hole 5a provided at the second interlayer dielectric 5 is embedded with a conductive material, in such a state that it reaches the underlayer interconnection 3, and an upper layer interconnect 9 with a pattern formed on the second interlayer dielectric 5, in such a state as it is connected with the via 7. The connection hole 5 has an opening shape which is longer in an extended direction of the upper layer interconnect 9, and the hole is formed into a tapered shape, in which an opening diameter becomes smaller toward the side of the underlayer interconnection 3 from the side of the upper layer interconnect 9 at a continuous angle of inclination θ. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a multilayer wiring structure in which upper and lower wirings are connected by vias and a manufacturing method thereof.

  In recent years, with further higher integration and higher functionality of semiconductor devices, there has been a demand for multilayered and high-density wiring structures as well as finer element structures. In order to realize a high-density multilayer wiring, it is important to advance the miniaturization and narrowing of the wiring and vias. Here, the via means a conductive material portion embedded in a connection hole connecting a lower layer wiring and an upper layer wiring provided on the semiconductor substrate.

  Therefore, as a method of narrowing the wiring and via pitch, a tapered via capable of increasing the via opening area is formed in the lower insulating film, and then the upper insulating film above the tapered via is formed on the tapered via. A configuration in which a vertical via is formed with a lower diameter smaller than the diameter has been proposed. According to this method, since the upper layer wiring provided in the upper part of the via is connected by the vertical via having a small diameter, the space between the upper layer wiring is not narrowed by the via diameter. In addition, a via can be formed in a thick insulating film without increasing the aspect ratio (see Patent Document 1 below).

JP-A-7-226589

  By the way, in forming vias, via holes (connection holes) are formed by etching an insulating film using a resist pattern formed by lithography as a mask. However, as described above, with the progress of via miniaturization and narrow pitch, in recent years, the opening diameter of via holes is approaching the limit of lithography. This makes it impossible to obtain an exposure margin in pattern exposure during lithography, and there is a concern that the yield may decrease due to the occurrence of defects such as a short circuit between wirings. Further, due to the limitations of lithography, further increase in the density of semiconductor devices is hindered.

  In particular, in the via forming method of the above-described patent document, in order to form one via, two via forming steps, a tapered via forming step and a vertical via forming step, must be performed. There was also a problem that productivity was bad.

  Accordingly, the present invention provides a semiconductor device and a method for manufacturing the same that can widen an exposure margin in lithography when forming a connection hole without causing a decrease in productivity, thereby improving yield and further miniaturization. The purpose is to do.

  In order to achieve such an object, the semiconductor device of the present invention is provided in the interlayer insulating film so as to reach the lower layer wiring, the lower layer wiring provided on the substrate, the interlayer insulating film covering the lower layer wiring, and the lower layer wiring. A via is formed by burying the inside of the connection hole with a conductive material, and an upper layer wiring patterned on the interlayer insulating film in a state of being connected to the via. In particular, the connection hole is characterized by having an opening shape that is long in the extending direction of the upper layer wiring.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having the above-described structure, and is characterized in that the connection hole is formed in the interlayer insulating film as follows. That is, first, a resist pattern having an opening shape that is long in the extending direction of the upper layer wiring is formed on the interlayer insulating film by lithography. Then, by etching the interlayer insulating film based on the resist pattern, a connection hole reaching the upper layer wiring is formed in the interlayer insulating film.

  In the semiconductor device having such a configuration and the manufacturing method thereof, the connection hole has an opening shape that is long in one direction, so that a resist pattern that serves as a mask when forming the connection hole is also formed in an opening shape that is long in one direction. Will be. For this reason, the exposure margin in lithography when forming the resist pattern is widened. In other words, pattern exposure is possible if the opening shape is such that these opening shapes are elongated in one direction as compared with the case of forming a resist pattern having a square shape or a rounded corner shape or a regular circular opening shape. Since the focal depth at the time increases, the exposure margin increases. In this case, the depth of focus can be increased only by increasing the length in the longitudinal direction by 10% or more, preferably 20% or more, relative to the length of the opening shape in the short direction.

  And the connection hole which has such an opening shape is provided so that the longitudinal direction may correspond to the extending direction of upper layer wiring. Thereby, even if the side wall shape of this connection hole is tapered so that the opening diameter becomes smaller toward the lower layer wiring, even if adjacent connection holes contact each other in the longitudinal direction on the upper layer side reaching the upper layer wiring. Since these connection holes are connected to the same upper layer wiring, there is no problem in driving. In addition, since the isolation state on the lower layer side of the connection hole is maintained, there is no short circuit between the lower layer wirings.

  Furthermore, in such a manufacturing method, since the connection hole is formed by etching based on a resist pattern formed by one lithography, there is no increase in the number of steps.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present invention, since the number of lithography processes is not increased, the exposure margin in lithography when forming the connection hole is increased without reducing the productivity. This makes it possible to improve the yield and further miniaturize the semiconductor device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, the configuration of the semiconductor device will be described first, and then the method for manufacturing the semiconductor device will be described.

<Semiconductor device>
FIG. 1 is a main part plan view showing the configuration of the semiconductor device of the embodiment, and FIG. 2 is a cross-sectional view taken along line AA ′ in FIG. The semiconductor device shown in these drawings has a multilayer wiring structure in which wirings are laminated in a plurality of layers, and has the following configuration.

  That is, in the semiconductor device of the present embodiment, the first interlayer insulating film 1 is formed so as to cover elements formed on the surface side of a semiconductor substrate or a glass substrate not shown here. A lower layer wiring 3 is embedded and formed on the surface side of the first interlayer insulating film 1, and a second interlayer insulating film 5 is formed so as to cover the lower layer wiring 3. The second interlayer insulating film 5 is provided with a connection hole 5a reaching the lower layer wiring 3, and further, a via 7 embedded with a conductive material is provided in the connection hole 5a. An upper layer wiring 9 is patterned on the lower layer wiring 3 via the vias 7 on the second interlayer insulating film 5. The upper layer wiring 9 may be embedded in the surface side of the second interlayer insulating film 5.

  Here, the lower wiring 3 buried on the surface side of the first interlayer insulating film 1 is made of, for example, copper (Cu). In the illustrated portion, lower layer wirings 3 having a line width W1 (for example, W1 = 70 nm) are arranged in parallel at a pitch P1 (for example, P1 = 140 nm). These lower layer wirings 3 are connected to elements covered with the first interlayer insulating film 1 by contacts not shown here.

  A plurality of upper layer wirings 9 formed on the second interlayer insulating film 2 covering the lower layer wirings 3 are arranged in parallel in a state orthogonal to the lower layer wirings 3 in the illustrated portion. The upper wirings 9 having a line width W2 (for example, W2 = 75 nm) are arranged in parallel at a pitch P2 (for example, P2 = 150 nm). In the case where the upper layer wiring 9 is embedded in the surface side of the second interlayer insulating film 2, the upper layer wiring 9 is made of, for example, copper (Cu).

  The via 7 arranged at the position where the lower layer wiring 3 and the upper layer wiring 9 intersect, and the opening shape of the connection hole 5a in which the via 7 is embedded have the following two characteristic features. It has a shape. In the following description, the opening shape of the connection hole 5a will be described.

  First, the opening shape of the connection hole 5a, that is, the planar shape of the upper portion of the opening in contact with the upper layer wiring 9, is long along the extending direction of the upper layer wiring 9 (vertical direction in FIG. 1), for example, the upper layer wiring 9 An oblong shape or a rectangular shape with the extending direction as the major axis (longitudinal) direction, and a substantially rectangular shape obtained by rounding four corners of the rectangle.

  Second, the side wall shape of the connection hole 5a is shaped into a tapered shape having a continuous inclination angle from the upper layer wiring 9 side to the lower layer wiring 3 side and the opening diameter being narrowed. The inclination angle θ in the taper shape is substantially constant from the upper layer wiring 9 side to the lower layer wiring 3 side, or is a shape in which the inclination gradually decreases from the upper layer wiring 9 side to the lower layer wiring 3 side, It does not change rapidly.

  In the connection hole 5a having the first and second characteristics as described above, the dimension Wx in the short direction of the upper part of the opening is between the connection holes 5a (vias 7) arranged adjacent to each other in the short direction. It is set in a range that can completely prevent a short circuit. The setting of the dimension Wx in the short direction of the upper part of the opening in the connection hole 5a is the same as in the prior art.

  On the other hand, the longitudinal dimension Wy of the upper part of the opening of the connection hole 5a is equal to the longitudinal dimension Wy 'of the lower part of the opening of the connection hole 5a and the second interlayer necessary for insulation between the lower layer wiring 3 and the upper layer wiring 9 The insulating film 5 is set to be larger based on the film thickness t (for example, t = 300 nm) and the inclination angle θ (for example, θ = 87 °) of the connection hole 5a that can be realized in the etching process.

  That is, first, the dimension Wy ′ in the longitudinal direction of the lower portion of the opening in the connection hole 5a is based on, for example, the pitch P1 of the lower layer wiring 3, and the connection hole disposed adjacently at the position where the connection hole 5a reaches the lower layer wiring 3. 5a is set within a range that can be reliably separated. In addition, the dimension Wy ′ is preferably set to a value as large as possible so that the contact resistance between the connection hole 5a and the lower layer wiring 3 is sufficiently low.

  The dimension Wy in the longitudinal direction of the upper part of the opening of the connection hole 5a is the dimension Wy ′ thus set, the film thickness t of the second interlayer insulating film 5, and the connection hole 5a that can be realized in the etching process. Is set to a value at which the connection hole 5a is separated at a position where the connection hole 5a reaches the upper layer wiring 9. However, the upper layer portion of the connection hole 5a does not have to be reliably separated, and as shown in FIG. 2A, the upper layer portions of the plurality of connection holes connected to the same upper layer wiring 9 communicate with each other. May be.

  Note that the dimension Wx ′ in the short direction of the lower part of the opening of the connection hole 5a is the ratio of the dimension Wy ′ of the lower part of the opening to the longitudinal dimension Wy of the upper part of the opening of the connection hole 5a and the upper part of the opening of the connection hole 5a. This is a value determined from the dimension Wx in the short direction.

  The via 7 formed by embedding a conductive material in the connection hole 5a has the same shape as the connection hole 5a. Therefore, the upper layer portion of the connection hole 5a does not have to be reliably separated, and as shown in FIG. 2A, the upper layer portions of the plurality of connection holes 5a connected to the same upper layer wiring 9 communicate with each other. In this case, the vias 7 embedded in these connection holes 5a are connected to each other.

<Manufacturing method>
A method of manufacturing the semiconductor device having the above configuration will be described with reference to the sectional process diagram of FIG.

  First, as shown in FIG. 3A, a lower layer wiring 3 is buried and formed on the surface side of the first interlayer insulating film 1 covering the substrate on which the element is formed according to a normal buried wiring process. Next, a second interlayer insulating film 5 is formed on the first interlayer insulating film 1 so as to cover the lower layer wiring 3. The second interlayer insulating film 5 may have a laminated structure including a plurality of different films.

  Next, a resist pattern 11 for forming connection holes is formed on the second interlayer insulating film 5 by lithography. The resist pattern 11 is provided with an opening 11a having a planar shape corresponding to the opening shape in the upper part of the opening of the connection hole described above. That is, the opening 11a provided in the resist pattern 11 is long along the extending direction (left and right direction in the drawing) of the upper layer wiring formed in the subsequent steps.

  In addition, the opening 11a of the resist pattern 11 has an elliptical shape, a rectangular shape, or a substantially rectangular shape obtained by rounding four rectangular corners depending on the pattern data of the opening portion 11a used in pattern exposure in lithography. For example, if the pattern data is a rectangle, the opening 11a of the resist pattern 11 formed by lithography including pattern exposure is a substantially rectangle obtained by rounding four corners of an ellipse or a rectangle. On the other hand, if the pattern data is provided with a modification pattern by OPC (Optical & Process Correction) or other correction processing on the rectangle, the opening of the resist pattern 11 formed by lithography including pattern exposure is performed. The part 11a has a shape closer to a rectangle.

  Next, as shown in FIG. 3B, the second interlayer insulating film 5 is etched by etching using the resist pattern 11 as a mask, thereby forming a connection hole 5a reaching the lower layer wiring 3. At this time, the etching process is adjusted so that the inclination angle θ of the side wall of the connection hole 5a becomes a preset angle. The opening shape of the connection hole 5a thus obtained, that is, the planar shape of the upper portion of the opening, is an ellipse or rectangle that is long in one direction, similarly to the opening shape of the opening portion 11a of the resist pattern 11, and further this 4 of the rectangle. It is a rectangle with rounded corners.

  In forming the connection hole 5a, an inorganic mask may be formed by etching using the resist pattern 11 as a mask, and the second interlayer insulating film 5 may be etched from the inorganic mask. The inorganic mask may be a part of the second interlayer insulating film 5.

  Next, as shown in FIG. 3 (3), a via 7 is formed by filling the connection hole 5a with a conductive material. Here, a conductive material layer (not shown) such as a Cu film is formed on the second interlayer insulating film 5 via a barrier metal in a state in which the connection hole 5a is embedded, and this conductive material layer is subjected to CMP polishing. Thus, the via 7 is formed by leaving the conductive material layer only in the connection hole 5a.

  After the above, as shown in FIG. 2, the upper wiring 9 is patterned on the second interlayer insulating film 5 including the via 7. At this time, the upper layer wiring 9 is patterned so that the upper layer wiring 9 extends along the longitudinal direction of the via 7.

  When the upper layer wiring 9 is embedded in the surface layer of the second interlayer insulating film 5, a wiring groove is formed in the upper layer of the second interlayer insulating film 5 before and after the formation of the connection hole 5a. By performing the process, the connection hole 5 a is dug from the bottom of the wiring groove toward the lower layer wiring 3. However, the wiring groove is formed by etching based on a resist pattern different from the resist pattern 11. Then, in such a state that the wiring groove and the connection hole 5a are embedded, a conductive material layer is formed and this is subjected to CMP polishing, whereby the upper layer wiring 9 is integrally formed with the via 7 embedded in the connection hole 5a. Form.

  As described above, the semiconductor device having the structure described with reference to FIGS. 1 and 2 can be obtained.

  According to the semiconductor device having the above-described configuration and the manufacturing method thereof, the connection hole 5a has an opening shape that is long in one direction. Therefore, as described with reference to FIG. 3A, the resist pattern 11 serving as a mask when forming the connection hole 5a is also formed with an opening shape that is long in one direction. Thereby, the exposure margin in lithography when forming the resist pattern 11 is widened. In other words, pattern exposure is possible if the opening shape is such that these opening shapes are elongated in one direction as compared with the case of forming a resist pattern having a square shape or a rounded corner shape or a regular circular opening shape. Since the focal depth at the time increases, the exposure margin increases. In this case, as will be described later, the depth of focus can be increased only by increasing the length in the longitudinal direction by 10% or more, preferably 20% or more, with respect to the length in the short direction of the opening shape. it can.

  The connection hole 5 a having such an opening shape is provided so that the longitudinal direction thereof coincides with the extending direction of the upper layer wiring 9. Thus, the side wall shape of the connection hole 5a is tapered so that the opening diameter becomes smaller toward the lower layer wiring 3, so that the adjacent connection holes 5a are connected to the upper layer wiring 9 as will be described in detail later. Even if the upper layer is reached in the longitudinal direction (see FIG. 2A), these connection holes 5a are connected to the same upper layer wiring 9, so there is no problem in driving. Since the dimension Wx in the short direction at the upper part of the opening of the connection hole 5a may be the same as the conventional one, the short margin between the adjacent upper layer wirings 9 is not changed.

  In addition, since the side wall shape of the connection hole 5a is tapered so that the opening diameter decreases toward the lower layer wiring 3, the separation state on the lower layer side of the connection hole 5a is maintained. There is no short circuit. For this reason, for example, the upper layer wiring 9 and the lower layer wiring 3 each have a line width where the margin of the design rule is critical, and the line width and the space are narrowed to about 1: 1, and Even when the longitudinal direction of the connection hole 5a (via 7) coincides with the lower layer wiring 3 in a direction perpendicular to the lower layer wiring 3, the side wall shape of the connection hole 5a has an opening diameter toward the lower layer wiring 3. Therefore, the separation state on the lower layer side of the connection hole 5a is maintained.

  Furthermore, in such a manufacturing method, as described with reference to FIGS. 3A and 3B, the connection hole 5a is formed by etching based on the resist pattern 11 formed by one lithography. Therefore, there is no increase in the number of processes.

  As a result, according to the semiconductor device and the manufacturing method thereof described above, the number of lithography steps is not increased, so that the exposure margin in lithography when forming the connection hole 5a is increased without causing a decrease in productivity. As a result, the yield of the semiconductor device can be improved, and the performance of the exposure apparatus can be fully utilized to manufacture the most advanced ultrafine device.

  Next, in the step shown in FIG. 3A, the opening shape of the opening portion 11a of the resist pattern 11 serving as a mask for forming the connection hole 5a is made long in one direction, thereby forming the resist pattern. The effect of increasing the exposure margin in lithography when forming 11 will be described.

  Here, in order to show such an effect, as shown in FIG. 4, a simulation was performed in which the resist pattern 11 was formed by lithography processing using each value as a factor. That is, the size Wx in the x direction of the opening 11a formed in the resist pattern 11 is fixed to 100 nm. When the size Wy in the y direction (ie, the direction parallel to the upper layer wiring) is 100 nm, 110 nm, and 120 nm, the pattern pitch (Px and Py) is a factor, and the lithography margin is the focal point in pattern exposure. The depth DOF (Depth of Focus) was obtained by simulation.

  Note that the size Wx in the x direction and the size Wy in the y direction of the opening 11a formed in the resist pattern 11 are the dimensions Wx × Wy of the upper part of the opening in the connection hole (5a) obtained by etching using the resist pattern 11 as a mask. Are substantially the same, so the same reference numerals are used. The pattern pitch Px corresponds to the pitch P1 of the upper layer wiring (9), and the pattern pitch Py corresponds to the pitch P2 of the lower layer wiring (3).

  The results are shown in Tables 1 to 3 below. Table 1 shows the results of Wy = 100 nm, Table 2 shows the results of Wy = 110 nm, and Table 3 shows the results of Wy = 120 nm. The units of DOF in Tables 1 to 3 are nm.

  As shown in Table 1 above, in the formation of the conventional resist pattern 11 having the openings 11a with Wy = 100 nm (Wx = 100 nm), the DOF is within a range where the pitch Px of the openings 11a is small and the pitch Py is large. It turns out that it becomes narrow. In particular, in the arrangement in which the pitch Px in the short direction of the openings 11a is as dense as 150 nm and the pitch Py in the longitudinal direction of the openings 11a is relatively sparse such as 300 nm or more, the DOF is less than 125, and the lithography margin is almost zero. I understand that there is no.

  On the other hand, as shown in Table 2, when forming the resist pattern 11 having a long opening 11a in one direction with Wy = 110 nm (Wx = 100 nm), the DOF is wider than that in Table 1. You can see that And it turns out that DOF is expanded to 150 or more in the range which performed the simulation.

  Further, as shown in Table 3, when forming a resist pattern 11 having an opening 11a with Wy = 120 nm (Wx = 100 nm) and longer in one direction, the DOF is compared with Table 1 and Table 2. Can be seen to be wider. And it turns out that DOF is expanded to 175 or more in the range which performed the simulation.

  From the above, the DOF can be widened simply by increasing the length of the opening in the opening 11a of the resist pattern 11 by 10% or more, preferably 20% or more, with respect to the length in the short direction. It was confirmed that the exposure margin is effectively enlarged.

  According to Tables 1 to 3, it is concluded that the DOF can be increased to 150 or more by using the present invention for the opening 11a having a Py of 300 nm or more under the optical conditions used in the simulation. For this reason, even if the longitudinal dimension Wy in the opening 11a is 120 nm, the distance between the openings 11a, that is, the distance between the connection holes and the vias can be kept at 180 nm, and adjacent connection holes (vias) are short-circuited. There is no.

  Even if Py is 140 nm, the effect can be obtained by applying the present invention if it is necessary to use optical conditions that do not allow a lithography margin. In this case, by setting the longitudinal dimension Wy in the opening 11a to 120 nm, the interval between the openings 11a becomes as narrow as 20 nm. However, there is no problem because the connection hole is reliably separated in the lower layer wiring portion by forming the connection hole having the side wall taper shape by etching using the resist pattern 11 as a mask.

  It should be noted that even if there is no explanation of the conditions of the optical system and the explanation of the simulation conditions, it is clear that it is sufficient to explain the embodiments of the present invention, that is, it can be carried out by those skilled in the art, and is not described here. Furthermore, the values and assumptions used in this explanation do not limit the claims of the present invention.

  Next, the effect obtained by making the side wall shape of the connection hole 5a into a tapered shape in which the opening diameter decreases toward the lower layer wiring 3 will be described.

  For example, as shown in FIG. 1, the pitch P1 of the lower layer wiring 3 is 140 nm and the line width is 70 nm, the pitch P2 of the upper layer wiring 9 is 150 nm, and the line width is 75 nm. Consider a case where 9 and 9 cross each other at an angle of approximately 90 °. In this case, since the opening shape of the connection hole 5a in contact with the upper layer wiring 9 is long in one direction as described above, the problems of the lithography process margin and the short margin are solved.

  However, if the connection hole 5a is not tapered, the pitch P1 of the lower layer wiring 3 is 140 nm, whereas the longitudinal dimension Wy ′ of the connection hole 5a reaching the lower layer wiring 3 is 120 nm. , The space is only 20 nm, resulting in a structure with a very short margin.

  However, by forming the connection hole 5a in a tapered shape, the short margin on the surface in contact with the lower layer wiring of the via can be improved.

  For example, referring to FIG. 2, when the film thickness t of the second interlayer insulating film 5 necessary for insulation between the lower layer wiring 3 and the upper layer wiring 9 is 300 nm, and the inclination angle of the tapered shape is θ = 87 ° , Wy ′ is about 88.6 nm, the space is 51.4 nm, and it is clear that the short margin is improved.

  FIG. 2 is an example in which shrinkage in the resist process is not taken into consideration, but in the lithography stage, that is, in the process with respect to the opening dimension of the opening 11a in the resist pattern 11 shown in FIG. There is no problem even if the present invention is applied after the opening dimensions Wx and Wy in the actual pattern (connection hole) are reduced by using taper etching at the resist stage or resist shrink technology. Needless to say, the above case is also included in the present invention.

  Next, as in the example shown in FIG. 1, when the upper layer wiring 9 and the lower layer wiring 3 are both dense and intersect with each other at an angle of about 90 degrees, they contact the short margin in the lower layer wiring 3. The relationship of resistance will be discussed with reference to FIG. Each figure of FIG. 5 is a plan view of the lower layer wiring 3 and the bottom portion (lower opening) of the connection hole 5a reaching the height of the lower layer wiring 3.

  FIG. 5B in the center is a case where the present invention is not used, and the dimension of the opening lower portion of the connection hole 5a is substantially Wx ′ = Wy ′. In contrast, in FIGS. 5A and 5C, Wx ′ <Wy ′. The magnitude relationship of Wx ′ is FIG. 5 (a) = FIG. 5 (b)> FIG. 5 (c), and the magnitude relationship of Wy ′ is FIG. 5 (a)> FIG. 5 (b) = FIG. 5 (c). It has become.

  In this case, the short margin in the lower layer wiring 3 is approximately as shown in FIG. 5 (a) <FIG. 5 (b) <FIG. 5 (c), and the contact resistance is approximately as shown in FIG. 5 (a) = FIG. 5 (b) <FIG. Become. As a result, the inclination angle θ of the tapered shape of the connection hole 5a is determined in consideration of the balance between the short margin generated by the ratio of Wx ′ and Wy ′ and the contact resistance.

  The ratio of Wx ′ and Wy ′ is substantially the same as that of Wx and Wy. Generally, as described with reference to Tables 1 to 3, Wy is about 10% to 20% at most with respect to Wx (10 nm to Since the lithography margin is drastically improved by making the ellipse to be large (about 20 nm, etc.), a solution satisfying the above-mentioned short margin and contact resistance is obtained (that is, Wx ′ and Wy). It is obvious that setting a realistic target value of 'is not difficult for those skilled in the art compared to the case of not using the present invention.

  Further, the inclination angle θ of the tapered shape of the connection hole 5a depends on the film thickness t of the second interlayer insulating film 5 necessary for insulation between the lower layer wiring 3 and the upper layer wiring 9, and the ratio of Wy and Wy ′ is constant. In this case, it is necessary to reduce the thickness t of the second interlayer insulating film 5 as the thickness t decreases. However, if t = about 300 nm, the inclination angle θ may be about 85 degrees at most, and this does not make the process difficult.

It is a principal part top view of the semiconductor device of an embodiment. It is A-A 'sectional drawing in FIG. It is sectional process drawing which shows the manufacturing method of the semiconductor device of embodiment. It is a top view explaining the simulation of resist pattern formation. It is a top view explaining the relationship between the short margin in a lower layer wiring, and contact resistance.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 3 ... Lower layer wiring, 5 ... 2nd interlayer insulation film, 5a ... Connection hole, 7 ... Via, 9 ... Upper layer wiring, 11 ... Resist pattern, (theta) ... Inclination angle

Claims (8)

A lower layer wiring provided on the substrate, an interlayer insulating film covering the lower layer wiring, a via formed by burying a conductive hole in a connection hole provided in the interlayer insulating film in a state of reaching the lower layer wiring, In a semiconductor device provided with an upper layer wiring patterned on the interlayer insulating film in a state of being connected to a via,
The connection hole has a long opening shape in the extending direction of the upper layer wiring. The semiconductor device according to claim 1,
The connection hole is shaped into a tapered shape having a continuous inclination angle from the upper-layer wiring side to the lower-layer wiring side and having a narrow opening diameter. The semiconductor device according to claim 2,
The lower layer wiring and the upper layer wiring are disposed in a state of being orthogonal to each other. The semiconductor device according to claim 2,
An upper layer portion of a plurality of connection holes connected to the same upper layer wiring among the upper layer wirings communicates with each other. After forming the connection hole reaching the lower layer wiring in the interlayer insulating film covering the lower layer wiring, the via hole reaching the lower layer wiring is formed by filling the connection hole with the conductive material film, and the upper layer connected to the via In a method for manufacturing a semiconductor device in which wiring is formed on the interlayer insulating film,
When forming the connection hole,
A resist pattern having an opening shape that is long in the extending direction of the upper layer wiring is formed on the interlayer insulating film by lithography, and the interlayer insulating film is etched based on the resist pattern to thereby form the upper layer on the interlayer insulating film. A method for manufacturing a semiconductor device, comprising: forming a connection hole reaching a wiring. In the manufacturing method of the semiconductor device according to claim 5,
The method of manufacturing a semiconductor device, wherein the etching of the interlayer insulating film is performed so as to have a tapered shape having a continuous inclination angle toward the lower layer wiring side and having a narrow opening diameter. The method of manufacturing a semiconductor device according to claim 6.
The method for manufacturing a semiconductor device, wherein the upper layer wiring is formed to be orthogonal to the lower layer wiring. The method of manufacturing a semiconductor device according to claim 6.
A method for manufacturing a semiconductor device, wherein upper portions of connection holes arranged adjacent to each other in the longitudinal direction of the opening shape of the connection holes are formed to communicate with each other.

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