JP2007180081A - Integrated inductor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inductor having a small parasitic capacity and wire resistance by directing the axis of its helical structure toward a direction parallel to the substrate plane, as well as making the height in a direction perpendicular to the substrate plane (longitudinal direction) sufficiently larger than the conventional one. <P>SOLUTION: Vertical holes are formed in a substrate 50 and vertical interconnections 55 are formed inside the vertical holes, and an upper lateral interconnection 56 is formed on the surface of the substrate 50. Then, a trench 60 having nearly the same depth as the vertical interconnections 55 is formed, and a lower lateral interconnection 61 is formed at the bottom face of the trench 60. Thereafter, the substrate 50 is so etched that at least the top face of the lower lateral interconnection 61, the vertical interconnections 55, and the upper lateral interconnection 56 may be exposed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an integrated inductor formed on a substrate, more specifically to an integrated inductor formed on an insulator substrate or a semiconductor substrate and capable of being integrated with other elements, and a method for manufacturing the same. .

  As an inductor (inductance element) formed on an insulating substrate, a spiral electrode is generally formed on the substrate, and an inner end portion of the electrode is drawn out through some insulating means. An inductor in which this spiral electrode is formed is disclosed in Patent Document 1, for example.

Here, the structure and manufacturing method of the inductor of Patent Document 1 will be described based on the cross-sectional view shown in FIG.
First, as shown in FIG. 1A, a spiral groove 2 'is formed on the upper surface of the semiconductor substrate 1 by patterning and etching a photoresist film. Next, as shown in (b), the conductor 3 'is formed only inside the spiral groove 2', and as shown in (c), the spiral groove 2 'formation region on the surface of the semiconductor substrate 1 is removed by etching, and the inductor line 3 Configure. Thereafter, as shown in (d), the lead-out wiring 3b and the air bridge wiring 3a are formed to constitute an inductor having a spiral inductor line.

  On the other hand, it is generally desirable that the inductor has a helical structure in terms of area efficiency and Q factor improvement. A method of forming this helical inductor on a semiconductor substrate is disclosed in Patent Document 2.

Here, the inductor disclosed in Patent Document 2 will be described with reference to FIG.
As shown in FIG. 2, a polymer 29 is first deposited on a semiconductor substrate, an inductor bottom metal 25 is formed on the polymer 29, and a polymer layer (not shown) is deposited on the polymer 29. The inductor is formed on the surface of the passivation layer 18 of the semiconductor substrate by forming the upper metal of the inductor on the top surface of the layer and forming vias 23 in the polymer layer.
Japanese Patent No. 3068266 JP 2003-86690 A

  Compared with the case where a spiral conductor is formed on a substrate as shown in Patent Document 1, it is better to form a conductor in a helical shape as in Patent Document 2 in terms of improvement in area efficiency and Q value. It is advantageous. However, the structure disclosed in Patent Document 2 has a problem that an inductor having a sufficiently high height cannot be formed on the substrate. That is, as shown in Patent Document 2, an interlayer insulating film and a polymer layer are stacked, and a via is formed in the thickness direction of the layer that constitutes the inductor so that a contact between the upper conductor wiring and the lower conductor wiring is formed. In the so-called damascene method, there is a limit to the thickness of the material to be stacked. For example, even a thick polymer is about 150 μm. Moreover, a process of flattening is required after stacking.

  Further, when a pattern is formed on the outermost surface, a resist film is used, but the thickness is limited. At most, it is several tens of μm. In order to obtain an inductor having a small parasitic capacitance and wiring resistance, it is necessary to increase the thickness in the direction perpendicular to the surface of the substrate and to narrow the wiring width. However, in the process of Patent Document 2, the thickness is increased in the vertical direction (vertical direction). Since this is not possible, there has been a problem that inductors with small parasitic capacitance and wiring resistance cannot be obtained.

  Therefore, an object of the present invention is to make the axis of the helical structure face in a direction parallel to the surface of the substrate and to increase the height in the vertical direction (longitudinal direction) with respect to the surface of the substrate. Thus, an inductor having a small parasitic capacitance and wiring resistance is obtained.

In order to solve the above-described problems, the present invention is configured as follows.
The integrated inductor of the present invention includes a vertical wiring extending in a direction perpendicular to the main surface of the substrate, and an upper horizontal wiring and a lower horizontal wiring extending in a direction parallel to the main surface of the substrate and having different heights. In an integrated inductor in which the upper horizontal wiring and the lower horizontal wiring are sequentially connected by the vertical wiring so that the wiring forms a helical shape as a whole, the vertical wiring is formed inside a vertical hole formed in the substrate. The upper horizontal wiring is formed on the surface of the substrate, a groove reaching the depth of the bottom of the vertical hole is formed at a position where the lower horizontal wiring is to be formed, and the bottom of the groove It is assumed that the lower horizontal wiring is formed in

  The method for manufacturing an integrated inductor according to the present invention includes a step of forming a vertical hole at a position where the vertical wiring is to be formed on the substrate, a step of forming a vertical wiring by a conductor in the vertical hole, and the lower horizontal wiring. Forming a groove in the substrate reaching the depth of the bottom of the vertical hole at a position between the two vertical holes to be formed, and forming the lower horizontal wiring at the bottom of the groove, A step of forming the upper horizontal wiring on the surface of the substrate before, during or after each of the steps is provided.

  For example, when forming the lower horizontal wiring at the bottom of the groove, the upper horizontal wiring may be formed on the surface of the substrate.

  Further, following the step of forming the lower horizontal wiring, a step of removing the substrate surface to a depth at which the vertical wiring is exposed leaving at least the lower surface of the lower horizontal wiring may be further provided.

  Since a vertical hole is formed in the substrate, a conductor is provided in the vertical hole, a vertical wiring is formed, and a groove is formed between the vertical holes so that a lower horizontal wiring is formed at the depth of the bottom. A sufficient length (height) of the vertical wiring extending in the direction perpendicular to the main surface of the capacitor can be secured, and an inductor having a small parasitic capacitance and wiring resistance can be obtained.

  Also, if the substrate surface is removed so that the vertical wiring is exposed leaving at least the lower surface of the lower horizontal wiring, most of the inductor is exposed in the space, so that an inductor that is not affected by the physical properties of the substrate material can be configured.

<< First Embodiment >>
An integrated inductor and a manufacturing method thereof according to the first embodiment will be described with reference to FIGS.
FIG. 3 is a flowchart showing the manufacturing process of the integrated inductor according to the first embodiment in order. 4 and 5 are diagrams showing the structure in each step. FIG. 6 is a perspective view of the main part of the integrated inductor.

  4 (A), (C), (D), and FIG. 5 (A), (B), each upper part is a plan view in each step, and the lower part is a cross-sectional view of the AA portion of the plan view. It is. 4B and 4E, and FIGS. 5C and 5D are cross-sectional views in each step.

  First, FIG. 4A is a diagram showing a state in the vertical hole forming step shown in step S11 of FIG. In FIG. 4A, a substrate 50 is an insulating substrate such as an insulating ceramic, or a semi-insulating substrate such as a GaAs substrate or Si substrate, and has a predetermined depth in a direction perpendicular to its main surface (upper surface). A plurality (eight in this example) of vertical holes 51 are formed. For example, it is formed by photolithography including patterning of a photoresist film and wet etching.

  Next, in the base conductor film forming step shown in step S12 of FIG. 3, the base conductor film is formed on the upper surface of the substrate 50 (the entire surface of the integrated inductor formation region) and the inner surface of the vertical hole 51 as shown in FIG. 52 are formed simultaneously. For example, the base conductor film 52 having a constant film thickness is formed by sputtering of Au or vacuum deposition.

  Next, in the upper horizontal wiring and vertical wiring forming step shown in step S13 of FIG. 3, as shown in FIG. 4C, a photoresist film is applied and formed on the upper surface of the substrate 50, and the mask pattern is overlaid and exposed. By developing, a resist film 53 is formed in which the vertical hole 51 and a region where an upper horizontal wiring is to be formed later are used as a resist film opening 54. Subsequently, as shown in FIG. 4D, the base conductor film 52 is used as a conductor film for electroplating, and the inside of the vertical hole 51 is filled with a plating film by performing electroplating of Au, and then a resist film 53 is removed. Thereby, the vertical wiring 55 is formed. At the same time, the electrode film thickness of the resist film opening 54 is increased by plating. Thereby, the upper horizontal wiring 56 is formed.

  Next, in the base conductor film removal step shown in step S14 of FIG. 3, as shown in FIG. 4E, the resist film 53 is removed and the whole is lightly etched to form the base conductor film 52 on the upper surface of the substrate 50. Remove. At this time, the vertical wiring 55 and the upper horizontal wiring 56 remain because they are formed thick by the plating.

  Next, in the groove forming step shown in step S15 of FIG. 3, as shown in FIG. 5A, a photoresist film is applied and formed on the upper surface of the substrate 50, and a mask pattern is overlaid and exposed and developed. A resist film 58 is formed in which a region where a groove is to be formed later between the two vertical wirings 55 is used as a resist film opening 59. Subsequently, as shown in FIG. 5B, the substrate 50 is etched to a depth substantially equal to the depth of the vertical wiring 55 using the resist film 58. For example, a substrate material such as GaAs or Si is etched by a dry etching method using ICP (Inductively Coupled Plasma). Thereby, the groove 60 is formed. In this etching, the conductor (electrode material) of the vertical wiring 55 remains without being etched.

  Next, in the lower horizontal wiring forming step shown in step S16 of FIG. 3, a conductor film is formed on the inner surface of the groove 60 as shown in FIG. For example, Au is sputtered or vacuum deposited. Thereafter, the resist film 58 is removed.

  Next, in the groove inner wall surface conductor film removing step shown in step S17 in FIG. 3, the conductor film adhering to the inner wall surface (excluding the bottom surface) of the groove 60 is removed by lightly etching the entire substrate 50. As a result, the lower horizontal wiring 61 is left only on the bottom surface of the groove 60. At this stage, a helical inductor is completed.

  Next, in the substrate upper surface removal step shown in step S18 of FIG. 3, as shown in FIG. 5D, the substrate 50 is etched to a depth at which the vertical wiring 55 is exposed, leaving at least the lower surface portion of the lower horizontal wiring 61. . Thereby, as shown in FIG. 6, an integrated inductor in which a part (at least the upper surface) of the lower horizontal wiring 61, the upper horizontal wiring 56, and the vertical wiring 55 are exposed is obtained.

  4 to 6, the upper lead wire 57 is formed at the same height as the upper horizontal wire, but the lead wire may be formed at the same height as the lower horizontal wire. In this case, the upper lead wire 57 shown in FIG. 6 is located on the upper surface of the substrate 50, and the connection between this lead wire and another wire formed on the upper surface of the substrate 50 becomes easy.

<< Second Embodiment >>
Next, an integrated inductor and a method for manufacturing the integrated inductor according to a second embodiment will be described with reference to FIGS.
FIG. 7 is a flowchart showing the manufacturing process of the integrated inductor according to the second embodiment in order. 8 and 9 are diagrams showing the structure in each step.

  8A, 8E, and 9A, the upper part is a plan view in each step, and the lower part is a cross-sectional view of the AA portion of the plan view. Moreover, (B), (C), (D), (F) in FIG. 8 and (B), (C) in FIG. 9 are cross-sectional views in each step.

  First, FIG. 8A is a diagram showing a state in the vertical hole forming step shown in step S21 of FIG. In FIG. 8A, a substrate 50 is an insulating substrate such as an insulating ceramic, or a semi-insulating substrate such as a GaAs substrate or Si substrate, and has a predetermined depth in a direction perpendicular to its main surface (upper surface). A plurality (eight in this example) of vertical holes 51 are formed. For example, it is formed by photolithography including patterning of a photoresist film and wet etching.

  Next, in the base conductor film forming step shown in step S22 of FIG. 7, as shown in FIG. 8B, the base conductor film is formed on the upper surface of the substrate 50 (the entire surface of the integrated inductor formation region) and the inner surface of the vertical hole 51. 52 are formed simultaneously. For example, the base conductor film 52 having a constant film thickness is formed by sputtering of Au or vacuum deposition.

  Next, in the vertical wiring forming step shown in step S23 of FIG. 7, as shown in FIG. 8C, a resist film 53 having an opening in the vertical hole 51 portion is formed, and the inside of the vertical hole 51 is formed by electroplating Au. The vertical wiring 55 is formed by filling the plating film.

  Next, in the substrate upper surface underlying conductor film removing step shown in step S24 of FIG. 7, the entire surface of the substrate 50 is lightly etched after the resist film 53 is removed, as shown in FIG. 8D. The underlying conductor film 52 is removed.

  Next, in the groove forming step shown in step S25 of FIG. 7, as shown in FIG. 8E, a region where a groove is to be formed later is formed on the upper surface of the substrate 50 between the two vertical holes 55, respectively. A resist film 62 to be the opening 63 is formed. Then, as shown in FIG. 8F, a groove 60 having a depth substantially equal to the depth of the vertical wiring 55 is formed by etching. For example, a substrate material such as GaAs or Si is etched by a dry etching method using ICP. During this etching, the conductor (electrode material) of the vertical wiring 55 remains without being etched.

  Next, in the upper and lower horizontal wiring forming step shown in step S26 of FIG. 7, as shown in FIG. 9A, the region where the upper horizontal wiring is to be formed later and the opening of the groove 60 are formed on the upper surface of the substrate 50. Forms a resist film 64 which is a resist film opening 65. Then, as shown in FIG. 9B, an upper horizontal wiring 56 is formed on the upper surface of the substrate 50 by Au sputtering or vacuum deposition, and a conductor film is formed on the bottom surface of the groove 60, and then the resist film 64 is removed. To do. Thereafter, the whole is lightly etched to remove an unnecessary thin conductor film attached to the inner wall surface (excluding the bottom surface) of the groove 60, and the lower horizontal wiring 61 is left on the bottom surface of the groove 60. At this stage, a helical inductor is completed.

  Next, in the substrate upper surface removing step shown in step S28 of FIG. 7, the substrate 50 is etched to a depth at which the vertical wiring 55 is exposed, leaving at least the lower surface portion of the lower horizontal wiring 61, as shown in FIG. 9C. . Thus, an integrated inductor similar to that shown in FIG. 6 in which a part (at least the upper surface) of the lower horizontal wiring 61, the upper horizontal wiring 56, and the vertical wiring 55 are exposed is obtained.

  In the first and second embodiments, the upper horizontal wiring, the lower horizontal wiring, and the vertical wiring are all made of Au. However, other conductive materials such as Cu may be used, or a plurality of types of conductive materials may be combined. May be. Further, the conductor film and the plating film as the base may be made of different materials.

  The horizontal wiring is formed simultaneously with the vertical wiring 55 in the first embodiment and simultaneously with the lower horizontal wiring in the second embodiment. However, the present invention is not limited to this. Any method may be used as long as it is a stage before the substrate top surface removing process. In this case, a general electrode forming method on the upper surface of the substrate can be used.

It is a figure which shows the structure of the inductor currently disclosed by patent document 1, and its manufacturing method. It is a figure which shows the structure of the inductor currently disclosed by patent document 2, and its manufacturing method. It is the figure which represented the process of the manufacturing method of the integrated inductor which concerns on 1st Embodiment as a flowchart. It is a figure which shows the state in each process of the integrated inductor. It is a figure which shows the state in each process of the integrated inductor. It is an external appearance perspective view of the integrated inductor. It is the figure which represented the process of the manufacturing method of the integrated inductor which concerns on 2nd Embodiment as a flowchart. It is a figure which shows the state in each process of the integrated inductor. It is a figure which shows the state in each process of the integrated inductor.

Explanation of symbols

50-substrate 51-vertical hole 52-underlying conductor film 53-resist film 54-resist film opening 55-vertical wiring 56-upper horizontal wiring 57-upper lead wiring 58-resist film 59-resist film opening 60-groove 61- Lower horizontal wiring 62 -resist film 63 -resist film opening 64 -resist film 65 -resist film opening

Claims (3)

A vertical wiring that extends in a direction perpendicular to the main surface of the substrate and an upper horizontal wiring and a lower horizontal wiring that extend in a direction parallel to the main surface of the substrate and have different heights, and the wiring forms a helical shape as a whole. A method of manufacturing an integrated inductor in which the upper horizontal wiring and the lower horizontal wiring are sequentially connected by the vertical wiring,
Forming a vertical hole at a position where the vertical wiring of the substrate is to be formed;
Forming a vertical wiring with a conductor in the vertical hole;
Forming in the substrate a groove reaching the depth of the bottom of the vertical hole at a position between the two vertical holes where the lower horizontal wiring is to be formed;
Forming the lower horizontal wiring at the bottom of the groove,
Furthermore, the manufacturing method of the integrated inductor provided with the process of forming the said upper horizontal wiring in the surface of the said board | substrate before and during each said process.   A method for manufacturing an integrated inductor, further comprising the step of removing the surface of the substrate to a depth at which the vertical wiring is exposed, after performing each step according to claim 1, leaving at least a lower surface portion of the lower horizontal wiring. A vertical wiring that extends in a direction perpendicular to the main surface of the substrate and an upper horizontal wiring and a lower horizontal wiring that extend in a direction parallel to the main surface of the substrate and have different heights, and the wiring forms a helical shape as a whole. In an integrated inductor in which the upper horizontal wiring and the lower horizontal wiring are sequentially connected by the vertical wiring,
The vertical wiring is formed inside the vertical hole formed in the substrate,
The upper horizontal wiring is formed on the surface of the substrate,
A groove reaching the bottom of the vertical hole is formed at a position where the lower horizontal wiring is to be formed, and the lower horizontal wiring is formed at the bottom of the groove;
Integrated inductor.

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