CN108975267B - 3D pipeline forming method - Google Patents
3D pipeline forming method Download PDFInfo
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- CN108975267B CN108975267B CN201810800783.XA CN201810800783A CN108975267B CN 108975267 B CN108975267 B CN 108975267B CN 201810800783 A CN201810800783 A CN 201810800783A CN 108975267 B CN108975267 B CN 108975267B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00055—Grooves
- B81C1/00063—Trenches
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00095—Interconnects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
The invention provides a 3D pipeline forming method, which comprises the steps of manufacturing a first groove in a first medium layer; forming a first metal layer on the bottom wall and the side wall of the first groove to obtain a first cavity; forming a second metal layer on the first dielectric layer to cover the first cavity; etching the second metal layer on the top of the first cavity to form a second cavity and expose the first cavity; forming a second dielectric layer on the second metal layer; and manufacturing a second groove in the second dielectric layer, wherein the second groove is communicated with the second cavity. By forming the first cavity and the second cavity, the second groove is communicated with the second cavity, and further the second groove is communicated with the first cavity through the second cavity. And finally, the metal pipelines in the two adjacent metal layers are communicated to form a 3D metal pipeline, so that the total length of the pipeline is increased, and more functions can be realized.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a 3D pipeline forming method.
Background
In the semiconductor manufacturing industry, the next step of the integrated circuit process flow is to arrange metal connecting lines between transistors and other titanium silicide non-contacts, a local interconnection method is generally adopted, the step of forming the local interconnection is as complicated as the step of forming shallow trench isolation, the process firstly requires to deposit a layer of dielectric film, then chemical mechanical polishing, imprinting, etching and metal deposition are carried out, finally, metal layer polishing is carried out, and finally, a refined pattern of inlaid jewelries or artworks is obtained on the surface of a silicon wafer as the result of the process, and the patterns are generally metal interconnection structures such as through holes; typically, depositing a metal film in the via will seal the via to form a plug structure for local interconnection of CMOS circuitry, and may also be used to form a conduit structure in a MEMS device.
However, the metal pipeline structure formed in this way is a two-dimensional structure, and the two-dimensional plane limits the total length of the pipeline which can be designed, thereby limiting the design and the function of the MEMS device.
Disclosure of Invention
The invention aims to provide a 3D pipeline forming method, which aims to solve the problem that the total length of a pipeline is limited due to the fact that a metal pipeline locally interconnected in the prior art is a two-dimensional metal pipeline.
In order to achieve the above object, the present invention provides a 3D pipe forming method, comprising the steps of:
manufacturing a first groove in the first dielectric layer;
forming a first metal layer on the bottom wall and the side wall of the first groove to obtain a first cavity;
forming a second metal layer on the first dielectric layer to cover the first cavity;
etching the second metal layer on the top of the first cavity to form a second cavity and expose the first cavity;
forming a second dielectric layer on the second metal layer; and
and manufacturing a second groove in the second dielectric layer, wherein the second groove is communicated with the second cavity.
Optionally, an aspect ratio of the first groove or the second groove is less than or equal to 2.5.
Optionally, an auxiliary groove is also formed in the first dielectric layer or the second dielectric layer while the first groove is formed in the first dielectric layer or the second groove is formed in the second dielectric layer.
Optionally, the aspect ratio of the auxiliary groove is greater than or equal to 3.
Optionally, the thickness of the first metal layer is smaller than half of the widths of the first groove and the second groove and greater than or equal to half of the width of the auxiliary groove.
Optionally, the second metal layer on the top of the first cavity is etched while the second metal layer is etched to form a metal interconnection line.
Optionally, the bottom of the second cavity is communicated with the top of the first cavity.
Optionally, an aspect ratio of the second cavity is less than or equal to 2.5.
Optionally, when a second dielectric layer is formed on the second metal layer, the second dielectric layer fills a part of the second cavity.
Optionally, when the second groove is manufactured, the second dielectric layer in the second cavity is etched away.
Optionally, the second groove is communicated with the second cavity at a position above the bottom of the second cavity.
Optionally, the second groove communicates with the first cavity through the second cavity.
Optionally, after a second groove is formed in the second dielectric layer and the second groove is communicated with the second cavity, the method further includes: and forming a first metal layer on the side wall of the second groove and the side wall of the second cavity to obtain a third cavity, wherein the third cavity is communicated with the first cavity.
In summary, in the 3D pipeline forming method provided by the present invention, the first groove is formed in the first dielectric layer; forming a first metal layer on the bottom wall and the side wall of the first groove to obtain a first cavity; forming a second metal layer on the first dielectric layer to cover the first cavity; etching the second metal layer on the top of the first cavity to form a second cavity and expose the first cavity; forming a second dielectric layer on the second metal layer; and manufacturing a second groove in the second dielectric layer, wherein the second groove is communicated with the second cavity. According to the method provided by the invention, the first cavity is formed, the second metal layer at the top of the first cavity is etched while the metal interconnection line is etched, the second cavity is formed, then the second groove is formed at the position corresponding to the first groove, the second groove is communicated with the second cavity, so that the second groove is communicated with the first cavity through the second cavity, and finally the metal pipelines in two adjacent metal layers are communicated to form the 3D metal pipeline, so that the total length of the pipeline is increased, and more functions are realized.
Drawings
Fig. 1 is a schematic flow chart of a 3D pipe forming method according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a three-dimensional metal pipeline formed when two adjacent layers of metal pipelines provided by an embodiment of the present invention are communicated;
fig. 3 is a top view of the first recess and the auxiliary recess in the first dielectric layer in step S1 according to an embodiment of the present invention;
fig. 4 is a cross-sectional view of the first recess and the auxiliary recess in the first dielectric layer in the direction AA' in step S1 according to an embodiment of the present invention;
fig. 5 is a top view of the first cavity and the plug in the first dielectric layer in step S1 according to an embodiment of the present invention;
fig. 6 is a cross-sectional view of the first cavity and the plug in the first dielectric layer in the direction AA' in step S1 according to an embodiment of the present invention;
fig. 7 is a cross-sectional view of the second metal layer sealing the first cavity in step S2 according to the embodiment of the present invention;
fig. 8 is a cross-sectional view of the second cavity formed in step S3 according to the embodiment of the present invention;
FIG. 9 is a cross-sectional view of an embodiment of the present invention providing a second dielectric filling a second cavity;
fig. 10 is a cross-sectional view of a second recess and an auxiliary recess formed in a second dielectric layer according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view of a third cavity formed as provided by an embodiment of the present invention;
the structure comprises a first metal pipeline 1, a first groove 11, an auxiliary groove 12, a first dielectric layer 13, a first cavity 14, a first metal layer 15, a plug 16, a second metal layer 17, a second cavity 18, a second metal pipeline 2, a second dielectric layer 21, a second groove 22, a third cavity 23, a third metal layer 24 and a joint 3.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
As described in the background art, when a cmos process is used to fabricate a semiconductor device, since adjacent inter-layer dielectric layers are separated by metal layers and are not connected to each other, the existing locally interconnected metal pipes are two-dimensional metal pipes, the two-dimensional plane limits the total length of the pipe that can be designed, and if 3D pipe connection can be implemented, the total length of the pipe can be greatly increased to implement more functions.
Accordingly, in order to solve the above-described problems in manufacturing a semiconductor device, the present invention provides a 3D pipe forming method.
Referring to fig. 1, which is a schematic flow chart of a 3D pipeline forming method according to an embodiment of the present invention, as shown in fig. 1, the 3D pipeline forming method includes the following steps:
step S1: manufacturing a first groove in the first dielectric layer;
step S2: forming a first metal layer on the bottom wall and the side wall of the first groove to obtain a first cavity;
step S3: forming a second metal layer on the first dielectric layer to cover the first cavity;
step S4: etching the second metal layer on the top of the first cavity to form a second cavity and expose the first cavity;
step S5: forming a second dielectric layer on the second metal layer; and
step S6: and manufacturing a second groove in the second dielectric layer, wherein the second groove is communicated with the second cavity.
Specifically, referring to fig. 2, a schematic structural diagram of a three-dimensional metal pipe formed when two adjacent metal pipes are communicated according to an embodiment of the present invention is provided, where a first metal pipe 1 and a second metal pipe 2 are each located in two adjacent second metal layers.
Specifically, before forming the first metal layer and the second metal layer, the first dielectric layer is formed, and step S1 and step S2 are performed. Further, referring to fig. 3 to 6, top views and cross-sectional views of the first recess and the auxiliary recess in the first dielectric layer and the first cavity and the plug in the first dielectric layer in step S1 are provided according to the embodiments of the present invention.
Specifically, in step S1, the first dielectric layer 13 is a metal local interconnect dielectric layer, and specifically may be an oxide layer. Referring to fig. 3 and 4, in an embodiment, a first recess 11 is formed on the metal local interconnect dielectric layer, and an aspect ratio of the first recess 11 is less than or equal to 2.5. Specifically, the first groove 11 is preferably an elongated groove; further, by limiting the aspect ratio of the first groove 12 to meet the required standard of the first groove 12, the aspect ratio of the first groove may be preferably between 1.5 and 2.5.
Furthermore, while the first groove 11 is formed in the first dielectric layer 13, an auxiliary groove 12 is also formed in the first dielectric layer 13, and the aspect ratio of the auxiliary groove 12 is greater than or equal to 3. The auxiliary recess 12 defines a plug structure for local interconnects of the CMOS circuit. Optionally, the auxiliary groove 12 is a circular hole groove or a square hole groove. Preferably, the depth-to-width ratio of the auxiliary groove 12 may be between 3.5 and 4.5.
Next, referring to fig. 5 and 6, in step S2, a first metal layer is filled in the first recess 11 and the auxiliary recess 12. Further, the first recess 11 and the auxiliary recess 12 are filled with a first metal layer starting from the side walls. In one embodiment, the depth-to-width ratio of the auxiliary groove 12 is between 3.5 and 4.5, and the depth-to-width ratio of the first groove 11 is between 1.5 and 2.5. Then, for the auxiliary groove 12, since the aspect ratio of the auxiliary groove 12 is between 3.5 and 4.5, when the thickness of the first metal layer is larger than half of the width of the auxiliary groove 12 and smaller than half of the width of the first groove 11 during the first metal layer filling process, the auxiliary groove 12 is filled with the first metal layer, the plug 16 is formed by sealing, and the lead hole of the circuit is formed after the first metal layer in the auxiliary groove 12 is CMP-finished. In contrast, for the first recess 11, since the aspect ratio is between 1.5 and 2.5, and the width is greater than twice the thickness of the first metal layer to be filled, the sidewall cannot be closed after the first metal layer is filled, so that the first metal layer is formed on the bottom wall and the sidewall of the first recess 11, and then the first cavity 14 is formed after the metal CMP in the auxiliary recess 12. Preferably, the metal is tungsten metal, and the first metal layer 15 is a tungsten metal layer.
Referring to fig. 7, in step S3, after the first cavity 14 and the lead holes of the circuit are formed in the first dielectric layer 13, a first layer of the second metal layer 17 is formed on the first dielectric layer 13. Further, since the width of the first cavity 14 is small, the second metal layer 17 cannot be filled; the second metal layer 17 seals the first cavity 14 and connects to the lead vias. Specifically, the metal of the second metal layer 17 may be aluminum or an aluminum copper alloy.
Further, in fig. 2, a process of forming a joint 3 structure of a first metal pipe 1 and a second metal pipe 2. Referring specifically to fig. 8 to 11, fig. 8 to 11 are sectional views during the formation of the joint structure, wherein fig. 11 shows a sectional view of the finally formed joint 3.
Further, referring to fig. 8, in the step S4, the second metal layer 17 on top of the first cavity 14 is etched away while the second metal layer 17 is etched to form a metal interconnection line, so as to form a second cavity 18 and expose the first cavity 14. Further, the bottom of the second cavity 18 communicates with the first cavity 14. Preferably, the width of the second cavity 18 is equal to the width of the first cavity 14.
Referring to fig. 9 to 11, in the step S5, a second dielectric layer 21 is formed on the etched second metal layer 17, where the second dielectric layer 21 is a metal local interconnect dielectric layer, and may be an oxide layer. Further, when the second dielectric layer 21 is formed on the second metal layer, the aspect ratio of the second cavity 18 is less than or equal to 2.5, and the second cavity 18 cannot be filled with the second dielectric layer 21 filling a part of the second cavity 18.
Next, step S6 is performed. Specifically, in step S6, as shown in fig. 10, when the second groove 22 is formed on the second medium 21 layer, the second groove 22 intersects the first groove 11 at the connection portion 3 in fig. 2, and specifically, the position of the second groove 22 corresponds to the position of the first groove 11 and is located above the second cavity 18. Further, the aspect ratio of the formed second groove 22 is less than or equal to 2.5, and preferably, the second groove 22 is an elongated groove. Specifically, the required standard of the second groove 22 is achieved by limiting the depth-to-width ratio of the second groove 22. Preferably, the depth-to-width ratio of the second groove 22 may be between 1.5 and 2.5. Preferably, the width of the second groove 22 is equal to the width of the first groove 11. Specifically, the second dielectric partially filled in the second cavity 18 is etched while the second groove 22 is formed, because the bottom of the second cavity 18 is not filled, after the second dielectric layer 21 in the second cavity 18 is etched, the second groove 22 is communicated with the second cavity 18 (located in the joint 3 in fig. 2) at a position above the bottom of the second cavity 18, and because the second cavity 18 is communicated with the first cavity 14, the second groove 22 is communicated with the first cavity 14 through the second cavity 18.
Furthermore, an auxiliary groove 12 is formed on the second dielectric layer 21 at the same time of forming the second groove 22 on the second dielectric layer 21, and the aspect ratio of the auxiliary groove is greater than or equal to 3. Optionally, the auxiliary groove 12 is a circular hole groove or a square hole groove. Preferably, the depth-to-width ratio of the auxiliary groove 12 may be between 3.5 and 4.5.
Further, after the step S6, as shown in fig. 11, the method further includes: a first metal layer is formed on the side walls of the second recess 22 and the second cavity 18, obtaining a third cavity 23, the third cavity 23 being in communication with the first cavity 14. Specifically, after step S6, a first metal layer is filled in the second groove 22 and the auxiliary groove 12, and for the auxiliary groove 12, since the aspect ratio of the auxiliary groove 12 is between 3.5 and 4.5, when the thickness of the filled first metal layer is greater than half of the width of the auxiliary groove 12 and less than half of the width of the second groove 11, the auxiliary groove 12 is quickly filled with the first metal layer when the first metal layer is filled, and the plug 16 is hermetically formed. After the CMP of the first metal layer in the auxiliary groove 12, a wire hole in the metal pipe is formed. In contrast, for the second recess 22, since the aspect ratio is between 1.5-2.5, and the width is greater than twice the thickness of the first metal layer to be filled, the sidewall cannot be closed after the first metal layer is filled, so that the first metal layer is formed on the bottom wall and the sidewall of the second recess 22 and the sidewall of the second cavity 18, and then the third cavity 23 is formed after the CMP of the first metal layer in the auxiliary recess 12. Preferably, the metal is tungsten metal, and the first metal layer 15 is a tungsten metal layer.
The third cavity 23 is communicated with the first cavity 14, a second layer of second metal layer is formed on the second medium layer 21, and the top of the third cavity 23 is sealed, so that the third cavity enables the metal pipeline in the second layer of second metal layer to be communicated with the metal pipeline in the first layer of second metal layer, and a three-dimensional metal pipeline is formed. Preferably, the second metal layer is aluminum or aluminum copper alloy.
If necessary, the steps can be repeated to form a multilayer cavity connected 3D structure.
In summary, in the 3D pipeline forming method provided by the present invention, the first groove is formed in the first dielectric layer; forming a first metal layer on the bottom wall and the side wall of the first groove to obtain a first cavity; forming a second metal layer on the first dielectric layer to cover the first cavity; etching the second metal layer on the top of the first cavity to form a second cavity and expose the first cavity; forming a second dielectric layer on the second metal layer; and manufacturing a second groove in the second dielectric layer, wherein the second groove is communicated with the second cavity. According to the method provided by the invention, the first cavity is formed, the second metal layer at the top of the first cavity is etched while the metal interconnection line is etched, the second cavity is formed, the second groove is formed at the position corresponding to the first groove and is communicated with the second cavity, so that the second groove is communicated with the first cavity through the second cavity, and finally the metal pipelines in two adjacent metal layers are communicated to form the 3D metal pipeline, so that the total length of the pipeline is increased, and the functions of flowing, mixing and the like of liquid or gas can be realized.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (13)
1. A method of forming a 3D pipe, comprising,
manufacturing a first groove in the first dielectric layer;
forming a first metal layer on the bottom wall and the side wall of the first groove to obtain a first cavity;
forming a second metal layer on the first dielectric layer to cover the first cavity;
etching the second metal layer on the top of the first cavity to form a second cavity and expose the first cavity;
forming a second dielectric layer on the second metal layer; and
and manufacturing a second groove in the second dielectric layer, wherein the second groove is communicated with the second cavity.
2. The method of forming a 3D pipe according to claim 1, wherein the first groove or the second groove has an aspect ratio of 2.5 or less.
3. The method of claim 1, wherein an auxiliary recess is also formed in the first dielectric layer or the second dielectric layer while forming the first recess in the first dielectric layer or the second recess in the second dielectric layer.
4. The 3D tubing method of claim 3, wherein the auxiliary groove has an aspect ratio of 3 or greater.
5. The method of claim 4, wherein a thickness of the first metal layer is less than half a width of the first and second grooves and greater than or equal to half a width of the auxiliary groove.
6. The 3D duct forming method of claim 1, wherein the second metal layer at a top of the first cavity is etched while the second metal layer is etched to form metal interconnect lines.
7. The method of forming a 3D pipe according to claim 1, wherein the second cavity bottom communicates with the first cavity top.
8. The 3D duct forming method of claim 1, wherein an aspect ratio of the second cavity is 2.5 or less.
9. The method of forming a 3D pipe of claim 8, wherein the second dielectric layer fills at least a portion of the second cavity when formed on the second metal layer.
10. The method of claim 8, wherein the second dielectric layer in the second cavity is etched away when the second recess is made.
11. The method of forming a 3D duct of claim 9, wherein the second groove communicates with the second cavity at a location above a bottom of the second cavity.
12. The 3D duct forming method of claim 10, wherein the second groove communicates with the first cavity through the second cavity.
13. The method of forming a 3D pipe according to claim 10, wherein after forming a second recess in the second dielectric layer, the second recess communicating with the second cavity, further comprising: and forming a third metal layer on the side wall of the second groove and the side wall of the second cavity to obtain a third cavity, wherein the third cavity is communicated with the first cavity.
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| CN201810800783.XA CN108975267B (en) | 2018-07-20 | 2018-07-20 | 3D pipeline forming method |
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| US5739579A (en) * | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
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| JP2006024831A (en) * | 2004-07-09 | 2006-01-26 | Sony Corp | Semiconductor device and manufacturing method thereof |
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| US6349401B2 (en) * | 1996-09-12 | 2002-02-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit, design method and computer-readable medium using a permissive current ratio |
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| US5739579A (en) * | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
| JPH10144878A (en) * | 1996-11-06 | 1998-05-29 | Hitachi Ltd | Semiconductor integrated circuit device and fabrication thereof |
| JP2006024831A (en) * | 2004-07-09 | 2006-01-26 | Sony Corp | Semiconductor device and manufacturing method thereof |
| CN103377987A (en) * | 2012-04-17 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Forming method and processing method of semiconductor structure |
| CN103204461A (en) * | 2013-03-22 | 2013-07-17 | 上海宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN104576764A (en) * | 2013-10-29 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Integrated passive device and manufacturing method thereof |
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