JP4975698B2 - 光電変換モジュール - Google Patents
光電変換モジュール Download PDFInfo
- Publication number
- JP4975698B2 JP4975698B2 JP2008199270A JP2008199270A JP4975698B2 JP 4975698 B2 JP4975698 B2 JP 4975698B2 JP 2008199270 A JP2008199270 A JP 2008199270A JP 2008199270 A JP2008199270 A JP 2008199270A JP 4975698 B2 JP4975698 B2 JP 4975698B2
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- JP
- Japan
- Prior art keywords
- laminated substrate
- optical element
- optical
- substrate
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Semiconductor Lasers (AREA)
- Light Receiving Elements (AREA)
Description
この場合、前記ガイドピンは、前記光素子を挟んでその両側に配置されていてもよい。
(1)第1積層基板51の作製
(2)第2積層基板61の作製
(3)光素子17の搭載
(4)半導体集積回路素子18の搭載
集積回路素子搭載部63を有する第2積層基板主面を上向きにして第2積層基板61をチップマウンタにセットし、集積回路素子搭載部63上に半導体集積回路素子18を接着剤で接着して搭載する。次に、第2積層基板主面を上向きにして第2積層基板61をボンディング装置にセットし、ワイヤボンディングを実施する。その結果、第2積層基板61に搭載された半導体集積回路素子18が第2積層基板61側の導体と電気的に接続される。本工程においては、第2積層基板61の第2積層基板主面を上向きにできるので、接着やワイヤボンディングを比較的簡単に行うことができる(図6参照)。
(5)第1積層基板51と第2積層基板61との接合
(6)ガイドピン31の接合、プリント配線基板11上への実装など
従って、本実施形態によれば以下の効果を得ることができる。
18…半導体集積回路素子
21…他部品としてのMTコネクタ
31…光結合部材としてのガイドピン
40…積層基板接合体
41,141,241,341…光電変換モジュール
44…断熱層としての異方導電性材料層
51…第1積層基板
52,62…絶縁層としてのセラミック絶縁層
53…光素子搭載部
61…第2積層基板
92…精密加工穴
142…半導体集積回路素子用キャビティ
143…光素子用キャビティ
242…断熱層としての接着剤層
342…断熱層としてのアンダーフィル
Claims (2)
- モジュール搭載用配線基板の厚さ方向と直交する方向に複数の絶縁層を積層してなる多層基板を有し、前記多層基板の下面に複数のバンプ用パッドが設けられ、前記多層基板の側面に光素子用キャビティが設けられた第1積層基板と、
前記第1積層基板の前記側面にて前記光素子用キャビティ内に収容された状態で搭載された光素子と、
前記第1積層基板の前記側面に設けられ、前記光素子と前記光素子に光結合されるべき他部品との光軸合わせの際の位置基準となる光結合部材としてのガイドピンと、
前記第1積層基板に搭載された光素子駆動用半導体集積回路素子及び光信号増幅用半導体集積回路素子のうちの少なくともいずれかと
を備え、前記第1積層基板において前記光素子及び前記ガイドピンが設けられた前記側面とは別の側面には、さらに側面接続パッドが設けられていることを特徴とする光電変換モジュール。 - 前記ガイドピンは、前記光素子を挟んでその両側に配置されていることを特徴とする請求項1に記載の光電変換モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008199270A JP4975698B2 (ja) | 2008-08-01 | 2008-08-01 | 光電変換モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008199270A JP4975698B2 (ja) | 2008-08-01 | 2008-08-01 | 光電変換モジュール |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004248486A Division JP4555026B2 (ja) | 2004-05-31 | 2004-08-27 | 光電変換モジュール、積層基板接合体 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008263240A JP2008263240A (ja) | 2008-10-30 |
JP4975698B2 true JP4975698B2 (ja) | 2012-07-11 |
Family
ID=39985437
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008199270A Expired - Fee Related JP4975698B2 (ja) | 2008-08-01 | 2008-08-01 | 光電変換モジュール |
Country Status (1)
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JP (1) | JP4975698B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201132246A (en) * | 2010-03-09 | 2011-09-16 | Nan Ya Printed Circuit Board | Side packaged type printed circuit board |
CN102202463A (zh) * | 2010-03-24 | 2011-09-28 | 南亚电路板股份有限公司 | 侧边封装型印刷电路板 |
JP6629718B2 (ja) * | 2013-04-29 | 2020-01-15 | シリコン・ライン・ゲー・エム・ベー・ハー | 光信号をカップリングおよび/又はデカップリングするための装置 |
JP2018085384A (ja) * | 2016-11-21 | 2018-05-31 | オムロン株式会社 | 電子装置およびその製造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3483102B2 (ja) * | 1997-09-22 | 2004-01-06 | 日本電信電話株式会社 | 光素子実装体 |
JP2000200937A (ja) * | 1999-01-06 | 2000-07-18 | Sumitomo Electric Ind Ltd | 光並列伝送用送信器 |
JP2002299649A (ja) * | 2001-03-30 | 2002-10-11 | Kyocera Corp | 光半導体素子キャリア及びそれを用いた光デバイス |
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2008
- 2008-08-01 JP JP2008199270A patent/JP4975698B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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JP2008263240A (ja) | 2008-10-30 |
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