JP4963131B2 - Wafer batch contact board - Google Patents

Description

  The present invention relates to a wafer batch contact board used for collectively inspecting (testing) a plurality of semiconductor devices formed on a wafer in a wafer state, a manufacturing method thereof, and the like.

Inspection of many semiconductor devices formed on a wafer is roughly classified into product inspection (electrical characteristic test) using a probe card and burn-in test which is a reliability test performed thereafter.
The burn-in test is one of screening tests performed to remove a semiconductor device having an inherent defect or a device causing a failure depending on time and stress from manufacturing variations. While the probe card inspection is an electrical characteristic test of the manufactured device, the burn-in test is a thermal acceleration test.

  The burn-in test is a normal method (one-chip burn-in system) in which a wafer is cut into chips by dicing and packaged one by one after an electrical characteristic test performed for each chip by a probe card. Then there are many problems in terms of cost. Therefore, development and practical application of a wafer batch contact board (burn-in board) for performing a burn-in test on a plurality of semiconductor devices formed on the wafer all at once are being promoted (Japanese Patent Laid-Open No. 7-231019). . The wafer batch burn-in system using the wafer batch contact board has many advantages in terms of cost, and is also an important technology for realizing the latest technological flow such as bare chip shipment and bare chip mounting.

The details of the burn-in test are shown below.
Static burn-in is a burn-in test in which a power supply voltage is applied at or above the rated voltage at a high temperature and current is passed through the device to apply temperature and voltage stress to the device. .
The dynamic burn-in is a burn-in test that is performed while applying a power supply voltage that is rated or exceeding that at a high temperature and applying a signal close to actual operation to the input circuit of the device.
Monitored burn-in is a burn-in test that has the function of not only applying a signal to the input circuit of a device but also monitoring the characteristics of the output circuit in dynamic burn-in.
The test burn-in is a burn-in test that can perform pass / fail judgment and evaluation of a device under test.

  The wafer batch contact board is different from the conventional probe card in that the wafer batch contact board is used for the batch wafer inspection and the heating test, and the required level is high. When the wafer batch contact board is put into practical use, in addition to the burn-in test (including the case where the electrical characteristic test is performed) described above, a part of the product inspection (electrical characteristic test) which has been conventionally performed by the probe card is performed. It is also possible to perform the wafer batch.

FIG. 9 shows a specific example of the wafer batch contact board.
As shown in FIG. 9, the wafer batch contact board has a contact part 30 fixed on a multilayer wiring board for wafer batch contact board (hereinafter referred to as a multilayer wiring board) 10 with an anisotropic conductive rubber sheet 20 interposed therebetween. It has a structure.
The contact component 30 takes charge of the contact portion that is in direct contact with the device under test. In the contact component 30, an isolated bump 33 is formed on one surface of the insulating film 32, and an isolated pad 34 is formed on the other surface in a one-to-one correspondence with the isolated bump 33. The insulating film 32 is stretched over a ring 31 having a low coefficient of thermal expansion in order to avoid misalignment due to thermal expansion. The isolated bumps 33 are electrodes formed on the periphery or center line of each semiconductor device (chip) on the wafer 40 (about 600 to 1000 pins per chip, and the number of electrodes obtained by multiplying this number by the number of chips) Are formed at positions corresponding to approximately the same number as this electrode.
The multilayer wiring board 10 has wiring and pad electrodes for applying a predetermined burn-in test signal or the like to each bump 33 isolated on the insulating film 32 via an isolated pad 34 on the insulating substrate. The multilayer wiring board 10 has a multilayer wiring structure because wiring is complicated. The multilayer wiring board 10 uses an insulating substrate having a low thermal expansion coefficient in order to avoid a connection failure due to a positional shift with the isolated pad 34 on the insulating film 32 due to thermal expansion.
The anisotropic conductive rubber sheet 20 is a connecting component that electrically connects a pad electrode (not shown) on the multilayer wiring board 10 and an isolated pad 34 on the insulating film 32, and is perpendicular to the main surface. It is a sheet-like connecting component having an elastic body (anisotropic conductive rubber made of silicon resin in which metal particles are embedded in portions corresponding to the isolated pad 34 and the pad electrode) having conductivity only in the direction. The anisotropic conductive rubber sheet 20 is in contact with an isolated pad 34 on the insulating film 32 by a projection (not shown) of the anisotropic conductive rubber formed so as to protrude from the surface of the sheet. Both the flexibility and the flexibility of the insulating film 32 absorb the unevenness on the surface of the semiconductor wafer 40 and the variation in the height of the isolated bump 33, and the like. The isolated bump 33 is securely connected.

  Each semiconductor device (chip) is formed with electrodes (power supply electrodes, ground electrodes, signal electrodes) that serve as power supply terminals, ground terminals, and signal input / output terminals (signal terminals) of the integrated circuit, and all electrodes of the semiconductor chip. The isolated bumps 33 of the wafer collective contact board are formed in a one-to-one relationship and connected to each other. In the multilayer wiring in the wafer batch contact board, the power supply wiring, the ground wiring, and the signal input / output wiring (signal wiring) are made common for the purpose of reducing the number of wirings.

[Problems to be solved by the invention]
When performing the wafer batch burn-in test using the wafer batch contact board described above, all the chips on the wafer are measured at the same time, so there is a lot of noise generated during switching of each chip, and this noise waveform is the input pulse signal. It was found that there was a problem due to the occurrence of a malfunction (error) and the like. For this reason, in the conventional wafer batch contact board, a power supply voltage can be applied only up to about 10 MHz, and there is a problem that high frequency characteristics are not sufficient.

The present invention has been made under such a background, and it is a first object of the present invention to provide a wafer batch contact board that is resistant to high-frequency noise and has improved high-frequency characteristics, a method of manufacturing the same, and the like.
A second object of the present invention is to provide a wafer collective contact board that is resistant to high-frequency noise and has improved high-frequency characteristics and can be easily produced without increasing costs and processes, and a manufacturing method thereof. .

[Means for solving problems]
In order to achieve the above object, the present invention is configured as follows.

(Configuration 1) A wafer batch contact board used to collectively test a plurality of semiconductor devices formed on a wafer,
Contact parts responsible for the contact portion of the wafer batch contact board; and
A wiring substrate for a wafer batch contact board having a structure in which wirings are stacked through an insulating layer and upper and lower wirings are connected through contact holes formed in the insulating layer, and the wiring substrate and the contact component are electrically connected An anisotropic conductive rubber sheet connected to
A wafer having a structure in which a GND wiring and / or a power wiring in the wiring substrate is connected to a frame having a metal part at least partially supporting the anisotropic conductive rubber in the anisotropic conductive rubber sheet. Bulk contact board.

(Configuration 2) A wafer batch contact board used to collectively test a plurality of semiconductor devices formed on a wafer,
An insulating film stretched over a ring; an isolated pad formed on one surface of the insulating film; and the isolated film formed on the other surface of the insulating film in a one-to-one correspondence with the isolated pad A contact component for a wafer batch contact board having an isolated bump connected to the pad;
A wiring substrate for a wafer batch contact board having a structure in which wirings are stacked through an insulating layer and upper and lower wirings are connected through contact holes formed in the insulating layer, and the wiring substrate and the contact component are electrically connected An anisotropic conductive rubber sheet connected to
A conductive pattern is formed on the front surface and / or back surface of the insulating film in the contact component, avoiding the isolated pad and / or the isolated bump, and a GND wiring and / or a power source on the wiring board is formed on the conductive pattern. A wafer batch contact board characterized by having a structure in which wiring is connected.

  (Structure 3) Either or both of the frame in the anisotropic conductive rubber sheet according to claim 1 and the conductive pattern in the contact component according to claim 2 are used in the wiring board according to claim 1 or 2. A wafer batch contact board characterized by having a structure connected to power supply wiring.

  (Structure 4) Either or both of the frame in the anisotropic conductive rubber sheet according to claim 1 and the conductive pattern in the contact component according to claim 2 are used in the wiring board according to claim 1 or 2. A wafer batch contact board having a structure connected to GND wiring.

  (Structure 5) Either one of the frame in the anisotropic conductive rubber sheet according to claim 1 and the conductive pattern in the contact component according to claim 2 is used as the power supply wiring in the wiring board according to claim 1 or 2. A wafer collective contact board having a structure in which a bypass capacitor is formed between the frame and the conductive pattern with the other connected to the GND wiring on the wiring board.

  (Structure 6) The wafer batch contact board according to claim 5, wherein a dielectric material layer is formed on a surface of the frame.

(Structure 7) The wiring board according to any one of claims 1 to 6 has a structure in which wirings are stacked through an insulating layer, and upper and lower wirings are connected through contact holes formed in the insulating layer. ,
A plurality of pad electrodes provided on the wiring substrate in a one-to-one correspondence with the electrodes on each chip in the multiple semiconductor devices;
Power supply common wiring provided in a multilayer wiring layer for the purpose of electrically commonly connecting power supply electrodes of the same type in the multiple semiconductor devices;
A GND common wiring provided in a multilayer wiring layer for the purpose of electrically connecting GND electrodes in the plurality of semiconductor devices, and
7. A wafer batch contact board, wherein a GND wiring or a power wiring in the wiring board according to claim 1 is the GND common wiring or the power common wiring.

(Configuration 8) An insulating film stretched over a ring, an isolated bump formed on one surface of the insulating film, and formed on the other surface of the insulating film in a one-to-one correspondence with the isolated bump A contact part for a wafer batch contact board, comprising: an isolated pad; and a connecting portion that connects the isolated bump and the isolated pad through a bump hole formed in an insulating film,
For the purpose of connecting to the GND wiring or the power supply wiring on the wiring board, it has a step of forming a conductive pattern on one surface and / or the other surface of the insulating film while avoiding isolated pads and / or isolated bumps. A method of manufacturing a contact component for a wafer batch contact board.

  (Configuration 9) Inspection of a semiconductor device characterized by using the wafer batch contact board according to any one of Configurations 1 to 6 to collectively test a semiconductor device formed on a wafer in a wafer state. Method.

[Action]
In the configuration 1, as shown in FIG. 1, the GND in the wiring substrate 10 is attached to the frame 22 (the frame having at least a conductive portion) that supports the anisotropic conductive rubber 21 in the anisotropic conductive rubber sheet 20. By connecting wiring or power supply wiring (not shown), noise against high frequency is reduced and high frequency characteristics are further improved. Further, by using a frame that has not been used electrically in the past, it is possible to easily improve the high-frequency characteristics without increasing costs and processes. Here, as shown in FIG. 1, the anisotropic conductive rubber sheet 20 has openings arranged in a frame 22 made of a conductive thin plate, and an anisotropic made of a resin containing conductive particles in the opening. A conductive rubber 21 is formed. In FIG. 1, 12 is a power supply wiring, 13 is a GND wiring, and 14 is a signal wiring, which are connected to each pad electrode (power supply pad, GND pad, signal pad) (not shown) on the wiring board. . The other parts in FIG. 1 are assigned the same numbers as in FIG. The same applies to FIGS.
The thickness of the GND wiring or the power supply wiring on the wiring board is about 3 to 5 μm, and the volume of the frame is sufficiently larger than this. Therefore, by connecting the power supply wiring or the GND wiring in the wiring board to the frame, noise can be reduced and the high frequency characteristics can be further improved. In particular, by connecting the GND common wiring or the power supply common wiring on the wiring board to the frame, all the isolated GND pads or the isolated power supply pads on the insulating film can be connected to the frame. Therefore, the GND common wiring or the power supply common wiring can be connected to the frame. The resistance can be reduced, and a decrease in power supply voltage due to wiring resistance can be suppressed (so-called “strengthening of power supply” can be achieved), or the resistance value of GND can be lowered (so-called “strengthening of GND”). Is preferable. As shown in FIG. 2, the frame 22 shown in FIG. 1 is more on the wafer 40 than in the case where the GND 11 having a large area is provided on the substrate surface or in the wiring layer (middle layer or uppermost layer) in the multilayer wiring substrate 10. Since it is close to the chip and has a large capacity as GND, it is resistant to noise.
A method for connecting the GND wiring or the power supply wiring on the wiring board to the frame is not particularly limited. For example, when an anisotropic conductive rubber sheet is used, the connection can be easily made without increasing the cost and the process.
Specifically, as shown in FIG. 3, by connecting the portion of the anisotropic conductive rubber 21a corresponding to the power supply pad 12a in the wiring board 10 to the frame 22 without applying a magnetic field, the power supply pad 12a is interposed. A power supply wiring (not shown) in the wiring board 10 and the frame 22 can be connected. The portions of the anisotropic conductive rubber 21c and 21b corresponding to the GND pad 12c and the signal pad 12b in the wiring substrate 10 are formed by forming portions 21c ′ and 21b ′ in which conductive particles are brought to the center by a normal magnetic field. Insulate from the frame. In FIG. 3, the power supply and the GND may be switched to connect the GND wiring (GND pad 12 c) and the frame 22 in the wiring substrate 10.
In the configuration 1, for example, in the case of using a frame in which two conductive material layers insulated from each other are formed on the surface of the non-metallic frame, one of the conductive material layers in the frame is connected to the GND in the wiring board. Wiring can be connected, and the power supply wiring in the wiring board can be connected to the other conductive material layer.

In Configuration 2, a conductive pattern is formed on one surface and / or the other surface of the insulating film of the contact component while avoiding isolated pads and / or isolated bumps, and this conductive pattern is connected to GND on the wiring board. By connecting the wiring or the power supply wiring, noise with respect to the high frequency is reduced and the high frequency characteristics are further improved. In addition, by utilizing the space on the front and back of the insulating film that has not been used conventionally, it is possible to easily improve the high frequency characteristics without increasing the cost or increasing the number of processes. Further, by devising the pattern shape of the conductive pattern, there is an effect of suppressing the elongation of the insulating film and improving the positional accuracy of the isolated pad and the isolated bump.
The thickness of the GND wiring or the power supply wiring on the wiring board is about 3 to 5 μm, and the thickness of the conductive pattern that can be formed on the front and back of the insulating film is about 20 μm, for example, and the sheet resistance is small. Therefore, by connecting the GND wiring or the power supply wiring in the wiring board to this conductive pattern, noise can be reduced and the high frequency characteristics can be further improved. In particular, all the isolated GND pads or isolated power pads on the insulating film can be connected to the conductive pattern by connecting the power supply common wiring or GND common wiring on the wiring board to this conductive pattern, and therefore the GND common wiring Alternatively, it is preferable because the resistance of the power supply common line can be reduced and the GND or the power supply can be strengthened. Further, as shown in FIG. 1, since the conductive pattern 35 on the contact component 30 is closest to the chip on the wafer 40, the resistance of the GND wiring or power supply wiring can be reduced, and the GND or power supply can be further strengthened.
The conductive pattern can be easily formed. In particular, since the conductive pattern on the isolated pad side can be formed simultaneously with the isolated pad as a remaining pattern when forming the isolated pad, it can be easily formed without increasing the number of processes and cost.
The method for connecting the GND wiring or the power supply wiring on the wiring board to the conductive pattern is not particularly limited. For example, as shown in FIG. 3, the isolated GND pad 34 ′ on the insulating film 32 and the conductive pattern 35 ′ are connected. Then, the GND wiring on the wiring board and the conductive patterns 35 ′ and 35 (connected to 35 ′ at other parts of the wiring board) can be connected via the anisotropic conductive rubber 21 c and the GND pad 12 c on the wiring board. . In FIG. 3, the power supply and the GND may be switched to connect the power supply wiring (power supply pad 12 a) and the conductive pattern 35 ′ in the wiring board 10.
Further, for example, as shown in FIG. 4, in the peripheral part of the wafer batch contact board, the conductive pattern 36 on the insulating film 32 is wired via the anisotropic conductive rubber 21d and the GND pad 12d separately provided. It can also be connected to a GND wiring (ground trace) 15 on the substrate.

In addition, when forming a conductive pattern on the front and back of an insulating film, both the front and back conductive patterns can be connected to either the GND wiring or the power supply wiring on the wiring board.
Also, when forming conductive patterns on the front and back of the insulating film, as described in Configuration 3, one is connected to the power supply wiring of the wiring board and the other is connected to the GND wiring of the wiring board. A bypass capacitor can be formed. This bypass capacitor can be formed, for example, by forming a conductive pattern with a large area on both the front and back sides of the insulating film. In this case, an insulating film such as polyimide (dielectric constant 3.2) becomes a dielectric layer in the capacitor. Further, this bypass capacitor can be formed at a rate of one per chip by forming an isolated conductive pattern at a rate of one for each isolated pad and each isolated bump.
Furthermore, in Configuration 2, two conductive patterns insulated from each other are formed on the surface of the insulating film, the GND wiring in the wiring board is connected to one conductive pattern in the insulating film, and the other conductive pattern is connected to the other conductive pattern. Power supply wiring on the wiring board can be connected.

  Configuration 3 is a combination of Configuration 1 and Configuration 2 in which both the frame and the conductive pattern are connected to the power supply wiring on the wiring board. This is particularly effective in suppressing a decrease in power supply voltage due to wiring resistance and ensuring the reliability of the operation of all chips.

  Configuration 4 is a combination of Configuration 1 and Configuration 2 in which both the frame and the conductive pattern are connected to the GND wiring on the wiring board. Thereby, the resistance value of GND can be lowered, and so-called “strengthening of GND” can be achieved.

Configuration 5 is a combination of Configuration 1 and Configuration 2, in which one of the frame and the conductive pattern is connected to the power supply wiring on the wiring board, and the other is connected to the GND wiring, and the frame and the conductive pattern are connected. By forming a bypass capacitor between them, noise for high frequency is reduced and high frequency characteristics are further improved.
Here, an air layer is interposed between the frame and the conductive pattern, and a resin insulating layer on the surface of the frame is further interposed. By forming the dielectric layer on the surface of the frame, the capacitance of the capacitor can be increased and noise can be further reduced.
A capacitor material can be increased by forming a dielectric material layer, particularly a ferroelectric material layer containing barium titanate, strontium titanate, titanium oxide, or the like on the surface of the frame (Configuration 6). A method of forming the dielectric material layer by oxidizing the surface of the frame (thermal oxidation or anodic oxidation) is desirable because it is simple.
The bypass capacitor of Configuration 5 can be formed, for example, by forming a conductive pattern with a large area on the front surface and / or back surface of the insulating film and between the conductive pattern and the frame. Further, as shown in FIG. 5, the bypass capacitor of the configuration 5 has an isolated conductive pattern 37 on the insulating film 32 at a ratio of one to each isolated GND pad (under 21 ′) on the insulating film 32. And connecting them, a capacitor can be formed at a rate of one per chip.

  According to Configuration 9, by using the wafer batch contact board of the present invention, the reliability of the operation of all the chips can be achieved, and the wafer batch type semiconductor inspection can be efficiently performed.

[Embodiment of the Invention]
The contact component in the wafer batch contact board of the present invention will be described.
In the contact component, the material of the insulating film is not particularly limited as long as it has electrical insulation, but preferably has insulation and flexibility. Specifically, a polyimide resin, an epoxy resin, Examples include silicone resins, polyester resins, urethane resins, polystyrene resins, polyethylene resins, polyamide resins, ABS copolymer resins, polycarbonate resins, fluorine resins, and other thermosetting resins, or thermoplastic resins. Can be appropriately selected according to the purpose. Of these resins, polyimide resins that are excellent in heat resistance, chemical resistance, mechanical strength, and workability are particularly preferably used. Since polyimide has a large absorption in the ultraviolet region, it is suitable for laser ablation processing. Since the polyimide film has high flexibility, it can absorb variations in height of isolated bumps on contact parts and electrodes (contact points) on the object to be inspected.
The thickness of the insulating film can be arbitrarily selected. In the case of a polyimide film, the thickness is usually preferably about 5 to 200 μm, more preferably 10 to 50 μm from the viewpoint of the formability of bump holes described later.

As the conductive layer for forming the isolated pad and the conductive pattern on the insulating film of the contact component, any conductive layer may be used. For example, a single metal such as copper, nickel, chromium, aluminum, gold, platinum, cobalt, silver, lead, tin, indium, rhodium, tungsten, ruthenium, iron, or various alloys containing these components (for example, solder, nickel- Tin, gold-cobalt) and the like. As will be described later, when an isolated bump or the like is formed by electrolytic plating, a conductive layer that becomes an electrode (cathode) in electrolytic plating is selected. The conductive layer may have a single-layer structure composed of the above metal layers or a laminated structure. For example, a laminated structure in which a base film such as Cr or Ni, a Cu film, a Ni film, and an Au film are sequentially laminated from the insulating film side can be used. In this case, the Cr undercoating film or the Ni undercoating film is preferable because it improves adhesion with an insulating film such as a polyimide film. The Cu film is a main component of the conductive layer. The Ni film has a role of preventing oxidation of Cu, a role of improving the mechanical strength of the conductive layer, and a role of an intermediate layer for forming an Au layer on the outermost surface of the conductive layer. The Au film is formed for the purpose of preventing oxidation of the surface of the conductive layer and reducing contact resistance. Note that a gold-cobalt alloy, rhodium, palladium, or the like can be used instead of the Au film. In particular, when a gold-cobalt alloy is used, the mechanical strength of the isolated pad increases.
Note that the isolated layer and the conductive layer for forming the conductive pattern may be made of the same material or different materials.

As a method for forming these conductive layers, a film forming method such as sputtering or vapor deposition, or a plating method such as electroless plating or electrolytic plating can be used. In this case, the conductive layer can be formed by a combination of sputtering and plating. For example, after a thin film is formed by a sputtering method, a thick film can be formed by plating. Note that the Ni film or the Au film on the Cu film is required to have a mechanical strength and needs to be a relatively thick film, so that it is desirable to form by a plating method (electroless plating or electrolytic plating).
The thickness of the conductive layer is not particularly limited and can be set as appropriate. However, the thickness of the conductive pattern on the isolated bump side in the insulating film is preferably set not to exceed the height of the isolated bump, and more preferably sufficiently lower than the height of the isolated bump.

The isolated pad or conductive pattern on the insulating film can be formed, for example, by patterning a conductive layer formed on the entire surface of the insulating film. Specifically, for example, after forming a resist pattern on the conductive layer formed on the entire surface of the insulating film, the exposed conductive layer is etched to obtain a desired isolated pad or conductive pattern.
The isolated pad and / or the conductive pattern can be formed directly on the insulating film. For example, by masking the part other than the part where the isolated pad or conductive pattern is to be formed and performing film formation using a film forming method such as sputtering, various types of vapor deposition, and various types of plating, it is possible to isolate the part that is not masked. Pads and / or conductive patterns can be formed directly.
Further, the isolated pad or the conductive pattern can be directly drawn and formed using a dispenser or by a printing method or the like.
The isolated pad and the conductive pattern on the insulating film may be formed at the same time in the same process or separately in another process.

  The constituent material of the isolated bump in the contact component is not particularly limited as long as it is a metal having conductivity, and the same material as that of the conductive layer described above can be used. Among these, Ni, Au, Ag, Cu, Sn, Co, In, Rh, Cr, W, Ru, or an alloy mainly containing these metal components is preferable.

Examples of the method for forming an isolated bump include an electrolytic plating method, an electroless plating method, a CVD method, etc. Among them, the electrolytic plating method is preferable because the shape controllability is good and a high-precision isolated bump can be formed. .
In the method of forming an isolated bump by the electrolytic plating method, after forming a conductive layer and a bump hole (a hole for forming a bump, a hole for connecting the isolated bump and the isolated pad) on the insulating film. Then, it is immersed in a plating bath to conduct with the conductive layer as a cathode, and plating is grown at least in the bump hole to form an isolated bump. Here, in the case of forming an isolated bump that protrudes from the insulating film surface, the portion in the bump hole corresponds to the root of the isolated bump and corresponds to a connection portion that connects the isolated bump and the isolated pad. When an isolated bump is formed only in the bump hole, a portion on the isolated pad side corresponds to the connection portion, and a contact portion with the electrode on the wafer corresponds to the isolated bump. In addition, when forming the isolated bump which protruded from the insulating film surface, the connection part in a bump hole and the isolated bump which protruded from the insulating film surface can also be formed by another material.

  Various metal films may be formed on the surface of the isolated bumps as necessary. For example, Au, Au—Co, Rh, Pt, Pd, Ag or the like or these metal components are added to the surface of the isolated bump for the purpose of improving the hardness of the isolated bump surface or preventing the contamination of the isolated bump due to migration in the burn-in test. A metal coating such as a main alloy may be formed. The metal coating may be a single layer or a multilayer.

  In the present invention, the isolated bump is a contact portion provided on the surface of the insulating film for the purpose of electrical contact and connection. The isolated bumps may or may not protrude from the surface of the insulating film. Further, the three-dimensional shape of the isolated bump is not limited, and can be any three-dimensional shape. For example, the cross-sectional shape of the isolated bump is convex or flat according to the shape of the member to be contacted. The shape may be either concave or concave. When contacting the flat electrode on the wafer, it is preferable from the viewpoint of electrical connection reliability that the bump has a mushroom shape. The height and size of the isolated bump can be freely set according to the purpose.

Examples of the method for forming the bump hole in the insulating film include laser processing, lithographic method (including etching method), plasma processing, optical processing, machining, etc. Laser processing is preferable from the viewpoints of degree and processing accuracy.
In the case of laser processing, excimer laser, CO ₂ laser, YAG laser, etc. with high irradiation power are preferable as the laser light to be irradiated. Among them, the processing method by laser ablation using excimer laser is the melting of the insulating film by heat. Etc. are particularly preferred because a high aspect ratio can be obtained and fine drilling can be performed. In the case of laser processing, a bump hole is formed by irradiating the surface of the insulating film with a laser beam with a narrowed spot.
In other cases, bump holes are formed by performing plasma etching in an atmosphere containing oxygen or fluoride gas, dry etching such as RIE (reactive ion etching), or sputter etching using the resist pattern as a mask. can do.
A bump hole can also be formed by bringing a mask having a hole having a desired hole shape (round, square, diamond, etc.) into contact with the surface of the insulating film and etching the mask.
In general, the hole diameter of the bump hole is 5 to 200 μm, preferably about 20 to 50 μm. When forming a solder ball-compatible bump, the hole diameter of the bump hole is preferably about the same as the diameter of the solder ball (about 300 to 1000 μm).

  The ring in the contact component may be a support frame that can be supported in a state where the insulating film is stretched, and includes a support frame having an arbitrary shape such as a circle or a square. The ring in the contact component is preferably formed of a material having a low coefficient of thermal expansion such as SiC.

Next, the wiring board in the wafer batch contact board will be described. The wiring substrate for a wafer batch contact board used in the present invention is not limited to a multilayer wiring substrate having a multilayer wiring layer, and a wiring substrate having a single wiring layer can be used.
In the wiring substrate, the material of the insulating layer (insulating film) is preferably a resin material, and examples thereof include a polyimide resin, an acrylic resin, and an epoxy resin. A polyimide resin excellent in chemical properties is particularly preferable.
The insulating layer can be formed on the glass substrate or the wiring layer by, for example, spin coating, roll coating, curtain coating, spray coating, printing method, or the like.

In a wiring board, for example, a conductive thin film is formed on a glass substrate or an insulating layer by a thin film forming method such as sputtering, and a desired pattern is formed by a photolithography method (resist application, exposure, development, etching, etc.). A wiring having a thickness can be formed.
The wiring material and the wiring layer structure in the wiring are not particularly limited. For example, the main wiring material is Cu, a Cr / Cu / Ni multilayer structure from below, a Cu / Ni / Au multilayer structure from below, or from below. The wiring can have a Cr / Cu / Ni / Au multilayer structure.
Here, Cr and Ni can prevent oxidation of Cu, which is easily oxidized (particularly, corrosion resistance is improved by Ni), and Cr and Ni have good adhesion with Cu and adjacent layers other than Cu (for example, Adhesion between the Au layer in the case of Ni and a glass substrate or insulating layer in the case of Cr is good, so that the adhesion between the layers can be improved.
Examples of alternative materials for Cu as the main wiring material include Al and Mo. The film thickness of Cu as the main wiring material is preferably in the range of 0.5 to 15 μm, more preferably in the range of 1.0 to 7.0 μm, and still more preferably in the range of 2.5 to 6 μm.
Examples of alternative materials for Cr as the base film include metals such as W, Ti, Al, Mo, Ta, and CrSi.
Examples of the substitute material for Ni include metals having high adhesion in relation to the respective materials forming the upper and lower layers.
Examples of the substitute material for Au include Au, Ag, Pt, Ir, Os, Pd, Rh, and Ru.
In the case of a multilayer wiring board, the uppermost layer (outermost surface) wiring surface is coated with gold or the like in order to prevent and protect the wiring surface oxidation and reduce contact resistance, but the lower layer (inner layer) The wiring surface may not be coated with gold or the like. However, in view of the contact resistance, there is no problem other than the increase in cost even if a gold coat is added to the inner wiring layer.
Even if gold or the like is added to the wiring surface later, or a conductive layer (wiring layer) having a multilayer structure in which gold or the like is formed on the entire outer surface is formed in advance and then wet-etched sequentially to form a wiring pattern. Good. In addition, after the contact hole is formed, gold or the like can be coated only on the bottom of the contact hole (a part of the inner wiring surface).
When forming a conductive layer having a multilayer structure of Cr / Cu / Ni from below, Cr and Cu are formed by sputtering, and Ni is formed by electrolytic plating. In particular, Ni by electrolytic plating is thick. Therefore, the cost can be reduced. In addition, since the surface of Ni is rough, adhesion of a film to be deposited on Ni can be improved. When forming an Au film or the like on Ni, it is preferable to perform continuous plating or the like so as not to oxidize Ni.
Even if the wiring board is a multilayer wiring or single layer wiring formed on one side of the insulating substrate, a multilayer wiring or single layer wiring is formed on both sides of the insulating substrate, or one side of the insulating substrate A multilayer wiring may be formed on the other surface, and a single-layer wiring may be formed on the other surface.

The insulating substrate in the wiring substrate of the present invention is preferably a substrate such as a glass substrate, a ceramic substrate (SiC, SiN, alumina, etc.), a glass ceramic substrate, or a silicon substrate. The thermal expansion coefficient of the insulating substrate is preferably 10 ppm / ° C. or less.
Among these, a glass substrate is preferable from the following viewpoints. Compared to ceramic substrates, glass substrates are cheaper, easier to process, and have good flatness due to high-precision polishing, and are transparent so that alignment is easy and thermal expansion can be controlled by the material, making it electrically insulating. Also excellent. Further, no warping due to stress occurs and molding is easy. Furthermore, if it is an alkali-free glass, there is no adverse effect due to surface elution of alkali.
Examples of the glass substrate having a thermal expansion coefficient of 10 ppm / ° C. or less include those having the following compositions.
_{SiO 2: 1~85wt%, Al 2} O 3: 0~40wt%, B 2 O 3: 0~50wt%, RO: 0~50wt% ( where, R represents alkaline earth metal elements; Mg, Ca, Sr Ba), R ′ ₂ O: 0 to 20 wt% (where R ′ is an alkali metal element; Li, Na, K, Rb, Cs), other components: 0 to 5 wt% (for example, As ₂ O ₃ , Sb ₂ O ₃ , ZrO, ZnO, P ₂ O ₅ , La ₂ O ₃ , PbO, F, Cl, etc.).

The material of the frame in the anisotropic conductive rubber sheet constituting the wafer batch contact board is preferably a material having high conductivity and a low coefficient of thermal expansion. Examples of such a frame material include Ni, Co, Fe, and alloys containing these. The effect of the present invention is the highest when the frame is entirely formed of a conductive material. However, in order to obtain the effect of the present invention, a frame having a conductive portion at least partially is used. Good. For example, even a frame in which a conductive material layer is formed on the surface of a non-metallic frame is effective.
The material of the dielectric material layer formed on the surface of the frame is not particularly limited. For example, Ba ₂ TiO ₄ (dielectric constant 2900 to 5000), Sr ₂ TiO ₄ , Rochelle salt (KNaC ₄ H ₄ O ₆ , dielectric constant 4000), TiO ₂ (dielectric constant 85), CuO (dielectric constant 12), NiO Etc.

  In the present invention, “a frame formed of a conductive thin plate has openings arranged therein, resin containing conductive particles is injected into the opening, and the conductive particles are moved toward the center by a magnetic field to form a frame. Forming an insulated anisotropic conductive rubber, and forming an anisotropic conductive rubber in which at least one portion corresponding to the GND pad or the power supply pad in the wiring board is connected to the frame without applying a magnetic field. A method for producing an anisotropic conductive rubber sheet, which includes a step of forming a dielectric material layer on the surface of the frame, is included.

[Example]
EXAMPLES Hereinafter, although this invention is described in detail with an Example and a comparative example, this invention is not limited at all by these.

Example 1
In Example 1, contact parts for wafer collective contact board, multilayer wiring board for wafer collective contact board, and anisotropic conductive rubber sheet were produced, and these were assembled to produce a wafer collective contact board.

Fabrication of Contact Parts for Wafer Batch Contact Board Next, a method for fabricating the contact parts for wafer batch contact board will be described with reference to FIGS.
First, as shown in FIG. 6A, a silicon rubber sheet 102 having a uniform thickness of 5 mm is placed on an aluminum plate 101 having a high flatness.
On the other hand, for example, after casting a polyimide precursor on a copper foil, the polyimide precursor is heated and dried and cured to bond a copper foil (thickness 18 μm) and a polyimide film (thickness 25 μm). A laminated film 103 having the above structure is prepared.
Note that the constituent material, forming method, thickness, and the like of the laminated film 103 can be selected as appropriate. For example, a polyimide film having a thickness of about 12 to 50 μm, an epoxy resin film, or a silicon rubber sheet having a thickness of about 0.1 to 0.5 mm can be used. Further, for example, a laminated film 103 can be formed by forming a copper film with a thickness of 18 μm on a polyimide film with a thickness of 25 μm by a sputtering method or a plating method. Further, a structure in which a plurality of conductive metals are sequentially formed on one surface of the film and a conductive metal layer having a laminated structure is formed on one surface of the film can be used.
Further, a thin Ni film may be formed between polyimide and Cu for the purpose of improving the adhesion between them and preventing film contamination, although not particularly shown.

  Next, a laminated film 103 having a structure in which a copper foil and a polyimide film are bonded together is adsorbed onto the silicon rubber sheet 102 in a state where the laminated film 103 is uniformly developed with the copper foil side down. At this time, by utilizing the property that the laminated film 103 is adsorbed on the silicon rubber sheet 102, the air layer is expelled and adsorbed so as not to cause wrinkles or deflection, and adsorbed in a uniformly developed state.

Next, a thermosetting adhesive 107 is thinly and evenly applied to the adhesive surface of the circular SiC ring 106 having a diameter of about 8 inches and a thickness of about 2 mm, and is placed on the laminated film 103. . Here, as the thermosetting adhesive 107, an adhesive that cures at a temperature 0 to 50 ° C. higher than the set temperature 80 to 150 ° C. of the burn-in test is used. In this example, Bond High Chip HT-100L (main agent: curing agent = 4: 1) (manufactured by Konishi Co., Ltd.) was used.
Further, a highly flat aluminum plate (having a weight of about 2.5 kg) is placed on the SiC ring 16 as a weight (not shown).

After finishing the above preparation process, the laminated film 103 and the SiC ring 106 are bonded by heating at a temperature (for example, 200 ° C., 2.5 hours) higher than the set temperature (80 to 150 ° C.) of the burn-in test (see FIG. 6 (b)).
At this time, since the thermal expansion coefficient of the silicon rubber sheet 102 is larger than the thermal expansion coefficient of the laminated film 103, the laminated film 103 adsorbed on the silicon rubber sheet 102 expands following the thermal expansion of the silicon rubber sheet 102. That is, since the thermal expansion of the silicon rubber sheet is larger than when the laminated film 103 is simply heated at a temperature equal to or higher than the set temperature (80 to 150 ° C.) of the burn-in test, the polyimide film is further expanded by this stress. In a state where the tension is large, the thermosetting adhesive 107 is cured, and the laminated film 103 and the SiC ring 106 are bonded. In addition, since the laminated film 103 on the silicon rubber sheet 102 is adsorbed in a uniformly developed state without wrinkles, deflection, or loosening, the laminated film 103 is applied to the SiC ring 106 without wrinkling, bending, or loosening. Can be glued. Furthermore, since the silicon rubber sheet 102 has high flatness and elasticity, the laminated film 103 can be evenly adhered to the adhesion surface of the SiC ring 106 evenly. The tension | tensile_strength of the polyimide film was 0.5 kg / cm < ² >.
In addition, when a thermosetting adhesive is not used, the film shrinks and the tension is weakened. In addition, since the curing time of the adhesive varies depending on the location, the SiC ring cannot be evenly and uniformly bonded to the bonding surface.

  After finishing the heating and bonding step, the product is cooled to room temperature and contracted to a state before heating. Thereafter, the laminated film 103 outside the SiC ring 106 is cut and removed along the outer periphery of the SiC ring 106 with a cutter, and an intermediate part is produced in which the laminated film 103 is stretched over the SiC ring 106 (FIG. 6C). .

  Next, a process of processing the intermediate part to form isolated bumps, isolated pads, and conductive patterns will be described.

  First, as shown in FIG. 7A, a Ni film (not shown) is formed on the copper foil 104 of the laminated film 103 having a structure in which the copper foil 104 and the polyimide film 105 produced above are bonded together by an electrolytic plating method. ) With a thickness of 0.2 to 0.5 μm.

Next, as shown in FIG. 7A, a bump hole 108 having a diameter of about 30 μm is formed at a predetermined position of the polyimide film 105 using an excimer laser.
Next, plasma treatment was applied to the inside of the pump hole 108 and the surface of the polyimide film 105 to remove a polyimide decomposition substance mainly composed of carbon, which was generated by laser processing and adhered to the bump hole and the periphery thereof.

Next, in order to prevent the copper foil 104 side from being plated, a protective film such as a resist is applied to the entire surface on the copper foil 104 side except for a part used as an electrode with a thickness of about 2 to 3 μm, Protect.
Immediately, one of the electrodes is connected to the copper foil 104, and electrolytic plating (current density: 0.1 to 60 A / dm ² ) of Ni or Ni alloy is performed on the polyimide film 105 side. The plating conditions can be appropriately selected. For example, a brightener, boric acid, nickel bromide, a PH adjuster, etc. can be added to the plating solution. Further, the hardness and surface state of the isolated bump can be changed by adjusting the content of the brightener in the plating solution. By electrolytic plating, the plating grows so as to fill the bump holes 108 shown in FIG. 7B, and then reaches the surface of the polyimide film 105 and isotropically spreads to grow into a substantially hemispherical shape with a hardness of 600 Hv or more. An isolated bump 109 made of Ni or a Ni alloy such as a Ni—Co alloy is formed.
Subsequently, an Au film having a thickness of 1 to 2 μm is formed on the surface of the isolated bump 109 by electrolytic plating (not shown). Thereafter, the protective film on the copper foil 104 side is peeled off.

Next, a resist is newly applied on the entire surface of the copper foil 104, and a resist pattern (not shown) is formed in a portion where an isolated pad and a conductive pattern (remaining pattern) are to be formed.
Next, as shown in FIG. 7C, the thin Ni film and the Cu film are etched with a ferric chloride aqueous solution or the like and rinsed well, and then the resist is peeled off to isolate the isolated pad 110 and the conductive pattern. A (remaining pattern) 111 is formed at the same time. At this time, as shown in FIG. 3, all the isolated GND pads 34 ′ and the conductive patterns 35 ′ are connected, and the GND common wiring in the multilayer wiring board 10 is connected via the anisotropic conductive rubber 21c and the GND pad 12c. And a conductive pattern 35 ′ (corresponding to 111 in FIG. 7C). Further, consideration was given to the area of the conductive pattern 111 as large as possible.

  Through the above process, the contact parts for the wafer batch contact board are completed.

Production of Multilayer Wiring Substrate FIG. 8 is a cross-sectional view of the principal part showing an example of the manufacturing process of the multilayer wiring substrate.
As shown in step (a) of FIG. 8, a glass substrate 201 (SiO ₂ : 60.0 mol%, Al ₂ O ₃ : 9.0 mol%, CaO having a size of 320 mm square and a thickness of 3 mm whose surface is polished flat) : 9.4 mol%, MgO: 9.3 mol%, ZnO: 9.3 mol%, PbO: 3.0 mol%) on one side), a Cr film is formed by sputtering to about 300 Å, Cu A Cr / Cu / Ni wiring layer 202 is formed by sequentially forming a film with a thickness of about 2.5 μm and a Ni film with a thickness of about 0.3 μm.
Here, Cr is provided for the purpose of strengthening the adhesion between glass and Cu. Ni is used for the purpose of preventing the oxidation of Cu, the purpose of strengthening the adhesion to the resist (the adhesion between Cu and resist is poor), and the reaction between Cu and polyimide causes polyimide to form at the bottom of the contact hole (via). It is provided for the purpose of preventing it from remaining.
In addition, the formation method of Ni is not limited to a sputtering method, You may form by the electroplating method. It is also possible to reduce the contact resistance by forming an Au film or the like on the Ni film by sputtering, electrolytic plating or electroless plating.

Next, as shown in step (b) of FIG. 8, a predetermined photolithography step (resist coating, exposure, development, etching) is performed, and the Cr / Cu / Ni wiring layer 202 is patterned to form the first layer. A wiring pattern 202a is formed.
Specifically, first, a resist (manufactured by Clariant: AZ350) is coated to a thickness of 3 μm, baked at 90 ° C. for 30 minutes, and the resist is exposed and developed using a predetermined mask to obtain a desired resist pattern (not shown). Z). Using this resist pattern as a mask, the Cr / Cu / Ni wiring layer 202 is etched using an etching solution such as a ferric chloride aqueous solution, then the resist is stripped using the resist stripping solution, washed with water and dried. Thus, the first wiring pattern 202a is formed.

Next, as shown in step (c) of FIG. 8, a polyimide polyimide film 203 is formed by applying a photosensitive polyimide precursor to the thickness of 10 μm on the first wiring pattern 202a using a spinner or the like. Then, a contact hole 204 is formed in the polyimide insulating film 203.
Specifically, the applied photosensitive polyimide precursor is baked at 80 ° C. for 30 minutes, exposed and developed using a predetermined mask, and the contact hole 204 is formed. Curing is performed at 350 ° C. for 4 hours in a nitrogen atmosphere to completely polymide the photosensitive polyimide precursor. The thickness of the polyimide insulating film 203 after curing was reduced to half (5 μm) after coating. Thereafter, the surface of the polyimide is roughened by plasma treatment to increase the adhesion with the second wiring layer formed in the next step, and the polyimide decomposition product, developer, etc. generated by laser irradiation in the contact hole 204 Organic substances such as residue are oxidized and removed.

Next, as shown in step (d) of FIG. 8, a Cr / Cu / Ni wiring layer 205 is formed in the same manner as in step (a).
Next, as shown in step (e) of FIG. 8, the Cr / Cu / Ni wiring layer 205 is patterned in the same manner as in the step (b) to form a second wiring pattern 205a.

Next, the above-described steps (c) to (e) are repeated in the same manner to sequentially form a second layer polyimide insulating film and contact holes, and a third layer wiring pattern, thereby forming a three-layer glass multilayer wiring board. Obtained (not shown).
Next, for the purpose of preventing oxidation and improving the electrical contact property with the anisotropic conductive rubber only in the contact terminal portion (power supply pad, ground pad and signal pad portion) in the third layer wiring pattern. A 0.3 μm thick Au film was formed on a 1 μm thick Ni film by an electroless plating method (not shown).

  Finally, polyimide as an insulating film was applied on the substrate (not shown), and the protective terminal insulating film was formed by removing the polyimide at the contact terminal portion to obtain a multilayer wiring board for wafer batch contact board.

Anisotropic conductive rubber sheet prepared Next, as shown in FIG. 3, open the sequence formed in the metal frame 22 made of Ni thin plate 50~100μm thickness, in the opening portion, a printing method a silicon resin containing metal particles The portions of the anisotropic conductive rubber 21c and 21b corresponding to the GND pad 12c and the signal pad 12b in the multilayer wiring board 10 form portions 21c ′ and 21b ′ in which metal particles are moved to the center by a magnetic field. The anisotropic conductive rubber sheet 20 having a structure in which the anisotropic conductive rubber 21a corresponding to all the power supply pads 12a was connected to the metal frame without applying a magnetic field was produced. As a result, an anisotropic conductive rubber sheet 20 having a structure for connecting the power common wiring in the multilayer wiring board 10 and all the power pads 12a was obtained.
In addition, the metal frame which consists of Ni thin plate used what formed the NiO dielectric material layer by thermally oxidizing the surface beforehand.

Assembling process The anisotropic conductive rubber sheet 20 manufactured as described above was bonded to a predetermined position of the multilayer wiring board 10 for wafer batch contact board, and the contact component 30 was further bonded to complete the wafer batch contact board.
As a result, as shown in FIG. 3, a bypass capacitor was formed between the metal frame 22 and the conductive pattern 35 (between the power supply common line and the GND common line).

Burn-in test After aligning the position of the electrode on the wafer and the isolated bump of the contact part with a chuck, the wafer was placed in the burn-in apparatus and tested in an operating environment of 125 ° C. The evaluation target was an 8-inch wafer in which 400 chips of 64MDRAM were formed. For comparison, in the above-described embodiment, (1) the metal frame 22 and the power supply pad 12a are not connected, (2) the conductive patterns 35 'and 35 are not formed, and (3) the metal frame 22 is used. A wafer batch contact board was prepared in the same manner as in Example 1 except that no bypass capacitor was formed between the conductive pattern 35 ′ and the conductive pattern 35 ′ (Comparative Example 1).
As a result, when the evaluation was performed using the substrate of Comparative Example 1, only the operation of 10 MHz could be confirmed, but the operation using the substrate of Example 1 and the operation of 20 MHz could be confirmed simultaneously for all the chips. Thus, according to the present invention, a substrate that is more resistant to noise than the conventional substrate can be produced. Moreover, the high frequency characteristics could be maximized without changing the current structure.
It should be noted that the operation of 20 MHz was also confirmed for all chips simultaneously for hot water using the substrate of Example 1, for example, a microprocessor and an ASIC.
Further, the TiO ₂ dielectric layer in the capacitor was not cracked by heat or deteriorated in performance by heat.

(Example 2)
The power supply and GND are switched in the first embodiment, and in FIG. 3, (1) the metal frame 22 and the GND pad 12c are connected, and (2) the conductive pattern 35 ′ and the power supply pad 12a are connected. Thus, a wafer batch contact board was manufactured and a burn-in test was performed.
As a result, the operation of 20 MHz was confirmed at the same time for all the chips.

(Example 3)
In Example 1, except that (1) the metal frame 22 and the power supply pad 12a were not connected, a wafer batch contact board was fabricated and a burn-in test was performed in the same manner as in Example 1.
As a result, the operation of 20 MHz was confirmed at the same time for all the chips.

Example 4
In Example 1, except that (2) the conductive patterns 35 'and 35 were not formed, a wafer batch contact board was produced and a burn-in test was performed in the same manner as in Example 1.
As a result, the operation of 20 MHz was confirmed at the same time for all the chips.

(Example 5)
A wafer batch contact board was prepared in the same manner as in Example 1 except that a TiO or barium titanate (Ba ₂ TiO ₄ ) ferroelectric film was formed on the surface of the metal frame 22 instead of NiO in Example 1. A burn-in test was conducted.
As a result, the operation of 20 MHz was confirmed at the same time for all the chips.
The barium titanate dielectric layer was not cracked by heat or deteriorated in performance by heat.

(Example 6)
In Example 1, a wafer batch contact board was prepared in the same manner as in Example 1 except that a conductive pattern was also formed on the surface of the polyimide film 105 on the isolated bump 109 side, and a bypass capacitor was formed on the contact component. A burn-in test was conducted.
As a result, the operation of 20 MHz was confirmed at the same time for all the chips.

(Example 7)
In Example 1, as shown in FIG. 5, the conductive pattern 111 is formed at a ratio of one to all the isolated GND pads, and this isolated conductive pattern 37 is connected to each isolated GND pad. Except for this, a wafer batch contact board was fabricated in the same manner as in Example 1, and a burn-in test was performed.
As a result, the operation of 20 MHz was confirmed at the same time for all the chips.

(Example 8)
In Example 1, a wafer batch contact board was produced and a burn-in test was performed in the same manner as in Example 1 except that both the metal frame 22 and the conductive pattern 35 ′ were connected to the power supply wiring on the wiring board.
As a result, the operation of all non-defective chips on the wafer was confirmed as in Example 1.

Example 9
In Example 1, a wafer batch contact board was prepared and burn-in test was performed in the same manner as in Example 1 except that both the metal frame 22 and the conductive pattern 35 ′ were connected to the GND wiring on the wiring board.
As a result, the operation of all non-defective chips on the wafer was confirmed as in Example 1.

  In addition, this invention is not limited to the said Example, It can deform | transform suitably.

For example, in addition to the burn-in test described in the section of the prior art, the wafer batch contact board of the present invention is a part of product inspection (electrical property test) conventionally performed by a probe card, and wafer level batch CSP inspection. Can also be used for The multilayer wiring board for wafer batch contact board of the present invention is particularly suitable for test burn-in.
The wiring layers in the multilayer wiring board may have 2 to 10 layers or more. The multilayer wiring board used for the burn-in board has 3 to 4 layers for memory, 5 to 6 layers for logic, and about 10 layers for hybrid.

[Effect of the invention]
According to the present invention, it is possible to provide a wafer batch contact board that is resistant to high-frequency noise and has improved high-frequency characteristics, and a method for manufacturing the same.
Further, it is possible to provide a wafer batch contact board that can be easily manufactured without increasing costs and processes, and a method for manufacturing the same.

It is sectional drawing which shows typically one specific example of the wafer batch contact board concerning this invention. It is sectional drawing which shows typically a specific example of a wafer lump contact board. It is principal part sectional drawing which shows typically one specific example of the wafer batch contact board concerning this invention. It is a top view which shows typically a specific example of the wafer batch contact board concerning this invention. It is principal part sectional drawing which shows typically the other specific example of the wafer batch contact board concerning this invention. It is sectional drawing which shows a part of manufacturing process of the contact component concerning one Example of this invention. It is principal part sectional drawing which shows a part of manufacturing process of the contact component concerning one Example of this invention. It is principal part sectional drawing for demonstrating the manufacturing process of the multilayer wiring board for wafer collective contact boards concerning one Example of this invention. It is sectional drawing which shows typically the specific example of the conventional wafer collective contact board.

DESCRIPTION OF SYMBOLS 10 Wiring board 20 Anisotropic conductive rubber sheet 21 Anisotropic conductive rubber 22 Frame 30 Contact component 31 Ring 32 Insulating film 33 Isolated bump 34 Isolated pad 35 Conductive pattern 40 Silicon wafer 101 Aluminum plate 102 Silicon rubber sheet 103 Laminated film 104 Copper Foil 105 Polyimide Film 106 SiC Ring 107 Thermosetting Adhesive 108 Bump Hole 109 Isolated Bump 110 Isolated Pad 111 Conductive Pattern 201 Glass Substrate 202 Wiring Layer 202a First Wiring Pattern 203 Insulating Film 204 Contact Hole 205 Wiring Layer 205a Second layer wiring pattern

Claims (8)

A wafer batch contact board used to collectively test a plurality of semiconductor devices formed on a wafer,
An insulating film stretched over a ring, an isolated pad formed on one surface of the insulating film , and formed on the other surface of the insulating film in a one-to-one correspondence with the isolated pad and An isolated bump connected to an isolated pad, and the isolated pad and the isolated bump are an isolated power bump connected to the isolated power pad, an isolated GND bump connected to the isolated GND pad, and an isolated signal pad, respectively. A contact component for a wafer batch contact board having an isolated signal bump connected to
The wiring laminated through an insulating layer, and has a structure in which connecting the wires vertically through the formed contact holes in the insulating layer, the wiring has power wiring, GND wiring, the signal wiring, A wiring substrate for a wafer batch contact board having a power pad, a GND pad, and a signal pad, each electrically connected to the power wiring, the GND wiring, and the signal wiring ;
An anisotropic conductive rubber sheet for electrically connecting the wiring board and the contact component;
One surface of the insulating film in the contact part, the other surface, or on one surface and the other surface, respectively, the isolated pad, the isolated bumps or avoiding the isolation pad and the isolated bumps, conductive forming a sexual patterns, the conductive patterns, respectively, the isolated GND pad, the isolated GND bumps, or by connecting the isolated GND pad and the isolated GND bump, the conductive and the GND wiring in the wiring substrate Wafer contact board characterized by having a structure in which a conductive pattern is electrically connected. A wafer batch contact board used to collectively test a plurality of semiconductor devices formed on a wafer,
An insulating film stretched over a ring, an isolated pad formed on one surface of the insulating film , and formed on the other surface of the insulating film in a one-to-one correspondence with the isolated pad and An isolated bump connected to an isolated pad, and the isolated pad and the isolated bump are an isolated power bump connected to the isolated power pad, an isolated GND bump connected to the isolated GND pad, and an isolated signal pad, respectively. A contact component for a wafer batch contact board having an isolated signal bump connected to
The wiring laminated through an insulating layer, and has a structure in which connecting the wires vertically through the formed contact holes in the insulating layer, the wiring has power wiring, GND wiring, the signal wiring, A wiring substrate for a wafer batch contact board having a power pad, a GND pad, and a signal pad, each electrically connected to the power wiring, the GND wiring, and the signal wiring ;
An anisotropic conductive rubber sheet for electrically connecting the wiring board and the contact component;
One surface of the insulating film in the contact part, the other surface, or on one surface and the other surface, respectively, the isolated pad, the isolated bumps or avoiding the isolation pad and the isolated bumps, conductive forming a sexual patterns, the conductive patterns, respectively, the isolated power supply pad, the isolated power source bump, or by connecting the isolated power supply pads and said isolated power supply bump, the conductive and the power supply wiring in the wiring substrate Wafer contact board characterized by having a structure in which a conductive pattern is electrically connected. A wafer batch contact board used to collectively test a plurality of semiconductor devices formed on a wafer,
An insulating film stretched over a ring, an isolated pad formed on one surface of the insulating film , and formed on the other surface of the insulating film in a one-to-one correspondence with the isolated pad and An isolated bump connected to an isolated pad, and the isolated pad and the isolated bump are an isolated power bump connected to the isolated power pad, an isolated GND bump connected to the isolated GND pad, and an isolated signal pad, respectively. A contact component for a wafer batch contact board having an isolated signal bump connected to
The wiring laminated through an insulating layer, and has a structure in which connecting the wires vertically through the formed contact holes in the insulating layer, the wiring has power wiring, GND wiring, the signal wiring, A wiring substrate for a wafer batch contact board having a power pad, a GND pad, and a signal pad, each electrically connected to the power wiring, the GND wiring, and the signal wiring ;
An anisotropic conductive rubber sheet for electrically connecting the wiring board and the contact component;
On one surface and the other surface of the insulating film in the contact part, respectively, to avoid the isolated pad and the isolated bumps, forming a conductive pattern,
By connecting the isolated power pad and the conductive pattern formed on the one surface, by connecting the isolated GND bump and the conductive pattern formed on the other surface,
The conductive pattern formed on the one surface is electrically connected to the power supply wiring on the wiring substrate, and the conductive pattern formed on the other surface is electrically connected to the GND wiring on the wiring substrate. ,
A wafer batch contact board , wherein a bypass capacitor is formed between the conductive pattern formed on the one surface and the conductive pattern formed on the other surface . A wafer batch contact board used to collectively test a plurality of semiconductor devices formed on a wafer,
An insulating film stretched over a ring, an isolated pad formed on one surface of the insulating film , and formed on the other surface of the insulating film in a one-to-one correspondence with the isolated pad and An isolated bump connected to an isolated pad, and the isolated pad and the isolated bump are an isolated power bump connected to the isolated power pad, an isolated GND bump connected to the isolated GND pad, and an isolated signal pad, respectively. A contact component for a wafer batch contact board having an isolated signal bump connected to
The wiring laminated through an insulating layer, and has a structure in which connecting the wires vertically through the formed contact holes in the insulating layer, the wiring has power wiring, GND wiring, the signal wiring, A wiring substrate for a wafer batch contact board having a power pad, a GND pad, and a signal pad, each electrically connected to the power wiring, the GND wiring, and the signal wiring ;
An anisotropic conductive rubber sheet for electrically connecting the wiring board and the contact component;
On one surface and the other surface of the insulating film in the contact part, respectively, to avoid the isolated pad and the isolated bumps, forming a conductive pattern,
By connecting the isolated GND pad and the conductive pattern formed on the one surface, by connecting the isolated power bump and the conductive pattern formed on the other surface,
The conductive pattern formed on the one surface is electrically connected to the GND wiring on the wiring board, and the conductive pattern formed on the other surface is electrically connected to the power supply wiring on the wiring board. ,
A wafer batch contact board , wherein a bypass capacitor is formed between the conductive pattern formed on the one surface and the conductive pattern formed on the other surface . 5. The bypass capacitor according to claim 3, wherein the bypass capacitor has a structure formed at a ratio of one per chip by forming an isolated conductive pattern at a ratio of one for each isolated pad and each isolated bump. Wafer batch contact board. A wafer batch contact board used to collectively test a plurality of semiconductor devices formed on a wafer,
An insulating film stretched over a ring, an isolated pad formed on one surface of the insulating film , and formed on the other surface of the insulating film in a one-to-one correspondence with the isolated pad and An isolated bump connected to an isolated pad, and the isolated pad and the isolated bump are an isolated power bump connected to the isolated power pad, an isolated GND bump connected to the isolated GND pad, and an isolated signal pad, respectively. A contact component for a wafer batch contact board having an isolated signal bump connected to
The wiring laminated through an insulating layer, and has a structure in which connecting the wires vertically through the formed contact holes in the insulating layer, the wiring has power wiring, GND wiring, the signal wiring, A wiring substrate for a wafer batch contact board having a power pad, a GND pad, and a signal pad, each electrically connected to the power wiring, the GND wiring, and the signal wiring ;
An anisotropic conductive rubber sheet for electrically connecting the wiring board and the contact component;
Forming two conductive patterns insulated from each other on one side or the other side of the insulating film;
By connecting the one conductive pattern and the isolated GND pad or the isolated GND bump, and connecting the other conductive pattern and the isolated power pad or the isolated power bump,
A wafer batch comprising a structure in which the GND wiring in the wiring board is connected to the one conductive pattern in the insulating film, and the power wiring in the wiring board is connected to the other conductive pattern. Contact board . A wafer batch contact board used to collectively test a plurality of semiconductor devices formed on a wafer,
An insulating film stretched over a ring, an isolated pad formed on one surface of the insulating film , and formed on the other surface of the insulating film in a one-to-one correspondence with the isolated pad and An isolated bump connected to an isolated pad, and the isolated pad and the isolated bump are an isolated power bump connected to the isolated power pad, an isolated GND bump connected to the isolated GND pad, and an isolated signal pad, respectively. A contact component for a wafer batch contact board having an isolated signal bump connected to
The wiring laminated through an insulating layer, and has a structure in which connecting the wires vertically through the formed contact holes in the insulating layer, the wiring has power wiring, GND wiring, the signal wiring, A wiring substrate for a wafer batch contact board having a power pad, a GND pad, and a signal pad, each electrically connected to the power wiring, the GND wiring, and the signal wiring ;
An anisotropic conductive rubber sheet for electrically connecting the wiring board and the contact component;
The surface of the anisotropic conductive rubber sheet side of the insulating film in the contact parts, to avoid the isolated pad, forming a conductive pattern, the conductive pattern, separately provided in the peripheral portion to the above The GND wiring and the conductive pattern on the wiring board are electrically connected through the electrically connected portion by the anisotropic conductive rubber and the GND pad of the wiring board provided in the peripheral portion separately from the above. A wafer batch contact board characterized by having a structure. Using the wafer batch contact board according to any one of claims 1 to 7, a method of inspecting a semiconductor device, characterized in that collectively performed testing of a number formed semiconductor devices on a wafer in a state of wafer.

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