JP4640738B2 - Contact component for wafer batch contact board and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a contact part which is a component part of a wafer batch contact board used for collectively inspecting (testing) semiconductor devices formed on a wafer in the state of a wafer, a manufacturing method thereof, and the like.
[0002]
[Prior art]
Inspection of many semiconductor devices formed on a wafer is roughly classified into product inspection (electrical characteristic test) using a probe card and burn-in test which is a reliability test performed thereafter.
The burn-in test is one of screening tests performed to remove a semiconductor device having an inherent defect or a device causing a failure depending on time and stress from manufacturing variations. While the probe card inspection is an electrical characteristic test of the manufactured device, the burn-in test is a thermal acceleration test.
[0003]
The burn-in test is a normal method (one-chip burn-in system) in which a wafer is cut into chips by dicing and packaged one by one after an electrical characteristic test performed for each chip by a probe card. Then, cost is not feasible. Therefore, development and practical application of a wafer batch contact board (burn-in board) for performing a burn-in test on a plurality of semiconductor devices formed on the wafer all at once are being promoted (Japanese Patent Laid-Open No. 7-231019). . Wafer batch burn-in system using wafer batch contact board is not only highly feasible in terms of cost, but also an important technology to enable the latest technological flow such as bare chip shipment and bare chip mounting. .
[0004]
The details of the burn-in test are shown below.
Static burn-in is a burn-in test in which a power supply voltage is applied at or above the rated voltage at a high temperature and current is passed through the device to apply temperature and voltage stress to the device. .
The dynamic burn-in is a burn-in test that is performed while applying a power supply voltage that is rated or exceeding that at a high temperature and applying a signal close to actual operation to the input circuit of the device.
Monitored burn-in is a burn-in test that has the function of not only applying a signal to the input circuit of a device but also monitoring the characteristics of the output circuit in dynamic burn-in.
The test burn-in is a burn-in test that can perform pass / fail judgment and evaluation of a device under test.
[0005]
The wafer batch contact board is different from the conventional probe card in that the wafer batch contact board is used for the batch wafer inspection and the heating test, and the required level is high. When the wafer batch contact board is put into practical use, in addition to the burn-in test (including the case where the electrical characteristic test is performed) described above, a part of the product inspection (electrical characteristic test) which has been conventionally performed by the probe card is performed. It is also possible to perform the wafer batch.
[0006]
FIG. 11 shows a specific example of the wafer batch contact board.
In the wafer batch contact board, as shown in FIG. 11, a contact component 30 is fixed on a multilayer wiring board for wafer batch contact board (hereinafter referred to as a multilayer wiring board) 10 via an anisotropic conductive rubber sheet 20. It has a structure.
The contact component 30 takes charge of the contact portion that is in direct contact with the device under test. In the contact component 30, an isolated bump 33 is formed on one surface of the insulating film 32, and an isolated pad 34 is formed on the other surface in a one-to-one correspondence with the isolated bump 33. The insulating film 32 is stretched over a ring 31 having a low coefficient of thermal expansion in order to avoid misalignment due to thermal expansion. The isolated bumps 33 are electrodes formed on the periphery or center line of each semiconductor device (chip) on the wafer 40 (about 600 to 1000 pins per chip, and the number of electrodes obtained by multiplying this number by the number of chips) Corresponding to the same number as the electrodes.
The multilayer wiring board 10 has wiring and pad electrodes for applying a predetermined burn-in test signal or the like to each bump 33 isolated on the insulating film 32 via an isolated pad 34 on the insulating substrate. The multilayer wiring board 10 has a multilayer wiring structure because wiring is complicated. The multilayer wiring board 10 uses an insulating substrate having a low thermal expansion coefficient in order to avoid a connection failure due to a positional shift with the isolated pad 34 on the insulating film 32 due to thermal expansion.
The anisotropic conductive rubber sheet 20 is a connecting component that electrically connects a pad electrode (not shown) on the multilayer wiring board 10 and an isolated pad 34 on the insulating film 32, and is perpendicular to the main surface. It is a sheet-like connecting component having an elastic body (anisotropic conductive rubber made of silicon resin in which metal particles are embedded in portions corresponding to the isolated pad 34 and the pad electrode) having conductivity only in the direction. The anisotropic conductive rubber sheet 20 is in contact with an isolated pad 34 on the insulating film 32 by a projection (not shown) of the anisotropic conductive rubber formed so as to protrude from the surface of the sheet. Both the flexibility and the flexibility of the insulating film 32 absorb the unevenness on the surface of the semiconductor wafer 40 and the variation in the height of the isolated bump 33, and the like. The isolated bump 33 is securely connected.
[0007]
Each semiconductor device (chip) is formed with electrodes (power supply electrode, ground electrode, I / O electrode) to be a power supply terminal, a ground terminal, and a signal input / output terminal (I / O terminal) of the integrated circuit, and the semiconductor chip. Isolated bumps 33 of the wafer batch contact board are formed and connected in a one-to-one relationship corresponding to all the electrodes. In the multilayer wiring in the wafer batch contact board, the power supply wiring, the ground wiring, and the signal input / output wiring (I / O wiring) are made common for the purpose of reducing the number of wirings.
[0008]
A method for manufacturing a contact component is shown below.
FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the contact component.
First, as shown in FIG. 4A, after casting a polyimide precursor to a thickness of about 25 μm on a copper foil 104 having a thickness of about 18 μm, the polyimide precursor is heated and dried and cured to obtain a copper foil 104. And a laminated film 103 having a structure in which a polyimide film 105 is bonded.
Next, as shown in FIG. 4A, a silicon rubber sheet 102 having a uniform thickness of 5 mm is placed on an aluminum plate 101 with high flatness. On this silicon rubber sheet 102, the laminated film 103 is adsorbed in a state where the laminated film 103 is uniformly developed with the copper foil 104 side down.
Next, as shown in FIG. 4 (1), the thermosetting adhesive 107 is thinly and uniformly (50 to 100 μm) on the bonding surface of a circular SiC ring (ceramic ring) 106 having a diameter of about 8 inches and a thickness of about 2 mm. ) Apply. Here, as a thermosetting adhesive, what is hardened | cured at 0-50 degreeC higher than the preset temperature (80-150 degreeC) of a burn-in test is used.
[0009]
Next, as shown in FIG. 4 (2), an SiC ring 106 coated with a thermosetting adhesive 107 on the bonding surface is placed on the laminated film 103, and an aluminum plate (heavy plate) with high flatness is placed on the SiC ring 106. About 2.5 kg) is placed as a weight plate 112.
[0010]
After finishing the above preparation process, the laminated film 103 and the SiC ring 106 are bonded by heating at a temperature (for example, 200 ° C., 2.5 hours) higher than the set temperature (80 to 150 ° C.) of the burn-in test (see FIG. 4 (3)).
[0011]
Next, as shown in FIG. 5 (1), the heat-bonded step is cooled to room temperature and contracted to a state before heating. The laminated film 103 outside the SiC ring 106 is cut and removed along the outer periphery of the SiC ring 106 with a cutter.
[0012]
Next, as shown in FIG. 5B, a bump hole 108 having a diameter of about 30 μmφ is formed at a predetermined position of the polyimide film 105 in the laminated film 103 by using an excimer laser.
[0013]
Next, after protecting the surface of the copper foil 104 from being plated, one of the electrodes for plating is connected to the copper foil 104 to perform electroplating of Ni. As shown in FIG. 5 (3), after the plating grows so as to fill the bump holes 108, when it reaches the surface of the polyimide film 105, it spreads isotropically and grows into a substantially hemispherical shape. A bump 109 is formed.
[0014]
Next, a resist is applied onto the copper foil 104, a resist pattern is formed by exposure and development (not shown), and the copper foil 104 is etched using the resist pattern as a mask, as shown in FIG. An isolated pad 110 is formed. FIG. 13 shows a plan view. In FIG. 13, the same reference numerals as in FIG.
A contact component is manufactured through the above steps.
As described above, the contact parts for the wafer batch contact board are affected by the thermal expansion of the polyimide film even at a burn-in temperature (for example, about 120 ° C.) by sticking to a ceramic ring having a thermal expansion coefficient close to that of silicon while maintaining tension. Instead, it is designed to follow the thermal expansion and contraction of the ceramic ring.
[0015]
[Problems to be solved by the invention]
However, in the above method, since the laminated film 103 having the structure in which the copper foil 104 and the polyimide film 105 are bonded together is heated and bonded to the SiC ring 106 in a thermally expanded state, after bonding, the laminated film 103 is brought to room temperature. When returned, the contraction tension of the copper foil 104 is applied toward the center of the SiC ring 106. At this time, the SiC ring 106 contracts by about 50 to 100 μm in the radial direction with respect to the ring diameter of 8 inches (200 mm) due to the tension of the copper foil 104.
Thereafter, when the copper foil 104 is etched to form the isolated pad 110, most of the copper foil 104 is removed by etching (see FIG. 13), so that the contraction tension applied to the center direction by the copper foil 104 is reduced. Once opened, the SiC ring 106 attempts to return to its original dimensions. At this time, although the tension of the polyimide film 105 remains, it is much smaller than the tension of the copper foil 104, so that the SiC ring 106 returns almost to its original dimension. As a result, the flexible polyimide film 105 follows the movement of the SiC ring 106 returning to its original size, so that the positions of the isolated pad 110 and the isolated bump 109 on the polyimide film 105 are shifted outward by the amount of expansion of the ring. There is a problem that the positional accuracy of the isolated pad 110 and the isolated bump 109 deteriorates.
In particular, in recent years, the pitch of semiconductor devices (chips) on wafers has been narrowed (160 μm or less), and the requirement for positional accuracy of isolated bumps has become strict (within ± 10 μm), and this requirement can be met. It was difficult. Specifically, there is a possibility that a short circuit occurs during the burn-in test due to the positional deviation between the isolated bump and the electrode on the wafer, causing a failure that damages the chip on the wafer.
Further, the positional deviation of the isolated pad may cause a positional deviation with the anisotropic conductive rubber for connection to the multilayer wiring board, which may cause a defective product as a wafer batch contact board.
[0016]
In order to solve the above-mentioned problem, a position shift due to the SiC ring 106 before and after etching the copper foil 104 is predicted in advance, and the position of the isolated pad and the isolated bump is reduced. A method of producing contact parts using laser processing data and using these data is conceivable.
However, in this method, there is a case where the tension of the laminated film 103 is not uniform at the time when the laminated film 103 is attached to the SiC ring 106 (this is due to the unevenness of the way of attachment, the thickness of the copper foil, etc. This is because non-uniformity or the like causes non-uniform tension in the partial portion), and it is not possible to accurately predict the displacement due to the ceramic ring before and after etching the copper foil. The position of isolated pad and bump formation differs from device to device, and the amount of displacement varies depending on the position of isolated pad and bump formation. It is difficult and practically impossible to produce laser processing data for use.
[0017]
In addition, the isolated pads and the isolated bumps must be formed in a one-to-one correspondence with the electrodes on each chip on the wafer. 14 (1), if the notch 120 is not made in the polyimide film 105 between the isolated pads 110 formed on the polyimide film 105, it corresponds to variations in the height of the electrodes, isolated pads and isolated bumps on the wafer. Therefore, the flexibility may be impaired.
However, in this case, as shown in FIG. 14B, when the isolated pad 110 is formed by etching the copper foil, the cut 120 is widened, and the positional accuracy of the isolated pad and the isolated bump is further deteriorated.
[0018]
Furthermore, when performing a wafer batch burn-in test using the wafer batch contact board described above, all the chips on the wafer are measured simultaneously, so there is a great deal of noise generated during switching of each chip, and this noise waveform is input. It became clear that there was a problem due to malfunctions (errors) caused by overlapping with the pulse signal. For this reason, in the conventional wafer batch contact board, a power supply voltage can be applied only up to about 10 MHz, and there is a problem that high frequency characteristics are not sufficient.
[0019]
The present invention has been made under such a background, and a first object of the present invention is to provide a contact component for a wafer batch contact board in which the positional accuracy of isolated pads and isolated bumps is further improved, a manufacturing method thereof, and the like. .
Further, the present invention provides a wafer batch contact board contact component that can be easily manufactured without increasing costs and processes, and a method for manufacturing the contact component for a wafer batch contact board that further improves the positional accuracy of the isolated pads and bumps. Second purpose.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured as follows.
[0021]
(Configuration 1) A contact component that takes charge of a contact portion in a wafer batch contact board used to collectively test a plurality of semiconductor devices formed on a wafer,
An insulating film stretched over a ring; an isolated pad formed on one surface of the insulating film; and the isolated film formed on the other surface of the insulating film in a one-to-one correspondence with the isolated pad In contact parts for wafer batch contact boards having isolated bumps connected to pads,
A contact part for a wafer collective contact board, wherein a remaining pattern is formed on the front surface and / or back surface of the insulating film so as to avoid at least one of the isolated pad and / or the isolated bump.
[0022]
(Structure 2) The contact part for a wafer collective contact board according to Structure 1, wherein the remaining pattern is formed so that a positional shift of the isolated pad and / or the isolated bump is 5 ppm% or less.
[0023]
(Configuration 3) A wafer batch contact board used to collectively test a plurality of semiconductor devices formed on a wafer,
Contact parts for wafer batch contact board according to Configuration 1 or 2,
A multilayer wiring board for a wafer collective contact board having a structure in which wirings are stacked through an insulating layer and upper and lower wirings are connected through contact holes formed in the insulating layer;
A wafer batch contact board comprising an anisotropic conductive rubber sheet for electrically connecting the multilayer wiring board and the contact component.
[0024]
(Configuration 4) An insulating film stretched over a ring, an isolated pad formed on one surface of the insulating film, and formed on the other surface of the insulating film in a one-to-one correspondence with the isolated pad And a method of manufacturing a contact component for a wafer batch contact board having an isolated bump connected to the isolated pad,
A contact component for a wafer batch contact board, comprising a step of forming a remaining pattern on one surface and / or the other surface of the insulating film while avoiding at least one isolated pad and / or isolated bump. Manufacturing method.
[0025]
(Configuration 5) A step of preparing a laminated film having a structure in which an insulating film and a conductive layer are laminated,
When pasting the laminated film on the ring at a predetermined temperature, the step of pasting the laminated film with a tension that causes the laminated film to shrink by the conductive layer when returned to normal temperature;
Forming a bump hole at a predetermined position of the insulating film in the laminated film;
Electroplating by connecting one of the electrodes for plating to the conductive layer, and growing a plating in at least the bump hole to form an isolated bump; and
The conductive layer is selectively etched to form isolated pads at positions corresponding to the bumps on the insulating film, and at least one of the isolated pads is avoided on the insulating film, leaving a remaining pattern. Forming, and
A method of manufacturing a contact component according to Configuration 4, characterized by comprising:
[0026]
(Configuration 6) A step of forming a conductive layer on the surface of the insulating film on the side where the isolated bump is formed;
Avoiding at least one of the isolated bumps on the surface of the insulating film on which the isolated bumps are to be formed, and forming a remaining pattern; and
A method of manufacturing a contact component according to the configuration 5, characterized by comprising:
[0027]
[Action]
As in Configuration 1, in the method for producing contact parts according to the present invention, since the pattern is formed on the insulating film, the isolated pad is formed by etching the conductive layer such as copper foil. Since the release of tension due to etching of the conductive layer is extremely small, the elongation of the insulating film in the direction of the outer peripheral portion is extremely small, and the deterioration of the positional accuracy of isolated pads and isolated bumps caused by releasing the tension of the conductive layer is extremely small. Therefore, the position accuracy of the isolated pad and the isolated bump is high, and a highly accurate contact component can be obtained.
That is, in the present invention, since the tension of the polyimide film is very weak compared to the restoring force to return to the original of the SiC ring, a remaining pattern is formed on the polyimide film. , Against the restoring force of the ceramic ring.
In the present invention, a pattern can be formed on the surface of the insulating film on the isolated bump forming side. In this case, the thickness of the remaining pattern on the surface of the insulating film on the side where the isolated bump is formed is preferably a thickness that does not exceed the height of the isolated bump, and should be sufficiently lower than the height of the isolated bump. Further preferred. By forming the pattern on the front and back of the insulating film in this way, the positional accuracy of the isolated pad and the isolated bump can be further increased.
[0028]
As in Configuration 2, it is preferable to form the remaining pattern so that the positional deviation of the isolated pad and / or the isolated bump is 5 ppm or less. Specifically, for example, it is preferable to form the remaining pattern so that the positional deviation of the isolated pad and / or the isolated bump is 10 μm or less with respect to the ring diameter of 8 inches (about 200 mm). 8 μm or less is more preferable, and 5 μm or less is more preferable.
[0029]
If the layout pattern allows, as shown in FIG. 1, only the periphery of each isolated pad 34 of the conductive layer formed on the entire surface of the insulating film 32 is etched and the other portions are left as shown in FIG. With the pattern 35, the elongation due to the restoring force of the ring is minimized.
In the case of FIG. 1, it is preferable to make the area of the remaining pattern 35 as large as possible.
[0030]
When the mode of the remaining pattern is a ring shape as shown in FIG. 2 (1), the ring-shaped remaining pattern 35 is evenly opposed to the restoring force of the ring 31, so that it is inside the ring-shaped remaining pattern 35. The insulating film 32 is prevented from stretching, and the position accuracy of the isolated pad 34 and the isolated bump (not shown) can be maintained. Further, the ring-shaped remaining pattern 35 as shown in FIG. 2A is preferable in that it has the fewest restrictions on the layout of the isolated pads 34 and the isolated bumps and can cope with the progress of narrow pitch.
The ring-shaped remaining pattern has an effect of countering the restoring force of the ring 31 even when the part of the ring-shaped remaining pattern 35 is interrupted as shown in FIG. 2 (2) or (3).
In the case of FIGS. 2 (1) to 2 (3), the larger the ring-shaped remaining pattern 35, the better the positional accuracy. In particular, the cases (1) and (3) are more preferable because they can withstand the tensile tension almost uniformly in the radial direction of the ring.
[0031]
When the pattern of the remaining pattern is a lattice shape as shown in FIG. 3 (1), since the lattice-shaped remaining pattern 35 counteracts the restoring force of the ring 31, the elongation of the insulating film 32 is suppressed. Therefore, the positional accuracy of the isolated pad 34 and the isolated bump (not shown) can be maintained. Furthermore, the lattice-like remaining pattern 35 as shown in FIG. 3A is preferable because it can easily correspond to the arrangement of the chip of the device.
In the case of the lattice-like remaining pattern, the end of the lattice-like pattern 35 may overlap the ring 31 as shown in FIG. In this case, the elongation of the ring itself can be suppressed, which is preferable.
In the case of a lattice-like remaining pattern, there are a mode in which a plurality of isolated pads 34 as shown in FIG. 3 (3) are surrounded by blocks, a mode in which each isolated pad 34 is surrounded as shown in FIG. 3 (4), and the like. It is done.
In the case of FIG. 3 (3), in order to cope with the sandwiching pitch, a cut 38 can be made in the insulating film 32 between the isolated pads 34 to provide flexibility in the height direction.
[0032]
As another mode of the remaining pattern, a radial mode or the like can be used if allowed by the layout.
[0033]
According to Configuration 3, in the present invention, as described above, the position accuracy of the isolated pad and the isolated bump is high, and a highly accurate contact component can be obtained. For this reason, for example, there is no product defect due to the positional deviation between the isolated pad and the anisotropic conductive rubber sheet during contact board assembly, and the positional deviation between the isolated bump and the electrode on the wafer in the burn-in test. As a result, a short circuit does not occur during the burn-in test, and a failure that damages the chips on the wafer does not occur. Therefore, a wafer batch contact board can be obtained with a high yield.
[0034]
In the present invention, by connecting the GND wiring or the power supply wiring in the multilayer wiring board to the remaining pattern on the insulating film in the contact component, noise against high frequency can be reduced and high frequency characteristics can be improved. Further, by using the remaining pattern, it is possible to easily improve the high frequency characteristics without increasing costs and processes. In particular, all the isolated GND pads or isolated power pads on the insulating film can be connected to the remaining pattern by connecting the power common wiring or the GND common wiring in the multilayer wiring board to the remaining pattern. It is preferable because the resistance of the power supply common line can be reduced and the GND or power supply can be strengthened.
The method of connecting the GND wiring or power supply wiring to the pattern leaving the multilayer wiring board is not particularly limited. For example, as shown in FIG. 9, the remaining pattern 36 on the insulating film 32 is formed in the peripheral portion of the wafer batch contact board. In addition, the anisotropic conductive rubber sheet 20 and the anisotropic conductive rubber 21 ′ and the GND pad provided separately from the anisotropic conductive rubber 21 and the pad electrode 12 for GND, I / O, and power supply in the multilayer wiring board 10 are provided. It can be connected to the GND wiring (ground trace) 15 in the multilayer wiring board 10 via 12 ′.
In addition, when the mode of the remaining pattern is a mode as shown in FIG. 1, the high frequency characteristics are the best.
Moreover, when forming the pattern to leave on the front and back of an insulating film, both the patterns on the front and back can be connected to either GND wiring or power supply wiring in a multilayer wiring board. In this case, the high frequency characteristics are improved.
[0035]
According to the configuration 4 or the configuration 5, the wafer batch contact board contact component having high positional accuracy of the isolated pad and the isolated bump described above can be easily manufactured without increasing costs and processes.
[0036]
In the present invention, the remaining pattern can be formed by avoiding the isolated bump on the surface of the insulating film on the side where the isolated bump is formed (Configuration 6). The aspect of the remaining pattern is the same as that described above. In this case, the remaining pattern may be formed of a material having no conductivity.
In the present invention, it is also possible to form a remaining pattern made of a non-conductive material on the conductive layer before etching the conductive layer to form an isolated pad and a remaining pattern. .
[0037]
DETAILED DESCRIPTION OF THE INVENTION
The contact component in the wafer batch contact board of the present invention will be described.
In the contact component, the material of the insulating film is not particularly limited as long as it has electrical insulation, but preferably has insulation and flexibility. Specifically, a polyimide resin, an epoxy resin, Examples include silicone resins, polyester resins, urethane resins, polystyrene resins, polyethylene resins, polyamide resins, ABS copolymer resins, polycarbonate resins, fluorine resins, and other thermosetting resins, or thermoplastic resins. Can be appropriately selected according to the purpose. Of these resins, polyimide resins that are excellent in heat resistance, chemical resistance, mechanical strength, and workability are particularly preferably used. Since polyimide has a large absorption in the ultraviolet region, it is suitable for laser ablation processing. Since the polyimide film has high flexibility, it can absorb variations in height of isolated bumps on contact parts and electrodes (contact points) on the object to be inspected.
The thickness of the insulating film can be arbitrarily selected. In the case of a polyimide film, the thickness is usually preferably about 5 to 200 μm, more preferably 10 to 50 μm from the viewpoint of the formability of bump holes described later.
[0038]
The material of the conductive layer for forming the isolated pad and the remaining pattern on the insulating film of the contact part may be any material as long as it has conductivity, but resists the restoring force of the ring when the remaining pattern is formed. A strong material is preferred. Examples of such a material include single metals such as copper, nickel, chromium, aluminum, gold, platinum, cobalt, silver, lead, tin, indium, rhodium, tungsten, ruthenium, and iron, or various alloys containing these as components. (For example, solder, nickel-tin, gold-cobalt) and the like. As will be described later, when an isolated bump or the like is formed by electrolytic plating, a conductive layer that becomes an electrode (cathode) in electrolytic plating is selected. The conductive layer may have a single-layer structure composed of the above metal layers or a laminated structure. For example, a laminated structure in which a base film such as Cr or Ni, a Cu film, a Ni film, and an Au film are sequentially laminated from the insulating film side can be used. In this case, the Cr undercoating film or the Ni undercoating film is preferable because it improves adhesion with an insulating film such as a polyimide film. The Cu film is a main component of the conductive layer. The Ni film has a role of preventing oxidation of Cu, a role of improving the mechanical strength of the conductive layer, and a role of an intermediate layer for forming an Au layer on the outermost surface of the conductive layer. The Au film is formed for the purpose of preventing oxidation of the surface of the conductive layer and reducing contact resistance. Note that a gold-cobalt alloy, rhodium, palladium, or the like can be used instead of the Au film. In particular, when a gold-cobalt alloy is used, the mechanical strength of the isolated pad increases.
[0039]
As a method for forming these conductive layers, a film forming method such as sputtering or vapor deposition, a plating method such as electroless plating or electrolytic plating, or a method using a metal foil such as copper foil may be used. it can. In addition, the conductive layer can be formed by a combination of sputtering and plating. For example, after a thin film is formed by a sputtering method, a thick film can be formed by plating.
Note that the Ni film or the Au film on the Cu film is required to have a mechanical strength and needs to be a relatively thick film, so that it is desirable to form by a plating method (electroless plating or electrolytic plating).
The thickness of the conductive layer is not particularly limited and can be set as appropriate.
[0040]
The isolated pad and the remaining pattern on the insulating film can be simultaneously formed in the same process, for example, by patterning a conductive layer formed on the entire surface of the insulating film. Specifically, for example, after forming a resist pattern on the conductive layer formed on the entire surface of the insulating film, the exposed conductive layer is etched to obtain a desired isolated pad and a remaining pattern.
[0041]
The constituent material of the isolated bump in the contact component is not particularly limited as long as it is a metal having conductivity, and the same material as that of the conductive layer described above can be used. Among these, Ni, Au, Ag, Cu, Sn, Co, In, Rh, Cr, W, Ru, or an alloy mainly containing these metal components is preferable.
[0042]
Examples of the method for forming an isolated bump include an electrolytic plating method, an electroless plating method, a CVD method, etc. Among them, the electrolytic plating method is preferable because the shape controllability is good and a high-precision isolated bump can be formed. .
In the method of forming an isolated bump by the electrolytic plating method, after forming a conductive layer and a bump hole (a hole for forming a bump, a hole for connecting the isolated bump and the isolated pad) on the insulating film. Then, it is immersed in a plating bath to conduct with the conductive layer as a cathode, and plating is grown at least in the bump hole to form an isolated bump. Here, in the case of forming an isolated bump that protrudes from the insulating film surface, the portion in the bump hole corresponds to the root of the isolated bump and corresponds to a connection portion that connects the isolated bump and the isolated pad. When an isolated bump is formed only in the bump hole, a portion on the isolated pad side corresponds to the connection portion, and a contact portion with the electrode on the wafer corresponds to the isolated bump. In addition, when forming the isolated bump which protruded from the insulating film surface, the connection part in a bump hole and the isolated bump which protruded from the insulating film surface can also be formed by another material.
[0043]
Various metal films may be formed on the surface of the isolated bumps as necessary. For example, Au, Au—Co, Rh, Pt, Pd, Ag or the like or these metal components are added to the surface of the isolated bump for the purpose of improving the hardness of the isolated bump surface or preventing the contamination of the isolated bump due to migration in the burn-in test. A metal coating such as a main alloy may be formed. The metal coating may be a single layer or a multilayer.
[0044]
In the present invention, the isolated bump is a contact portion provided on the surface of the insulating film for the purpose of electrical contact and connection. The isolated bumps may or may not protrude from the surface of the insulating film. Further, the three-dimensional shape of the isolated bump is not limited, and can be any three-dimensional shape. For example, the cross-sectional shape of the isolated bump is convex or flat according to the shape of the member to be contacted. The shape may be either concave or concave. When contacting the flat electrode on the wafer, it is preferable from the viewpoint of electrical connection reliability that the bump has a mushroom shape. The height and size of the isolated bump can be freely set according to the purpose.
[0045]
Examples of the method for forming the bump hole in the insulating film include laser processing, lithographic method (including etching method), plasma processing, optical processing, machining, etc. Laser processing is preferable from the viewpoints of degree and processing accuracy.
In the case of laser processing, excimer laser with a large irradiation output, CO₂Lasers, YAG lasers, etc. are preferable. Among them, a processing method by laser ablation using an excimer laser is particularly preferable because the insulating film is less melted by heat, a high aspect ratio is obtained, and fine and fine drilling can be performed. . In the case of laser processing, a bump hole is formed by irradiating the surface of the insulating film with a laser beam with a narrowed spot.
In other cases, bump holes are formed by performing plasma etching in an atmosphere containing oxygen or fluoride gas, dry etching such as RIE (reactive ion etching), or sputter etching using the resist pattern as a mask. can do.
A bump hole can also be formed by bringing a mask having a hole having a desired hole shape (round, square, diamond, etc.) into contact with the surface of the insulating film and etching the mask.
In general, the hole diameter of the bump hole is 5 to 200 μm, preferably about 20 to 50 μm. When forming a solder ball-compatible bump, the hole diameter of the bump hole is preferably about the same as the diameter of the solder ball (about 300 to 1000 μm).
[0046]
The ring in the contact component may be a support frame that can be supported in a state where the insulating film is stretched, and includes a support frame having an arbitrary shape such as a circle or a square. The ring in the contact component is made of a material having a low coefficient of thermal expansion such as SiC, SiN, SiCN, Invar nickel, or a material having a thermal expansion coefficient close to Si and high strength (for example, ceramics, low expansion glass, metal, etc.). Preferably it is formed.
[0047]
Next, the multilayer wiring board in the wafer batch contact board will be described.
In the multilayer wiring board, the material of the insulating layer (insulating film) is preferably a resin material, and examples thereof include a polyimide resin, an acrylic resin, an epoxy resin, and the like. A polyimide resin having excellent chemical resistance is particularly preferable.
The insulating layer can be formed on the glass substrate or the wiring layer by, for example, spin coating, roll coating, curtain coating, spray coating, printing method, or the like.
[0048]
In a multilayer wiring board, for example, a conductive thin film is formed on a glass substrate or an insulating layer by a thin film forming method such as a sputtering method, and desired wiring is formed by a photolithography method (resist coating, exposure, development, etching, etc.). A wiring having a pattern can be formed.
The wiring material and the wiring layer structure in the wiring are not particularly limited. For example, the main wiring material is Cu, a Cr / Cu / Ni multilayer structure from below, a Cu / Ni / Au multilayer structure from below, or from below. The wiring can have a Cr / Cu / Ni / Au multilayer structure.
Here, Cr and Ni can prevent oxidation of Cu, which is easily oxidized (particularly, corrosion resistance is improved by Ni), and Cr and Ni have good adhesion with Cu and adjacent layers other than Cu (for example, Adhesion between the Au layer in the case of Ni and a glass substrate or insulating layer in the case of Cr is good, so that the adhesion between the layers can be improved.
Examples of alternative materials for Cu as the main wiring material include Al and Mo. The film thickness of Cu as the main wiring material is preferably in the range of 0.5 to 15 μm, more preferably in the range of 1.0 to 7.0 μm, and still more preferably in the range of 2.5 to 6 μm.
Examples of alternative materials for Cr as the base film include metals such as W, Ti, Al, Mo, Ta, and CrSi.
Examples of the substitute material for Ni include metals having high adhesion in relation to the respective materials forming the upper and lower layers.
Examples of the substitute material for Au include Au, Ag, Pt, Ir, Os, Pd, Rh, and Ru.
In the case of a multilayer wiring board, the uppermost layer (outermost surface) wiring surface is coated with gold or the like in order to prevent and protect the wiring surface oxidation and reduce contact resistance, but the lower layer (inner layer) The surface may not be coated with gold or the like. However, in view of the contact resistance, there is no problem other than the increase in cost even if a gold coat is added to the inner wiring layer.
Even if gold or the like is added to the wiring surface later, or a conductive layer (wiring layer) having a multilayer structure in which gold or the like is formed on the entire outer surface is formed in advance and then wet-etched sequentially to form a wiring pattern. Good. In addition, after the contact hole is formed, gold or the like can be coated only on the bottom of the contact hole (a part of the inner wiring surface).
When forming a conductive layer having a multilayer structure of Cr / Cu / Ni from below, Cr and Cu are formed by sputtering, and Ni is formed by electrolytic plating. In particular, Ni by electrolytic plating is thick. Therefore, the cost can be reduced. In addition, since the surface of Ni is rough, adhesion of a film to be deposited on Ni can be improved. When forming an Au film or the like on Ni, it is preferable to perform continuous plating or the like so as not to oxidize Ni.
The multilayer wiring board may be a multilayer wiring formed on one side of an insulating substrate or a multilayer wiring formed on both sides of the insulating substrate.
[0049]
The insulating substrate in the multilayer wiring board of the present invention is preferably a glass substrate, a ceramic substrate (SiC, SiN, alumina, etc.), a glass ceramic substrate, a silicon substrate, or the like. The thermal expansion coefficient of the insulating substrate is preferably 10 ppm / ° C. or less.
Among these, a glass substrate is preferable from the following viewpoints. Compared to ceramic substrates, glass substrates are cheaper, easier to process, and have good flatness due to high-precision polishing, and are transparent so that alignment is easy and thermal expansion can be controlled by the material, making it electrically insulating. Also excellent. Further, no warping due to stress occurs and molding is easy. Furthermore, if it is an alkali-free glass, there is no adverse effect due to surface elution of alkali.
Examples of the glass substrate having a thermal expansion coefficient of 10 ppm / ° C. or less include those having the following compositions.
SiO₂: 1 to 85 wt%, Al₂O_Three: 0 to 40 wt%, B₂O_Three: 0-50 wt%, RO: 0-50 wt% (where R is an alkaline earth metal element; Mg, Ca, Sr, Ba), R '₂O: 0 to 20 wt% (where R ′ is an alkali metal element; Li, Na, K, Rb, Cs), other components: 0 to 5 wt% (for example, As₂O_Three, Sb₂O_Three, ZrO, ZnO, P₂O_Five, La₂O_Three, PbO, F, Cl, etc.).
[0050]
【Example】
EXAMPLES Hereinafter, although this invention is described in detail with an Example and a comparative example, this invention is not limited at all by these.
[0051]
Example 1
In Example 1, contact parts for wafer collective contact board, multilayer wiring board for wafer collective contact board, and anisotropic conductive rubber sheet were produced, and these were assembled to produce a wafer collective contact board.
[0052]
Fabrication of contact parts for wafer batch contact boards
A method for manufacturing a contact component for a wafer batch contact board will be described with reference to FIGS.
First, as shown in FIG. 4A, a silicon rubber sheet 102 having a uniform thickness of 5 mm is placed on an aluminum plate 101 having a high flatness.
On the other hand, for example, after casting a polyimide precursor on the copper foil 104, the polyimide precursor is heated and dried and cured to obtain a copper foil 104 (thickness 18 μm) and a polyimide film 105 (thickness 25 μm). A laminated film 103 having a structure in which is laminated is prepared.
Note that the constituent material, forming method, thickness, and the like of the laminated film 103 can be appropriately selected.
For example, a polyimide film having a thickness of about 12 to 50 μm, an epoxy resin film, or a silicon rubber sheet having a thickness of about 0.1 to 0.5 mm can be used. Further, for example, a laminated film 103 can be formed by forming a copper film with a thickness of 18 μm on a polyimide film with a thickness of 25 μm by a sputtering method or a plating method. Further, a structure in which a plurality of conductive metals are sequentially formed on one surface of the film and a conductive metal layer having a laminated structure is formed on one surface of the film can be used.
Further, a thin Ni film may be formed between polyimide and Cu for the purpose of improving the adhesion between them and preventing film contamination, although not particularly shown.
[0053]
Next, as shown in FIG. 4A, a laminated film 103 having a structure in which a copper foil and a polyimide film are bonded together is adsorbed on the silicon rubber sheet 102 in a state where the laminated film 103 is uniformly spread with the copper foil side down. . At this time, by utilizing the property that the laminated film 103 is adsorbed on the silicon rubber sheet 102, the air layer is expelled and adsorbed so as not to cause wrinkles or deflection, and adsorbed in a uniformly developed state.
[0054]
Next, as shown in FIG. 4 (1), a thermosetting adhesive 107 is thinly and uniformly applied to the bonding surface of a circular SiC ring 106 having a diameter of about 8 inches and a thickness of about 2 mm, and a thickness of about 50 to 100 μm. And put on the laminated film 103. Here, as the thermosetting adhesive 107, an adhesive that cures at a temperature 0 to 50 ° C. higher than the set temperature 80 to 150 ° C. of the burn-in test is used. In this example, Bond High Chip HT-100L (main agent: curing agent = 4: 1) (manufactured by Konishi Co., Ltd.) was used.
[0055]
Next, as shown in FIG. 4 (2), a highly flat aluminum plate (weight approximately 2.5 kg) is placed on the SiC ring 106 as a weight plate 112.
[0056]
Next, as shown in FIG. 4 (3), the above-described preparation step is heated at a temperature (for example, 200 ° C., 2.5 hours) equal to or higher than the set temperature (80 to 150 ° C.) of the burn-in test. The laminated film 103 and the SiC ring 106 are bonded.
At this time, since the thermal expansion coefficient of the silicon rubber sheet 102 is larger than the thermal expansion coefficient of the laminated film 103, the laminated film 103 adsorbed on the silicon rubber sheet 102 expands by the same amount as the silicon rubber sheet 102. That is, since the thermal expansion of the silicon rubber sheet is larger than when the laminated film 103 is simply heated at a temperature equal to or higher than the set temperature (80 to 150 ° C.) of the burn-in test, the polyimide film is further expanded by this stress. In a state where the tension is large, the thermosetting adhesive 107 is cured, and the laminated film 103 and the SiC ring 106 are bonded. In addition, since the laminated film 103 on the silicon rubber sheet 102 is adsorbed in a uniformly developed state without wrinkles, deflection, or loosening, the laminated film 103 is applied to the SiC ring 106 without wrinkling, bending, or loosening. Can be glued. Furthermore, since the silicon rubber sheet 102 has high flatness and elasticity, the laminated film 103 can be evenly adhered to the adhesion surface of the SiC ring 106 evenly. The tension of the laminated film 103 is 0.5 kg / cm²It was.
In addition, when a thermosetting adhesive is not used, the film shrinks and the tension is weakened. In addition, since the curing time of the adhesive varies depending on the location, the SiC ring cannot be evenly and uniformly bonded to the bonding surface.
[0057]
Next, the heat-bonded step is cooled to room temperature and contracted to a state before heating. Thereafter, as shown in FIG. 5A, the laminated film 103 outside the SiC ring 106 is cut and removed along the outer periphery of the SiC ring 106 with a cutter.
Next, a Ni film (not shown) is 0.2 to 0.5 μm by electrolytic plating on the copper foil 104 of the laminated film 103 having a structure in which the copper foil 104 and the polyimide film 105 manufactured above are bonded. The thickness is formed.
[0058]
Next, as shown in FIG. 5B, a bump hole 108 having a diameter of about 30 μm is formed at a predetermined position of the polyimide film 105 using an excimer laser.
Next, plasma treatment is performed on the inside of the pump hole 108 and the surface of the polyimide film 105 to remove a polyimide decomposition substance mainly composed of carbon that has been generated by laser processing and adhered to the bump hole and its periphery.
[0059]
Next, in order to prevent the copper foil 104 side from being plated, a protective film such as a resist is applied to the entire surface on the copper foil 104 side except for a part used as an electrode with a thickness of about 2 to 3 μm, Protect (not shown).
Immediately, one of the electrodes was connected to the copper foil 104, and Ni or Ni alloy electroplating (current density: 0.1 to 60 A / dm) on the polyimide film 105 side.²)I do. The plating conditions can be appropriately selected. For example, a brightener, boric acid, nickel bromide, a PH adjuster, etc. can be added to the plating solution. Moreover, the hardness and surface state of the isolated bump can be changed by adjusting the content of the brightener in the plating solution. By electrolytic plating, the plating grows so as to fill the bump holes 108 shown in FIG. 5 (3), and when it reaches the surface of the polyimide film 105, it spreads isotropically and grows into a substantially hemispherical shape with a hardness of 600 Hv or more. An isolated bump 109 made of Ni or a Ni alloy such as a Ni—Co alloy is formed.
Subsequently, an Au film having a thickness of 1 to 2 μm is formed on the surface of the isolated bump 109 by electrolytic plating (not shown). Thereafter, the protective film on the copper foil 104 side is peeled off.
[0060]
Next, a resist is newly applied on the entire surface of the copper foil 104, and a resist pattern (not shown) is formed in a portion where an isolated pad and a remaining pattern (remaining pattern) are to be formed.
Next, the thin Ni film and Cu film are etched with a ferric chloride aqueous solution or the like and rinsed well, and then the resist is peeled off, so that the isolated pad 110 and the remaining pattern 111 are removed as shown in FIG. Are formed at the same time. At this time, the remaining pattern 111 is configured such that only the periphery of the isolated pad 110 is removed as shown in FIG. At this time, the remaining pattern 111 was considered to have as large an area as possible. Further, in order to cope with the sandwiching pitch, a cut 120 was made in the polyimide film 105 between each isolated pad 110 to give flexibility in the height direction, but the cut 120 was hardly spread.
Furthermore, as shown in FIG. 9, the remaining pattern 111 connects all the isolated GND pads 34 ′ on the insulating film 32 and the remaining pattern 36 (111) (the connection portion is a portion other than the illustrated cross section), The structure is connected to the GND common wiring 15 in the multilayer wiring board 10 through the anisotropic conductive rubber 21 ′ and the GND pad 12 ′.
[0061]
Through the above process, the contact parts for the wafer batch contact board are completed.
[0062]
(Example 2)
As shown in FIGS. 7A and 7B, a wafer batch contact board contact component was fabricated in the same manner as in Example 1 except that the remaining pattern 111 was ring-shaped. The other parts in FIG. 7 are assigned the same numbers as in FIG.
The same applies to FIG.
[0063]
(Example 3)
As shown in FIGS. 8 (1) and (2), a wafer batch contact board contact component was produced in the same manner as in Example 1 except that the remaining pattern 111 was in the form of a lattice.
[0064]
(Comparative Example 1)
A contact component for a wafer batch contact board was produced in the same manner as in Example 1 except that the remaining pattern 111 was not formed.
[0065]
(Evaluation)
In the case of Comparative Example 1, when the isolated pad 110 was formed, the SiC ring extended by about 50 to 100 μm with respect to the ring diameter of 8 inches (about 200 mm), and the isolated pad was shifted by about 50 to 100 μm accordingly. In the example, the displacement of the isolated pad 110 was about 5 μm in Example 1, about 8 μm in Example 2, about 10 μm in Example 3, and within 10 μm or less in Examples 1-3.
[0066]
Fabrication of multilayer wiring board
FIG. 10 is a fragmentary cross-sectional view showing an example of the manufacturing process of the multilayer wiring board.
As shown in step (1) of FIG. 10, a glass substrate 201 (SiO2 having a size of 320 mm square and a thickness of 3 mm whose surface has been polished flatly).₂: 60.0 mol%, Al₂O_Three: 9.0 mol%, CaO: 9.4 mol%, MgO: 9.3 mol%, ZnO: 9.3 mol%, PbO: 3.0 mol% of glass) on one side) by sputtering. A Cr / Cu / Ni wiring layer 202 is formed by sequentially forming a film with a thickness of about 300 Å, a Cu film with a thickness of about 2.5 μm, and a Ni film with a thickness of about 0.3 μm.
Here, Cr is provided for the purpose of strengthening the adhesion between glass and Cu. Ni is used for the purpose of preventing the oxidation of Cu, the purpose of strengthening the adhesion to the resist (the adhesion between Cu and resist is poor), and the reaction between Cu and polyimide causes polyimide to form at the bottom of the contact hole (via). It is provided for the purpose of preventing it from remaining.
In addition, the formation method of Ni is not limited to a sputtering method, You may form by the electroplating method. It is also possible to reduce the contact resistance by forming an Au film or the like on the Ni film by sputtering, electrolytic plating or electroless plating.
[0067]
Next, as shown in step (2) in FIG. 10, a predetermined photolithography step (resist coating, exposure, development, etching) is performed, and the Cr / Cu / Ni wiring layer 202 is patterned to form the first layer. A wiring pattern 202a is formed.
Specifically, first, a resist (manufactured by Clariant: AZ350) is coated to a thickness of 3 μm, baked at 90 ° C. for 30 minutes, and the resist is exposed and developed using a predetermined mask to obtain a desired resist pattern (not shown). Z). Using this resist pattern as a mask, the Cr / Cu / Ni wiring layer 202 is etched using an etching solution such as a ferric chloride aqueous solution, then the resist is stripped using the resist stripping solution, washed with water and dried. Thus, the first wiring pattern 202a is formed.
[0068]
Next, as shown in step (3) of FIG. 10, a photosensitive polyimide precursor is applied to the first wiring pattern 202a with a thickness of 10 μm using a spinner or the like to form a polyimide insulating film 203. Then, a contact hole 204 is formed in the polyimide insulating film 203.
Specifically, the applied photosensitive polyimide precursor is baked at 80 ° C. for 30 minutes, exposed and developed using a predetermined mask, and the contact hole 204 is formed. Curing is performed at 350 ° C. for 4 hours in a nitrogen atmosphere to completely polymide the photosensitive polyimide precursor. The thickness of the polyimide insulating film 203 after curing was reduced to half (5 μm) after coating. Thereafter, the surface of the polyimide is roughened by plasma treatment to increase the adhesion with the second wiring layer formed in the next step, and the polyimide decomposition product, developer, etc. generated by laser irradiation in the contact hole 204 Organic substances such as residue are oxidized and removed.
[0069]
Next, as shown in step (4) of FIG. 10, a Cr / Cu / Ni wiring layer 205 is formed in the same manner as in step (a).
Next, as shown in step (5) of FIG. 10, the Cr / Cu / Ni wiring layer 205 is patterned in the same manner as in step (b) to form a second wiring pattern 205a.
[0070]
Next, the steps (3) to (5) are repeated in the same manner to form a second-layer polyimide insulating film and contact holes, and a third-layer wiring pattern in order, thereby forming a glass multilayer wiring board having a three-layer structure. Obtained (not shown).
Next, for the purpose of preventing oxidation only in the contact terminal portion (power supply pad, ground pad and I / O pad portion) in the third-layer wiring pattern, the electrical contact property with the anisotropic conductive rubber is improved, etc. For the purpose, a 0.3 μm thick Au film was formed on a 1 μm thick Ni film by an electroless plating method (not shown).
[0071]
Finally, polyimide as an insulating film was applied on the substrate (not shown), the polyimide at the contact terminal portion was removed, and a protective insulating film was formed to obtain a multilayer wiring board for wafer batch contact board.
[0072]
Assembly process
As shown in FIG. 11, an anisotropic conductive rubber sheet 20 is bonded to a predetermined position of the multilayer wiring board 10 for wafer batch contact board manufactured as described above, and a contact component 30 is further bonded to the wafer batch contact. Completed the board.
[0073]
Burn-in test
The electrodes on the wafer and the isolated bumps of the contact parts were aligned, fixed with a chuck, put in this state, and tested in an operating environment of 125 ° C. The evaluation target was an 8-inch wafer in which 400 chips of 64MDRAM were formed.
As a result, when the contact part of Comparative Example 1 was used, the test was performed due to a defective product as a wafer collective contact board due to a misalignment between the isolated pad and the anisotropic conductive rubber, or a misalignment between the isolated bump and the electrode on the wafer. A short circuit occurred during the burn-in test, and there was a problem that a damage to the chips on the wafer occurred. On the other hand, there were no hot water using the substrates of Examples 1 to 3, such product defects, or obstacles.
[0074]
(Example 4)
In Example 1, a multilayer wiring board for wafer batch contact board was produced and burn-in test was performed in the same manner as in Example 1 except that a pattern was also formed on the surface of the polyimide film 105 on the isolated bump 109 side. .
As a result, when the isolated pad 110 and the remaining pattern 111 were simultaneously formed, the elongation of the SiC ring (position shift of the isolated pad 110) was about 4 μm.
[0075]
In addition, this invention is not limited to the said Example, It can deform | transform suitably.
[0076]
For example, in addition to the burn-in test described in the section of the prior art, the wafer batch contact board of the present invention is a part of product inspection (electrical characteristic test) conventionally performed by a probe card, or wafer level batch CSP inspection. Can also be used for
The wiring layers in the multilayer wiring board may have 2 to 10 layers or more. The multilayer wiring board used for the burn-in board has 3 to 4 layers for memory, 5 to 6 layers for logic, and about 10 layers for hybrid.
[0077]
【The invention's effect】
According to the present invention, a contact component for a wafer collective contact board in which the positional accuracy of isolated pads and isolated bumps is further improved can be obtained.
In addition, a contact component for a wafer batch contact board in which the position accuracy of the isolated pad and the isolated bump is further improved can be easily manufactured without increasing costs and processes.
[Brief description of the drawings]
FIG. 1 is a plan view of an essential part schematically showing one specific example of contact parts for a wafer batch contact board according to the present invention.
FIG. 2 is a plan view schematically showing another specific example of contact parts for a wafer batch contact board according to the present invention.
FIG. 3 is a plan view schematically showing another specific example of contact parts for a wafer batch contact board according to the present invention, wherein (1) and (2) are overall plan views, and (3) and (4). These are the top views of the principal part.
FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the contact component according to one embodiment of the present invention.
FIG. 5 is a fragmentary cross-sectional view showing a part of the manufacturing process of the contact component according to the embodiment of the present invention.
6A and 6B are diagrams schematically showing a contact component according to an embodiment of the present invention, where FIG. 6A is a cross-sectional view and FIG. 6B is a plan view.
FIGS. 7A and 7B are diagrams schematically showing a contact component according to another embodiment of the present invention, in which FIG. 7A is a cross-sectional view and FIG. 7B is a plan view.
FIGS. 8A and 8B are diagrams schematically showing a contact component according to another embodiment of the present invention, in which FIG. 8A is a cross-sectional view and FIG. 8B is a plan view.
FIG. 9 is a cross-sectional view schematically showing a main part of a wafer batch contact board.
FIG. 10 is a cross-sectional view of an essential part for explaining the manufacturing process of the multilayer wiring board for wafer collective contact board according to one embodiment of the present invention.
FIG. 11 is a cross-sectional view schematically showing a wafer batch contact board.
FIG. 12 is a cross-sectional view schematically showing a contact part for a conventional wafer batch contact board.
FIG. 13 is a plan view schematically showing a conventional contact part for a wafer batch contact board.
FIG. 14 is a plan view schematically showing the main part of a conventional contact part for a wafer batch contact board.
[Explanation of symbols]
10 Multilayer wiring board
20 Anisotropic conductive rubber sheet
21 Anisotropic conductive rubber
30 Contact parts
31 rings
32 Insulating film
33 Isolated bump
34 Isolated pad
35 Left pattern
38 notches
40 Silicon wafer
101 aluminum plate
102 Silicone rubber sheet
103 laminated film
104 Copper foil
105 Polyimide film
106 SiC ring
107 thermosetting adhesive
108 Bumphole
109 Isolated bump
110 isolated pad
111 Left pattern
112 Heavy stone board
120 notches
201 glass substrate
202 Wiring layer
202a First layer wiring pattern
203 Insulating film
204 Contact hole
205 Wiring layer
205a Second layer wiring pattern

Claims (5)

An insulating film stretched over a ring, an isolated pad formed on one surface of the insulating film, and formed on the other surface of the insulating film in a one-to-one correspondence with the isolated pad; A method of manufacturing a contact component for a wafer batch contact board for burn-in test , having an isolated bump connected to an isolated pad,
Preparing a laminated film having a structure in which the insulating film and the conductive layer are laminated;
When pasting the laminated film on the ring at a predetermined temperature, the step of sticking with a tension that the laminated film shrinks by the conductive layer when returned to normal temperature,
Forming a bump hole at a predetermined position of the insulating film in the laminated film;
Electroplating by connecting one of the electrodes for plating to the conductive layer, and forming an isolated bump by growing the plating in at least the bump hole; and
The pasted of the laminated film stretched in a ring in the process, selectively etching the conductive layer, thereby forming the isolated pad to the position corresponding to the isolated bumps on the insulating film, the isolated Forming a remaining pattern of a shape that generates the tension against the restoring force of the ring generated when forming a pad at a position avoiding the isolated pad on the insulating film;
A method of manufacturing a contact component for a wafer batch contact board for burn-in testing, comprising : When the diameter of the ring is 8 inches (200 mm) , the positional deviation between the electrode on the wafer provided at the position corresponding to the isolated pad and the isolated bump and the isolated pad and the isolated bump is 10 μm or less. The method for manufacturing a contact component for a wafer batch contact board for burn-in test according to claim 1 , wherein the remaining pattern is formed. The burn-in test wafer batch contact board according to claim 1 or 2 , wherein the remaining pattern is a ring-shaped remaining pattern that resists the tension substantially uniformly with respect to a radial direction of the ring. Method for manufacturing contact parts. A wafer batch contact board for burn-in test used to collectively test a plurality of semiconductor devices formed on a wafer,
A contact element wafer batch contact board for burn-in test obtained by the production method according to any one of claims 1 to 3,
A multilayer wiring board for a wafer batch contact board for a burn-in test having a structure in which wirings are stacked through an insulating layer and upper and lower wirings are connected through contact holes formed in the insulating layer;
A wafer batch contact board for burn-in test comprising an anisotropic conductive rubber sheet for electrically connecting the multilayer wiring board and the contact component. Wherein said residual patterns in the contact parts wafer batch contact board for burn-in test, the wafer batch contact board for burn-in test according to claim 4, GND wiring or power wiring in the multilayer wiring board is characterized in that it is connected .

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