JP2002076074A - Contact component for wafer batch contact board and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a contact component for a wafer batch contact board on which the positioning accuracy of isolation pads and isolation bumps is improved, and manufacturing method, etc., of the same. SOLUTION: In a wafer batch contact board used for tests of many semiconductor devices formed on a wafer by a batch test system, in order to reduce the expansion of insulation film 32 in the contact area due to ring 31, remaining pattern 35 is formed on the front surface and/or rear surface of insulation film 32 for avoiding isolation pads 34 and/or isolation bumps 33 so that the positioning shift is limited within 5 ppm%.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact component which is a component of a wafer batch contact board used to collectively inspect (test) a large number of semiconductor devices formed on a wafer in a wafer state. And its manufacturing method.

[0002]

2. Description of the Related Art Inspection of a large number of semiconductor devices formed on a wafer is roughly classified into a product inspection (electrical characteristic test) using a probe card and a burn-in test which is a reliability test performed thereafter. The burn-in test is one of screening tests performed to remove a semiconductor device having an intrinsic defect or a device which causes a time- and stress-dependent failure from manufacturing variations. The burn-in test can be said to be a thermal acceleration test, while the inspection with a probe card is an electrical characteristic test of the manufactured device.

[0003] The burn-in test is an ordinary method (one chip) in which a wafer is cut into chips by dicing after a electrical characteristic test performed for each chip by a probe card, and the packaged products are subjected to a burn-in test one by one. Burn-in systems are not feasible in terms of cost. Accordingly, development and commercialization of a wafer batch contact board (burn-in board) for simultaneously performing a burn-in test of a large number of semiconductor devices formed on a wafer at once are being promoted (Japanese Patent Laid-Open No. 7-2310).
No. 19). Wafer and batch burn-in systems using wafer batch contact boards are not only highly feasible in terms of cost, but also important technologies for realizing the latest technological flows such as bare chip shipping and bare chip mounting. .

The details of the burn-in test are shown below. Static burn-in is a burn-in test in which a power supply voltage at or above a rated voltage is applied at a high temperature and current is applied to the device to apply temperature and voltage stress to the device, and is also called a high-temperature bias test. . Dynamic burn-in (dy
The “namic burn-in” is a burn-in test performed at a high temperature by applying a power supply voltage that is rated or higher than that and applying a signal close to actual operation to an input circuit of the device. Monitored burn-in
Is a burn-in test having a function of not only applying a signal to an input circuit of a device but also monitoring characteristics of an output circuit in dynamic burn-in. Test burn-in is a burn-in test in which the quality of a device under test can be determined and evaluated in burn-in.

[0005] The wafer batch contact board is different from the conventional probe card in required characteristics in that the wafer is inspected in a batch and used in a heating test, and the required level is high.
When the wafer batch contact board is put into practical use, the burn-in test described above (including the case where an electrical characteristic test is performed)
In addition, a part of the product inspection (electrical characteristic test) conventionally performed by the probe card can be performed for the whole wafer.

FIG. 11 shows a specific example of a wafer batch contact board. The wafer batch contact board is shown in FIG.
As shown in FIG. 1, a contact component 30 is fixed on a multilayer wiring board for a wafer batch contact board (hereinafter, referred to as a multilayer wiring board) 10 via an anisotropic conductive rubber sheet 20. The contact component 30 is responsible for a contact portion that directly contacts the device under test. In the contact component 30, an isolated bump 33 is formed on one surface of the insulating film 32, and an isolated pad 34 is formed on the other surface in one-to-one correspondence with the isolated bump 33. The insulating film 32 is stretched over the ring 31 having a low coefficient of thermal expansion in order to avoid displacement due to thermal expansion. The isolated bumps 33 include electrodes formed on the periphery or center line of each semiconductor device (chip) on the wafer 40 (about 600 to 1000 pins per chip, and the number of electrodes obtained by multiplying this number by the number of chips is equal to the number of chips). (Located above), the same number of electrodes are formed at corresponding positions. The multilayer wiring board 10 has wirings and pad electrodes for applying a predetermined burn-in test signal or the like to each of the bumps 33 isolated on the insulating film 32 via the isolated pad 34 on the insulating substrate. The multilayer wiring board 10 has a multilayer wiring structure because the wiring is complicated. Further, in the multilayer wiring board 10, an insulating substrate having a low coefficient of thermal expansion is used in order to avoid a connection failure due to displacement of the isolated pad 34 on the insulating film 32 due to thermal expansion. The anisotropic conductive rubber sheet 20 includes pad electrodes (not shown) on the multilayer wiring board 10 and isolated pads 34 on the insulating film 32.
And an elastic body (made of silicon resin) having conductivity only in a direction perpendicular to the main surface, and metal particles are embedded in portions corresponding to the isolated pads 34 and the pad electrodes. Sheet-like connecting component having an anisotropic conductive rubber). Anisotropic conductive rubber sheet 2
Numeral 0 denotes a protrusion (not shown) of anisotropic conductive rubber formed on the surface of the sheet and abutting on the isolated pad 34 on the insulating film 32, thereby insulating the elasticity and flexibility of the rubber. Together with the flexibility of the insulating film 32, the unevenness on the surface of the semiconductor wafer 40 and the variation in the height of the isolated bumps 33 are absorbed, and the electrodes on the semiconductor wafer and the isolated bumps 33 on the insulating film 32 are separated. Connect securely.

Each semiconductor device (chip) has a power terminal, a ground terminal, and a signal input / output terminal (I
/ O terminal) is formed respectively (power supply electrode,
The isolated bumps 33 of the wafer batch contact board are formed in a one-to-one relationship and connected to all the electrodes of the semiconductor chip (ground electrode, I / O electrode). In the multilayer wiring in the wafer batch contact board, a power supply wiring, a ground wiring, and a signal input / output wiring (I / O wiring) are used in order to reduce the number of wirings.
Are common.

A method for manufacturing a contact component will be described below.
FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the contact component. First, as shown in FIG.
After the polyimide precursor is cast to a thickness of about 25 μm on the copper foil 104 of m, the polyimide precursor is heated and dried and cured to prepare a laminated film 103 having a structure in which the copper foil 104 and the polyimide film 105 are bonded together. I do. Next, as shown in FIG. 4A, a silicon rubber sheet 102 having a uniform thickness of 5 mm is placed on an aluminum plate 101 having a high flatness. The laminated film 103 is adsorbed onto the silicon rubber sheet 102 in a state of being uniformly spread with the copper foil 104 side down. Next, FIG.
As shown in (1), a thermosetting adhesive 107 is thinly and uniformly (50 to 100) on the bonding surface of a circular SiC ring (ceramic ring) 106 having a diameter of about 8 inches and a thickness of about 2 mm.
μm). Here, as the thermosetting adhesive,
The temperature is lower than the set temperature of the burn-in test (80 to 150 ° C).
Use a material that cures at a temperature higher by ５０50 ° C.

Next, as shown in FIG. 4B, a SiC ring 106 having a thermosetting adhesive 107 applied to the bonding surface is placed on the laminated film 103, and the SiC ring 106
Aluminum plate with high flatness on top (weight about 2.5kg)
As a weight plate 112.

After completion of the above-mentioned preparation step, a temperature (for example, 2 ° C.) which is equal to or higher than the set temperature (80 to 150 ° C.) of the burn-in test
(00 ° C., 2.5 hours).
3 and the SiC ring 106 (FIG. 4)
(3)).

Next, as shown in FIG. 5A, the product after the heating and bonding step is cooled to room temperature and shrunk to a state before heating. The laminated film 10 on the outer side of the SiC ring 106 is cut along the outer periphery of the SiC ring 106 by a cutter.
3 is cut off.

Next, as shown in FIG. 5 (2), a predetermined diameter of the polyimide film 105 in the laminated film 103 is about 30 μm in diameter using an excimer laser.
Is formed.

Next, after protecting the surface of the copper foil 104 so as not to be plated, one of the plating electrodes is connected to the copper foil 104 to perform Ni electroplating. As shown in FIG. 5 (3), plating grows so as to fill the bump holes 108, and then spreads isotropically and grows almost hemispherically when reaching the surface of the polyimide film 105. A bump 109 is formed.

Next, a resist is applied on the copper foil 104,
A resist pattern is formed by exposure and development (not shown), and the copper foil 10
4 and the isolated pad 1 as shown in FIG.
Form 10. FIG. 13 shows a plan view. Note that FIG.
Are assigned the same reference numerals as in FIG. 12 and description thereof is omitted.
Through the above steps, a contact component is manufactured. As described above, the contact parts for a wafer batch contact board are attached to a ceramic ring having a coefficient of thermal expansion close to silicon while maintaining tension, so that the thermal expansion of the polyimide film is affected even at a burn-in temperature (for example, about 120 ° C.). Instead, it is designed to follow the thermal expansion and contraction of the ceramic ring.

[0015]

However, according to the above method, the laminated film 103 having the structure in which the copper foil 104 and the polyimide film 105 are bonded to each other is thermally bonded to the SiC ring 106 by applying tension to the laminated film 103. Therefore, when the temperature is returned to normal temperature after bonding, the contraction tension of the copper foil 104 is applied to the center of the SiC ring 106. At this time, the SiC ring 106 contracts radially by about 50 to 100 μm with respect to the ring diameter of 8 inches (200 mm) due to the tension of the copper foil 104. Then, copper foil 104
To form the isolated pad 110 by etching
Since most of the copper foil 104 is removed by etching (see FIG. 13), the contraction tension applied to the center direction by the copper foil 104 is released, and the SiC ring 10 is removed.
6 tries to return to the original size. At this time, the tension of the polyimide film 105 remains, but is much smaller than the tension of the copper foil 104, so that the SiC ring 106 returns to almost its original size. As a result, the position of the isolated pads 110 and the isolated bumps 109 on the polyimide film 105 shifts outward by an amount corresponding to the expansion of the ring because the flexible polyimide film 105 follows the movement of the SiC ring 106 to return to the original size. Therefore, there is a problem that the positional accuracy of the isolated pad 110 and the isolated bump 109 is deteriorated. In particular, in recent years, the pitch of semiconductor devices (chips) on a wafer has become narrower (160 μm or less), and the requirements for the positional accuracy of isolated bumps have become stricter (within ± 10 μm). Was difficult. Specifically, a short circuit may occur during a burn-in test due to a displacement between an isolated bump and an electrode on a wafer, and a failure may occur that damages a chip on the wafer. In addition, the position shift of the isolated pad causes the position shift with the anisotropic conductive rubber for connecting to the multilayer wiring board, and there is a possibility that a product defect as a wafer batch contact board may occur.

In order to solve the above-mentioned problem, a position shift due to the SiC ring 106 before and after the etching of the copper foil 104 is predicted in advance, and an exposure mask and a bump hole for forming an isolated pad having a reduced size of the isolated pad and the isolated bump are provided. A method is considered in which laser processing data for formation is prepared, and a contact component is prepared using the data. However, in the case of this method, when the laminated film 103 is attached to the SiC ring 106, the tension of the laminated film 103 may not be uniform. This is because the non-uniformity causes unevenness in the tension of the portions), and it is not possible to accurately predict the displacement due to the ceramic ring before and after etching the copper foil. The formation position of the isolated pad and the isolated bump is different for each device, and the amount of displacement varies depending on the formation position of the isolated pad and the isolated bump. Therefore, by accurately predicting this displacement, the exposure mask for forming the isolated pad and the formation of the bump hole are formed. It is difficult and practically impossible to generate laser processing data for use.

Also, the isolated pads and the isolated bumps must be formed in a one-to-one correspondence with the electrodes on each chip on the wafer. As a result, as shown in FIG. 14A, if the cut 120 is not made in the polyimide film 105 between the isolated pads 110 formed on the polyimide film 105, the height variation of the electrodes, the isolated pads, and the isolated bumps on the wafer. In some cases, the flexibility to cope with the situation may be impaired. However, in this case, as shown in FIG. 14B, when the isolated pad 110 is formed by etching the copper foil, the cut 120 is widened, and the positional accuracy of the isolated pad and the isolated bump is further deteriorated.

Further, when performing the wafer batch burn-in test using the above-described wafer batch contact board, since all the chips on the wafer are measured at the same time, the noise generated when switching each chip is very large. It has been found that a malfunction occurs due to the waveform overlapping with the input pulse signal, which causes a problem. For this reason, in the conventional wafer batch contact board,
There is a problem that the power supply voltage can be applied only up to about 10 MHz and the high frequency characteristics are not sufficient.

The present invention has been made under such a background, and a first object of the present invention is to provide a contact component for a wafer batch contact board and a method of manufacturing the same, in which the positional accuracy of an isolated pad and an isolated bump is further improved. Aim. Further, the present invention provides a contact component for a wafer package contact board, which can easily produce a contact component for a wafer package contact board in which the positional accuracy of the isolated pad and the isolated bump is further improved without increasing the cost and the number of processes, and a method of manufacturing the same. The second purpose.

[0020]

Means for Solving the Problems To achieve the above object, the present invention has the following configuration.

(Structure 1) A contact component which serves as a contact portion of a wafer batch contact board used to collectively test a large number of semiconductor devices formed on a wafer, and is an insulating member stretched over a ring. Film, an isolated pad formed on one surface of the insulating film, and an isolated bump formed on the other surface of the insulating film in one-to-one correspondence with the isolated pad and connected to the isolated pad. Wherein the remaining pattern is formed on the front surface and / or the back surface of the insulating film, avoiding at least one of the isolated pads and / or the isolated bumps. Parts for batch contact board for wafers.

(Structure 2) The structure 1 wherein the remaining pattern is formed such that the displacement of the isolated pad and / or the isolated bump is 5 ppm% or less.
The contact component for a wafer batch contact board described in the above.

(Structure 3) A contact package for a wafer package contact board according to Structure 1 or 2, which is used for conducting a test of a large number of semiconductor devices formed on a wafer at a time. When,
A multilayer wiring board for a wafer batch contact board having a structure in which wiring is stacked via an insulating layer and upper and lower wirings are connected via contact holes formed in the insulating layer, and the multilayer wiring board and the contact component A wafer batch contact board, comprising: an anisotropic conductive rubber sheet that is electrically connected.

(Structure 4) An insulating film stretched over a ring, an isolated pad formed on one surface of the insulating film, and the other of the insulating film in one-to-one correspondence with the isolated pad. A method for manufacturing a contact component for a wafer batch contact board, comprising: an isolated bump formed on a surface and connected to the isolated pad, wherein at least one surface of the insulating film has at least one surface. Avoid one isolated pad and / or isolated bump,
A method for manufacturing a contact component for a wafer batch contact board, comprising a step of forming a remaining pattern.

(Structure 5) A step of preparing a laminated film having a structure in which an insulating film and a conductive layer are laminated, and a step of attaching the laminated film on a ring at a predetermined temperature.
A step of attaching the conductive film to the conductive film so that the conductive film shrinks when the temperature is returned to room temperature, forming a bump hole at a predetermined position of the insulating film in the conductive film; Connecting one of the electrodes to perform electroplating, growing plating at least in the bump hole to form an isolated bump, and selectively etching the conductive layer to form the bump on the insulating film. Forming an isolated pad at a position corresponding to the above, and forming a remaining pattern avoiding at least one of the isolated pads on the insulating film. Production method.

(Structure 6) A step of forming a conductive layer on a surface of the insulating film on a side on which the isolated bump is formed,
6. The method of manufacturing a contact component according to claim 5, further comprising: forming a remaining pattern on the surface of the insulating film on the side where the isolated bump is formed, avoiding at least one of the isolated bumps.

[0027]

According to the first aspect of the present invention, in the method of manufacturing a contact part according to the present invention, since a pattern is formed on an insulating film, a conductive layer such as a copper foil is etched to form an isolated pad. In this case, the tension release due to the etching of the conductive layer is extremely small, so the extension of the insulating film in the outer peripheral direction is extremely small, and the deterioration of the positional accuracy of the isolated pad and the isolated bump caused by the release of the tension of the conductive layer is extremely small. small. Therefore, the position accuracy of the isolated pad and the isolated bump is high, and a highly accurate contact component can be obtained. That is, in the present invention, since the tension of the polyimide film is very weak compared to the restoring force of returning to the SiC ring, a pattern is formed on the polyimide film, and the remaining pattern is formed. , Against the restoring force of the ceramic ring. In the present invention, a pattern can be formed on the surface of the insulating film on the side where the isolated bumps are formed. In this case, it is preferable that the thickness of the remaining pattern on the surface of the insulating film on the side where the isolated bumps are formed be not more than the height of the isolated bumps, and be sufficiently lower than the height of the isolated bumps. More preferred. By forming the remaining pattern on the front and back surfaces of the insulating film in this way, the positional accuracy of the isolated pad and the isolated bump can be further improved.

As in the configuration 2, it is preferable that the remaining pattern is formed such that the displacement of the isolated pad and / or the isolated bump is 5 ppm or less. Specifically, for example, the displacement of the isolated pad and / or the isolated bump is 10 μm for a ring diameter of 8 inches (about 200 mm).
It is preferable to form the remaining pattern as described below. It is more preferably at most 8 μm, more preferably at most 5 μm.

If the layout pattern permits, as shown in FIG. 1, only the periphery of each isolated pad 34 of the conductive layer formed on the entire surface of the insulating film 32 is etched as shown in FIG. Part is left pattern 35
Then, the elongation due to the restoring force of the ring is minimized. In the case of FIG. 1, it is preferable to make the area of the remaining pattern 35 as large as possible.

When the form of the remaining pattern is a ring shape as shown in FIG. 2A, the ring-shaped remaining pattern 35 evenly opposes the restoring force of the ring 31. The extension of the insulating film 32 inside 35 is suppressed, and the positional accuracy of the isolated pad 34 and the isolated bump (not shown) can be maintained. Furthermore, in the case of the ring-shaped remaining pattern 35 as shown in FIG. 2A, the layout restriction of the isolated pad 34 and the isolated bump is the least, and it can cope with the progress of the narrow pitch.
preferable. The ring-shaped remaining pattern has an effect of opposing the restoring force of the ring 31 even when a part of the ring-shaped remaining pattern 35 is interrupted as shown in FIG. 2 (2) or (3). In the case of FIGS. 2A to 2C, the thicker the ring-shaped remaining pattern 35, the better the positional accuracy. Also,
In particular, the cases (1) and (3) are more preferable because the tension can be almost evenly resisted in the radial direction of the ring.

When the form of the remaining pattern is a lattice shape as shown in FIG.
Since the lattice-shaped remaining patterns 35 are evenly opposed, the elongation of the insulating film 32 is suppressed, and the positional accuracy of the isolated pads 34 and the isolated bumps (not shown) can be maintained. Further, a grid-like remaining pattern 35 as shown in FIG.
The case of (1) is preferable because it is easy to correspond to the arrangement of the device chips. In the case of a lattice-shaped remaining pattern, FIG.
As shown in FIG.
May overlap. In this case, the elongation of the ring itself can be suppressed, which is preferable. In the case of the lattice-shaped remaining pattern, a plurality of isolated pads 3 as shown in FIG.
4 may be surrounded by blocks, or by surrounding each isolated pad 34 as shown in FIG. 3D.
In the case of FIG. 3 (3), a cut 38 may be made in the insulating film 32 between the isolated pads 34 to provide flexibility in the height direction in order to cope with the narrow pitch.

As another mode of the remaining pattern, a mode such as a radial pattern may be used if layout permits.

According to the configuration 3, according to the present invention, as described above, the positional accuracy of the isolated pad and the isolated bump is high, and a highly accurate contact component can be obtained. Therefore, for example, a product defect does not occur due to a positional shift between the isolated pad and the anisotropic conductive rubber sheet at the time of assembling the contact board, and a positional shift between the isolated bump and the electrode on the wafer in the burn-in test. Accordingly, a short circuit does not occur during a burn-in test, and a failure that damages chips on a wafer does not occur. Therefore, a wafer batch contact board can be obtained with a high yield.

According to the present invention, by connecting the GND wiring or the power supply wiring in the multilayer wiring board to the remaining pattern on the insulating film in the contact component, it is possible to reduce high frequency noise and improve high frequency characteristics. Further, by using the remaining pattern, it is possible to easily improve the high frequency characteristics without increasing the cost and the number of steps. In particular, by connecting the power supply common wiring or the GND common wiring in the multilayer wiring board to this remaining pattern, all the isolated GND pads or isolated power supply pads on the insulating film can be connected to the remaining pattern,
Therefore, the resistance of the GND common wiring or the power supply common wiring can be reduced, and the GND or the power supply can be strengthened. The method for connecting the GND wiring or the power supply wiring to the remaining pattern in the multilayer wiring board is not particularly limited. For example, as shown in FIG.
And anisotropic conductive rubber 21 ′ separately provided from the anisotropic conductive rubber sheet 20 and the pad electrode 12 for GND, I / O and power supply connection in the anisotropic conductive rubber sheet 20 and the multilayer wiring board 10, and GND. It can be connected to the GND wiring (ground trace) 15 in the multilayer wiring board 10 via the pad 12 '. In addition, the mode of the left pattern is
In the case of the mode as shown in FIG. 1, the high-frequency characteristics are the best. In the case of forming the remaining patterns on the front and back of the insulating film, both of the left and right patterns can be connected to either the GND wiring or the power supply wiring in the multilayer wiring board. In this case, the high frequency characteristics are improved.

According to the configuration 4 or 5, the contact component for a wafer batch contact board having high positional accuracy of the above-mentioned isolated pads and isolated bumps can be easily manufactured without increasing the cost and the number of steps.

In the present invention, a remaining pattern can be formed on the surface of the insulating film on the side where the isolated bump is formed, avoiding the isolated bump (configuration 6).
The mode of the remaining pattern is the same as the above-described mode. In this case, the remaining pattern may be formed of a material having no conductivity. Further, in the present invention, before forming the isolated pad and the remaining pattern by etching the conductive layer, it is also possible to form a remaining pattern formed of a material having no conductivity on the conductive layer. .

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A contact component in a wafer batch contact board according to the present invention will be described. In the contact parts, the insulating film is not particularly limited in its material as long as it has electrical insulation, but preferably has flexibility as well as insulation, specifically, a polyimide resin, an epoxy resin, Silicone resin,
Polyester resin, urethane resin, polystyrene resin, polyethylene resin, polyamide resin, ABS
A thermosetting resin such as a copolymer resin, a polycarbonate-based resin, and a fluorine-based resin, or a thermoplastic resin may be used, and may be appropriately selected depending on the purpose. Among these resins, a polyimide resin excellent in heat resistance, chemical resistance, mechanical strength, workability and the like is particularly preferably used.
Polyimide has a large absorption in the ultraviolet region and is suitable for laser ablation processing. Since the polyimide film has high flexibility, it can absorb variations in the height of an isolated bump on a contact component or the height of an electrode (contact) on a device under test. The thickness of the insulating film can be arbitrarily selected. In the case of a polyimide film, it is usually preferably about 5 to 200 μm, more preferably 10 to 50 μm, from the viewpoint of forming bump holes described later.

The material of the conductive layer for forming the isolated pad and the remaining pattern on the insulating film of the contact component may be any material having conductivity.
A material having a strong force against the restoring force of the ring when the remaining pattern is formed is preferable. Such materials include:
For example, single metals such as copper, nickel, chromium, aluminum, gold, platinum, cobalt, silver, lead, tin, indium, rhodium, tungsten, ruthenium and iron, or various alloys containing these (for example, solder, nickel-
Tin, gold-cobalt) and the like. As will be described later, when an isolated bump or the like is formed by electrolytic plating, a conductive layer serving as an electrode (cathode) in electrolytic plating is selected. The conductive layer may have a single-layer structure composed of the above-described metal layers, or may have a laminated structure. For example, from the insulating film side, a base film such as Cr or Ni, a Cu film,
A laminated structure in which an i film and an Au film are sequentially laminated can be used. In this case, a Cr underlayer or a Ni underlayer is preferable because it improves the adhesion to an insulating film such as a polyimide film. The Cu film becomes a main component of the conductive layer. N
The i-film has a role of preventing oxidation of Cu, a role of improving the mechanical strength of the conductive layer, and a role as an intermediate layer for forming an Au layer on the outermost surface of the conductive layer. The Au film is formed for the purpose of preventing oxidation of the conductive layer surface and reducing the contact resistance. Note that a gold-cobalt alloy, rhodium, palladium, or the like can be used instead of the Au film. In particular, using a gold-cobalt alloy increases the mechanical strength of the isolated pad.

As a method for forming these conductive layers, a film forming method such as a sputtering method or a vapor deposition method, a plating method such as electroless plating or electrolytic plating, or a method using a metal foil such as a copper foil is used. can do. Further, a conductive layer can be formed by a combination of a sputtering method and a plating method. For example, after a thin film is formed by a sputtering method, a thick film can be formed by plating. Note that a Ni film or an Au film on a Cu film requires mechanical strength and is preferably formed by a plating method (electroless plating, electrolytic plating) because it needs to be relatively thick. The thickness of the conductive layer is not particularly limited, and can be set as appropriate.

The isolated pad and the remaining pattern on the insulating film can be simultaneously formed in the same step by, for example, patterning a conductive layer formed on the entire surface of the insulating film. Specifically, for example, after forming a resist pattern on the conductive layer formed on the entire surface of the insulating film,
The exposed conductive layer is etched to obtain the desired isolated pad and remaining pattern.

The constituent material of the isolated bump in the contact component is not particularly limited as long as it is a metal having conductivity, and the same material as the above-described conductive layer can be used. Among these, Ni, Au, Ag, Cu, Sn, Co, I
n, Rh, Cr, W, Ru or an alloy mainly containing these metal components is preferable.

Examples of the method for forming the isolated bump include an electrolytic plating method, an electroless plating method, and a CVD method.
Among these, the electrolytic plating method is preferable because the shape controllability is good and a highly accurate isolated bump can be formed. In the method of forming an isolated bump by electrolytic plating, after forming a conductive layer and a bump hole (a hole for forming a bump, a hole for connecting an isolated bump and an isolated pad) in an insulating film, Then, the conductive layer is immersed in a plating bath to conduct electricity, and plating is grown at least in the bump hole to form an isolated bump. Here, when forming an isolated bump protruding from the surface of the insulating film, the portion in the bump hole corresponds to the root of the isolated bump and corresponds to a connection portion connecting the isolated bump and the isolated pad. When an isolated bump is formed only in a bump hole, the portion on the isolated pad side corresponds to the connection portion, and the portion in contact with the electrode on the wafer corresponds to the isolated bump. In the case of forming an isolated bump protruding from the insulating film surface, a connection portion in the bump hole,
The isolated bump protruding from the insulating film surface can be formed of another material.

Various metal films may be formed on the surface of the isolated bumps as necessary. For example, Au, Au-Co, Rh, Pt, Pd, and Ag are applied to the surface of the isolated bump for the purpose of improving the hardness of the surface of the isolated bump and preventing contamination of the isolated bump due to migration in a burn-in test.
Or a metal coating such as an alloy mainly containing these metal components. The metal coating may be a single layer or a multilayer.

In the present invention, the isolated bump is a contact portion provided on the surface of the insulating film for the purpose of electrical contact and connection. It does not matter whether the isolated bump projects from the surface of the insulating film. Also, the three-dimensional shape of the isolated bump is not limited, and can be any three-dimensional shape.
The shape may be any of a convex shape, a planar shape, and a concave shape according to the shape of the member to be contacted. When making contact with a flat electrode on the wafer, it is preferable that the pump be in a mushroom-like shape from the viewpoint of electrical connection reliability. The height and size of the isolated bump can be freely set according to the purpose and the like.

Examples of the method of forming bump holes in the insulating film include laser processing, lithographic method (including etching method), plasma processing, optical processing, and mechanical processing. Laser processing is preferred from the viewpoint of the degree of freedom of the shape and the processing accuracy.
In the case of laser processing, the laser light to be irradiated is preferably an excimer laser, a CO ₂ laser, a YAG laser or the like having a large irradiation output. Among them, a processing method by laser ablation using an excimer laser is a method of melting an insulating film by heat. And the like, and a high aspect ratio can be obtained, and fine and fine drilling can be performed. In the case of laser processing, a bump hole is formed by irradiating a laser beam having a focused spot on the surface of the insulating film. In other cases, using a resist pattern or the like as a mask, plasma etching in an atmosphere containing oxygen or a fluoride gas, or RIE
Bump holes can be formed by performing dry etching such as (reactive ion etching) or sputter etching. Also, the desired hole shape (round,
A mask having a square (diamond, rhombus, etc.) hole can be formed in close contact with the surface of the insulating film, and an etching process can be performed on the mask to form a bump hole. The hole diameter of the bump hole is usually 5 to 200 μm, preferably about 20 to 50 μm. When a bump corresponding to a solder ball is formed, the hole diameter of the bump hole is preferably about the same as that of the solder ball (about 300 to 1000 μm).

The ring in the contact part may be any support frame that can support the insulating film in a stretched state, and includes a support frame of any shape such as a circle and a square. The ring in the contact component is, for example, SiC, Si
It is preferably formed of a material having a low coefficient of thermal expansion such as N, SiCN, invar nickel, or a material having a coefficient of thermal expansion close to that of Si and having high strength (for example, ceramics, low-expansion glass, metal, etc.).

Next, a multilayer wiring board in a wafer batch contact board will be described. In the multilayer wiring board, as a material of the insulating layer (insulating film), a resin material is preferable, and a polyimide resin, an acrylic resin, an epoxy resin, or the like can be used. A polyimide resin having excellent chemical resistance is particularly preferred. The insulating layer includes, for example, spin coating, roll coating,
It can be formed on a glass substrate or a wiring layer by a curtain coat, a spray coat, a printing method, or the like.

In the multilayer wiring board, the wiring is, for example,
A conductive thin film is formed on a glass substrate or an insulating layer by a thin film forming method such as a sputtering method, and a wiring having a desired pattern is formed by a photolithographic method (resist coating, exposure, development, etching, etc.). it can. The wiring material and the wiring layer configuration in the wiring are not particularly limited. For example, a Cu / Main multilayer material using Cu as a main wiring material, a Cr / Cu / Ni multilayer structure from below, or a Cu / Ni
/ Au multilayer structure or a wiring having a Cr / Cu / Ni / Au multilayer structure from below. Where C
r and Ni can prevent oxidation of Cu which is easily oxidized (in particular, corrosion resistance is improved by Ni), and Cr and Ni have good adhesion to Cu and an adjacent layer other than Cu (for example, Ni
In the case of (1), the adhesion to the Au layer and in the case of Cr (glass substrate or insulating layer) is also good, so that the adhesion between the layers can be improved. Al, Mo, and the like can be cited as substitutes for Cu as the main wiring material. The film thickness of Cu as a main wiring material is 0.5 to 15
The range of μm is preferred, the range of 1.0 to 7.0 μm is more preferred, and the range of 2.5 to 6 μm is even more preferred.
W, Ti, A
metals such as 1, Mo, Ta, and CrSi. N
As a substitute material for i, a metal or the like having high adhesion in relation to the respective materials forming the upper and lower layers can be used. Au
Are Au, Ag, Pt, Ir, O
s, Pd, Rh, Ru and the like. In the case of a multilayer wiring board, the uppermost wiring surface (outermost surface) is coated with gold or the like in order to prevent and protect the wiring surface from oxidation and to reduce contact resistance. The surface need not be coated with gold or the like. However, considering the contact resistance, there is no problem even if the cost is increased even if the inner wiring layer is further coated with gold. Gold or the like may be post-installed on the surface of the wiring, or a multi-layered conductive layer (wiring layer) in which gold or the like is formed on the entire outermost surface may be formed in advance and wet-etched in order to form a wiring pattern. Good. After the formation of the contact hole, only the bottom of the contact hole (a part of the wiring surface of the inner layer) may be coated with gold or the like. Cr / Cu / Ni from below
When forming a conductive layer having a multilayer structure, Cr and Cu are formed by a sputtering method, and Ni is formed by an electrolytic plating method. Can be planned. Also, N
Since the surface of i is rough, it is possible to improve the adhesion of the film to be applied on Ni. When forming an Au film or the like on Ni, N
It is preferable to perform continuous plating or the like so as not to oxidize i. The multilayer wiring board may have a multilayer wiring formed on one surface of an insulating substrate or a multilayer wiring formed on both surfaces of an insulating substrate.

As the insulating substrate in the multilayer wiring board of the present invention, a glass substrate, a ceramics substrate (SiC, Si
Substrates such as N, alumina, etc.), glass ceramics substrates, and silicon substrates are preferred. The thermal expansion coefficient of the insulating substrate is preferably 10 ppm / ° C. or less. Of these, a glass substrate is preferred from the viewpoints described below. Compared with ceramic substrates, glass substrates are inexpensive, easy to process, have high flatness due to high-precision polishing, are transparent, and are easy to align. Is also excellent. Also, no warpage due to stress occurs, and molding is easy. Furthermore, if the glass is non-alkali, there is no adverse effect due to elution of alkali on the surface. Thermal expansion coefficient is 10p
Examples of the glass substrate having a temperature of pm / ° C. or lower include those having the following composition. SiO ₂ : 1 to 85 w
_{t%, Al 2 O 3:} 0~40wt%, B 2 O 3: 0~50w
t%, RO: 0 to 50 wt% (R is an alkaline earth metal element; Mg, Ca, Sr, Ba), R ′ ₂ O: 0 to 0%
20 wt% (R 'is an alkali metal element; Li, N
a, K, Rb, Cs), other components: 0 to 5 wt%
(For example, As ₂ O ₃ , Sb ₂ O ₃ , ZrO, ZnO, P ₂
O ₅ , La ₂ O ₃ , PbO, F, Cl, etc.).

[0050]

The present invention will be described in detail below with reference to examples and comparative examples, but the present invention is not limited to these examples.

Example 1 In Example 1, a contact component for a wafer batch contact board, a multilayer wiring board for a wafer batch contact board, and an anisotropic conductive rubber sheet were produced, and these were assembled to produce a wafer batch contact board. did.

Contact for wafer batch contact board
A method for manufacturing a contact component for a wafer batch contact board will be described with reference to FIGS. First, as shown in FIG.
A silicon rubber sheet 102 having a uniform thickness of 5 mm is placed on the surface 01. On the other hand, for example, after the polyimide precursor is cast on the copper foil 104, the polyimide precursor is heated and dried and cured to form the copper foil 104 (18 μm in thickness) and the polyimide film 105 (25 μm in thickness).
m) is prepared. The constituent materials of the laminated film 103, the forming method,
The thickness and the like can be appropriately selected. For example, a polyimide film or epoxy resin film having a thickness of about 12 to 50 μm, or a silicon rubber sheet having a thickness of about 0.1 to 0.5 mm can be used. Further, for example, a laminated film 103 can be formed by depositing copper to a thickness of 18 μm on a polyimide film having a thickness of 25 μm by a sputtering method or a plating method.
Further, a film having a structure in which a plurality of conductive metals are sequentially formed on one surface of a film and a conductive metal layer having a laminated structure is formed on one surface of the film may be used. A thin Ni film (not shown) may be formed between the polyimide and Cu for the purpose of improving the adhesion between them and preventing film contamination.

Next, as shown in FIG. 4A, a laminated film 103 having a structure in which a copper foil and a polyimide film are bonded on the silicon rubber sheet 102 is uniformly spread with the copper foil side down. To adsorb. At this time, by utilizing the property that the laminated film 103 is adsorbed on the silicon rubber sheet 102, the air layer is adsorbed while being expelled so as not to generate wrinkles or bending, so that the air layer is adsorbed in a uniformly developed state.

Next, as shown in FIG.
The thermosetting adhesive 107 is thinly and uniformly applied to the bonding surface of the circular SiC ring 106 having a thickness of about 2 mm and a thickness of 50 to 10 mm.
It is applied with a thickness of about 0 μm and placed on the laminated film 103. Here, as the thermosetting adhesive 107, an adhesive that cures at a temperature higher by 0 to 50 ° C. than the set temperature of the burn-in test of 80 to 150 ° C. is used. In this embodiment, the bond high chip HT-100L (base agent: curing agent = 4: 1)
(Manufactured by Konishi Co., Ltd.) was used.

Next, as shown in FIG. 4B, an aluminum plate having a high flatness (about 2.5 kg in weight) was placed on the weight plate 11.
As No. 2, it is placed on the SiC ring 106.

Next, as shown in FIG. 4 (3), after the above-mentioned preparatory process, the burn-in test was performed at a set temperature (80 to 80 ° C.).
150 ° C) or higher (for example, 200 ° C, 2.5 hours)
To bond the laminated film 103 and the SiC ring 106 together. At this time, the silicone rubber sheet 102
Since the coefficient of thermal expansion of the laminated film 103 is larger than the coefficient of thermal expansion of the laminated film 103, the laminated film 103 adsorbed on the silicon rubber sheet 102 thermally expands as much as the silicon rubber sheet 102. That is, since the thermal expansion of the silicon rubber sheet is larger than when the laminated film 103 is simply heated at a temperature higher than the set temperature (80 to 150 ° C.) of the burn-in test, the polyimide film expands more due to this stress. In a state where the tension is large, the thermosetting adhesive 107 is cured, and the laminated film 103 and the SiC ring 1 are hardened.
06 is adhered. Further, since the laminated film 103 on the silicon rubber sheet 102 is adsorbed in a state where the laminated film 103 is uniformly developed without wrinkling, bending, or loosening, the laminated film 103 is not creased, bent, or loosened.
The laminated film 103 can be bonded to 6. Further, since the silicon rubber sheet 102 has high flatness and elasticity, the laminated film 103 can be uniformly and uniformly bonded to the bonding surface of the SiC ring 106.
The tension of the laminated film 103 was 0.5 kg / cm ² . When the thermosetting adhesive is not used, the film shrinks and the tension is weakened, and the curing time of the adhesive varies depending on the location, so that the adhesive cannot be uniformly and uniformly bonded to the bonding surface of the SiC ring.

Next, the product after the heating and bonding step is cooled to room temperature and contracted to a state before heating. afterwards,
As shown in FIG. 5A, the SiC ring 10 is
Along the outer periphery of 6, the laminated film 103 outside the SiC ring 106 is cut and removed. Next, a Ni film (not shown) is formed on the copper foil 104 of the laminated film 103 having the structure in which the copper foil 104 and the polyimide film 105 are laminated by an electrolytic plating method to a thickness of 0.2 to 0.5 μm. Formed with a thickness of

Next, as shown in FIG. 5B, a bump hole 108 having a diameter of about 30 μm is formed at a predetermined position of the polyimide film 105 by using an excimer laser. Next, plasma treatment is performed on the inside of the pump hole 108 and the surface of the polyimide film 105 to remove a polyimide-decomposed substance mainly composed of carbon, which is generated by laser processing and adheres to the bump hole and its periphery.

Next, in order to prevent plating on the copper foil 104 side, a protective film such as a resist is coated on the entire surface of the copper foil 104 side except for a part used as an electrode by about 2 to 3 μm.
To protect it (not shown). Immediately, one of the electrodes is connected to the copper foil 104 and the polyimide film 1
Electroplating of Ni or a Ni alloy (current density: 0.1 to 60 A / dm ² ) is performed on the 05 side. The plating conditions can be appropriately selected. For example, a brightener, boric acid, nickel bromide, a pH adjuster, and the like can be added to the plating solution. Further, by adjusting the content of the brightener in the plating solution, the hardness and surface state of the isolated bump can be changed. Fig. 5
After growing so as to fill the bump hole 108 shown in (3), when it reaches the surface of the polyimide film 105, it expands isotropically and grows almost in a hemispherical shape, and has a hardness of 600.
An isolated bump 109 made of Ni or a Ni alloy such as a Ni-Co alloy having Hv or more is formed. Subsequently, an Au film having a thickness of 1 to 2 μm is formed on the surface of the isolated bump 109 by an electrolytic plating method (not shown). Thereafter, the protective film on the copper foil 104 side is peeled off.

Next, a resist is newly applied on the entire surface of the copper foil 104, and a resist pattern (not shown) is formed on a portion where an isolated pad and a remaining pattern (remaining pattern) are to be formed. Next, the thin Ni film and the Cu film are etched with a ferric chloride aqueous solution or the like, rinsed well, and then the resist is peeled off, as shown in FIG. Are simultaneously formed.
At this time, the remaining pattern 111 has a form in which only the periphery of the isolated pad 110 is removed as shown in FIG. At this time, care was taken to make the area of the remaining pattern 111 as large as possible. In order to cope with the narrow pitch, a cut 120 was made in the polyimide film 105 between the isolated pads 110 to provide flexibility in the height direction, but the cut 120 hardly spread. Further, as shown in FIG. 9, the remaining pattern 111 connects all the isolated GND pads 34 'on the insulating film 32 and the remaining pattern 36 (111) (the connection portion is a portion other than the cross section shown in the drawing). Anisotropic conductive rubber 2
1 ′ and the GND pad 12 ′ via the multilayer wiring board 1
0 is connected to the GND common wiring 15.

Through the above steps, a contact component for a wafer batch contact board is completed.

Example 2 As shown in FIGS. 7A and 7B, a contact component for a wafer batch contact board was produced in the same manner as in Example 1 except that the remaining pattern 111 was formed in a ring shape. . The other parts of FIG. 7 are assigned the same reference numerals as in FIG. The same applies to FIG.

Example 3 As shown in FIGS. 8A and 8B, a contact component for a wafer batch contact board was produced in the same manner as in Example 1 except that the remaining pattern 111 was formed in a lattice shape. .

Comparative Example 1 A contact part for a wafer batch contact board was produced in the same manner as in Example 1 except that the remaining pattern 111 was not formed.

(Evaluation) In the case of Comparative Example 1, the isolated pad 11
When the 0 is formed, the SiC ring extends about 50 to 100 μm with respect to a ring diameter of 8 inches (about 200 mm), and the isolated pad also shifts by about 50 to 100 μm. Example 1
In Example 2, it was about 5 μm, Example 2 was about 8 μm, Example 3 was about 10 μm, and Examples 1 to 3 were within 10 μm or less.

Fabrication of Multilayer Wiring Board FIG. 10 is a fragmentary cross-sectional view showing one example of a manufacturing process of the multilayer wiring board. As shown in step (1) of FIG. 10, a glass substrate 201 (SiO ₂ : 60.0 mol%, Al ₂ O ₃ :
9.0 mol%, CaO: 9.4 mol%, MgO: 9.3 mol
1%, ZnO: 9.3 mol%, PbO: 3.0 mol%, on one surface of a glass), a sputtering method is used to form a Cr film of about 300 Å, a Cu film of about 2.5 μm,
A Ni film is sequentially formed in a thickness of about 0.3 μm to form a Cr / C
The u / Ni wiring layer 202 is formed. Here, Cr is provided for the purpose of strengthening the adhesion between glass and Cu.
Ni is used to prevent Cu from being oxidized, to enhance the adhesion to the resist (the adhesion between Cu and the resist is poor), and to cause the polyimide at the bottom of the contact hole (via) by the reaction between Cu and the polyimide. It is provided for the purpose of preventing it from remaining. Note that the method for forming Ni is not limited to the sputtering method, and may be formed by an electrolytic plating method. In addition, it is also possible to reduce the contact resistance by forming an Au film or the like on the Ni film by a sputtering method, an electrolytic plating method, or an electroless plating method.

Next, as shown in step (2) of FIG.
A predetermined photolithography process (resist coating, exposure, development, and etching) is performed to pattern the Cr / Cu / Ni wiring layer 202 to form a first wiring pattern 2
02a is formed. More specifically, first, a resist (manufactured by Clariant: AZ350) is coated to a thickness of 3 μm,
After baking at 90 ° C. for 30 minutes, the resist is exposed and developed using a predetermined mask to form a desired resist pattern (not shown). Using this resist pattern as a mask, an etching solution such as an aqueous solution of ferric chloride is used to remove C
The r / Cu / Ni wiring layer 202 is etched, and then the resist is stripped using a resist stripper, washed with water and dried to form a first wiring pattern 202a.

Next, as shown in step (3) of FIG.
A photosensitive polyimide precursor is applied to a thickness of 10 μm using a spinner or the like on the first wiring pattern 202a to form a polyimide insulating film 203, and a contact hole 204 is formed in the polyimide insulating film 203.
Specifically, the applied photosensitive polyimide precursor is baked at 80 ° C. for 30 minutes, and exposed and developed using a predetermined mask to form a contact hole 204. Cure at 350 ° C. for 4 hours in a nitrogen atmosphere to completely polyimide the photosensitive polyimide precursor. The thickness of the polyimide insulating film 203 after curing is half (5 μm) of the thickness after coating.
Decreased to. Thereafter, the surface of the polyimide is roughened by plasma treatment to increase the adhesion to the second wiring layer formed in the next step, and the contact hole 204 is formed.
Organic substances such as polyimide decomposed products and developer residues generated by laser irradiation in the inside are oxidized and removed.

Next, as shown in step (4) of FIG.
Cr / Cu / Ni wiring layer 2 in the same manner as in the above step (a)
05 is formed. Next, as shown in step (5) of FIG. 10, the Cr / Cu / Ni wiring layer 205 is patterned in the same manner as in step (b) to form a second wiring pattern 2
05a is formed.

Next, the above steps (3) to (5) are repeated in the same manner to sequentially form a second-layer polyimide insulating film and contact holes, and a third-layer wiring pattern, thereby forming a three-layer glass multilayer. A wiring board was obtained (not shown). Then 3
For the purpose of preventing oxidation and improving the electrical contact with the anisotropic conductive rubber only for the contact terminal portions (power supply pad, ground pad and I / O pad portion) in the wiring pattern of the layer, An Au film having a thickness of 0.3 μm was formed on a Ni film having a thickness of 1 μm by electroless plating (not shown).

Finally, polyimide as an insulating film is applied on the substrate (not shown), and the polyimide at the contact terminal portion is removed to form a protective insulating film. Obtained.

Assembling process As shown in FIG. 11, an anisotropic conductive rubber sheet 20 is bonded to a predetermined position of the multilayer wiring board 10 for a wafer batch contact board manufactured as described above, and further, a contact part 30 is bonded. Thus, a wafer batch contact board was completed.

Burn-in test The electrodes on the wafer and the isolated bumps of the contact parts were aligned and fixed with a chuck, and then placed in a burn-in apparatus and tested in an operating environment at 125 ° C. The evaluation target was an 8-inch wafer on which 400 chips of 64 MDRAM were formed. As a result, when the contact component of Comparative Example 1 was used, the test was performed due to a product defect as a wafer batch contact board due to a displacement between the isolated pad and the anisotropic conductive rubber, and a displacement between the isolated bump and the electrode on the wafer. During the burn-in test, a short circuit may occur and damage to chips on a wafer may occur. On the other hand, there was no such a product failure or a failure, using the substrates of Examples 1 to 3.

Example 4 A multilayer wiring board for a wafer batch contact board was prepared in the same manner as in Example 1 except that a pattern was formed also on the surface of the polyimide film 105 on the side of the isolated bump 109. It was fabricated and subjected to a burn-in test. As a result, when the isolated pad 110 and the remaining pattern 111 were simultaneously formed, the elongation of the SiC ring (the displacement of the isolated pad 110) was about 4 μm.

The present invention is not limited to the above embodiment, but can be modified as appropriate.

For example, in addition to the burn-in test described in the section of the prior art, the wafer batch contact board of the present invention can be used for a part of a product inspection (electrical characteristic test) conventionally performed by a probe card and a wafer level test. Batch CSP
It can also be used for inspection. The number of wiring layers in the multilayer wiring board may be two to ten or more.
As a multilayer wiring board used for burn-in boards,
There are 3 to 4 layers for memory, 5 to 6 layers for logic, and about 10 layers for hybrid.

[0077]

According to the present invention, it is possible to obtain a contact component for a wafer batch contact board in which the positional accuracy of an isolated pad and an isolated bump is further improved. Further, a contact component for a wafer batch contact board in which the positional accuracy of the isolated pads and the isolated bumps is further improved can be easily manufactured without increasing the cost and the number of processes.

[Brief description of the drawings]

FIG. 1 is a plan view of a main part schematically showing a specific example of a contact component for a wafer batch contact board according to the present invention.

FIG. 2 is a plan view schematically showing another specific example of the contact component for a wafer batch contact board according to the present invention.

FIG. 3 is a plan view schematically showing another specific example of a contact component for a wafer batch contact board according to the present invention, wherein (1) and (2) are overall plan views, and (3) and (4). FIG. 3 is a plan view of a main part.

FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the contact component according to the embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view showing a part of the manufacturing process of the contact component according to the embodiment of the present invention.

FIG. 6 is a view schematically showing a contact component according to one embodiment of the present invention, wherein (1) is a cross-sectional view and (2) is a plan view.

FIG. 7 is a view schematically showing a contact component according to another embodiment of the present invention, wherein (1) is a sectional view and (2) is a plan view.

FIG. 8 is a view schematically showing a contact component according to another embodiment of the present invention, wherein (1) is a sectional view and (2) is a plan view.

FIG. 9 is a cross-sectional view schematically showing a main part of the wafer batch contact board.

FIG. 10 is a fragmentary cross-sectional view for explaining the manufacturing process of the multilayer wiring board for a wafer batch contact board according to one embodiment of the present invention;

FIG. 11 is a sectional view schematically showing a wafer batch contact board.

FIG. 12 is a cross-sectional view schematically showing a conventional contact component for a wafer batch contact board.

FIG. 13 is a plan view schematically showing a conventional contact component for a wafer batch contact board.

FIG. 14 is a plan view schematically showing a main part of a conventional contact component for a wafer batch contact board.

[Explanation of symbols]

 Reference Signs List 10 multilayer wiring board 20 anisotropic conductive rubber sheet 21 anisotropic conductive rubber 30 contact component 31 ring 32 insulating film 33 isolated bump 34 isolated pad 35 remaining pattern 38 cut 40 silicon wafer 101 aluminum plate 102 silicon rubber sheet 103 laminated film Reference Signs List 104 Copper foil 105 Polyimide film 106 SiC ring 107 Thermosetting adhesive 108 Bump hole 109 Isolated bump 110 Isolated pad 111 Remaining pattern 112 Weight plate 120 Cut 201 Glass substrate 202 Wiring layer 202a First-layer wiring pattern 203 Insulating film 204 Contact Hole 205 Wiring layer 205a Second wiring pattern

Continued on the front page F term (reference) 2G003 AA10 AC01 AC03 AD01 AG04 AG07 AG12 AH05 2G011 AA16 AB06 AB08 AC13 AC14 AE03 4M106 AA01 AA02 BA01 BA14 CA56 DD03 DD04 DD10

Claims (6)

[Claims] An insulative film stretched over a ring, which is a contact component for a contact portion of a wafer batch contact board used for batch testing of a large number of semiconductor devices formed on a wafer. And an isolated pad formed on one surface of the insulating film, and an isolated bump formed on the other surface of the insulating film and connected to the isolated pad in one-to-one correspondence with the isolated pad,
A contact component for a wafer batch contact board comprising: a wafer, wherein a remaining pattern is formed on a front surface and / or a back surface of the insulating film, avoiding at least one of the isolated pads and / or the isolated bumps. Contact parts for batch contact board. 2. The contact component for a wafer batch contact board according to claim 1, wherein the remaining pattern is formed such that a displacement of the isolated pad and / or the isolated bump is 5 ppm% or less. 3. A wafer batch contact board used for collectively testing a large number of semiconductor devices formed on a wafer, wherein the contact component for a wafer batch contact board according to claim 1 or 2 is provided. A multilayer wiring board for a wafer batch contact board having a structure in which wiring is stacked via an insulating layer and upper and lower wirings are connected via contact holes formed in the insulating layer; and the multilayer wiring board and the contact component. And an anisotropic conductive rubber sheet for electrically connecting the same. 4. An insulating film stretched over a ring, an isolated pad formed on one surface of the insulating film, and a one-to-one correspondence with the isolated pad on the other surface of the insulating film. A method of manufacturing a contact component for a wafer batch contact board, comprising: an isolated bump formed and connected to the isolated pad, wherein one surface and / or the other surface of the insulating film include:
A method for manufacturing a contact component for a wafer batch contact board, comprising a step of forming a remaining pattern avoiding at least one isolated pad and / or isolated bump. 5. A step of preparing a laminated film having a structure in which an insulating film and a conductive layer are laminated; and, when attaching the laminated film on a ring at a predetermined temperature, the conductive layer is used when the temperature is returned to normal temperature. A step of attaching the laminated film with a contracting tension, a step of forming a bump hole at a predetermined position of the insulating film in the laminated film, and connecting one of the plating electrodes to the conductive layer to perform electroplating. Forming an isolated bump by growing plating at least in the bump hole; and selectively etching the conductive layer to form an isolated pad at a position corresponding to the bump on the insulating film. And forming a leaving pattern on the insulating film, avoiding at least one of the isolated pads. Contact element manufacturing method according to claim 4, symptoms. 6. A step of forming a conductive layer on a surface of the insulating film on which the isolated bump is formed, and avoiding at least one of the isolated bumps on a surface of the insulating film on which the isolated bump is formed. Forming a remaining pattern.
A method for manufacturing the contact component described in the above.