JP4948035B2 - 樹脂封止型半導体装置の製造方法 - Google Patents
樹脂封止型半導体装置の製造方法 Download PDFInfo
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- JP4948035B2 JP4948035B2 JP2006140995A JP2006140995A JP4948035B2 JP 4948035 B2 JP4948035 B2 JP 4948035B2 JP 2006140995 A JP2006140995 A JP 2006140995A JP 2006140995 A JP2006140995 A JP 2006140995A JP 4948035 B2 JP4948035 B2 JP 4948035B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
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- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
図1、図2は、本実施形態の樹脂封止型半導体装置の製造に用いるマトリクス基板の一部を拡大して示す図であり、図1はそのチップ搭載面(上面)、図2は実装面(下面)をそれぞれ示している。
前記実施の形態1では、配線材料を使ってマトリクス基板1Aの実装面にアドレス情報パターン8を形成したが、これに限定されるものではなく、例えば次のような方法でアドレス情報パターン8を形成することもできる。
2 パッド
3 アライメントターゲット
4 パッド
5 配線
6 アライメントターゲット
7 インデックスパターン
8 アドレス情報パターン
9 ソルダレジスト
11 ガイドホール
12 半導体チップ
13 ワイヤ
14 樹脂
15 金型
15a 上型
15b 下型
16 スリット
17 半田バンプ
18 アライメントターゲット
19 マーク
20 樹脂封止型半導体装置
BP ボンディングパッド
Claims (6)
- (a)上面と、前記上面に設けられた複数の半導体チップ搭載領域と、前記上面とは反対側の下面とを有するマトリクス基板を準備する工程、
(b)複数の半導体チップを前記複数の半導体チップ搭載領域に、それぞれ搭載する工程、
(c)前記複数の半導体チップのそれぞれと前記マトリクス基板に形成された前記複数の第1パッドとを、複数のワイヤで接続する工程、
(d)前記複数の半導体チップおよび前記複数のワイヤを樹脂で封止する工程、
(e)前記複数の半導体チップのうちの互いに隣り合う領域における前記マトリクス基板および前記樹脂を切断し、複数の樹脂封止型半導体装置を取得する工程、
を含み、
取得された前記複数の樹脂封止型半導体装置のそれぞれは、分割された前記マトリクス基板の前記下面に、複数の第2パッドと、複数の配線と、アドレス情報パターンとを有し、
分割された前記マトリクス基板の前記上面は、前記樹脂で覆われており、
前記複数の配線は、前記複数の第2パッドのそれぞれと一体に形成され、
前記アドレス情報パターンは、前記複数の第2パッドおよび前記複数の配線を除く領域に形成されており、
前記アドレス情報パターンは、前記(b)工程に先立ち、形成されていることを特徴とする樹脂封止型半導体装置の製造方法。 - 前記マトリクス基板は、ガラス・エポキシ樹脂からなることを特徴とする請求項1記載の樹脂封止型半導体装置の製造方法。
- 取得された前記複数の樹脂封止型半導体装置のそれぞれに形成された前記アドレス情報パターンは、互いに異なっていることを特徴とする請求項2記載の樹脂封止型半導体装置の製造方法。
- 前記複数の樹脂封止型半導体装置のそれぞれの封止樹脂体の表面には、マークが形成されており、
前記複数の樹脂封止型半導体装置のそれぞれの分割された前記マトリクス基板の前記下面には、さらに、前記複数の第2パッドおよび前記複数の配線を除く領域にインデックスパターンが形成されていることを特徴とする請求項3記載の樹脂封止型半導体装置の製造方法。 - 前記複数の樹脂封止型半導体装置のそれぞれの分割された前記マトリクス基板の前記上面には、前記複数の第1パッドのそれぞれを露出するように、ソルダレジストが形成されており、
前記複数の樹脂封止型半導体装置のそれぞれの分割された前記マトリクス基板の前記下面には、前記複数の第2パッドのそれぞれ、および前記アドレス情報パターンを露出するように、ソルダレジストが形成されていることを特徴とする請求項4記載の樹脂封止型半導体装置の製造方法。 - 前記複数の樹脂封止型半導体装置のそれぞれの分割された前記マトリクス基板の前記上面には、前記複数の第1パッドのそれぞれを露出するように、ソルダレジストが形成されており、
前記複数の樹脂封止型半導体装置のそれぞれの分割された前記マトリクス基板の前記下面には、前記複数の第2パッドのそれぞれを露出し、かつ前記アドレス情報パターンを覆うように、ソルダレジストが形成されていることを特徴とする請求項4記載の樹脂封止型半導体装置の製造方法。
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JP2009231295A (ja) * | 2008-03-19 | 2009-10-08 | Powertech Technology Inc | 半導体装置及びその製造方法 |
JP5613463B2 (ja) | 2010-06-03 | 2014-10-22 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
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