JP4947925B2 - 気密封止パッケージおよびその製造方法 - Google Patents
気密封止パッケージおよびその製造方法 Download PDFInfo
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- JP4947925B2 JP4947925B2 JP2005181775A JP2005181775A JP4947925B2 JP 4947925 B2 JP4947925 B2 JP 4947925B2 JP 2005181775 A JP2005181775 A JP 2005181775A JP 2005181775 A JP2005181775 A JP 2005181775A JP 4947925 B2 JP4947925 B2 JP 4947925B2
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- sealing member
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- melting point
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Description
Claims (5)
- 内側に電子部品を収納する気密封止パッケージであって、
パッケージ本体と、
Auを含まない、Sn、Sn−Pb、Sn−Pb−Sb、Sn−Ag、Sn−Ag−Cuのいずれかの材料からなり、前記パッケージ本体と接着される第1の封止部材と、
Sn、またはSnにPb、Ag、Cu、Zn、Bi、Inのうちの少なくとも1つが添加されている材料からなり、前記第1の封止部材の融点よりも低い融点であり、前記第1の封止部材の上に接着される第2の封止部材と、
前記第2の封止部材により前記第1の封止部材の上に接合されるシールリングと、
前記シールリングに溶接される蓋と、を備える気密封止パッケージ。 - 前記第1の封止部材の融点は、200℃以上300℃以下である、請求項1に記載の気密封止パッケージ。
- 内側に電子部品を収納する気密封止パッケージの製造方法であって、
パッケージ本体の表面に、Auを含まない、Sn、Sn−Pb、Sn−Pb−Sb、Sn−Ag、Sn−Ag−Cuのいずれかの材料からなる第1の封止部材を固着する工程と、
Sn、またはSnにPb、Ag、Cu、Zn、Bi、Inのうちの少なくとも1つが添加されている材料からなり、前記第1の封止部材の融点よりも低い融点の第2の封止部材を、前記第1の封止部材の上に配置する工程と、
前記第2の封止部材の上にシールリングを配置して、前記第1の封止部材の融点より低い温度で前記第2の封止部材を熱処理することにより前記第2の封止部材を溶融凝固させることによって、前記第2の封止部材と前記シールリングとを溶着する工程と、
前記シールリングに蓋を溶接する工程と、を備える、気密封止パッケージの製造方法。 - 前記第1の封止部材を固着する工程では、前記パッケージ本体は、前記第1の封止部材のみと接着される、請求項3に記載の気密封止パッケージの製造方法。
- 請求項3または請求項4に記載の気密封止パッケージの製造方法により製造される、気密封止パッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005181775A JP4947925B2 (ja) | 2005-06-22 | 2005-06-22 | 気密封止パッケージおよびその製造方法 |
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JP2005181775A JP4947925B2 (ja) | 2005-06-22 | 2005-06-22 | 気密封止パッケージおよびその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2007005439A JP2007005439A (ja) | 2007-01-11 |
JP4947925B2 true JP4947925B2 (ja) | 2012-06-06 |
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JP2005181775A Active JP4947925B2 (ja) | 2005-06-22 | 2005-06-22 | 気密封止パッケージおよびその製造方法 |
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JP (1) | JP4947925B2 (ja) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6060739A (ja) * | 1983-09-14 | 1985-04-08 | Hitachi Ltd | 半導体装置 |
JP3794454B2 (ja) * | 1998-09-16 | 2006-07-05 | 富士電機ホールディングス株式会社 | 窒化物セラミックス基板 |
JP3716186B2 (ja) * | 2001-02-20 | 2005-11-16 | 京セラ株式会社 | 光半導体素子収納用パッケージ |
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2005
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