JP4942239B2 - シールド回路設計装置およびシールド回路設計方法 - Google Patents

シールド回路設計装置およびシールド回路設計方法 Download PDF

Info

Publication number
JP4942239B2
JP4942239B2 JP2000227759A JP2000227759A JP4942239B2 JP 4942239 B2 JP4942239 B2 JP 4942239B2 JP 2000227759 A JP2000227759 A JP 2000227759A JP 2000227759 A JP2000227759 A JP 2000227759A JP 4942239 B2 JP4942239 B2 JP 4942239B2
Authority
JP
Japan
Prior art keywords
cell
shield
wiring
driving
circuit design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000227759A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002043431A (ja
JP2002043431A5 (enExample
Inventor
玄一 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2000227759A priority Critical patent/JP4942239B2/ja
Priority to US09/759,262 priority patent/US6467071B2/en
Publication of JP2002043431A publication Critical patent/JP2002043431A/ja
Publication of JP2002043431A5 publication Critical patent/JP2002043431A5/ja
Application granted granted Critical
Publication of JP4942239B2 publication Critical patent/JP4942239B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2000227759A 2000-07-27 2000-07-27 シールド回路設計装置およびシールド回路設計方法 Expired - Fee Related JP4942239B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000227759A JP4942239B2 (ja) 2000-07-27 2000-07-27 シールド回路設計装置およびシールド回路設計方法
US09/759,262 US6467071B2 (en) 2000-07-27 2001-01-16 Shield circuit designing apparatus and shield circuit designing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000227759A JP4942239B2 (ja) 2000-07-27 2000-07-27 シールド回路設計装置およびシールド回路設計方法

Publications (3)

Publication Number Publication Date
JP2002043431A JP2002043431A (ja) 2002-02-08
JP2002043431A5 JP2002043431A5 (enExample) 2007-08-02
JP4942239B2 true JP4942239B2 (ja) 2012-05-30

Family

ID=18721164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000227759A Expired - Fee Related JP4942239B2 (ja) 2000-07-27 2000-07-27 シールド回路設計装置およびシールド回路設計方法

Country Status (2)

Country Link
US (1) US6467071B2 (enExample)
JP (1) JP4942239B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7739638B2 (en) * 2003-03-06 2010-06-15 Fujitsu Limited Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium considering influence of signal input to peripheral circuit which does not have logical influence
US11087058B1 (en) * 2020-01-17 2021-08-10 University Of Florida Research Foundation, Inc. Prevention of front-side probing attacks

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01318164A (ja) * 1988-06-20 1989-12-22 Fujitsu Ltd 図面自動生成方式
JPH04142074A (ja) * 1990-10-02 1992-05-15 Seiko Epson Corp 半導体装置
JPH06314741A (ja) 1993-04-30 1994-11-08 Kawasaki Steel Corp 集積回路とその自動配置配線設計方法
JP3249871B2 (ja) * 1993-12-22 2002-01-21 三菱電機株式会社 半導体記憶装置
JPH08306867A (ja) * 1995-05-11 1996-11-22 Yamaha Corp 半導体集積回路
JPH09237870A (ja) * 1996-03-01 1997-09-09 Hitachi Ltd 信号線駆動装置
JPH09307061A (ja) 1996-05-16 1997-11-28 Rohm Co Ltd 集積回路装置
JPH1140699A (ja) 1997-07-22 1999-02-12 Toshiba Corp 半導体装置
JP3264267B2 (ja) * 1999-04-21 2002-03-11 日本電気株式会社 集積回路装置
KR20010009697A (ko) * 1999-07-13 2001-02-05 윤종용 차폐선을 구비한 반도체 집적회로

Also Published As

Publication number Publication date
JP2002043431A (ja) 2002-02-08
US20020074671A1 (en) 2002-06-20
US6467071B2 (en) 2002-10-15

Similar Documents

Publication Publication Date Title
US7398490B2 (en) Digital circuit layout techniques using binary decision diagram for identification of input equivalence
Xie et al. Design space exploration for 3D architectures
US5724250A (en) Method and apparatus for performing drive strength adjust optimization in a circuit design
US6701289B1 (en) Method and apparatus for using a placement tool to manipulate cell substitution lists
Dally et al. The role of custom design in ASIC chips
US5864487A (en) Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool
US6311318B1 (en) Design for test area optimization algorithm
CN117688894B (zh) 芯片布局优化方法、装置、计算机设备及存储介质
JP3629250B2 (ja) 半導体集積回路のレイアウト方法及び半導体集積回路
JP2010257164A (ja) 半導体集積回路装置の設計方法およびプログラム
JP2001175702A (ja) 回路設計方法
JP4942239B2 (ja) シールド回路設計装置およびシールド回路設計方法
US7260804B1 (en) Method for circuit block routing based on switching activity
JP2010087244A (ja) 半導体集積回路、半導体集積回路のレイアウト方法、及び半導体集積回路のレイアウトプログラム
JPH11149496A (ja) ゲーテッドクロック設計支援装置、ゲーテッドクロック設計支援方法、及びゲーテッドクロック設計支援プログラムを格納したコンピュータ読み取り可能な記録媒体
US6704916B1 (en) Method and apparatus for optimizing placement and routing and recording medium for recording program for optimizing placement and routing
US7360193B1 (en) Method for circuit block placement and circuit block arrangement based on switching activity
US8788997B1 (en) Method for simplifying RTL schematic by grouping nodes into a cloud
US20060085778A1 (en) Automatic addition of power connections to chip power
JP4451629B2 (ja) 半導体集積回路のレイアウト装置および方法ならびこれらを使用して製造された半導体装置
JP2930087B2 (ja) 論理設計支援システム
Tung et al. Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
EP1650688A1 (en) Automatic addition of power connections to chip power supply network
Mo et al. Checkerboard: A regular structure and its synthesis
JP2001243262A (ja) 半導体集積回路のレイアウト変更方法及びレイアウト変更支援装置及びレイアウト変更支援プログラムが記録された記録媒体

Legal Events

Date Code Title Description
RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20060123

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070615

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070615

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20071101

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100222

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100519

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110426

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110624

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111220

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120119

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120221

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120228

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150309

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees