JP4903687B2 - 半導体装置、半導体装置の製造方法および半導体装置の制御方法 - Google Patents
半導体装置、半導体装置の製造方法および半導体装置の制御方法 Download PDFInfo
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- JP4903687B2 JP4903687B2 JP2007504592A JP2007504592A JP4903687B2 JP 4903687 B2 JP4903687 B2 JP 4903687B2 JP 2007504592 A JP2007504592 A JP 2007504592A JP 2007504592 A JP2007504592 A JP 2007504592A JP 4903687 B2 JP4903687 B2 JP 4903687B2
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- 239000004065 semiconductor Substances 0.000 title claims description 56
- 238000000034 method Methods 0.000 title claims description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000003860 storage Methods 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 26
- 238000009825 accumulation Methods 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000003892 spreading Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 41
- 238000010586 diagram Methods 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000011161 development Methods 0.000 description 7
- 230000015654 memory Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 230000001066 destructive effect Effects 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- -1 Metal Oxide Nitride Chemical class 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003203 everyday effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
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- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
Claims (15)
- 半導体基板上に形成されたONO膜と、
該ONO膜上に形成された第1のゲートと、
該第1のゲートの対向する側部の前記半導体基板表面に形成されたソースおよびドレインと、
前記半導体基板上に形成される第2のゲートとを有し、
前記第1のゲートは、印加されるゲート電圧に応じて前記半導体基板の直下の領域に選択的に反転層を形成し、
該第2のゲートは前記1ゲートの前記対向する側部以外の側部に形成され、印加されるコントロール電圧に応じて自身の直下の半導体基板領域に蓄積状態領域を形成するとともに前記蓄積状態領域と前記反転層との間に空乏層を形成するためのサイドゲートであり、前記空乏層の広がりにより前記反転層幅が調整され、前記反転層と前記ONO膜との間での電荷移動により前記ONO膜の蓄積電荷量を調整する、半導体装置。 - 前記第1のゲートの下であって、前記ソースと前記ドレインの間にチャネルを具備し、
前記サイドゲートが前記チャネルの横部に形成される、請求項1記載の半導体装置。 - 前記サイドゲートと前記半導体基板の間に、絶縁膜を備える、請求項1または2記載の半導体装置。
- 前記サイドゲートに印加する電圧に応じて、前記ONO膜、前記第1のゲート、前記ソース及び前記ドレインを含むトランジスタの電気的特性を不揮発的に変更することができる、請求項1から3のいずれか一項記載の半導体装置。
- 前記トランジスタの電気的特性の不揮発的な変更は、前記ONO膜の窒化膜であるN膜中に電荷蓄積領域を形成することにより行う、請求項4記載の半導体装置。
- 前記トランジスタの電気的特性は、トランジスタの閾値電圧とドレイン電流の少なくも一方である、請求項4または5記載の半導体装置。
- 前記ONO膜に電荷が蓄積されている、請求項1から4のいずれか一項記載の半導体装置。
- 半導体基板上にソース、ドレイン、電荷蓄積層を有する絶縁膜、前記絶縁膜上のゲート、および前記ゲートのチャネル幅方向の側部に配置されるサイドゲートを有するトランジスタを形成する工程と、
前記ゲートおよびサイドゲートに電圧を印加することにより、前記半導体基板表面の前記ゲート下に反転層を形成し、前記再度ゲート下に蓄積状態領域を形成するとともに前記蓄積状態領域と前記反転層との間に空乏層を形成して前記反転層の幅を調整し、前記反転層と前記絶縁膜との間の電荷の移動により前記絶縁膜の電荷蓄積層の電荷蓄積量を制御して前記トランジスタの電気的特性を電気的かつ不揮発的に変更し調整する工程と、を備えた半導体装置の製造方法。 - 前記トランジスタの電気的特性を電気的かつ不揮発的に変更し調整する工程が、
前記トランジスタの電気的特性を確認する工程と、
前記トランジスタの電気的特性が所望の特性か判断する工程と、
前記トランジスタの電気的特性が所望の特性でなければ、前記トランジスタの電気的特性の電気的かつ不揮発的な変更を行う工程と、を備えた請求項8記載の半導体装置の製造方法。 - 前記トランジスタの電気的特性は閾値電圧とドレイン電流の少なくとも一方である、請求項8または9に記載の半導体装置の製造方法。
- 前記トランジスタの電気的特性を電気的かつ不揮発的に変更する工程は、前記トランジスタに含まれる前記絶縁膜の電荷蓄積層内の電荷蓄積領域をプログラム又は消去する工程とを含む、請求項8記載の半導体装置の製造方法。
- トランジスタの電気的特性を確認するステップと、
前記トランジスタの電気的特性が所望の特性か判断するステップと、
前記トランジスタの電気的特性が所望の特性でなければ、前記トランジスタのチャネルの近傍に設けられたサイドゲートおよび前記チャネル上に形成されるゲートに電圧を印加することにより、前記サイドゲート下に蓄積状態領域を形成するとともに前記ゲート下に反転層を形成しかつ前記蓄積状態領域と前記反転層との間の空乏層を形成して前記反転層の幅を調整し、前記幅が調整された反転層と前記ゲート下に形成される絶縁膜の電荷蓄積層の電荷蓄積量を調整して、前記トランジスタの電気的特性を電気的かつ不揮発的に変更するステップと、
を備えた半導体装置の制御方法。 - 前記絶縁膜はONO膜であり、前記電荷蓄積層は前記ONO膜の窒化シリコン膜であるN膜であり、前記トランジスタの電気的特性の電気的かつ不揮発的な変更は、前記窒化膜に電荷蓄積領域を形成することにより行う、請求項12記載の半導体装置の制御方法。
- 前記トランジスタの電気的特性は閾値電圧とドレイン電流の少なくとも一方である、請求項12または13記載の半導体装置の制御方法。
- 前記トランジスタの電気的特性を電気的かつ不揮発的に変更するステップは、前記ONO膜内の電荷蓄積領域をプログラム又は消去するステップを含む、請求項12記載の半導体装置の制御方法。
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US20090061608A1 (en) * | 2007-08-29 | 2009-03-05 | Merchant Tushar P | Method of forming a semiconductor device having a silicon dioxide layer |
US10199385B1 (en) | 2017-08-01 | 2019-02-05 | United Microelectronics Corp. | Non-volatile memory device with reduced distance between control gate electrode and selecting gate electrode and manufacturing method thereof |
Citations (2)
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JP2000031304A (ja) * | 1998-07-13 | 2000-01-28 | Sony Corp | メモリ素子およびメモリアレイ |
JP2004023044A (ja) * | 2002-06-20 | 2004-01-22 | Toshiba Corp | 不揮発性半導体記憶装置 |
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US5559735A (en) * | 1995-03-28 | 1996-09-24 | Oki Electric Industry Co., Ltd. | Flash memory having select transistors |
US6768165B1 (en) * | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
TW523881B (en) * | 2001-02-08 | 2003-03-11 | Samsung Electronics Co Ltd | Non-volatile memory device and method of manufacturing the same |
US6894931B2 (en) * | 2002-06-20 | 2005-05-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
KR100446308B1 (ko) * | 2002-09-11 | 2004-09-01 | 삼성전자주식회사 | 선택 트랜지스터 구조와 sonos 셀 구조를 갖는불휘발성 메모리 소자 및 그 제조 방법 |
US7569882B2 (en) * | 2003-12-23 | 2009-08-04 | Interuniversitair Microelektronica Centrum (Imec) | Non-volatile multibit memory cell and method of manufacturing thereof |
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- 2005-02-24 JP JP2007504592A patent/JP4903687B2/ja active Active
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Patent Citations (2)
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JP2000031304A (ja) * | 1998-07-13 | 2000-01-28 | Sony Corp | メモリ素子およびメモリアレイ |
JP2004023044A (ja) * | 2002-06-20 | 2004-01-22 | Toshiba Corp | 不揮発性半導体記憶装置 |
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US20060237779A1 (en) | 2006-10-26 |
US7323744B2 (en) | 2008-01-29 |
JPWO2006090458A1 (ja) | 2008-07-17 |
WO2006090458A1 (ja) | 2006-08-31 |
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