JP4857827B2 - Method for manufacturing MOS type semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device, particularly a MOS semiconductor device having a trench gate structure.

  In a power semiconductor element, a MOSFET having a unit cell density increased by adopting a trench gate structure in order to reduce the on-resistance of the element.

For example, such a trench MOSFET is manufactured as follows. As shown in FIG. 8, a high-resistance n-type silicon epitaxial layer 22 is grown on a high-concentration n ⁺ -type silicon substrate 21, and p-type dopant is selectively ion-implanted on the surface to oxidize the atmosphere. The p-well 23 is formed by thermal diffusion. A thermal oxide film formed on the surface at the time of forming the p-well 23 is patterned by photolithography to form a mask oxide film (not shown). A trench (groove) 27 is formed by anisotropic etching by RIE (Reactive Ion Etching). Thereafter, the silicon oxide film polymer and the mask oxide film remaining in the trench 27 are removed by etching using an HF etching solution to clean the inside. Next, soft etching for removing the damaged layer on the surface of the trench 27 by RIE etching and sacrificial oxide film formation (not shown) are performed. A gate oxide film 28 is formed on the surface in the trench from which the once formed sacrificial oxide film and mask oxide film are removed.

  In order to form the gate electrode 24, a phosphorous doped polysilicon layer is deposited on the substrate surface and buried in the trench portion, and then the polysilicon layer only on the substrate surface portion is etched back. Further, patterning is performed on the substrate surface region along the opening surface of the trench 27, and an n-type dopant is ion-implanted and diffused to form the source region 25.

Patterning is performed to form a p ⁺ contact region 29 on the surface of the p well 23 between the source regions 25 along the surface opening of each trench 27 between two adjacent trenches 27, and a p-type dopant is ion-implanted. Then, heat treatment is activated. After that, an interlayer insulating film 26 for insulating the source electrode 20 formed later is deposited on the gate electrode 24, and after patterning, the source electrode 20 and the gate electrode pad portion (not shown) are further formed on the substrate. It is produced by depositing an aluminum film on the surface side and patterning it.

The above is an explanation of a method for manufacturing a trench MOSFET fabricated on a silicon substrate. A trench gate structure having excellent characteristics in a high breakdown voltage region when a SiC (silicon carbide) substrate having a band gap energy larger than silicon is used. MOSFET can be manufactured. This SiC-MOSFET is manufactured as follows (not shown). A high-resistance n-type SiC film is deposited on the n-type SiC substrate by epitaxial growth, and p-type and n-type SiC thin films are deposited on the film in this order by epitaxial growth. Here, the p-type SiC epitaxial layer becomes a p-well, and the n-type SiC epitaxial layer becomes an n ⁺ source region. Next, after depositing a mask film for trench etching, patterning is performed by photolithography, and RIE etching is performed from the surface to the n ⁺ type source region immediately below the p-well to form a trench (groove) portion. Thereafter, the inside of the trench is cleaned, soft etching and sacrificial oxide formation for removing a damaged layer by etching are performed, and then the sacrificial oxide film and the mask film are removed. The gate oxide film is formed by depositing polysilicon and then oxidizing it. The gate electrode is produced by depositing phosphorous-doped polysilicon on the substrate surface, filling the trench portion, and etching back the polysilicon on the substrate surface portion. Further, patterning for providing an n ⁺ source region and a p ⁺ contact region of a p well is performed, and n-type and p-type dopants are ion-implanted, heat-treated, and activated. Fabricated by depositing and patterning an interlayer insulation film on the surface to insulate the gate electrode from the n ⁺ source region, and then patterning the source electrode and the pad portion of the gate electrode by depositing an aluminum film on the substrate surface side To do.

  However, in the MOS type device using the above-described trench gate structure, electric field concentration occurs at the trench opening and bottom even when any of the aforementioned crystal materials is used. In addition, when the gate oxide film is formed of a thermal oxide film, the trench gate structure is not sufficient in terms of reliability, such as being thinned at the bottom of the trench, and there remains a problem to be solved.

  Therefore, a method has been proposed in which the gate oxide film at the bottom of the trench is thickened to solve the above problem (Patent Documents 1 and 2). For example, Patent Document 1 proposes a method of forming a thick LOCOS structure at the bottom of a trench.

  Regarding the SiC trench gate MOSFET, there is a description regarding a structure for preventing the gate oxide film from being broken at the bottom of the trench (Patent Document 3).

  It is disclosed that the gate insulating film formed in the trench is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film, thereby improving the breakdown voltage of the gate insulating film (Patent Document 4-paragraph). 0006-paragraph 0008).

It is described that by providing a thick gate oxide film at the bottom of the trench, the drain-gate capacitance is reduced and switching loss is reduced (Patent Document 5).
Japanese Patent Laid-Open No. 2003-8018 Japanese Patent Laid-Open No. 2001-196587 JP-A-10-308512 Japanese Patent No. 3471473 JP 2004-303802 A

  However, as shown in FIG. 9, in Patent Document 1, since a thick LOCOS oxide film 28-1 is formed at the bottom of the trench by thermal oxidation, there is a strain stress between the silicon epitaxial high resistance layer 22 and the oxide film 28-1. appear. As a result, the gate reliability is not necessarily improved sufficiently despite the thick oxide film.

  In the case of a SiC semiconductor, since the band gap energy of the SiC semiconductor crystal is larger than that of the silicon semiconductor crystal, the energy barrier with the silicon oxide film is smaller than that of silicon, and the leakage current from the gate is likely to increase. More severe than semiconductors. In addition, it is known that the formation of an oxide film by direct oxidation in a SiC semiconductor causes many defects at the MOS interface, which also causes problems in the reliability and channel mobility of the trench gate structure. easy.

  The present invention has been made in view of the above points, and the present invention solves the above-described problems and provides a new manufacturing method of a MOS semiconductor device having a highly reliable trench gate structure. is there.

According to the first aspect of the present invention, the step of forming a trench that reaches the second conductivity type high resistance layer from the one surface of the semiconductor substrate through the first conductivity type well layer, and in the trench A step of sequentially forming a gate oxide film, a polysilicon layer, and a silicon nitride film by a CVD method, and removing the silicon nitride film formed on the bottom of the trench and the surface of the semiconductor substrate to expose the polysilicon layer A step of oxidizing the exposed polysilicon layer to form a silicon oxide film, a step of removing the silicon nitride film and the polysilicon layer formed on the sidewall of the trench, and embedding doped polysilicon in the trench The object of the present invention is achieved by a method for manufacturing a MOS type semiconductor device having a trench gate structure forming step including the steps.

According to the invention of claim 2, wherein in the claims, it is desirable that the method of manufacturing a MOS type semiconductor device according to claim 1 of the appended claims to use a semiconductor silicon as the semiconductor substrate.

According to the patented invention in the range of claim 2 of the claims it is preferable to use a method of manufacturing a MOS type semiconductor device according to claim 1 of the appended claims to use a semiconductor silicon carbide as a semiconductor substrate.

In order to solve the above problems and achieve the object of the present invention, a gate oxide film is formed by CVD after forming a trench, and a non-doped polysilicon layer is deposited thereon. Further, a silicon nitride film is deposited thereon, and the silicon nitride film on the trench bottom and the substrate surface is removed by etching using RIE. In this method, the exposed polysilicon layer is thermally oxidized to thicken the gate oxide film at the bottom of the trench to form a trench gate structure.

  According to the present invention, it is possible to provide a method of manufacturing a MOS semiconductor device having a highly reliable trench gate structure.

    1 to 7 are cross-sectional views of a main part of a MOS type semiconductor substrate showing a process of forming a trench gate structure in the order of steps in the method for manufacturing a semiconductor device of the present invention. Hereinafter, a method for manufacturing a MOS semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

  Only in the description of the following examples, an epitaxial layer is deposited on a silicon substrate, or a semiconductor functional layer such as an impurity ion implantation layer, an impurity diffusion layer, an insulating film, or an electrode film is formed on the epitaxial layer. This is referred to as a wafer for convenience. In this specification as a whole, the generic term including the silicon substrate, silicon carbide substrate, and wafer is a semiconductor substrate.

Description will be made sequentially from FIG. A high resistance epitaxial layer 2 having a thickness of about 10 μm and doped with phosphorus is grown on the high concentration n ⁺ silicon substrate 1. Boron ions are implanted and diffused on the surface of the wafer to form a p-well layer 3 having a depth of about 1.5 μm and a thermal oxide film (not shown) having a thickness of 400 nm. In FIG. 1 to FIG. 7, the p-well layer 3 having a thickness of 1.5 μm is depicted thicker than the high-resistance epitaxial layer 2 having a thickness of about 8.5 μm. This is because the actual dimensional ratio is changed. The thermal oxide film on the wafer is patterned into a line having a width of 0.5 μm by a photolithography technique to form an etching mask. Etching is performed from the surface of the p-well 3 by the RIE method to form a trench 4 having a depth of 2 μm. In order to remove the damage layer on the inner surface of the trench 4 formed by this RIE etching, the surface is cleaned by performing isotropic etching and sacrificial oxide film forming treatment by CDE (Chemical Dry Etching) method (FIG. 1). ). Next, a gate oxide film 5 is formed to a thickness of 100 nm by a CVD method, and a polysilicon layer 6 is deposited to a thickness of 50 nm. Further, a silicon nitride film 7 was laminated (FIG. 2).

  Only the silicon nitride film 7 on the bottom of the trench 4 and the wafer surface is removed by RIE (FIG. 3), and the exposed polysilicon layer 6 is thermally oxidized to form a silicon oxide film (FIG. 4). After removing the oxide film on the silicon nitride film 7 thermally oxidized using an HF-based etchant, the silicon nitride film 7 and the polysilicon layer 6 on the side wall of the trench 4 are etched by the CDE method to form a film on the inner surface of the trench 4. Only the silicon oxide film 5 is used (FIG. 5). This silicon oxide film 5 has a thin trench sidewall and is a thick oxide film at the bottom and the substrate surface. In addition, since the film is not thickened by the thermal oxidation method, the strain generated at the interface is extremely small. Next, doped polysilicon 8 to be a gate electrode is buried in the trench 4 and etched back to the bottom of the opening of the trench 4 to remove the doped polysilicon layer 8 on the wafer surface (FIG. 6).

  In the first embodiment described above, the doped polysilicon layer 8 is deposited after the removal of the silicon nitride film 7 on the sidewall of the trench 4 and the polysilicon layer 6 therebelow, and the trench 4 is buried. The doped polysilicon layer 8 may be formed after depositing a CVD oxide film again after removing the silicon layer 6.

Next, the oxide film on the wafer surface is removed, a screen oxide film is formed again, patterning is performed, and arsenic (As) is ion-implanted and diffused to form the source region 9. Boron (B) ions are implanted into the surface of the p-well 3 and annealed to form the p ⁺ contact region 10. Next, a CVD oxide film of 200 nm and BPSG of 400 nm is deposited and reflowed as the interlayer insulating film 11. Thereafter, an electrode material (aluminum) is deposited on the source region 9 and the polysilicon gate lead portion and patterned to form the source electrode 12, the gate electrode pad, the metal wiring (not shown), etc. (FIG. 7). . The MOSFET having the trench gate structure manufactured as described above has improved gate reliability as compared with the conventional trench gate MOSFET.

On the n-type SiC substrate, an n ⁻ epitaxial layer, a p-type epitaxial layer, and an n ⁺⁺ epitaxial layer of a high resistance semiconductor layer are sequentially grown. Next, a mask film for trench etching is deposited on the substrate, patterned into a line having a width of 1 μm, and etched through the p epitaxial layer to the n ⁻ layer to form a trench.

  Next, a gate oxide film is formed to a thickness of 100 nm by CVD, and a polysilicon layer is deposited to 50 nm. After the silicon nitride film is deposited, the silicon nitride film on the trench bottom and the substrate surface is removed by RIE etching, and the polysilicon film is thermally oxidized. After removing the oxide film on the silicon nitride film by HF, the silicon nitride film and the polysilicon layer on the trench side wall are etched by CDE etching. Then, a doped polysilicon layer as a gate electrode is embedded in the trench, and etched back to the bottom of the trench opening to remove the doped polysilicon layer on the wafer surface.

Next, in order to form a contact region, after depositing an interlayer insulating film, the mesa surface is patterned and a trench penetrating the n ⁺ region is etched. A p-type dopant, for example, aluminum is ion-implanted at the bottom of the trench to form a contact region of the p ⁺⁺ layer. Then, a metal electrode is deposited, patterned and wired. It was confirmed that the gate leakage current of the device manufactured as described above was reduced as compared with the conventional device.

Sectional wafer cross-sectional view (No. 1) in the process step of the trench gate MOSFET according to the first embodiment of the present invention, Sectional wafer cross-sectional view (No. 2) in the process step of the trench gate MOSFET according to the first embodiment of the present invention, Sectional wafer sectional view (No. 3) in the process step of the trench gate MOSFET according to the first embodiment of the present invention, Sectional wafer sectional view (No. 4) in the process step of the trench gate MOSFET according to Example 1 of the present invention, Sectional wafer cross-sectional view (Part 5) in the process step of the trench gate MOSFET according to Example 1 of the present invention, Sectional wafer sectional view (No. 6) in the process step of the trench gate MOSFET according to Example 1 of the present invention, Sectional wafer sectional view (No. 7) in the process step of the trench gate MOSFET according to Example 1 of the present invention, Cross-sectional view of a main part of a MOSFET having a trench gate and a structure, The principal part different sectional view of MOSFET which has a trench game and a structure.

Explanation of symbols

1, silicon substrate 2, high-resistance silicon epitaxial layer 3, p-well region 4, trench 5, silicon oxide film 6, polysilicon layer 7, silicon nitride film 8, doped polysilicon layer (gate electrode)
9, source region 11, interlayer insulating film 12, source electrode.

Claims (3)

Forming a trench that penetrates the first conductivity type well layer from one surface of the semiconductor substrate and reaches the second conductivity type high resistance layer; and a gate oxide film, a polysilicon layer, and a silicon nitride film formed by CVD in the trench. A step of sequentially forming, a step of removing the silicon nitride film formed on the bottom of the trench and the surface of the semiconductor substrate to expose the polysilicon layer, and oxidizing the exposed polysilicon layer to form a silicon oxide film And a step of removing the silicon nitride film and the polysilicon layer formed on the sidewall of the trench, and a step of creating a trench gate structure including a step of embedding doped polysilicon in the trench. A method for manufacturing a MOS semiconductor device. 2. The method of manufacturing a MOS type semiconductor device according to claim 1 , wherein semiconductor silicon is used as the semiconductor substrate. 2. The method of manufacturing a MOS semiconductor device according to claim 1 , wherein semiconductor silicon carbide is used as the semiconductor substrate.

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