WO2012098861A1

WO2012098861A1 - Semiconductor device and method for manufacturing same

Info

Publication number: WO2012098861A1
Application number: PCT/JP2012/000243
Authority: WO
Inventors: 庭山　雅彦; 内田　正雄; 康太郎田中
Original assignee: パナソニック株式会社
Priority date: 2011-01-17
Filing date: 2012-01-17
Publication date: 2012-07-26

Abstract

A semiconductor device is provided with a silicon carbide layer (2) disposed on a main surface of a substrate (1), a trench (12) having a bottom surface and side surfaces disposed in the silicon carbide layer (2), an insulating film (11) disposed on the bottom surface and side surfaces of the trench, and a conductor layer (8) insulated from the silicon carbide layer (2) by the insulating film (11). The conductor layer (8) is constituted of silicon. The insulating film (11) has a first insulating layer (6) disposed on the bottom surface and side surfaces of the trench (12) and a second insulating layer (7), constituted of silicon, disposed between the part of the first insulating layer (6) positioned on the bottom surface of the trench (12) and the conductor layer (8). The second insulating layer (7) is in contact with the conductor layer (8), and the insulating film (11) thickness on the bottom surface of the trench (12) is three times or greater than that on the side surfaces of the trench (12).

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device using silicon carbide and a method for manufacturing the same.

Silicon carbide (silicon carbide: SiC) is a high-hardness semiconductor material having a larger band gap than silicon (Si), such as power elements (also called power devices), environmental elements, high-temperature operating elements, and high-frequency elements. It is applied to various semiconductor devices. Especially, application to power devices, such as a switching element and a rectifier, attracts attention.

As typical switching elements of power devices using SiC, metal-insulator-semiconductor field effect transistors (Metal Insulator Semiconductor Effect Transistor, hereinafter referred to as “MISFET”), metal-semiconductor field effect transistors (Metal Semiconductor Field Transistor Transistor). Hereinafter referred to as “MESFET”). In such a switching element, the voltage applied between the gate electrode and the source electrode can be switched between an on state in which a drain current of several A (amperes) or more flows and an off state in which the drain current is zero. Further, a high breakdown voltage of several hundred volts or more can be realized in the off state.

Also, as a typical rectifying element using SiC, there are a Schottky diode and a pn diode. These are expected as rectifying elements that realize a large current and a high breakdown voltage.

Since SiC has a higher dielectric breakdown electric field and thermal conductivity than Si, a power device using SiC (SiC power device) can easily achieve higher breakdown voltage and lower loss than Si power devices. For this reason, when realizing the same performance as the Si power device, the area and thickness can be greatly reduced as compared with the Si power device.

It is effective to increase the channel density in order to allow a larger current to flow in a power device such as MISFET. Therefore, a vertical power MISFET having a trench gate structure has been proposed instead of the conventional planar gate structure. In the planar gate structure, a channel region is formed on the surface of the silicon carbide layer, whereas in the trench gate structure, a channel region is formed on the side surface of the trench formed in the silicon carbide layer.

Hereinafter, a cross-sectional structure of a vertical MISFET having a trench gate structure which is one of switching elements using SiC will be described with reference to the drawings. A vertical MISFET generally includes a plurality of unit cells arranged two-dimensionally. Each unit cell is provided with a trench gate having a side surface perpendicular to the main surface of the substrate.

FIG. 6 is a cross-sectional view showing a conventional vertical MISFET unit cell 300U having a trench gate structure.

Unit cell 300U has silicon carbide substrate 1 and silicon carbide layer 2 formed on the main surface of silicon carbide substrate 1. Silicon carbide layer 2 has an n-type drift region 2d formed on the main surface of silicon carbide substrate 1, and a p-type body region 3 formed on drift region 2d. An n-type source region 4 is disposed in a part of the surface region of the body region 3. In silicon carbide layer 2, a trench 12 that penetrates source region 4 and reaches drift region 2 d is formed. In trench 12, gate electrode 8 and gate insulating film 5 for insulating gate electrode 8 and silicon carbide layer 2 are arranged. A source electrode 10 is provided on the silicon carbide layer 2 so as to be in contact with the source region 4. A drain electrode 9 is provided on the back surface of silicon carbide substrate 1.

The semiconductor device including the unit cell 300U is manufactured as follows, for example.

First, a silicon carbide layer 2 having the same crystal structure as that of silicon carbide substrate 1 is formed on the main surface of low resistance n-type silicon carbide substrate 1. For example, n-type drift region 2d and p-type body region 3 are formed in this order on the main surface of silicon carbide substrate 1 by epitaxial growth, and silicon carbide layer 2 is obtained. Thereafter, a mask layer (not shown) made of a silicon oxide film is disposed on a predetermined region of silicon carbide layer 2, and n-type impurity ions (for example, N (nitrogen) ions) are applied to body region 3 using this as a mask. By implanting, the source region 4 is formed in the body region 3.

After removing the mask layer, an Al film (not shown) is formed on a part of the source region 4 via an oxide film, and this is used as a mask to form a vertical trench 12 reaching the drift region 2d by the RIE method. Form.

Subsequently, the gate insulating film 5 and the gate electrode 8 are formed in the trench 12. The gate insulating film 5 is an oxide film formed by, for example, thermal oxidation of the silicon carbide layer 2.

The gate electrode 8 is formed by depositing polysilicon on the gate insulating film 5 by LP-CVD (Low Pressure Chemical Vapor Deposition), for example, and then patterning. Further, source electrode (source / body electrode) 10 is formed on silicon carbide layer 2 so as to extend over both body region 3 and source region 4, and drain electrode 9 is formed on the back surface of silicon carbide substrate 1. . In this way, a MISFET having a trench gate structure is completed.

In the MISFET having the trench gate structure, when the source electrode 10 is connected to the ground potential and the gate electrode 8 is connected to the ground potential or when a negative bias is applied to the gate electrode 8, Between the drift region 2d, holes are induced in a region in the vicinity of the interface between the body region 3 and the gate insulating film 5, and an electron path as a conduction carrier is blocked, so that no current flows ( Off). At this time, when a high voltage is applied between the drain electrode 9 and the source electrode 10 so that the drain electrode 9 side is positive, the pn junction between the body region 3 and the drift region 2d becomes a reverse bias state. A depletion layer spreads in the drift region 2d, and a high voltage is maintained.

In addition, when a positive bias of a threshold value or more is applied to the gate electrode 8, electrons are induced near the interface between the body region 3 and the gate insulating film 5 between the source region 4 and the drift region 2d, and the inversion state occurs. A layer is formed. As a result, carriers flow in the order of source electrode 10, source region 4, inversion layer (not shown) of body region 3, drift region 2d, silicon carbide substrate 1 and drain electrode 9 (ON state).

In a vertical MISFET having a planar structure, a JFET (junction field effect transistor) is formed parasitically between adjacent unit cells, and becomes a resistance component (JFET resistance). Since the JFET resistance increases as the unit cell interval (adjacent body region interval) decreases, the on-resistance increases as the JFET resistance increases as the cell pitch is reduced for miniaturization.

On the other hand, in the MISFET having the trench gate structure, since there is no JFET resistance, there is an advantage that the on-resistance decreases monotonously when the cell pitch is reduced. This is advantageous for miniaturization of the unit cell size.

However, the MISFET having the trench gate structure has a problem that the electric field strength applied to the gate insulating film at the bottom of the trench becomes very large. Hereinafter, it will be described in detail with reference to the drawings.

FIG. 7A is an enlarged cross-sectional view showing a structure within a broken line A of the conventional MISFET shown in FIG. FIGS. 7B and 7C are diagrams showing electric field strength distributions in an off state (when a drain voltage is applied) in the pn junction 30 and the MIS structure 40 indicated by broken lines in FIG. 7A, respectively. It is. The pn junction 30 is formed by the body region 3 and the drift region 2d. The MIS structure portion 40 is formed by the gate electrode 8, the gate insulating film 5, and the drift region 2d.

When a MISFET is used as a power device, the MISFET is ideally designed so that breakdown occurs when the peak electric field strength applied to the pn junction 30 exceeds the dielectric breakdown field strength of SiC (about 10 MV / cm). The However, before the electric field strength applied to the pn junction 30 reaches the dielectric breakdown electric field strength, the electric field strength applied to the gate insulating film (for example, SiO ₂ film) 5 at the bottom of the trench 12 may reach the dielectric breakdown electric field strength first. There is. For this reason, breakdown may occur at a voltage lower than the theoretical breakdown voltage.

This is because the difference between the relative dielectric constant of SiC (9.7 for 4H-SiC) and the relative dielectric constant of the SiO ₂ film (3.8) is the difference between the relative dielectric constant of Si (11.9) and the SiO ₂ film. This is because the SiC power device has a larger electric field strength on the gate insulating film 5 of the MIS structure portion 40 than the Si power device because it is smaller than the difference from the relative dielectric constant (3.8). Further, generally, the electric field concentrates on the portions of the gate insulating film 5 located at the bottom and corner portions of the trench, and a higher electric field is applied than the other portions. Furthermore, in Si devices, the dielectric breakdown electric field strength of Si is 0.2 MV / cm, which is two orders of magnitude lower than 10 MV / cm of the SiO ₂ film, so in most cases before dielectric breakdown occurs in the gate insulating film. , Breakdown occurs at the pn junction. On the other hand, in the SiC power device, the breakdown electric field strength of SiC (4H—SiC) is as large as ₂ MV / cm, and the difference from the breakdown electric field strength of the SiO ₂ film is small (about 0.5 to 1 digit). Therefore, before breakdown occurs at the pn junction 30, breakdown due to dielectric breakdown of the gate insulating film 5 may occur in the MIS structure 40, and dielectric breakdown of the gate insulating film 5 at the MIS structure 40 may occur. The problem becomes more prominent. Thus, the breakdown voltage of the MISFET may be limited due to the dielectric breakdown of the gate insulating film 5.

In order to solve this problem,

Patent Documents

1 and 2 propose a method of increasing the dielectric breakdown electric field by thickening the gate insulating film at the bottom of the trench.

In Patent Document 1, the thickness of the portion of the gate insulating film (thermal oxide film) located at the bottom of the trench is determined by using the (000-1) carbon surface having a high oxidation rate as the bottom of the trench. It has been proposed that the thickness be larger than the thickness of the portion located in the portion. Further, in the method proposed in Patent Document 2, after depositing a polysilicon film inside the trench, only a portion of the polysilicon film located at the bottom of the trench is selectively oxidized, and a gate insulating film is formed at the bottom of the trench. Is thickened. Thereafter, the polysilicon film left on the side surface of the trench is removed.

JP 7-326755 A JP 2007-242943 A

However, when the present inventors examined in detail, according to the methods proposed in

Patent Documents

1 and 2, the bottom of the trench is maintained while maintaining the thickness of the gate insulating film on the side surface of the trench (channel portion) at a predetermined thickness. It is difficult to sufficiently increase the thickness of the gate insulating film. Also, according to these conventional methods, it is difficult to independently control the thickness of the gate insulating film on the side surface of the trench and the bottom surface of the trench to an arbitrary thickness. Detailed description will be described later.

The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent dielectric breakdown of an insulating film due to electric field concentration at the bottom of a trench in a silicon carbide semiconductor device having a trench structure without deteriorating element characteristics. It is to suppress.

A semiconductor device according to the present invention includes a substrate, a silicon carbide layer disposed on the main surface of the substrate, a trench having a bottom surface and a side surface disposed on the silicon carbide layer, and a bottom surface and a side surface of the trench. And a conductive layer disposed in the trench and insulated from the silicon carbide layer by the insulating film. The conductive layer is made of silicon, and the insulating film is a bottom surface of the trench. And a first insulating layer disposed on a side surface, and a second insulating layer that is disposed between a portion of the first insulating layer located on the bottom surface of the trench and the conductive layer and is made of silicon. The second insulating layer is in contact with the conductive layer, and the thickness of the insulating film is three times or more on the side surface of the trench on the bottom surface of the trench.

The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device having a silicon carbide layer, wherein (A) a step of preparing a substrate having a silicon carbide layer formed on a main surface; Forming a trench having a bottom surface and a side surface in the silicon layer; (C) forming a first insulating layer on the bottom surface and side surface of the trench; and (D) a first layer on the first insulating layer. Forming a silicon film including a silicon layer and a second silicon layer formed on the first silicon layer and containing impurities at a higher concentration than the first silicon layer; and (E) performing a heat treatment to Including a step of forming a conductive layer by activating impurities contained in the silicon film, and a portion of the silicon film where the conductive layer is not formed becomes a second insulating layer, Is in contact with the conductive layer, Serial thickness of the first insulating layer and the second insulating layer and the formed insulating film, on the bottom surface of the trench is at least three times on the side of the trench.

According to the present invention, in the trench arranged in the silicon carbide layer, an insulating film thicker on the bottom surface of the trench than on the side surface of the trench can be formed between the conductive layer serving as the gate electrode and the silicon carbide layer. It becomes possible. Further, the thickness of the insulating film on the side surface of the trench and the bottom of the trench can be arbitrarily controlled independently of each other. Therefore, the electric field strength applied to the insulating film at the bottom of the trench can be reduced while maintaining the element characteristics, and the dielectric breakdown can be suppressed.

(A) And (b) is a typical sectional view and a top view of a semiconductor device of an embodiment by the present invention, respectively. FIGS. 4A to 4E are schematic process cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 4A to 4D are schematic process cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 4A to 4C are schematic process cross-sectional views for explaining another method for manufacturing the semiconductor device according to the embodiment of the present invention. It is typical sectional drawing of the other semiconductor device of embodiment by this invention. It is typical sectional drawing of one unit cell in the conventional MISFET which has a trench gate structure. (A) is sectional drawing which shows the enlarged structure of the broken line A in the conventional MISFET shown in FIG. 6, (b) and (c) are the OFF states (drain) in the pn junction part 30 and the MIS structure part 40, respectively. It is a figure which illustrates electric field strength distribution at the time of voltage application. It is a figure which shows the simulation result about the relationship between the thickness of the insulating film in the bottom face of a trench, and the electric field strength concerning an insulating film in the bottom face of a trench. It is a figure which shows the simulation result about the relationship between the ratio with respect to the thickness in the side surface of a trench of the thickness of the insulating film in a trench bottom face, and the strength of the electric field concerning a bottom face of a trench. (A) And (b) is typical process sectional drawing for demonstrating the further another manufacturing method of the semiconductor device of embodiment of this invention, respectively. FIGS. 4A to 4C are schematic process cross-sectional views for explaining still another method for manufacturing the semiconductor device according to the embodiment of the present invention.

As described above, according to the conventional methods proposed in

Patent Documents

1 and 2, it is difficult for the inventor to suppress the dielectric breakdown at the bottom of the trench while controlling the thickness of the gate insulating film on the side surface of the trench. I found out. Hereinafter, the examination result by this inventor is demonstrated.

FIG. 8 is a diagram showing a simulation result by the present inventor, and shows a relationship between the thickness of the gate insulating film (thermal oxide film) at the bottom of the trench and the electric field strength applied to the bottom of the trench. Here, it is calculated how the strength of the electric field applied to the bottom of the trench changes depending on the thickness of the gate insulating film at the bottom of the trench when 1200 V is applied to the drain voltage. The thickness of the gate insulating film in the channel portion on the side surface of the trench is 50 nm, 70 nm, and 90 nm. Further, the junction breakdown voltage between the drift region and the body region is set to 1200 V or more.

Usually, the breakdown electric field strength of the thermal oxide film is 10 MV / cm or more. However, when applied to an electronic device, the allowable electric field strength is set to be higher than the actual breakdown electric field in order to ensure reliability during long-term use. Is set to a sufficiently small value, for example, 3 to 4 MV / cm. That is, it is preferable to suppress the electric field strength applied to the vicinity of the bottom of the trench to at least 4 MV / cm or less.

As can be seen from the graph shown in FIG. 8, when the thickness of the gate insulating film on the side surface of the trench is 50 nm and the thickness of the gate insulating film at the bottom of the trench is set to 150 nm or more, the electric field strength applied to the bottom of the trench is 4 MV / cm. The following can be suppressed. When the thickness of the gate insulating film on the side surface of the trench is 70 nm, the thickness of the gate insulating film at the bottom of the trench is 210 nm or more, and when the thickness of the gate insulating film on the side surface of the trench is 90 nm, the thickness of the gate insulating film at the bottom of the trench. Is set to 270 nm or more, the electric field strength applied to the bottom of the trench can be suppressed to 4 MV / cm or less. As described above, the thickness of the gate insulating film that can reduce the electric field strength applied to the bottom of the trench to a predetermined value or less varies depending on the thickness of the gate insulating film on the side surface of the trench.

Therefore, the present inventor has normalized the thickness of the gate insulating film at the bottom of the trench with the thickness of the gate insulating film on the side of the trench, and examined the relationship between the normalized value and the electric field strength applied to the bottom of the trench.

The electric field strength at the bottom of the trench when a drain voltage of 1200 V was applied to a MISFET having a trench structure with an avalanche breakdown voltage of 1200 V or more at the junction of the drift region and the body region was calculated by simulation.

FIG. 9 is a diagram showing a simulation result by the present inventor. The horizontal axis represents the normalized value, that is, the ratio of the thickness of the gate insulating film (thermal oxide film) at the bottom of the trench to the thickness of the gate insulating film at the side of the trench (the thickness of the thermal oxide film at the bottom of the trench / the side of the trench). The thickness of the thermal oxide film) R), and the vertical axis represents the electric field strength applied to the bottom of the trench. Here, it is calculated how the strength of the electric field applied to the bottom of the trench varies depending on the thickness ratio R of the gate insulating film when 1200 V is applied to the drain voltage. In the calculation, the thickness of the gate insulating film in the channel portion on the side surface of the trench is 50 nm, 70 nm, and 90 nm. In FIGS. 8 and 9, black circles indicate simulation results when the thickness of the gate insulating film in the channel portion on the trench side surface is 50 nm, and triangles indicate results when the thickness of the gate insulating film in the channel portion on the trench side surface is 70 nm. As a result of the simulation, white circles show the simulation results when the thickness of the gate insulating film in the channel portion on the side surface of the trench is 90 nm.

The results shown in FIG. 9 indicate that the electric field strength exceeds 9 MV / cm when the thickness of the gate insulating film at the bottom of the trench is approximately the same as the thickness of the gate insulating film on the side surface of the trench. It can be seen that an electric field of 5 MV / cm is applied to the bottom of the trench even when the thickness of the gate insulating film at the bottom of the trench is set to twice the thickness on the side of the trench. It can also be seen that the electric field strength applied to the bottom of the trench can be suppressed to 4 MV / cm or less by setting the thickness of the gate insulating film at the bottom of the trench to 3 times or more the thickness of the side surface of the trench (channel portion). Therefore, it was confirmed that the electric field strength applied to the bottom of the trench can be reduced to 4 MV / cm or less by setting the thickness of the gate insulating film to 3 times or more of the side surface of the trench at the bottom of the trench. From the above results, it is possible to prevent the gate insulating film from being destroyed even when a drain voltage of 1200 V is applied by setting the thickness of the gate insulating film to three times or more of the side surface of the trench at the bottom of the trench. it can.

In the method proposed in Patent Document 1, the thickness of the gate insulating film on the bottom surface of the trench is selectively increased by utilizing the plane orientation dependence of the oxidation rate of silicon carbide. In this method, it is difficult to make the thickness of the gate insulating film significantly larger (for example, three times or more) than the side surface of the trench at the bottom of the trench. In addition, the thickness of the gate insulating film at the bottom and side surfaces of the trench cannot be controlled independently. For this reason, it is difficult to relax the electric field applied to the bottom of the trench to a predetermined value or less while ensuring the transistor characteristics, and there is a possibility that the dielectric breakdown of the gate insulating film cannot be reliably suppressed.

Further, according to the method proposed in Patent Document 1, in order to use the (000-1) carbon surface having a high oxidation rate as the bottom surface of the trench, the main surface for forming a device is the (000-1) carbon surface. It is necessary to. However, when the epitaxial film is grown on the carbon surface, there is a problem that it is difficult to control the growth conditions as compared with the silicon surface. For this reason, it is difficult not only to control the concentration and thickness of the epitaxial film, but also to form a film with few crystal defects (low defect layer). Therefore, it is difficult to form a drift region and a body region, and there is a possibility that a device having desired element characteristics cannot be easily manufactured.

In the method proposed in Patent Document 2, the process is complicated, and a film obtained by oxidizing a polysilicon film is used as a gate insulating film. There is a problem that it becomes lower than the insulating film formed by oxidation. Therefore, in order to suppress dielectric breakdown with certainty, it is necessary to oxidize a thicker polysilicon film. However, if the polysilicon film is thick, it is difficult to form a thermal oxide film, so it is difficult to make the thickness of the gate insulating film at the bottom of the trench significantly larger than the thickness at the side of the trench.

Based on the knowledge obtained from the various examination results described above, the inventor makes the thickness of the gate insulating film at the bottom of the trench larger than the thickness of the gate insulating film on the side surface of the trench without complicating the process. The present inventors have studied the structure of a semiconductor device (for example, three times or more), and have reached the present invention.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings. The semiconductor device of this embodiment is a silicon carbide MISFET having a trench gate structure.

FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 of the present embodiment. The semiconductor device 100 includes a plurality of unit cells arranged two-dimensionally.

1A is a cross-sectional view of a unit cell 100U in the semiconductor device 100. FIG. FIG. 1B is a plan view showing an example of the arrangement of unit cells 100U on the surface of the silicon carbide layer of semiconductor device 100. FIG. FIG. 1A is a cross-sectional view taken along the line I-I ′ of FIG.

The unit cell 100U of the semiconductor device 100 has a substrate 1 containing silicon carbide and a silicon carbide layer 2 made of silicon carbide and disposed on the surface (main surface) of the substrate 1. Silicon carbide layer 2 includes a first conductivity type (here, n-type) drift region 2d formed on the main surface of substrate 1, and a second conductivity type (here, p-type) formed on drift region 2d. ) Body region 3. A source region 4 of the first conductivity type (n-type) is disposed in a part of the surface region of the body region 3. In the illustrated example, the source region 4 is surrounded by the body region 3.

The silicon carbide layer 2 is provided with a trench 12 that penetrates the source region 4 and the body region 3 and reaches the drift region 2d. An insulating film 11 is disposed on the bottom and side surfaces of the trench 12. A conductive layer functioning as the gate electrode 8 is disposed in the trench 12. Gate electrode (conductive layer) 8 and silicon carbide layer 2 are insulated by insulating film 11.

In the present embodiment, the insulating film 11 includes a first insulating layer 6 disposed on the bottom surface and side surfaces of the trench 12, and a second insulating layer 7 disposed on the first insulating layer 6 at the bottom of the trench 12. It is constituted by. The second insulating layer 7 is disposed between the portion of the first insulating layer 6 located on the bottom surface of the trench 12 and the gate electrode 8.

The first insulating layer 6 may be a thermal oxide film, a nitride film, an oxide film, or a laminated film including at least one of them. The second insulating layer 7 and the gate electrode 8 are made of silicon. The gate electrode 8 and the second insulating layer 7 may be integrally formed using the same silicon film. In this embodiment, the gate electrode 8 is a doped polysilicon layer containing phosphorus at a concentration of 1 × 10 ²⁰ cm ⁻³ or more. The second insulating layer 7 is a polysilicon layer that does not contain impurities or contains the same impurities (phosphorus in this case) as the gate electrode 8 at a concentration of 1 × 10 ¹⁸ cm ⁻³ or less. In the present specification, a silicon layer that is not doped with impurities or has an extremely low impurity concentration (1 × 10 ¹⁸ cm ⁻³ or less) is referred to as an “undoped silicon layer”.

The semiconductor device 100 also includes a source electrode 10 provided on the silicon carbide layer 2 and a drain electrode 9 formed on the back surface of the substrate 1. Source electrode 10 is electrically connected to source region 4 and body region 3. An interlayer insulating film (not shown) is formed on the source electrode 10 and the gate electrode 8. A source wiring (not shown) is provided on the interlayer insulating film. The source wiring is electrically connected to the source electrode 10 in a contact hole formed in the interlayer insulating film.

According to the present embodiment, the insulating film 11 including the first and second insulating

layers

6 and 7 is disposed between the side and bottom surfaces of the trench 12 and the gate electrode 8. The insulating film 11 is thicker on the bottom surface of the trench 12 than on the side surface of the trench 12. For example, the thickness of the insulating film 11 on the bottom surface of the trench 12 can be three times or more the thickness of the insulating film 11 in the surface region (channel portion) of the body region 3 exposed on the side surface of the trench 12. For this reason, the electric field strength generated in the insulating film 11 at the bottom of the trench 12 can be reduced without deteriorating the transistor characteristics, and the dielectric breakdown can be suppressed.

In the present embodiment, the second insulating layer 7 is selectively disposed only at the bottom of the trench 12, and the first insulating layer 6 is in contact with the gate electrode 8 on the side surface of the trench 12. The upper surface of the second insulating layer 7 is preferably in contact with the lower surface of the gate electrode 8. When the upper surface of the second insulating layer 7 is in contact with the gate electrode 8, the interface between the gate electrode 8 and the second insulating layer 7 is preferably deeper than the interface between the drift region 2 d and the body region 3. . In other words, the second insulating layer 7 is preferably not disposed on a portion (channel portion) exposed on the side surface of the trench 12 in the surface of the body region 3. As a result, only the first insulating layer 6 can be interposed as a gate insulating film between the channel portion and the gate electrode 8. Therefore, by controlling the thickness of the first insulating layer 6, a gate insulating film having a desired thickness can be obtained, and characteristics such as a threshold voltage can be ensured. On the other hand, in addition to the first insulating layer 6, the second insulating layer 7 is disposed on the bottom surface of the trench 12. Therefore, the thickness of the insulating film 11 on the bottom surface of the trench 12 (the total thickness of the first and second insulating layers 6 and 7) is set to the thickness of the insulating film 11 on the side surface of the trench 12 (the first insulating layer 6). Only thicker). If the thickness of the first insulating layer 6 is substantially the same on the bottom surface and the side surface of the trench 12, the thickness of the insulating film 11 increases by the thickness of the second insulating layer 7 on the side surface of the trench 12. Therefore, by controlling the thickness of the second insulating layer 7, the thickness of the insulating film 11 disposed on the bottom surface of the trench 12 can be adjusted, so that the dielectric breakdown can be more effectively suppressed. . If the first insulating layer 6 is a thermal oxide film, the thickness of the first insulating layer 6 is not uniform due to the plane orientation dependence of the oxidation rate. In that case, the thickness of the second insulating layer 7 may be set in consideration of the non-uniformity of the thickness of the first insulating layer 6 due to the plane orientation. In this way, the thickness of the insulating film on the side surface (particularly the channel portion) of the trench 12 and the thickness of the insulating film on the bottom surface of the trench 12 can be set independently and arbitrarily.

In the manufacturing process to be described later, the gate electrode 8 is formed by doping impurities only in a part of the silicon film, and the part of the silicon film that is not doped with impurities (the part that remains undoped silicon) is subjected to the second insulation. Leave as layer 7. When such a process is used, the second insulating layer 7 may be formed also on the channel portion on the side surface of the trench 12 depending on the state of impurity diffusion. Even in such a case, since the second insulating layer 7 is much thinner on the channel portion than on the bottom surface of the trench 12, the above-described effects can be obtained.

The thickness of the insulating film constituted by the first insulating layer 6 and the second insulating layer 7 is three times or more on the side surface of the trench 12 (particularly on the channel portion) and on the bottom surface of the trench 12. More preferably, it is 5 times or more. Thereby, as described with reference to FIGS. 8 and 9, the electric field strength applied to the insulating film at the bottom of the trench 12 can be more effectively reduced.

In this embodiment, it is preferable that the (0001) silicon surface of the substrate 1 is a main surface, and the silicon carbide layer 2 is formed on the main surface. In the conventional semiconductor device, when the silicon surface is the main surface, there is a problem that the thickness of the insulating film (thermal oxide film) on the bottom surface of the trench, which is the silicon surface, is smaller than the thickness of the thermal oxide film on the side surface of the trench. It was. On the other hand, according to the present embodiment, the thickness of the insulating film located on the bottom surface of the trench can be made larger (for example, three times or more) than the thickness of the insulating film located on the side surface of the trench, so that a more remarkable effect can be obtained.

In the above description, the configuration of the semiconductor device 100 of the present embodiment has been described by taking an n-channel type MISFET as an example. However, the semiconductor device 100 may be a p-channel type MISFET. In the p-channel type MISFET, the conductivity type of the SiC substrate 1, the drift region 2d, and the source region 4 is p-type, and the conductivity type of the body region 3 is n-type.

Next, an example of a method for manufacturing the semiconductor device 100 of this embodiment will be described with reference to the drawings.

FIGS. 2A to 2E and FIGS. 3A to 3D are schematic process cross-sectional views for explaining an example of a method for manufacturing the semiconductor device 100, respectively.

First, as shown in FIG. 2A, silicon carbide is epitaxially grown on the main surface of the substrate 1, so that a drift region 2 d of a first conductivity type (here, n-type) and a second conductivity type (here) Then, p-type) body region 3 is formed in this order, and silicon carbide layer 2 is obtained. Thereafter, the source region 4 is formed in the body region 3.

As the substrate 1, for example, a low-resistance n-type SiC substrate containing nitrogen at a concentration of 3 × 10 ¹⁸ cm ⁻³ can be used. The drift region 2d is doped with nitrogen at a concentration of 8 × 10 ¹⁵ cm ⁻³ , for example. The thickness of the drift region 2d is, for example, 12 μm. Note that the thickness and concentration of the drift region 2d are determined by a desired breakdown voltage, and are not limited to the above-described thickness and concentration.

The body region 3 is doped with aluminum at a concentration of 2 × 10 ¹⁸ cm ⁻³ , for example. The thickness of the body region 3 is 1 μm, for example.

Here, the body region 3 is formed by epitaxial growth, but may be formed by ion implantation instead. Specifically, after forming n-type silicon carbide layer 2 by epitaxial growth, body region 3 may be formed by ion-implanting p-type impurities into the surface region. In that case, the region of silicon carbide layer 2 where the p-type impurity is not implanted becomes drift region 2d.

The source region 4 is formed by ion implantation, for example. First, a mask layer (not shown) made of a silicon oxide film is disposed on a predetermined region of silicon carbide layer 2. Next, using the mask layer as an implantation mask, n-type impurity ions (for example, nitrogen ions) are implanted into the portion of the body region 3 where the source region is to be formed. Here, for example, the acceleration energy is 100 keV and the dose is 5 × 10 ¹⁵ cm ⁻² . After removing the mask layer, annealing is performed in an inert gas atmosphere at a temperature of, for example, 1700 ° C. for about 30 minutes. Thereby, the implanted impurity ions are activated and the source region 4 is obtained.

Next, as shown in FIG. 2B, a trench (concave portion) 12 is formed in the silicon carbide layer 2 so as to penetrate the source region 4 and the body region 3 and have a bottom surface in the drift region 2d. In this embodiment, first, an Al film (not shown) is formed on a part of the source region 4 via an oxide film. Next, using this Al film as a mask, trenches (depth: 1.5 μm, width: 1 μm, for example) 12 are formed in the silicon carbide layer 2 by reactive ion etching (RIE). In the illustrated example, the side surface of the trench 12 is substantially perpendicular to the main surface of the substrate 1, but the trench 12 may have a side surface that is inclined with respect to the normal direction of the main surface of the substrate 1 ( Tapered shape).

Subsequently, as shown in FIG. 2C, the first insulating layer 6 and the silicon film 16 are formed in this order in the trench 12. In the illustrated example, the first insulating layer 6 and the silicon film 16 are formed on the upper surface of the silicon carbide layer 2 and in the trench 12, but may be formed at least on the bottom surface and side surfaces of the trench 12.

In this embodiment, a thermal oxide film is formed as the first insulating layer 6. Specifically, heat treatment is performed for 3 hours at a temperature of 1200 ° C. in a dry oxidation atmosphere. Thereby, the surface of silicon carbide layer 2 (including portions exposed at the bottom and side surfaces of trench 12) is thermally oxidized, and first insulating layer 6 is obtained. The heat treatment condition is controlled so that the thickness of the first insulating layer 6 is, for example, 70 nm on the side surface of the trench 12. At this time, the thickness of the first insulating layer 6 on the bottom surface of the trench 12 may be different from the thickness on the side surface of the trench 12 due to the surface orientation dependence of the oxidation rate. On the bottom surface of the trench 12, the thickness of the first insulating layer 6 is, for example, 50 to 100 nm although it depends on the plane orientation of the main surface.

Note that the first insulating layer 6 may be formed by a deposition method such as a CVD method instead of the thermal oxidation. Further, as the first insulating layer 6, a nitride film, an oxynitride film, or a laminated film including at least one of them may be formed. In the heat treatment process to be described later, since impurities are difficult to diffuse into these films, film quality deteriorates due to the diffusion of impurities into the first insulating layer 6 (for example, a decrease in passing charge amount Qbd until the oxide film is destroyed). Can be prevented.

The silicon film 16 may be an undoped polysilicon film or an undoped amorphous silicon film. Here, an undoped polysilicon film (thickness: for example, 800 nm) is formed by LP-CVD on the upper surface of silicon carbide layer 2 and inside trench 12. At this time, the inside of the trench 12 is filled with the silicon film 16 so that no void is generated inside the trench 12.

Subsequently, as shown in FIG. 2D, impurity ions (here, phosphorus ions) are implanted into a part of the silicon film 16. Here, phosphorus ions are implanted into the entire surface of the substrate 1 from above the substrate 1. The acceleration energy is set to 60 keV, for example, and the dose is set to 5 × 10 ¹⁵ cm ⁻² . Thereby, an impurity diffusion layer (also referred to as a second silicon layer) 8a is formed in a part of the silicon film 16. A portion of the silicon film 16 that is deeper than the impurity diffusion layer 8a and into which impurity ions are hardly implanted remains as an undoped silicon layer (also referred to as a first silicon layer) 7a. The implantation conditions are preferably adjusted so that a thin undoped silicon layer remains not only inside trench 12 but also between impurity diffusion layer 8 a and the upper surface of silicon carbide layer 2. Instead of ion implantation, the impurity diffusion layer 8a may be formed using thermal diffusion.

Next, as shown in FIG. 2E, a resist mask 21 having an opening that is slightly smaller than the opening of the trench 12 is formed on the impurity diffusion layer 8a. Thereafter, impurity ions (here, phosphorus ions) are implanted from above the substrate using the resist mask 21 as an implantation mask. The acceleration energy is set larger than the acceleration energy in the implantation step shown in FIG. 2D, for example, 300 keV. Further, to set the dose, approximately the same amount (e.g., 5 × 10 ¹⁵ cm ^-2) and a dose of the implantation step illustrated in Figure 2 (d). As a result, a further impurity diffusion layer (also referred to as a third silicon layer) 8b is formed in the trench 12 at a position deeper than the impurity diffusion layer 8a.

Thus, the impurity diffusion layers 8a and 8b having a range (Rp) of about 0.4 μm from the surface (the upper surface of the silicon film 16) and a junction depth (Rp + 3ΔRp) of about 0.7 μm from the surface are formed on the silicon film 16. Is formed. A portion of the silicon film 16 where the impurity diffusion layers 8a and 8b are not formed remains as an undoped silicon layer 7b. Undoped silicon layer 7 b is thick at the bottom of trench 12 and thin on the side surface of trench 12 and the top surface of silicon carbide layer 2.

After removing the resist mask 21, heat treatment for diffusing and activating impurities (phosphorus) in the silicon film 16 is performed. Here, as the heat treatment, an RTA (Rapid Thermal Anneal) process is performed in an inert gas atmosphere at a temperature of 1000 ° C. for 60 seconds. Thereby, as shown in FIG. 3A, phosphorus in the impurity diffusion layers 8a and 8b is diffused to become an active layer (conductive layer) functioning as the gate electrode 8. A portion of the silicon film 16 where phosphorus is not diffused (or a portion where the phosphorus concentration is 10 ¹⁸ cm ⁻³ or less) becomes the second insulating layer 7 made of undoped polysilicon. In this way, the insulating film 11 constituted by the first insulating layer 6 and the second insulating layer 7 is obtained.

In the illustrated example, phosphorus diffuses into the upper surface of the silicon carbide layer 2 and the channel portion of the trench 12 in the silicon film 16, and a conductive layer in contact with the first insulating layer 6 is obtained as the gate electrode 8. Further, undoped polysilicon selectively remains at the bottom of the trench 12 and becomes the second insulating layer 7. The interface between the second insulating layer 7 and the gate electrode 8 is deeper than the interface between the drift region 2 d and the body region 3. For this reason, the second insulating layer 7 is not formed on the channel portion on the side surface of the trench 12. The thickness of the second insulating layer 7, that is, the distance from the interface between the second insulating layer 7 and the gate electrode 8 to the bottom surface of the trench 12 is, for example, 350 nm. In the silicon film 16, the impurity concentration decreases as the depth increases. However, when the gradient of the concentration profile is relatively gentle, the interface between the second insulating layer 7 and the gate electrode 8 may not be clearly confirmed. is there. In such a case, the portion of the silicon film 16 where the impurity concentration is 1 × 10 ¹⁸ cm ⁻³ or less is the “second insulating layer 7”, and the portion where the impurity concentration is higher than 1 × 10 ¹⁸ cm ⁻³ is the gate. This is referred to as electrode 8 ”.

Depending on the conditions for doping impurities and the heat treatment conditions, the diffusion distance of the impurities becomes small, and the conductive layer (gate electrode 8) and the first insulating layer 6 are formed on the upper surface of the silicon carbide layer 2 or on the channel portion of the trench 12. In some cases, the undoped silicon layer (second insulating layer 7) remains thin. Even in such a case, the effect of the present invention can be obtained if the thickness of the second insulating layer 7 on the channel portion is sufficiently smaller than the thickness at the bottom of the trench 12. However, it is preferable that the second insulating layer 7 is not formed at least on the channel portion.

Subsequently, as shown in FIG. 3B, a resist mask 22 is formed on the gate electrode 8 so as to cover the trench 12. Thereafter, as shown in FIG. 3C, the gate electrode 8 is patterned by dry etching using the resist mask 22 as an etching mask.

After removing the resist mask 22, as shown in FIG. 3D, a source electrode (source / body electrode) is formed on the upper surface of the silicon carbide layer 2 so as to straddle both the body region 3 and the source region 4. 10 is formed. Further, the drain electrode 9 is formed on the surface (back surface) opposite to the main surface of the substrate 1. In this way, the semiconductor device 100 is obtained.

In such a semiconductor device 100, between the bottom surface of the trench 12 and the gate electrode 8, the first insulating layer 6 having a thickness of about 50 to 100 nm and the second insulating layer 7 which is an undoped polysilicon layer are provided. Is formed. The total thickness of these insulating

layers

6 and 7 is, for example, 400 nm or more. Thus, since a thicker insulating film than the conventional one can be arranged at the bottom of the trench 12, the electric field strength generated at the bottom of the trench 12 can be suppressed to 4 MV / cm or less, for example.

In the above method, after an undoped silicon film is provided inside the trench 12, a part of the silicon film is doped with impurities to form the gate electrode 8, and an undoped silicon film is selectively formed at the bottom of the trench 12. leave. As a result, a thicker insulating film than the conventional one can be disposed at the bottom of the trench 12 without increasing the number of manufacturing steps. In addition, the thickness of the insulating film at the bottom of the trench 12 can be controlled separately from the thickness of the insulating film disposed on the channel portion of the trench 12. Therefore, dielectric breakdown at the bottom of the trench 12 can be suppressed while ensuring desired transistor characteristics.

Also, according to this method, first, the silicon film 16 is doped with impurities from the entire upper surface of the silicon film 16 (FIG. 2D), and then the portion of the silicon film 16 located in the trench 12 is applied. Then, the impurity is doped (FIG. 2E). When the impurity is doped in two steps as described above, an undoped silicon layer having a desired thickness can be more reliably left between the impurity diffusion layers 8 a and 8 b and the silicon carbide layer 2. Therefore, in the subsequent heat treatment, it is possible to more reliably prevent impurities from diffusing into the first insulating layer 6 that becomes the gate insulating film.

In the above method, the impurity diffusion layer 8a is formed in the silicon film by ion implantation in the step shown in FIG. 2 (d). Instead, using silicon (PH ₃ ) or POCl ₃ (pockle), The impurity diffusion layer 8 a may be formed by thermally diffusing phosphorus from the surface of the film 16. Subsequent steps may be the same as those described above. Specifically, as shown in FIG. 2E, impurity ions may be implanted into a portion of the silicon film 16 located in the trench 12.

In the above method, the impurity diffusion layers 8a and 8b are formed in two stages. However, the impurity diffusion layers 8a and 8b can be formed in one stage without performing the ion implantation process corresponding to the process shown in FIG. Even when the ion implantation step shown in FIG. 2E is not performed, the gate electrode 8 is formed by diffusing phosphorus in the impurity diffusion layer 8a deeper than the body region 3 in the subsequent activation process (heat treatment). it can. The phosphorus diffusion distance can be adjusted by phosphorus implantation conditions such as ion implantation energy and ion implantation amount, temperature and time of activation treatment, and the like. Alternatively, the impurity diffusion layer may be formed in one step by the method described below.

4A to 4C are process cross-sectional views illustrating another method for manufacturing the semiconductor device 100, respectively.

After forming silicon carbide layer 2 on substrate 1 by the same method as described above with reference to FIGS. 2A and 2B, trench 12 is formed in silicon carbide layer 2.

Next, as shown in FIG. 4A, the first insulating layer 6 and the silicon film 26 are formed inside the trench 12 and on the upper surface of the silicon carbide layer 2. Although a thermal oxide film may be formed as the first insulating layer 6, it is preferable here to form a nitride film, an oxynitride film, or a laminated film including at least one of them by a CVD method. In the above-described method, the silicon film 16 (FIG. 2C) having a substantially flat upper surface is formed. Here, however, a silicon film 26 having a recess is formed on the trench 12.

Thereafter, as shown in FIG. 4B, an impurity diffusion layer (second silicon layer) 8a is formed in a region from the surface of the silicon film 26 to a predetermined depth by ion implantation or thermal diffusion. At this time, a part of the impurity diffusion layer 8 a is also formed in the trench 12. A portion of the silicon film 26 where the impurity diffusion layer 8a is not formed becomes an undoped silicon layer (first silicon layer) 7a.

Next, as shown in FIG. 4C, heat treatment is performed to activate the impurities contained in the silicon film 26, thereby forming an impurity active layer that becomes the gate electrode 8. The heat treatment conditions may be the same as the heat treatment conditions described above with reference to FIG. At this time, if the first insulating layer 6 is a thermal oxide film (SiO ₂ film), impurities easily diffuse into the first insulating layer 6 particularly near the opening of the trench 12. On the other hand, when a film containing nitrogen such as a nitride film or an oxynitride film is used as the first insulating layer 6, the impurity (phosphorus) in the impurity diffusion layer 8 a is difficult to diffuse into the first insulating layer 6. Therefore, it is possible to prevent the characteristics (for example, Qbd) of the first insulating layer 6 from being deteriorated. Subsequent steps are the same as those described above with reference to FIGS. 3B to 3D.

According to the method shown in FIG. 4, it suffices to dope impurities from the entire surface of the silicon film 26, and it is not necessary to perform a step of selectively doping impurities only in a portion located in the trench 12. For this reason, since the process of forming the resist mask used as an implantation mask can be omitted, the number of manufacturing processes can be reduced.

The semiconductor device manufacturing method of the present invention is not limited to the method described above with reference to FIGS.

In the above-described method, an undoped polysilicon film is formed as the

silicon films

16 and 26. Alternatively, a polysilicon film doped with impurities (for example, phosphorus) only in the surface layer may be formed. Further, an amorphous silicon film may be formed instead of the polysilicon film. When an amorphous silicon film is used as the

silicon films

16 and 26, the impurities doped in the amorphous silicon film are diffused and activated by the heat treatment shown in FIG. 3A or FIG. Crystallized. As a result, the gate electrode 8 which is a doped polysilicon layer and the second insulating layer 7 which is an undoped polysilicon layer are obtained. As the heat treatment conditions, for example, an RTA treatment for 60 seconds may be performed at a temperature of 1000 ° C. in an inert gas atmosphere. In the above method, the trench 12 having a depth of 1.5 μm is formed. However, the depth of the trench 12 reaches the drift region 2 d and an insulating film having a desired thickness can be formed on the bottom surface of the trench 12. There is no particular limitation as long as the depth is set.

Further, the thickness of the

silicon films

16 and 26 is not particularly limited, and may be set so that the entire inside of the trench 12 can be buried. The thickness of

such silicon films

16 and 26 varies depending on the width of the trench 12, but is generally preferably 50 to 80% of the width of the trench 12. The width of the trench 12 refers to the maximum width of the opening of the trench 12 when viewed from the normal direction of the main surface of the substrate 1.

Furthermore, the ion implantation conditions for forming the impurity diffusion layers 8a and 8b, the heat treatment conditions for activating the impurities in the impurity diffusion layers 8a and 8b to form the active layer (gate electrode 8), and the like are also described above. The conditions are not limited to the exemplified conditions. In particular, the acceleration energy at the time of implanting impurity ions, the temperature and time of the heat treatment for activation are as follows: an undoped silicon layer that becomes the second insulating layer 7 and an active layer (doped silicon layer) that becomes the gate electrode May be set as appropriate so that the interface between and the drift region 2d and the body region 3 is deeper. In the present embodiment, it is preferable to perform RTA as a heat treatment for activation. According to RTA, an undoped silicon layer can be left thicker (for example, 200 nm or more) than other heat treatment methods (for example, a vertical diffusion furnace).

The method for forming the silicon film is not limited to the method described above. The present embodiment includes a first silicon layer disposed on the bottom and side surfaces of the trench, and a second silicon layer disposed on the first silicon layer and containing impurities at a higher concentration than the first silicon layer. A silicon film may be formed. When such a silicon film is formed, a conductive layer functioning as a gate electrode can be obtained from part of the silicon film by activating impurities contained in the silicon film by heat treatment.

In the above-described method, the impurity concentration of the

silicon films

16 and 26 is partially increased by implanting impurity ions into part of the

silicon films

16 and 26, but instead, on the first silicon layer having a low impurity concentration. In addition, a second silicon layer having a higher impurity concentration than the first silicon layer may be deposited.

10A and 10B are process cross-sectional views illustrating an example of another method for manufacturing the semiconductor device of the present embodiment. In this example, a silicon film is formed by depositing a doped silicon layer on an undoped silicon layer.

First, after silicon carbide layer 2 is formed on substrate 1 by the same method as described above with reference to FIGS. 2A and 2B, trench 12 is formed in silicon carbide layer 2.

Next, as shown in FIG. 10A, a silicon layer (first silicon layer) 36 is formed inside the trench 12 and on the upper surface of the silicon carbide layer 2. Thereafter, a silicon layer 36 and a doped silicon layer (second silicon layer) 37 containing impurities (for example, phosphorus) at a higher concentration than the silicon layer 36 are formed in this order. The impurity concentration of the doped silicon layer 37 is, for example, 8 × 10 ²⁰ cm ⁻³ . In this way, the silicon film 46 is obtained.

It is preferable that the silicon layer 36 and the doped silicon layer 37 are formed continuously (in situ). In the illustrated example, the upper surfaces of the silicon layer 36 and the doped silicon layer 37 have recesses on the trench 12, but the upper surfaces of these

layers

36 and 37 may be substantially flat.

Thereafter, when heat treatment is performed, as shown in FIG. 10B, a part of the impurity (phosphorus) contained in the doped silicon layer 37 diffuses into the silicon layer 36 and is contained in the silicon film 46. The impurity is activated, and an impurity active layer (conductive layer) to be the gate electrode 8 is obtained. The remaining portion of the silicon film 46 as the insulating layer becomes the second insulating layer 7. The heat treatment conditions may be the same as the heat treatment conditions described above with reference to FIG.

Alternatively, as shown in FIG. 11A, after a silicon film 46 including the silicon layer 36 and the doped silicon layer 37 is formed, phosphorus ions are formed on a part of the silicon layer 36 as shown in FIG. An impurity diffusion layer (also referred to as a third silicon layer) 38 may be formed by implanting. The impurity diffusion layer 38 is formed at a position deeper than the doped silicon layer 37. The injection conditions may be the same as the injection conditions described above with reference to FIG.

Subsequently, by performing heat treatment, as shown in FIG. 11C, a part of phosphorus contained in the impurity diffusion layer 38 diffuses into the silicon layer 36, and in these

layers

36, 37, 38, The contained phosphorus is activated. Thereby, a conductive layer to be the gate electrode 8 is obtained from a part of the silicon film 46. The remaining portion of the silicon film 46 as the insulating layer becomes the second insulating layer 7.

In the above method, a 4H—SiC substrate is used as the substrate 1, but other crystal planes or other polytype SiC substrates may be used. When a 4H—SiC substrate is used, the silicon carbide layer 2 may be formed on the Si surface, the drain electrode 9 may be formed on the C surface, the silicon carbide layer 2 on the C surface, and the drain electrode 9 on the Si surface. May be formed.

In the cross-sectional views shown in FIGS. 2 to 4, 10, and 11, the side surface and the bottom surface of the trench 12 intersect perpendicularly to form a corner (corner portion), but the trench 12 has a tapered shape. However, the side surface and the bottom surface do not have to intersect perpendicularly. Even if the corner is rounded by etching or a process other than etching, the same effect as described above can be obtained.

The configuration of the semiconductor device of the present invention is not limited to the configuration shown in FIG. In semiconductor device 100 shown in FIG. 1, silicon carbide layer 2 includes body region 3, source region 4, and drift region 2d, but may further include other components. For example, a portion of the drift region 2d located near the bottom surface of the trench 12 may have a second conductivity type impurity layer for electric field relaxation. A channel layer may be formed on the side surface of the trench 12.

The semiconductor device 100 is a MISFET having an inverted channel structure, but the present invention is also applied to a MISFET having a storage channel structure, and the same effect as described above can be obtained.

FIG. 5 is a cross-sectional view illustrating a MISFET having a storage channel structure. For the sake of simplicity, the same components as those in FIG.

In the unit cell 200U of the semiconductor device shown in FIG. 5, a channel layer 18 made of silicon carbide is formed on the bottom and side surfaces of the trench 12. Channel layer 18 is a silicon carbide layer of the first conductivity type formed by, for example, epitaxial growth. The first insulating layer 6 may be formed by thermally oxidizing the surface portion of the channel layer 18. Other configurations are the same as those shown in FIG.

Furthermore, the present invention is not limited to a vertical MISFET, and can be applied to various semiconductor devices having a structure in which an electrode is disposed on a silicon carbide layer via an insulating film. For example, in the above embodiment, a MISFET is manufactured using a silicon carbide substrate having the same conductivity type as the silicon carbide layer (drift region). However, using a silicon carbide substrate having a conductivity type different from that of the silicon carbide layer (drift region). An insulated gate bipolar transistor (Insulated Gate Bipolar Transistor: IGBT) can also be manufactured.

The present invention can be widely applied to semiconductor devices using a silicon carbide layer. In particular, it is suitably used for a power SiC device such as a power MISFET and various control devices and driving devices provided with the device.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Silicon carbide layer 2d Drift region 3 Body region 4 Source region 5 Gate insulating film 6 First insulating layer 7

Second insulating layer

7a, 7b Undoped silicon layer 8

Gate electrode

8a, 8b Impurity diffusion layer 9 Drain electrode 10 Source electrode 11 Insulating film 12

Trench

16, 26, 46 Silicon film 18

Channel layer

21, 22 Resist mask

Claims

A substrate,
A silicon carbide layer disposed on a main surface of the substrate;
A trench having a bottom surface and a side surface disposed in the silicon carbide layer;
Insulating films disposed on the bottom and side surfaces of the trench;
A conductive layer disposed in the trench and insulated from the silicon carbide layer by the insulating film;
The conductive layer is made of silicon;
The insulating film is disposed between a first insulating layer disposed on a bottom surface and a side surface of the trench, a portion of the first insulating layer located on the bottom surface of the trench, and the conductive layer, and is made of silicon. A second insulating layer configured;
The second insulating layer is in contact with the conductive layer;
The thickness of the said insulating film is a semiconductor device which is 3 times or more on the side surface of the said trench on the bottom face of the said trench.
The silicon carbide layer includes a first conductivity type drift region and a second conductivity type body region disposed on the drift region;
The semiconductor device according to claim 1, wherein the trench penetrates the body region and has the bottom surface inside the drift region.
The upper surface of the second insulating layer is in contact with the lower surface of the conductive layer, and the interface between the second insulating layer and the conductive layer is deeper than the interface between the body region and the drift region on the side surface of the trench. The semiconductor device according to claim 2, which is in a position.
The semiconductor device according to claim 1, wherein the first insulating layer is in contact with the conductive layer on a side surface of the trench.
5. The semiconductor device according to claim 1, wherein a thickness of the second insulating layer is three times or more a thickness of the first insulating layer.
6. The semiconductor device according to claim 1, wherein the first insulating layer includes at least one of a nitride film and an oxynitride film.
The conductive layer is a silicon layer doped with impurities at a concentration higher than 1 × 10 18 cm −3 , and the second insulating layer does not contain the impurities, or 1 × 10 18 cm −3. The semiconductor device according to claim 1, which is a silicon layer containing the impurity at the following concentration.
The semiconductor device according to claim 1, wherein the substrate is a silicon carbide substrate, and the main surface is a (0001) silicon surface.
A method of manufacturing a semiconductor device having a silicon carbide layer,
(A) preparing a substrate having a silicon carbide layer formed on the main surface;
(B) forming a trench having a bottom surface and a side surface in the silicon carbide layer;
(C) forming a first insulating layer on the bottom and side surfaces of the trench;
(D) A silicon film including a first silicon layer on the first insulating layer and a second silicon layer formed on the first silicon layer and containing impurities at a higher concentration than the first silicon layer. Forming, and
(E) performing a heat treatment to activate impurities contained in the silicon film to form a conductive layer, and a portion of the silicon film where the conductive layer is not formed becomes a second insulating layer; Contains
The second insulating layer is in contact with the conductive layer;
The method of manufacturing a semiconductor device, wherein a thickness of an insulating film formed by the first insulating layer and the second insulating layer is three times or more on a bottom surface of the trench and on a side surface of the trench.
The step (D)
Forming a silicon film on the first insulating layer (d1);
A second silicon layer is formed in a part of the silicon film by doping impurities to a predetermined depth with respect to the silicon film, and a portion of the silicon film where the second silicon layer is not formed is The method for manufacturing a semiconductor device according to claim 9, further comprising a step (d <b> 2) of becoming a first silicon layer.
10. The semiconductor according to claim 9, wherein the step (D) includes a step of forming a first silicon layer on the first insulating layer and a step of depositing the second silicon layer on the first silicon layer. Device manufacturing method.
In the step (A), the silicon carbide layer includes a first conductivity type drift region and a second conductivity type body region disposed on the drift region,
In the step (B), the trench is formed so as to penetrate the body region and have the bottom surface inside the drift region;
The thickness and impurity concentration of the first silicon layer and the second silicon layer in the step (D), and the heat treatment conditions in the step (E) are such that the interface between the conductive layer and the second insulating layer is The method of manufacturing a semiconductor device according to claim 9, wherein the semiconductor device is controlled so as to be deeper than an interface between the body region and the drift region on a side surface of the trench.
In the step (D), the silicon film is formed in the trench and on the silicon carbide layer,
Forming a third silicon layer deeper than the second silicon layer by selectively ion-implanting the impurity into a portion of the silicon film located in the trench,
13. The method for manufacturing a semiconductor device according to claim 9, wherein in the step (E), impurities in the second silicon layer and the third silicon layer are activated.
14. The method of manufacturing a semiconductor device according to claim 9, wherein the first insulating layer includes at least one of a nitride film and an oxynitride film.
The method for manufacturing a semiconductor device according to claim 9, wherein the substrate is a silicon carbide substrate, and the main surface is a (0001) silicon surface.