JP4850974B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine that allows a player to play a predetermined game and give a predetermined gaming value to the player in accordance with the establishment of a specific condition.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Furthermore, a variable display device capable of changing the display state is provided, and is configured to give a predetermined game value to the player when the display result of the variable display device becomes a predetermined specific display mode There is.

  That the display result of the variable display device that displays the special symbol is a combination of a predetermined display mode is usually referred to as “big hit”. Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. It is to generate.

  When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended.

  When a game ball wins a winning opening provided on the game board, a predetermined number of prize balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of prize balls based on the winning is determined by the game control means, and the payout control means for controlling the payout mechanism for paying out the game balls as prizes. Sent to. Hereinafter, the game control means and the other control means may be referred to as electrical component control means, respectively. An electrical component is a component (such as a mechanism component or a circuit) provided in a gaming machine and operates electrically.

  Various electrical component control means including game control means are mounted on the gaming machine, but each electrical component control means is generally constituted by a microcomputer. That is, a program is stored in a ROM or the like, and data temporarily generated for control or data that changes as control proceeds is stored in the RAM. Then, when the power-off state due to a power failure or the like occurs in the gaming machine, the data in the RAM is lost. Therefore, when recovering from a power outage or the like, the player must return to the initial state (for example, the state when the game machine was first turned on at the game store for the first time in the day), which may cause a disadvantage to the player. There is. For example, if a power failure occurs during a big hit game and the gaming machine returns to the initial state, the player cannot enjoy the profit based on the occurrence of the big hit.

  In order to avoid such a situation, when an unexpected power supply stop such as a power failure occurs, the game control means stores necessary data in a backup RAM backed up and when the power is restored. The stored data may be restored to restore the gaming state and resume the game. In general, when a backup RAM is provided, a detection circuit that detects that power supply is stopped is provided, and a signal from the detection circuit (referred to as a power-off signal) is used as an interrupt signal. Input to the interrupt terminal of the computer, the microcomputer detects the stop of the power supply by the interrupt and executes a process of storing necessary data in the backup RAM. Since the necessary data stored in the backup RAM includes information for restoring the game state, the value of the program counter, the value of the register, and the like are generally stored in the stack area. The processing for storing the data necessary for the backup RAM is executed while the power supply voltage is at a voltage at which the microcomputer can operate when the power supply voltage decreases due to the stop of the power supply. After the execution of the process for saving is completed, the power supply voltage becomes 0 after being lowered to a voltage at which the microcomputer cannot operate.

  In the gaming machine configured as described above, when the power supply is stopped, the value of the power supply voltage becomes unstable, and thus there is a possibility that the power-off signal is continuously generated. If the power-off signal is continuously generated, the microcomputer is continuously interrupted, so that the process of saving necessary data in the backup RAM cannot be surely performed. Therefore, means (specifically, a circuit or the like) for preventing the power-off signal from being continuously generated may be provided on the detection circuit side.

  However, even if the power supply is not stopped, if the power-off signal is continuously input from the detection circuit side to the interrupt terminal of the microcomputer, the size of the stack area is reduced. Despite the limitations, the repeated interruption process repeatedly saves data in the stack area and eventually causes a stack overflow. As a result, program runaway occurs due to the contents of the RAM area being destroyed due to the stack overflow, and the watchdog timer is timed up, and the microcomputer is reset. The contents are initialized.

  Even if the power supply is not stopped, if a reset signal is input in the signal line from the detection circuit side to the reset terminal of the microcomputer, the microcomputer is forcibly reset, and the RAM The contents of the area are initialized.

  Whether or not to generate the above-mentioned big hit is generally determined in advance at a predetermined timing (for example, when a start prize is generated, that is, when a start prize signal is input), the count value of a random number generation counter formed in the RAM area is determined in advance. It is determined by whether or not it matches the jackpot determination value. As described above, if a power-off signal is continuously input or a reset signal is input, the system is reset and the contents of the RAM are initialized by the initialization process. The count value of the random number generation counter for determination is also initialized (returned to 0). Then, since the count value starts incrementing from 0, the timing at which the count value matches a predetermined jackpot determination value can be easily grasped.

  In other words, fraudulent means such as fraudulent boards are mounted on a gaming machine, and a power-off signal (interrupt signal) is continuously input to the microcomputer from the fraudulent means or a reset signal is input, and a random number is generated. By illegally sending a start winning signal to the game control board on which the microcomputer is mounted at a timing at which the count value of the counter coincides with the jackpot determination value, it is possible to cause a jackpot illegally. End up.

  In addition, when all areas of the RAM are backup RAMs, if a fraudulent act is performed in which the power supplied to the backup RAM is turned off by fraud and the contents of the RAM are initialized, The count value of the random number generation counter is also initialized (returned to 0). Even in that case, since the count starts from 0, it is possible to easily grasp the timing at which the count value matches the predetermined jackpot determination value.

The present invention, be made fraud such as feeding the non positively interrupt signal and a reset signal, and an object thereof is to provide a gaming machine which can be easily detected it.

The gaming machine according to the present invention is a gaming machine capable of giving a predetermined gaming value to a player in accordance with the establishment of a specific condition by the player playing a predetermined game , and controlling the progress of the game (For example, game control means including the CPU 56), effect control means for controlling the effect device based on a command output from the game control means, and variation data storage means for storing data that varies in accordance with the progress of the game ( for example RAM 55) and, a storage retaining means capable of retaining stored contents in a predetermined period fluctuation data storage means even if the power supply is stopped to the gaming machine (e.g., a backup power supply), the power of Jo Tokoro potential output voltage as the power supply monitoring means for outputting a detection signal when the monitor detects condition is satisfied (e.g., power-off signal) (for example, the power supply monitoring IC902), Misao which outputs an operation signal in accordance with the operation And means, the game control means, when the detection signal from the power supply monitoring means is outputted, the power supply stop process (e.g. step to make holding the variation data storage means data necessary to recover the control state S451 ˜S499 and steps S171, S172) can be executed, and when the power supply to the gaming machine is started , the stored contents of the variation data storage means are initialized when the operation signal is input from the operation means When the operation signal from the operation means is not input , an initialization process for initializing the stored contents of the variation data storage means based on the establishment of a predetermined condition (for example , the condition determined in steps S7 to S9). Recovery processing (for example, step S80) that recovers the control state based on (for example, steps S183 to S190) and the contents stored in the fluctuation data storage means S95) A capable of executing either one of the, in the case of execution of the initialization process, outputs to effect control means initialization notification command indicating execution of the initialization process, the performance control unit, A command indicating the execution of a predetermined control from the game control means when executing the initialization notification indicating the execution of the initialization process by the effect device based on the input of the initialization notification command and executing the initialization notification If the command is received, the command is invalidated .
According to such a configuration, even if an illegal act such as sending an interrupt signal or a reset signal is performed illegally, this can be easily detected .

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is the rear view which looked at the mechanism board to which various members were attached from the game machine back side. It is a disassembled perspective view which shows the structural example of a ball dispensing apparatus. It is a front view which shows the part of the switch board installed in the game board. It is a block diagram which shows an example of a structure of a clear switch. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a symbol control board. It is a block diagram which shows the circuit structure in a lamp control board. It is a block diagram which shows the circuit structure in a sound control board. It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a power supply board. It is a block diagram which shows one structural example of CPU periphery for a power supply monitoring and a power supply backup. It is a block diagram which shows the structural example for randomizing the initial value of the counter which produces | generates the random number for determining whether it is a big hit. It is explanatory drawing which shows an example of the bit allocation of an output port. It is explanatory drawing which shows an example of the bit allocation of an output port. It is explanatory drawing which shows an example of the bit allocation of an input port. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows a game state restoration process. It is a flowchart which shows a 2 ms timer interruption process. It is a flowchart which shows a special symbol process process. It is a flowchart which shows a start winning memory | storage process. It is a flowchart which shows the process which determines the stop symbol of variable display, and the process which determines a reach kind. It is a flowchart which shows the process which determines whether it is a big hit. It is explanatory drawing which shows an example of a random number. It is a flowchart which shows the random number update process for determination. It is a flowchart which shows the random number update process for determination. It is a flowchart which shows the random number update process for initial values. It is a flowchart which shows the random number update process for a display. It is explanatory drawing which shows an example of the count value of the counter for producing | generating random 1. FIG. It is explanatory drawing which shows an example of the command form of a control command. It is a timing diagram showing the relationship between an 8-bit control signal and an INT signal constituting a control command. It is explanatory drawing which shows an example of the content of a display control command. It is explanatory drawing which shows an example of the content of a lamp control command. It is explanatory drawing which shows an example of the content of a sound control command. It is explanatory drawing which shows the example of 1 structure of a command transmission table. It is explanatory drawing which shows one structural example of the command data 2, and another structural example. It is explanatory drawing which shows the example of 1 structure of INT data. It is explanatory drawing which shows the example of 1 structure of a command transmission table. It is a flowchart which shows a command control process. It is a flowchart which shows a command transmission process routine. It is a flowchart which shows an unmaskable interruption process (process at the time of an electric power supply stop). It is a flowchart which shows an unmaskable interruption process (process at the time of an electric power supply stop). It is a flowchart which shows an unmaskable interruption process (process at the time of an electric power supply stop). It is explanatory drawing which shows the address map of RAM. It is explanatory drawing for demonstrating an example of the checksum production method. It is a timing diagram which shows the mode of the power supply fall and NMI signal at the time of the electric power supply stop to a game machine. It is a flowchart which shows the main process which CPU for display control performs. It is a flowchart which shows the timer interruption process which CPU for display control performs. It is explanatory drawing which shows the structure of a command reception buffer. It is a flowchart which shows a command reception interruption process. It is a flowchart which shows a command analysis process. It is a flowchart which shows the main process which CPU for lamp control performs. It is a flowchart which shows the timer interruption process which CPU for lamp control performs. It is a flowchart which shows the main process which CPU for sound control performs. It is a flowchart which shows the timer interruption process which CPU for sound control performs. It is a block diagram which shows the structural example for making the initial value of the random 1 production | generation counter in other embodiment of this invention random. It is a flowchart which shows the main process in other embodiment of this invention. It is explanatory drawing which shows the other example of the count value of the counter for producing | generating random 1. FIG. FIG. 3 is a block diagram showing a CPU and main components connected thereto when monitoring by a watchdog timer using a system reset circuit.

Embodiment 1 FIG.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding game boards described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the hitting ball are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (special variable display device) 9 including a plurality of variable display portions each variably displaying a symbol as identification information. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. A start winning opening 14 is provided below the variable display device 9. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area) is detected by the V winning switch 22, and the winning ball from the opening / closing plate 20 is detected by the count switch 23. Is done. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided. Further, on the upper portion of the variable display device 9, a special symbol start memory display (hereinafter referred to as a start memory display) 18 using four LEDs for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number. Is provided. Every time there is a valid start prize, the start memory display 18 increases the number of LEDs to be turned on by one. Each time variable display of the variable display device 9 is started, the number of LEDs to be lit is reduced by one.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, a predetermined random number value is extracted if the normal symbol start memory has not reached the upper limit. And if it is a state which can start the variable display in which a display state changes in the normal symbol display 10, the variable display of the display of the normal symbol display 10 will be started. If the normal symbol display 10 is not ready to start variable display whose display state changes, the value of the normal symbol start memory is incremented by one. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of normal symbol start memories is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time the variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  In this embodiment, the left and right lamps (designs can be visually recognized when lit) are alternately lit to perform variable display, and the variable display continues for a predetermined time (for example, 29 seconds). If the left lamp is turned on at the end of the variable display, it is a win. Whether or not to win is determined by whether or not the value of the random number extracted when the game ball wins the gate 32 matches a predetermined hit determination value. When the display result of the variable display on the normal symbol display 10 is a win, the variable winning ball apparatus 15 is opened for a predetermined number of times for a predetermined time so that the game ball is likely to win. That is, the state of the variable winning ball device 15 changes from a disadvantageous state to a player's advantageous state when the normal symbol is a winning symbol.

  Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and one or both of the opening time and the number of times of opening of the variable winning ball device 15 are increased. It becomes even more advantageous. Further, in a predetermined state such as a probability change state, the variable display period (fluctuation time) in the normal symbol display 10 may be shortened, which may be more advantageous for the player.

  The gaming board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of the game balls to the winning holes 29, 30, 33 is detected by winning hole switches 29a, 30a, 33a, 39a, respectively. The Decorative lamps 25 blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a hit ball that has not won a prize is provided below. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. A top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided on the outer periphery of the game area 7. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball lamp 51 that is turned on when there is a remaining number of prize balls is provided in the vicinity of the left frame lamp 28b, and a ball that is turned on in the vicinity of the top frame lamp 28a when the supply ball is cut. A cut lamp 52 is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card. In addition, not only the magnetic card as a prepaid card but other recording media, such as an IC card, can also be used. The shape of the recording medium is not limited to the thin card shape of a business card, and various shapes such as IC coins can be used.

  The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in a usable state, and when the remaining amount information recorded in the card has a fraction (a number less than 100 yen), the fraction is indicated as a hitting tray. 3, a fraction display switch 152 for displaying on a frequency display LED provided in the vicinity of 3, a connecting table direction indicator 153 indicating which side of the pachinko gaming machine 1 corresponds to the card unit 50, in the card unit 50 Check the card insertion indicator lamp 154 indicating that a card is inserted, the card insertion slot 155 into which a card as a recording medium is inserted, and the mechanism of the card reader / writer provided on the back of the card insertion slot 155. In some cases, a card unit lock 156 is provided for releasing the card unit 50.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the hit ball enters the start winning opening 14 and is detected by the start opening switch 14a, the variable display device 9 starts variable display (variation) if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the start memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of the special symbols at the time of the stop is a jackpot symbol (specific display mode), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the V winning area while the opening / closing plate 20 is opened and is detected by the V winning switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the variable display device 9 at the time of stopping is a combination of jackpot symbols (probability variation symbols) with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. 3 and FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side. FIG. 4 is a rear view of the mechanism plate to which various members are attached as viewed from the back side of the gaming machine.

  As shown in FIG. 3, on the back side of the gaming machine, a game control board (main board) 31 on which a variable display control unit 49 including a symbol control board 80 for controlling the variable display device 9, a game control microcomputer, and the like are mounted. Is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. Further, various decoration LEDs provided on the game board 6, special symbol start memory display (start memory display) 18, normal symbol start memory display 41, decoration lamp 25, ceiling frame lamp provided on the frame side. 28a, a left frame lamp 28b, a right frame lamp 28c, a lamp control board 35 on which lamp control means for controlling the lighting of the prize ball lamp 51 and the out-of-ball lamp 52 are mounted, and a sound control means for controlling sound generation from the speaker 27. An onboard sound control board 70 is also provided. Further, a power supply board 910 and a launch control board 91 are provided as power supply boards on which power supply circuits for generating DC30V, DC21V, DC12V, and DC5V are mounted.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 has at least a ball break terminal for introducing and outputting an output of the ball break detection switch, an award ball terminal for outputting the award ball number signal to the outside, and a ball lending number signal externally output. A ball lending terminal is provided. In addition, an information terminal board 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  Further, the backup data held by the storage holding means such as a backup power source is cleared from the data in the fluctuation data storage means (for example, RAM) included in each board (main board 31 and payout control board 37 etc.). A switch board 190 on which a clear switch 921 is mounted as an initialization operation means is provided. The switch board 190 is provided with a clear switch 921 and a connector 922 connected to another board such as the main board 31.

  The game balls stored in the storage tank 38 pass through the guide rail 39 and, as shown in FIG. 4, reach the ball payout device covered with the prize ball case 40A through the curve rod 186. A ball break switch 187 as a game medium break detection means is provided on the upper part of the ball payout device. When the ball break switch 187 detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage. In the vicinity of the head). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  The ball break switch 187 is locked at a position where it can be detected that about 27 to 28 game balls are present in the payout ball passage leading to the ball payout device. That is, the ball break switch 187 has a maximum payout amount per unit of prize balls (15 in this embodiment) and a maximum payout amount per unit of ball lending (100 yen: 25 in this embodiment). It is installed in a position where it can be confirmed that it is secured.

  The game ball paid out from the ball payout device is guided to the hitting ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the connection port 45. A surplus ball passage 46 communicating with the surplus ball receiving tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45.

  A large number of game balls as prizes based on winning prizes and game balls based on ball lending requests are paid out and the hitting ball supply tray 3 becomes full, and finally game balls are paid out after the game balls reach the contact port 45. The game ball is guided to the surplus ball receiving tray 4 through the surplus ball passage 46. Further, when the game ball is paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device stops, the operation of the ball payout device stops, and the drive of the launching device also stops.

  As shown in FIG. 4, a ball removal passage 191 is formed on the side of the ball payout device from the curve rod 186 to the discharge port 192 at the lower part of the gaming machine. A ball removal lever 193 is provided above the ball removal passage 191. When the ball removal lever 193 is operated by a game clerk or the like, a game ball passage from the guide rail 39 to the ball removal passage 191 is formed, and the storage tank 38 is provided. The game balls stored inside are discharged from the discharge port 192 to the outside of the gaming machine.

  FIG. 5 is an exploded perspective view showing a configuration example of the ball dispensing device 97. In this example, a ball payout device 97 is formed inside three cases 140, 141, 142 as the prize ball case 40A. The upper portions of the cases 140 and 141 are provided with holes 170 and 171 communicating with the lower ball passage of the ball break switch 187, and the game balls flow into the ball dispensing device 97 through the holes 170 and 171.

  The ball payout device 97 includes a payout motor (for example, a stepping motor) 289 serving as a drive source. The rotational force of the payout motor 289 is transmitted to the gear 290 fitted to the rotation shaft of the payout motor 289, and further transmitted to the gear 291 that meshes with the gear 290. A sprocket 292 having a recess is fitted to the central axis of the gear 291. The game balls that have flowed in from the holes 170 and 171 are dropped one by one into the ball passage 293 below the sprocket 292 by the recess of the sprocket 292.

  The ball passage 293 is provided with a sorting member 311 for switching the flow path of the game balls. The distribution member 311 is driven by the solenoid 310, and when the prize ball is paid out, the game ball falls down so that the game ball flows down one flow path in the ball passage 293. To fall down. The payout motor 289 and the solenoid 310 are controlled by a payout control CPU mounted on the payout control board 37. The payout control CPU controls the payout motor 289 and the solenoid 310 in accordance with a command from the game control CPU mounted on the main board 31.

  A prize ball sensor (prize ball count switch) 301A as a payout detection means for detecting a game ball paid out by the ball payout device is provided below the flow path selected at the time of paying out the winning ball. A ball lending sensor (ball lending count switch) 301B for detecting a game ball dispensed by the ball dispensing device is provided below the downflow path. The detection signal of the winning ball count switch 301A and the detection signal of the ball lending count switch 301B are input to the payout control CPU of the payout control board 37. The payout control CPU counts the number of game balls actually paid out based on these detection signals.

  A plurality of protrusions 295 that form the payout motor position sensor 296 are formed on the periphery of the gear 291. The protrusion 295 transmits or blocks light from the light emitter (not shown) to the light receiving part (not shown) of the payout motor position sensor as the gear 291 rotates, that is, the payout motor 289 rotates. Or The payout control CPU can recognize the position of the payout motor 289 from the detection signal from the light receiving unit.

  In this embodiment, the ball payout device 97 as the payout means is configured to execute both ball lending and prize ball payout, but the mechanism for lending the ball and the mechanism for paying the prize ball are independent. The present invention can also be applied. When the ball lending mechanism and the prize ball paying mechanism are independent, the winning ball payout and the ball lending can be executed simultaneously, so that the relative payout speed of the game balls can be increased. Further, the sorting member 311 and the solenoid 310 for switching the flow path of the game ball are not necessary. Further, as the payout means, for example, a structure having a structure in which a prize ball is paid out when the motor rotates forward and a ball is lent out when the motor reverses can be used.

  FIG. 6 is a front view showing a part of the switch board 190 installed in the game board 6. As shown in FIG. 6, the switch board 190 is mounted with a connector 922 for connecting the output of the clear switch 921 to another board such as the main board 31 via a cable.

  FIG. 7 is a configuration diagram showing an example of the configuration of the clear switch 921 mounted on the switch board 190. FIG. 7A shows a clear switch 921 having a push button structure. When the clear switch 921 is pressed, a clear switch signal (operation signal) at a low level (ON state) is output, and is output to the main board 31 and the payout control board 37 via the connector 922. That is, the operation signal output from the clear switch 921 to the main board 31 and the payout control board 37 is turned on. If the clear switch 921 is not pressed, a high level (off state) signal is output. In this embodiment, since the clear switch signal is output to at least the main board 31 and the payout control board 37, a connector for outputting the clear switch signal to the main board 31 as the connector 922, and the payout control board A connector for outputting a clear switch signal to 37 may be provided separately.

  FIG. 7B is a configuration diagram illustrating another configuration example of the clear switch 921. The clear switch 921 shown in FIG. 7B includes a switching operation unit 921a for performing selection switching between “OFF”, “ON”, and “clear”. No signal is generated when “OFF” is selected by the switching operation unit 921a. When “ON” is selected, a high level signal is output. The clear switch 921 may also serve as a switch for switching on / off the power supply to the gaming machine 1. In that case, when “OFF” is selected, the power supply to the gaming machine 1 is stopped (the gaming machine is turned off). When “ON” or “Clear” is selected, power is supplied to the gaming machine 1 (the gaming machine is powered on). Further, when “Clear” is selected, a low-level clear switch signal is output.

  In this embodiment, the switch board 190 on which the clear switch 921 is mounted is provided separately from other boards (game control board, etc.), but even if the clear switch 921 is mounted on another board. Good. For example, the power supply board 910 may be mounted. When the clear switch 921 is mounted on the power board 910, even if the power board 910 is used as it is for the replaced game board 6 when the game board 6 is replaced, the replaced game board 6 The game state restoration process or the like can be executed as it is. That is, the power supply board 910 can be reused.

  Also, the clear switch 921 may be installed on the game board 6 side, but may be installed on the game frame side.

  FIG. 8 is a block diagram illustrating an example of a circuit configuration in the main board 31. 8 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a launch control board 91, and a symbol control board 80. The main board 31 includes a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V winning switch 22, a count switch 23, winning port switches 29a, 30a, 33a, 39a, A switch circuit 58 for supplying signals from the tongue switch 48, the ball break switch 187, the prize ball count switch 301A and the clear switch 921 to the basic circuit 53, a solenoid 16 for opening and closing the variable winning ball apparatus 15, and a solenoid for opening and closing the opening and closing plate 20. 21 and a solenoid circuit 59 for driving a solenoid 21A for switching a route in the special winning opening in accordance with a command from the basic circuit 53 is mounted.

  Although not shown in FIG. 8, the count switch short circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58. Further, the gate switch 32a, the start port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 29a, 30a, 33a, 39a, the full switch 48, the ball running switch 187, the winning ball count switch 301A, etc. Also, what is called a sensor may be used. That is, the name of the game medium detection means is not limited as long as it is a game medium detection means (game ball detection means in this example) that can detect a game ball. What is called a switch may be what is called a sensor, that is, that the switch is an example of a game medium detecting unit, as in other embodiments.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the variable display of the symbols in the variable display device 9, the probability variation has occurred. An information output circuit 64 for outputting an information output signal such as probability variation information indicating the above to an external device such as a hall computer is mounted.

  The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as storage means (means for storing variation data) used as a work memory, a CPU 56 for performing control operations according to the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached or built-in.

  Further, at least a part of the RAM 55 (may be a CPU built-in RAM) 55 is a backup RAM that is backed up by a backup power source created in the power supply board 910. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM 55 is stored for a predetermined period. However, in this embodiment, all of the RAM is backed up by a backup power source.

  A ball hitting device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

  In this embodiment, the lamp control means mounted on the lamp control board 35 performs display control of the start memory display 18, the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board. The display control of the top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, the prize ball lamp 51 and the ball-out lamp 52 provided on the frame side is performed. Each lamp may be an LED or other types of light emitters, and the LEDs used in this embodiment and other embodiments may be other types of light emitters. That is, a lamp or LED is an example of a light emitter. In addition, display control of the variable display device 9 for variably displaying the special symbol and the normal symbol display 10 for variably displaying the normal symbol is performed by display control means mounted on the symbol control board 80.

  FIG. 9 shows the circuit configuration in the symbol control board 80. The LCD (liquid crystal display device) 82, the normal symbol display 10, and the output ports (ports 0 and 2) of the main board 31 are examples of realization of the variable display device 9. It is a block diagram shown with 570,572 and output buffer circuit 620,62A. The output port (output port 2) 572 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal).

  The display control CPU 101 operates in accordance with a program stored in the control data ROM 102. When an INT signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105B, display control is performed via the input buffer circuit 105A. Receive commands. As the input buffer circuits 105A and 105B, for example, general-purpose ICs 74HC540 and 74HC14 can be used. When the display control CPU 101 does not have an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

  Then, the display control CPU 101 performs display control of the screen displayed on the LCD 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. The VDP 103 reads out necessary data from the character ROM 86. The VDP 103 generates image data to be displayed on the LCD 82 according to the input data, and outputs R, G, B signals and a synchronization signal to the LCD 82.

  FIG. 9 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, animal, or an image made up of characters, figures, symbols, or the like displayed on the LCD 82.

  The input buffer circuits 105 </ b> A and 105 </ b> B can pass signals only in the direction from the main board 31 toward the display control board 80. Therefore, there is no room for signals to be transmitted from the display control board 80 side to the main board 31 side. That is, the input buffer circuits 105A and 105B constitute irreversible information input means together with the input port. Even if the tampering is added to the circuit in the display control board 80, the signal output by the tampering is not transmitted to the main board 31 side.

  For example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 that cuts off the high-frequency signal. However, even if noise is added between the substrates due to the presence of the noise filter 107, the influence is eliminated. . A noise filter may also be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

  FIG. 10 is a block diagram showing signal transmission / reception portions in the main board 31 and the lamp control board 35. In this embodiment, the top frame lamp 28a provided on the outside of the game area 7, the left and right frame lamps 28b and 28c, the decoration lamp 25 provided on the game board, the start memory display 18 and the normal symbol start memory display. A lamp control command indicating lighting / extinguishing of the instrument 41 and lighting / extinguishing of the winning ball lamp 51 and the off-ball lamp 52 is output from the main board 31 to the lamp control board 35.

  As shown in FIG. 10, the lamp control command related to the lamp control is output from the output ports (output ports 0 and 3) 570 and 573 of the I / O port unit 57 in the basic circuit 53. The output port (output port 3) 573 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. In the lamp control board 35, a control command from the main board 31 is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. When the lamp control CPU 351 does not include an I / O port, an I / O port is provided between the input buffer circuits 355A and 355B and the lamp control CPU 351.

  On the lamp control board 35, the lamp control CPU 351 performs the top frame lamp 28a, left and right according to the lighting / extinguishing patterns of the top frame lamp 28a, left and right frame lamps 28b and 28c, and the decoration lamp 25 defined according to each control command. A lighting / extinguishing signal is output to the frame lamps 28 b and 28 c and the decoration lamp 25. The on / off signal is output to the top frame lamp 28 a, the left and right frame lamps 28 b and 28 c, and the decoration lamp 25. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  In the main board 31, the CPU 56 outputs a control command instructing lighting of the prize ball lamp 51 when there is an unpaid prize ball remaining in the stored contents of the RAM 55, and the upstream of the above-mentioned payout ball passage on the back of the game board. When the ball break switch 187 (see FIG. 3) installed in the player no longer detects a game ball, a control command for instructing lighting of the ball break lamp 52 is output. In the lamp control board 35, each control command is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the ball-out lamp 52 in accordance with these control commands. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  As the input buffer circuits 355A and 355B, for example, 74HC540 and 74HC14 which are general-purpose CMOS-ICs are used. The input buffer circuits 355A and 355B can pass signals only in the direction from the main board 31 toward the lamp control board 35. Therefore, there is no room for signals to be transmitted from the lamp control board 35 side to the main board 31 side. Even if unauthorized modification is added to the circuit in the lamp control board 35, the signal output by the unauthorized modification is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

  In the main board 31, buffer circuits 620 and 63A are provided outside the output ports 570 and 573. As the buffer circuits 620 and 63A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line that can give a signal from the lamp control board 70 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 63A.

  FIG. 11 is a block diagram showing a configuration example of the sound control command signal transmitting portion of the main board 31 and the sound control board 70. In this embodiment, a sound control command for instructing the sound output of the speaker 27 provided outside the game area 7 is output from the main board 31 to the sound control board 70 as the game progresses.

  As shown in FIG. 11, the sound control command is output from the output ports (output ports 0 and 4) 570 and 574 of the I / O port unit 57 in the basic circuit 53. The output port (output port 4) 574 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. In the sound control board 70, each signal from the main board 31 is input to the sound control CPU 701 via the input buffer circuits 705A and 705B. When the sound control CPU 701 does not have an I / O port, an I / O port is provided between the input buffer circuits 705A and 705B and the sound control CPU 701.

  Then, for example, a voice synthesis circuit 702 using a digital signal processor generates voice and sound effects according to instructions from the sound control CPU 701 and outputs them to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the sound control CPU 701 to a level corresponding to the set volume and outputs it to the volume amplification circuit 704. The volume amplification circuit 704 outputs the amplified sound signal to the speaker 27.

  As the input buffer circuits 705A and 705B, for example, 74HC540 and 74HC14, which are general-purpose CMOS-ICs, are used. The input buffer circuits 705A and 705B can pass signals only in the direction from the main board 31 toward the sound control board 70. Therefore, there is no room for signals to be transmitted from the sound control board 70 side to the main board 31 side. Therefore, even if unauthorized modification is added to the circuit in the sound control board 70, a signal output by the unauthorized modification is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

  In the main board 31, buffer circuits 620 and 67A are provided outside the output ports 570 and 574. As the buffer circuits 620 and 67A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line that can give a signal to the main board 31 from the sound control board 70 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 67A.

  FIG. 12 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 12, the detection signal from the full switch 48 is input to the I / O port unit 57 of the main board 31 via the relay board 71. The detection signal from the ball break switch 187 is also input to the I / O port portion 57 of the main board 31 through the relay board 72 and the relay board 71.

  The CPU 56 of the main board 31 should stop paying out when the detection signal from the ball-off switch 187 indicates a ball-out state, or when the detection signal from the full-tan switch 48 indicates a full-up state. A payout control command is sent to instruct that this is the case. When receiving a payout control command instructing that payout should be stopped, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

  Further, the detection signal from the prize ball count switch 301A is input to the I / O port portion 57 of the main board 31 via the relay board 72 and the relay board 71, and also from the payout control board 37 via the relay board 72. Input to the input port 372b. The prize ball count switch 301A is provided in a payout mechanism portion of the ball payout device 97, and detects a prize ball payout ball actually paid out.

  When there is a winning, a payout control command indicating the number of winning balls is input to the payout control board 37 from the output ports (ports 0, 1) 570, 571 of the main board 31. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. A payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 inputs a payout control command via the I / O port 372a, and drives the ball payout device 97 in accordance with the payout control command to perform prize ball payout. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and incorporates at least a RAM.

  In the main board 31, buffer circuits 620 and 68A are provided outside the output ports 570 and 571. As the buffer circuits 620 and 68A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, it is possible to more reliably eliminate a signal line from which a signal may be given from the payout control board 37 to the main board 31. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

  The payout control CPU 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 via the output port 372c. Further, an error signal is output to the error display LED 374 via the output port 372d.

  Further, detection signals from the ball lending count switch 301B and the payout motor position sensor 296 for detecting the rotational position of the payout motor 289 are input to the input port 372b of the payout control board 37 via the relay board 72. The The ball lending count switch 301B is provided in a payout mechanism portion of the ball payout device 97, and detects a lending ball actually paid out. The drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and the drive signal to the sorting solenoid 310 is This is transmitted to the sorting solenoid 310 in the payout mechanism portion of the ball payout device 97 via the output port 372e and the relay board 72. The output of the clear switch 921 is also input to the input port 372b.

  The card unit 50 is equipped with a card unit control microcomputer. Further, the card unit 50 is provided with a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected with a frequency display LED, a ball lending switch, and a return switch provided in the vicinity of the hitting ball supply tray 3.

  A ball lending switch signal and a return switch signal are given from the balance display board 74 to the card unit 50 via the payout control board 37 in accordance with the player's operation. Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given to the balance display board 74 from the card unit 50 via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is exchanged via the input port 372b and the output port 372e.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected / unconnected state based on the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. At this time, the sorting solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, if the BRDY signal from the card unit 50 is not on, prize ball payout control is executed.

  As described above, all signals from the card unit 50 are input to the payout control board 37. Accordingly, with respect to the ball lending control, no signal is input from the card unit 50 to the main board 31, and there is no room for an illegal signal input from the card unit 50 side to the basic circuit 53 of the main board 31. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  In this embodiment, a power-off signal is also input from the power supply board 910 to the payout control board 37. The power-off signal is input to a non-maskable interrupt (NMI) terminal of the payout control CPU 371. Furthermore, at least a part of the RAM (may be a CPU built-in RAM) present on the payout control board 37 is backed up by a backup power source created on the power board 910. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM is stored for a predetermined period. However, in this embodiment, all the RAMs are backed up by a backup power source.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 13 is a block diagram illustrating a configuration example of the power supply substrate 910. The power supply board 910 is installed independently of the electric part control boards such as the main board 31, the symbol control board 80, the sound control board 70, the lamp control board 35, and the payout control board 37, and each electric part control board in the gaming machine and Generates voltage used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21V, DC + 12V, and DC + 5V are generated. Further, a capacitor 916 serving as a backup power source, that is, a memory holding means, is charged from a line of power source for driving DC + 5V, that is, an IC on each substrate. Note that VSL is generated by rectifying and boosting AC24V with a rectifier element in the rectifier circuit 912. VSL is a solenoid driving power source.

  The transformer 911 converts AC voltage from the AC power source into 24V. The AC 24V voltage is output to the connector 915. The rectifier circuit 912 also generates a DC voltage of +30 V from AC 24 V and outputs it to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 has one or a plurality of converter ICs 924 (only one is shown in FIG. 13), generates + 21V, + 12V, and + 5V based on VSL and outputs them to the connector 915. A relatively large capacitor 923 is connected to the input side of the converter IC 924. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltage such as + 30V, + 12V, + 5V, etc., decreases relatively slowly. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each electric component control board and the mechanism component is supplied from the relay board.

  However, each connector reaching each electric component control board may be provided on the power supply board 910 to supply each voltage from the power supply board 910 to each board without going through the relay board. FIG. 13 shows one connector 915 as a representative, but the connector is provided for each electric component control board.

  The + 5V line from the DC-DC converter 913 branches to form a backup + 5V line. A large-capacitance capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 has a storage state with respect to the backup RAM of the electrical component control board when the power supply to the gaming machine is stopped (a RAM that is backed up by power, that is, a backup storage unit that can be in a storage content holding state even when the power supply is stopped) It becomes a backup power supply that supplies power so that it can be maintained. Further, a backflow preventing diode 917 is inserted between the + 5V line and the backup + 5V line. In this embodiment, +5 V for backup is supplied to the main board 31 and the payout control board 37.

  The power supply board 910 is mounted with a power monitoring IC 902 as a power monitoring circuit (power monitoring means). The power monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), a power-off signal is output because power supply is stopped. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used. A power-off signal from the power monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

  The predetermined value for the power monitoring IC 902 to detect the stop of power supply is lower than the normal voltage, but is a voltage that allows the CPU on each electrical component control board to operate for a while. Further, the power monitoring IC 902 is configured to monitor a voltage that is higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and immediately after being converted from AC to DC. Therefore, the monitoring range can be expanded for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. In other words, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop.

  When the voltage of the + 12V power supply decreases, the switch output becomes on. However, if the power supply voltage is monitored by monitoring the + 30V power supply voltage, which decreases faster than + 12V, and the power supply is stopped, the switch output is turned on. It is possible to enter a supply recovery waiting state and not detect the switch output.

  Further, since the power monitoring IC 902 is mounted on the power supply board 910 that is separate from the electrical component control board, a power-off signal can be supplied from the power monitoring circuit to the plurality of electrical component control boards. Even if there are any number of electrical component control boards that require a power-off signal, it is only necessary to provide one power supply monitoring means. Therefore, even if each electrical component control means in each electrical component control board performs recovery control described later. The cost of the gaming machine does not increase so much.

  In the configuration shown in FIG. 13, the detection signal (power cut-off signal) of the power monitoring IC 902 is supplied to each electric component control board (for example, the main board 31 and the payout control board 37) via the buffer circuits 918 and 919. For example, a configuration may be adopted in which one detection signal is transmitted to the relay board, and the same signal is distributed from the relay board to each electrical component control board. Further, a buffer circuit corresponding to the number of substrates that require a power-off signal may be provided. Further, regarding the power-off signal output to the main board 31 and the payout control board 37, the monitoring voltage of the power supply monitoring circuit that outputs the power-off signal may be different.

  FIG. 14 is a block diagram illustrating a configuration example around the CPU 56 in the main board 31. As shown in FIG. 14, the power-off signal from the power supply monitoring circuit of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the CPU 56 via the buffer circuit 900. Therefore, the CPU 56 can confirm the occurrence of the stop of power supply to the gaming machine by the non-maskable interrupt (NMI) process. The power-off signal is also input to the determination circuit 950. Since the signal output from the buffer circuit 900 is not substantially different from the detection signal from the power supply monitoring circuit 910 (only amplified), hereinafter, the signal output from the buffer circuit 900 is referred to as a detection signal or an NMI signal. Sometimes. Note that the CPU 56 accepts an interrupt at the falling edge when the input signal of the XNMI terminal becomes low level.

  FIG. 14 also shows a system reset circuit 65. When the power is turned on, the reset IC 651 sets the output to a low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to a high level when the predetermined time has elapsed. That is, a reset signal (system reset signal) that is a signal for initializing the operation of the control means is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage of VSL, which is the power supply voltage equal to the power supply voltage monitored by the power supply monitoring circuit of the power supply board 910, and the voltage value is a predetermined value (the power supply voltage at which the power supply monitoring circuit outputs a power-off signal). When the value is lower than the value, the output is set to low level. Accordingly, the CPU 56 performs a predetermined power supply stop process in response to the power-off signal from the power supply monitoring circuit, and then the system is reset. The system reset is a reset mode in which all the devices included in the CPU 56 are reset.

  As shown in FIG. 14, the reset signal from the reset IC 651 is input to the NAND circuit 947 and also input to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level. The Q5 output of the counter IC 941 is input to the NAND circuit 947 via the NOT circuits 945 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942. The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The output of the NAND circuit 947 is introduced into the other input of the OR circuit 949 via the NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56 as a reset signal. According to such a configuration, since the reset signal (low level signal) is given twice to the reset terminal of the CPU 56 when the power is turned on, the CPU 56 surely starts operation.

  For example, the detection voltage of the power supply monitoring circuit of the power supply substrate 910 (voltage that outputs a power-off signal) is set to + 22V, and the detection voltage for setting the reset signal to low level is set to + 9V. In such a configuration, since the power supply monitoring circuit and the system reset circuit 65 monitor the voltage of the same power supply VSL, the timing at which the voltage monitoring circuit outputs a power-off signal and the system reset circuit 65 reset the system. It is possible to reliably set the difference in timing for outputting the signal within a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop process in response to the power-off signal from the power supply monitoring circuit until the completion of the power supply stop process. The power supply voltage monitored by the power supply monitoring circuit and the system reset circuit 65 may be different.

  While power is not supplied from the + 5V power source that is the driving power source of the CPU 56 or the like, at least a part of the RAM is backed up by the backup power source supplied from the power supply board, and the contents are preserved even if the power supply to the gaming machine is stopped. Is done. When the +5 V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to a normal operation state. At that time, since necessary data is stored in the backup RAM, it is possible to restore the gaming state at the time of occurrence of a power failure or the like at the time of recovery from the power failure or the like.

  In the configuration shown in FIG. 14, a reset signal (low level is a reset level) is given to the reset terminal of the CPU 56 when the power is turned on, but even if the rising timing of the reset signal is only once, the reset is surely released. When using the CPU to be used, the circuit elements denoted by reference numerals 941 to 949 are not necessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

  The reset signal is also input to the determination circuit 950. The determination circuit 950 is a circuit that inputs an NMI signal and a reset signal and outputs a determination signal to the input port of the CPU 56. Specifically, the determination circuit 950 outputs a determination signal to the control means when the reset signal does not become low level within a predetermined period after the NMI signal is input. When the reset signal does not become low level within a predetermined period after the NMI signal is input, it can be determined that the NMI signal has been input illegally.

  The CPU 56 used in this embodiment also includes an I / O port (PIO) and a timer / counter circuit (CTC).

  A first oscillation circuit (OSC1) 92 that generates a clock signal is connected to the clock input terminal (EXTAL1 terminal) of the CPU 56. The CPU 56 divides the clock signal from the first oscillation circuit 92 as necessary and uses it as an internal clock.

  The system reset circuit 65 used in this embodiment outputs a system reset signal related to only the power supply voltage (set to low level and then set to high level), but periodically from the CPU 56 via the output port. The system reset signal may be output even when the signal is not output for a predetermined period of time. That is, the system reset circuit 65 may include a watch dog circuit. In this embodiment, since the system reset circuit 65 is mounted on the main board 31, the system reset signal does not appear outside on the main board 31, and there is a possibility that fraudulent acts may be performed on the system reset signal. To reduce.

  FIG. 15 shows an initial value (set in the initialization process) of a counter (in this embodiment, a random 1 generation counter, which will be described later) that generates a random number for determining whether or not to make a big hit on the main board 31. It is a block diagram which shows the example of a structure for randomizing (initial value) to be random. In the example shown in FIG. 15, a counter 931 that counts a clock signal generated by the second oscillation circuit (OSC2) 930 and a latch circuit 932 that latches the count value of the counter 931 are provided. The main board 31 is provided with a backup power source 933 as a numerical value holding means such as a capacitor or a battery that can supply power even when power supply to the gaming machine is stopped, and the second oscillation circuit 930, the counter 931, and the latch circuit 932 are provided. The power supply of the backup power source 933 operates. The counter 931 and the latch circuit 932 constitute counting means (second numerical value updating means). The latch circuit 932 is an example of numerical value output means.

  The backup power source 933 is preferably mounted on the main board 31 as in this embodiment. The main board 31 on which the game control means is mounted cannot be easily removed on the back side of the gaming machine, and is covered with a cover that shows the removal history, so that it is difficult to receive fraud. Therefore, if the backup power source 933 is mounted on the main board 31, there is a high possibility that an illegal act that forcibly turns off the backup power source 933 can be prevented.

  A latch signal output from the CPU 56 via the output port 576 is supplied to the latch circuit 932. The latch circuit 932 latches the count value of the counter 931 at the rising edge of the latch signal. Note that the latch circuit 932 may latch the count value of the counter 931 at the falling edge of the latch signal. The data latched by the latch circuit 932 is input to the CPU 56 via the input port 582. In this embodiment, the counter 931 is an 8-bit binary counter, and 8-bit data is input from the latch circuit 932 to the input port 582. Well, the count value of the counter 931 circulates from 0 to FF (H). That is, the counter 931 is a free run counter.

  Even when power supply to the gaming machine is stopped, power is supplied from the backup power source 933 to the second oscillation circuit 930, the counter 931, and the latch circuit 932. Therefore, the counter 931 counts the clock signal from the second oscillation circuit 930 even when the power supply to the gaming machine is stopped. Therefore, when the power supply to the gaming machine is resumed, the count value of the counter 931 is indefinite. As will be described later, when the power supply to the gaming machine is resumed and the initialization process is executed, a latch signal is output. However, since the count value of the counter 931 is indefinite, the latch circuit 932 latches. The data output to the input port 582 is also undefined.

  Note that after the supply of power to the gaming machine is resumed, a latch signal is output in the initialization process, so that power may not be supplied from the backup power source 933 to the latch circuit 932.

  In addition, power is supplied from the backup power source 933 only to the latch circuit 932. For example, the CPU 56 outputs a latch signal in a power supply stop process (a process executed when power supply to the gaming machine is stopped), which will be described later. You may do it. Then, the latch circuit 932 latches the count value of the counter 931 immediately before the power supply to the gaming machine is stopped, and holds the value even when the power supply to the gaming machine is stopped. When the power supply to the gaming machine is resumed and the initialization process is executed, the CPU 56 inputs the data held in the latch circuit 932 via the input port 582. Since the count value of the counter 931 immediately before the power supply is stopped is undefined, the data input via the input port 582 when the power supply to the gaming machine is resumed is also undefined. In this case, the CPU 56 does not output a latch signal in the initialization process (because if it is output, the data held in the latch circuit 932 is updated with the count value of the counter 931 at that time).

  Furthermore, the oscillation frequency of the second oscillation circuit 930 is different from the oscillation frequency of the first oscillation circuit 92. In addition, one of the oscillation frequency of the first oscillation circuit 92 and the oscillation frequency of the second oscillation circuit 930 is not an integral multiple of the other oscillation frequency. Since the CPU 56 operates based on the oscillation frequency of the first oscillation circuit 92, the increment of the counter generated internally (in software) by the CPU 56 operates based on the oscillation frequency of the second oscillation circuit 930. It is not synchronized with the increment of the count value of the counter 931. The counter generated internally by the CPU 56 includes, for example, a counter that generates a random number for determining whether or not to generate a big hit.

  FIGS. 16 and 17 are explanatory diagrams showing output port allocation in this embodiment. As shown in FIG. 16, the output port 0 is an output port for an INT signal of a control command sent to each electrical component control board. Further, 8-bit data (payout control signals CD0 to CD7) of the payout control command sent to the payout control board 37 is output from the output port 1 and 8-bit data of the display control command sent to the symbol control board 80. (Display control signals CD0 to CD7) are output from the output port 2, and 8-bit data (lamp control signals CD0 to CD7) of the lamp control command sent to the lamp control board 35 are output from the output port 3. As shown in FIG. 17, 8-bit data (sound control signals CD0 to CD7) of the sound control command sent to the sound control board 70 is output from the output port 4.

  Further, various information output signals from the output port 5 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output. Then, a drive signal from the output port 6 to the solenoid 16 for opening and closing the variable winning ball device 15, the solenoid 21 for opening and closing the opening / closing plate 20 of the big winning opening, and the solenoid 21A for switching the path in the big winning opening. Is output. Further, the output port 6 also outputs an initialization signal that is a signal for notifying a game shop clerk that the initialization process has been executed, and a latch signal that is given to the latch circuit 932 shown in FIG.

  As shown in FIGS. 16 and 17, each INT signal (payout control signal INT, display control signal INT, lamp) output to the payout control board 37, the symbol control board 80, the lamp control board 35 and the sound control board 70 is displayed. Output port (output port 0) that outputs control signal INT and sound control signal INT), output control signals CD0 to CD7, display control signals CD0 to CD7, ramp control signals CD0 to CD7, and audio control signals CD0 to CD7 The output ports (output ports 1 to 4) to be performed are different ports.

  Therefore, when outputting the INT signal, the possibility that the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the ramp control signals CD0 to CD7, and the audio control signals CD0 to CD7 are erroneously changed is reduced. Further, when outputting the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the ramp control signals CD0 to CD7, or the audio control signals CD0 to CD7, the possibility of erroneously changing the INT signal is reduced. As a result, a command for each electric component control board is more reliably sent from the game control means of the main board 31. Furthermore, since all the INT signals are output from the output port 0, the burden of the INT signal output process of the game control means is reduced.

  FIG. 18 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 18, the detection of the winning port switches 33a, 39a, 29a, 30a, the start port switch 14a, the count switch 23, the V winning switch 22, and the gate switch 32a are detected in bits 0 to 7 of the input port 0, respectively. A signal is input. In addition, the award ball count switch 301A, the full switch 48, the ball break switch 187 detection signal, the count switch short-circuit signal, and the clear switch 921 detection signal are input to bits 0 to 4 of the input port 1, respectively. The detection signal from each switch is logically inverted in the switch circuit 58. In this way, the detection signal of the clear switch 921, that is, the operation input of the initialization operation means, is the same input port as the input port (8-bit input unit) to which the detection signal of the switch for detecting the game ball is input. Is input to a bit (input port circuit).

  Further, the input port 2 corresponds to the input port 582 shown in FIG. 15, and the data output from the latch circuit 932 is input. Hereinafter, the data output from the latch circuit 932 is referred to as a determination random number initial value.

  Next, the operation of the gaming machine will be described. FIG. 19 is a flowchart showing main processing executed by game control means (CPU 56 and peripheral circuits such as ROM and RAM) in the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts main processing after step S1. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). Further, after initialization (step S5) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM is set in an accessible state (step S6).

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The CTC also includes two external clock / timer trigger inputs CLK / TRG2, 3 and two timer outputs ZC / TO0,1.

  The CPU 56 used in this embodiment is provided with the following three modes as maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that has issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: When an interrupt is accepted, the mode always jumps to address 0038 (H).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of sending an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Furthermore, unlike interrupt mode 1, it is also easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Next, the CPU 56 confirms the state of the output signal of the clear switch 921 input via the input port 1 only once (step S7). When the on-state is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S181 to S190). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. In the input port 1, the clear switch signal is in the high level (see FIG. 15). Further, for example, the game store clerk can easily execute the initialization process by starting the power supply to the gaming machine while the clear switch 921 is turned on. That is, RAM clear or the like can be performed.

  If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When such protection processing is performed, it is assumed that there is a backup. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

  In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area in the power supply stop process. For example, if “55 (H)” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55 (H)” is set, there is no backup (OFF state). means.

  After confirming that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply is stopped (step S10). ). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the address is restored.

  In this way, it is possible to accurately return the gaming state to the state when the power supply is stopped by checking whether the data in the backup RAM area is stored using the backup flag and check data such as a checksum. it can. That is, the certainty of the state restoration process based on the data in the backup RAM area is improved. In this embodiment, it is confirmed whether or not the data in the backup RAM area is stored by using both the backup flag and the check data, but only one of them may be used. That is, either the backup flag or the check data may be used as an opportunity for executing the state recovery process.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S181). In addition, a predetermined work area (for example, determination random number counter, display random number counter, initial value random number counter, normal symbol determination buffer, special symbol left middle right symbol buffer, special symbol process flag, payout command storage pointer, award A work area setting process for setting an initial value to a flag for selectively performing processing according to the control state, such as a ball flag, a ball break flag, and a payout stop flag is performed (step S182).

  Next, the CPU 56 outputs an initialization signal to an external device such as a hall computer via the information output circuit 64, for example (step S183). The initialization signal is a signal for informing a game clerk and the like that the initialization process has been executed at the time of activation. Accordingly, when receiving an initialization signal, an external device such as a hall computer performs a process of notifying that the initialization process has been executed by sound, lamp, display, or the like. Further, a process of transmitting a payout permission state designation command (hereinafter referred to as a payout enable state designation command) instructing that payout from the ball payout device 97 is possible to the payout control board 37 is performed (step S184). .

  Also, a process of transmitting an initialization command for initializing each sub board (dispensing control board 37, lamp control board 35, sound control board 70, symbol control board 80) to each sub board is executed (step S185). . As an initialization command, a command indicating the initial symbol displayed on the variable display device 9 (for the symbol control board 80) and a command for instructing the extinction of the prize ball lamp 51 and the ball-out lamp 52 (to the lamp control board 35) Etc). In this embodiment, since a payout enable state designation command is transmitted in step S184, a control command for the payout control board 37 is not transmitted in step S185. Further, the CPU 56 performs a process of transmitting an initialization notification command designating notification of execution of the initialization process to the symbol control board 80 (step S186). In this embodiment, a big hit start display command (see FIG. 39) is used as the initialization notification command. When the notification control for executing the initialization process is executed in the lamp control unit or the sound control unit, an initialization notification command is transmitted to the lamp control board 35 and the sound control board 70 in step S186. In this case, for example, a big hit start lamp designation command (see FIG. 40) is used as the initialization notification command transmitted to the lamp control board 35. As the initialization notification command to be transmitted to the sound control board 70, for example, a big hit start sound designation command (see FIG. 41) is used.

  In the initialization process, a payout enable state designation command is always transmitted to the payout control board 37. Even if the state of the gaming machine is a state in which a payout from the ball payout device 97 is not possible, the fact is detected in the game control process executed immediately after that and an instruction is given that the payout is not possible. There is no problem because a withdrawal prohibition state designation command to be sent (hereinafter referred to as a withdrawal stop state designation command) is transmitted.

  Further, the CPU 56 outputs a latch signal (step S187). In step S187, for example, a one-pulse signal is output as a latch signal. The latch signal is supplied from the output port 576 to the latch circuit 932 (see FIG. 15). When the latch signal is input, the latch circuit 932 inputs the count value of the counter 931 and latches it. The CPU 56 inputs data as a determination random number initial value latched by the latch circuit 932 via the input port 582 (step S188). Then, the input value is set in a random 1 generation counter for generating a big hit determination random number (step S189). That is, the game control means determines a numerical value for starting the update of the first numerical value updating means based on the numerical value of the second numerical value updating means. Instead of setting the value input via the input port 582 as it is in the random 1 generation counter, a value obtained by performing some operation (processing) on the input value may be set in the random 1 generation counter. .

  As described above, the data latched by the latch circuit 932 is the second oscillation in which the hardware counter 931 outputs a clock signal that is not synchronized with the clock signal from the first oscillation circuit 92 that determines the operating frequency of the CPU 56. A value obtained by counting the clock signals from the circuit 930 is an indefinite value. Accordingly, the value (initial value) set in the random 1 generation counter in step S189 in the initialization process is also an indefinite value.

  In addition, when power is supplied from the backup power source 933 only to the latch circuit 932 and, for example, the CPU 56 is configured to output a latch signal in the power supply stop process, the CPU 56 executes the process of step S187. Instead, the processes of steps S188 and S189 are performed. Since the count value of the counter 931 immediately before the power supply stop is indeterminate, the data input via the input port 582 when the power supply to the gaming machine is resumed is also indeterminate, and random 1 is generated in step S189. The value (initial value) set in the counter is also indefinite.

  Further, the counter 931 has a maximum count value (update upper limit value) that is the same as the maximum value of the random 1 generation counter (update upper limit value; 316 in this embodiment). It is preferable to be configured. In such a configuration, the value input from the latch circuit 932 can be set in the random 1 generation counter as it is. However, when the counter 931 is configured with an 8-bit binary counter as in this embodiment, the maximum value is 256. Therefore, in step S189, the CPU 56 generates one random value generated from the latch circuit 932. Set to the lower 8 bits of the counter.

  Then, the CPU 56 sets a CTC register provided in the CPU 56 so that a timer interrupt is periodically generated every 2 ms (step S190). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

  In this embodiment, when the CPU 56 detects that the clear switch 921 is on, the initialization process (steps S181 to S190) is executed regardless of whether data is stored in the backup RAM. Therefore, the game control means can be forcibly initialized on the game store side. That is, initialization of the game control means is realized in software. Even if the clear switch 921 is not turned on, the game control means can be initialized by software using the backup flag and check data such as a checksum. It is prevented that the gaming state is restored.

  Further, when it is not detected that the clear switch 921 is turned on, if it is confirmed that the data is not correctly stored in the backup RAM, the CPU 56 executes initialization processing (steps S181 to S190). Therefore, the CPU 56 initializes the stored contents of the variation data storage means when a predetermined initialization condition is satisfied even if the operation to the initialization operation means is not performed.

  When the execution of the initialization process (steps S181 to S190) is completed, the display random number update process (step S17) and the initial value random number update process (step S18) are repeatedly executed in the main process. When the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set (step S16). When the display random number update process and the initial value random number update process are finished, the interrupt enabled state is set. (Step S19). The display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. . The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value such as a counter (random 1 generation counter) for generating a random number for determining whether or not to win. In a game control process to be described later, when the count value of the random 1 generation counter makes one round, the initial value is set again in the counter. However, the count value of the counter for determining the initial value is used as the initial value set in the game control process.

  Note that when the display random number update process is executed, the interrupt is prohibited. The display random number update process is also executed in the timer interrupt process described later, and thus conflicts with the process in the timer interrupt process. This is to avoid that. That is, if the timer interrupt is generated during the process of step S17 and the counter value for generating the display random number is updated during the timer interrupt process, the continuity of the count value is impaired. There is a case. However, such an inconvenience does not occur if the interrupt is prohibited during the process of step S17.

  FIG. 20 is a flowchart illustrating an example of the game state restoration process. In the game state restoration process, the CPU 56 first performs a stack pointer restoration process (step S80). The value of the stack pointer is saved in a predetermined RAM area (power backed up) in the power supply stop process described in detail later. Therefore, in step S80, the RAM area value is set in the stack pointer to restore. Note that the register value and the value of the program counter (PC) when the power supply is stopped are saved in the area pointed to by the restored stack pointer (that is, the stack area).

  Next, the CPU 56 checks whether or not a stack overflow has occurred (step S81). In this embodiment, it is confirmed whether or not data exceeding a predetermined amount of data is stored in the stack area provided in the RAM 55. In this embodiment, the CPU 56 determines that the stack overflows when the recovered stack pointer value exceeds the allowable range. If it is a stack overflow, the CPU 56 stops the game state recovery process and sets the stack pointer designation address in the stack pointer (step S81a: the same process as step S3 described above), and then the initialization process (steps S181 to S181). Step S190) is executed.

  If it is not a stack overflow, the CPU 56 checks whether or not the payout has been stopped (step S82). Whether or not the payout is stopped is determined according to a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a special symbol, This is confirmed by a payout stop flag as payout state data in a symbol process flag, a payout command storage pointer, a winning ball flag, a ball runout flag, a payout stop flag, etc. If it is in the payout stop state, a payout control command (payout stop state designation command) for instructing the payout stop is transmitted to the payout control means mounted on the payout control board 37 (step S83). If it is not in the payout stop state, a payout control command (payable state designation command) for instructing that payout is possible is sent to the payout control means (step S84).

  Since the payout control means cannot recognize the shortage of supply balls or the full tank of the surplus ball receiving tray 4, if there is no notification from the game control means, the supply ball shortage or the surplus ball receiving tray 4 is full when recovering from a power failure or the like. Nevertheless, there is a risk of starting the game ball payout process. However, in this embodiment, in the game state recovery process, a payout control command for instructing stoppage of payout or a payout control command for instructing that payout is possible is transmitted. Even though the surplus ball receiving tray 4 is full, the game ball payout process is not started.

  Here, when the payout state determination means (a part of the game control means) for determining whether or not the game medium can be paid out detects that the payout is not possible, one type of the game medium is determined regardless of the cause. The payout stop state designation command is transmitted. However, the command may be transmitted separately for each cause (in this example, a command indicating a shortage of supply balls and a command indicating a lower pan full). Further, when the game ball cannot be paid out, a command instructing to prohibit the release of the game ball may be transmitted to the payout control board 37 in order to prohibit the continuation of the game. When the payout control means mounted on the payout control board 37 receives a command instructing prohibition of the game ball, the drive of the hitting ball launching device is stopped. In addition, when the game ball cannot be paid out, the game control means may give a signal instructing the launch control means to prohibit the launch of the game ball directly. Further, the payout control means may stop driving the ball striking device when a payout stop state designation command is received.

  Next, the CPU 56 checks whether or not the special display is changing in the variable display device 9 when the power supply is stopped (step S85). Whether or not the special symbol is changing when the power supply is stopped can be confirmed by, for example, the value of the special symbol process flag stored in the RAM area where the power is backed up. If the special symbol is changing, a special symbol power failure recovery command and a display control command for designating the left and right symbols are transmitted to the display control means mounted on the symbol control board 80 (step S86, S87). Here, the left and right symbols designated by the display control command are symbols that should have been stopped and displayed due to the special symbol fluctuation that was performed when the power supply was stopped.

  When receiving the special symbol power failure recovery command, the display control means performs a predetermined notification process. For example, the variable display device 9 displays that a power failure has occurred. Based on the various information that was backed up, the gaming state returns to the state prior to the stop of power supply.After that, when the special symbol change period ends, the gaming control means issues a confirmation command to the display control means. Send. Based on the receipt of the confirmation command, the display control means is in a state where the next special symbol can be changed.

  If the special symbol is not changing, the CPU 56 performs processing for transmitting a display control command for designating the left and right middle symbols, a confirmation command, and a customer waiting demo command to the display control means (steps S88 to S90). ). The left and right symbols designated by the display control command are the symbols displayed on the variable display device 9 when the power supply is stopped.

  When the display control means receives the confirmation command, the display control means controls the variable display device 9 to display the special symbol designated by the display control command for designating the left and right middle symbols. Further, when the customer waiting demonstration command is received, control is performed so that the display state of the variable display device 9 such as the background is set to the standby display state.

  Thereafter, the CPU 56 clears the backup flag (step S91), that is, resets a flag indicating that a predetermined storage protection process has been executed when the previous power supply was stopped. Also, the saved values of the various registers are read from the stack area and set in the various registers (step S92). That is, register restoration processing is performed. If the parity flag is not turned on, an interrupt permission state is set (steps S93 and S94). Finally, the AF register (accumulator and flag register) is restored from the stack area (step S95).

  Then, the RET instruction is executed, but the return destination here is not the part that called the gaming state recovery process. This is because, in step S81, the return processing of the stack pointer is performed, and the return address stored in the stack area pointed to by the returned stack pointer is the address where the NMI occurred when the previous power supply stop in the program. Therefore, in response to the RET instruction subsequent to step S95, the process returns to the address where the NMI occurred when the power supply was stopped. That is, the recovery control is executed based on the address saved in the stack area.

  When the game state restoration process is executed, the check results in step S8 and step S9 are “Y”, so that the stored content is stored in the memory holding means (in this example, the backup power supply even if the power supply to the gaming machine is stopped) This means that the content of the RAM serving as the variation data storage means stored in (1) is stored as it was immediately before the power supply to the gaming machine was stopped. Therefore, the count value of the counter that generates a random number for determining whether or not to win is stored. Therefore, the CPU 56 can restart the increment of the counter from the stored count value. That is, when the game control means executes the game state restoration process, the count value of the random 1 generation counter stored in the power-backed RAM 55 (first numerical value update stored in the fluctuation data storage means) Update of the count value of the random 1 generation counter can be started.

  When the timer interrupt occurs, the CPU 56 performs the register saving process (step S20), and then executes the game control process of steps S21 to S33 shown in FIG. In the game control process, the CPU 56 first inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a through the switch circuit 58. These state determinations are performed (switch processing: step S21).

  Next, various abnormality diagnosis processing is performed by a self-diagnosis function provided in the pachinko gaming machine 1, and processing for issuing an alarm is performed if necessary according to the result (error processing: step S22).

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S23). The CPU 56 further performs processing for updating the count value of the counter for generating the display random number (step S24), and further performs processing for updating the count value of the counter for generating the initial value random number ( Step S25).

  Further, the CPU 56 performs special symbol process processing (step S26). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S27). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs processing for setting a display control command related to the special symbol in a predetermined area of the RAM 55 and transmitting the display control command (special symbol command control processing: step S28). Further, a process for transmitting a display control command by setting a display control command related to the normal symbol in a predetermined area of the RAM 55 is performed (normal symbol command control process: step S29).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S30).

  Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S31). The solenoid circuit 59 drives the solenoids 16, 21, and 21A in response to a drive command in order to open or close the variable winning ball device 15 or the opening / closing plate 20, or to switch the game ball passage in the special winning opening. To do.

  Then, the CPU 56 executes prize ball processing for setting the number of prize balls based on detection signals from the start opening switch 14a, the prize opening switches 29a, 30a, 33a, 39a and the count switch 23 (step S32). Specifically, a payout control command indicating the number of winning balls is given to the payout control board 37 in response to detection of winning based on the start opening switch 14a, winning opening switches 29a, 30a, 33a, 39a and the count switch 23 being turned on. Output. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to a payout control command indicating the number of prize balls.

  Further, control for increasing the start winning memory is performed based on the winning of the game ball to the start port switch 14a (start winning memory processing: step S33). Thereafter, the contents of the register are restored (step S34), and the interrupt permission state is set (step S35).

  With the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  FIG. 22 is a flowchart illustrating an example of a special symbol process processing program executed by the CPU 56. The special symbol process shown in FIG. 22 is a specific process of step S26 in the flowchart of FIG. When performing the special symbol process, the CPU 56 performs any one of steps S300 to S309 according to the internal state (in this example, the special symbol process flag) after performing the variable shortening timer subtraction process (step S310). Perform the process.

  The variation shortening timer subtraction process is a process of subtracting the number of variation shortening timers corresponding to the maximum number that can be stored in the start memory (the memory that the start port switch 14a is turned on). In a special symbol jackpot determination process (step S301), which will be described later, for example, when the value of the fluctuation shortening timer is 0 and the low probability state (normal state), the starting memory number is the maximum value of the starting memory, and the probability variation. In the state, if the number of starting memories is “2” or more, it is determined to use a pattern with a shortened variation time as a symbol variation pattern. The start port switch passage confirmation process is a process for acquiring and storing predetermined random numbers when the start port switch 14a is turned on.

  In steps S300 to S309, the following processing is performed.

  Special symbol normal processing (step S300): The starting memory number is confirmed. If the starting memory number is not 0, the value of the special symbol process flag is changed so as to proceed to step S301.

  Special symbol jackpot determination process (step S301): The contents of a buffer or the like for storing various random numbers stored when a start win is received are shifted. As a result of the shift, it is determined whether or not to make a big hit based on the contents of the pushed-out buffer. Note that the maximum number of buffers that can be stored for start winnings is prepared. Further, the content of the buffer pushed out by the shift is the content corresponding to the start winning that occurred most recently. If it is decided to win, the big hit flag is set. Thereafter, the value of the special symbol process flag is changed so as to proceed to step S302.

  Stop symbol setting process (step S302): The stop symbol of the left and right middle symbols, which is the display result of the variable symbol variable display, is determined. Then, the value of the special symbol process flag is changed so as to proceed to step S303.

  Fluctuation pattern setting process (step S303): A special symbol variable display pattern, that is, a variable display pattern (variation pattern) is determined. Then, a process for outputting a display control command for notifying the determined variation pattern and stop symbol to the symbol control board 80 or the like is performed. Thereafter, the value of the special symbol process flag is changed so as to proceed to step S304.

  Special symbol variation processing (step S304): It is confirmed whether or not the variation time determined according to the variation pattern has elapsed. If it has elapsed, the value of the special symbol process flag is changed so as to proceed to step S305.

  Special symbol stop process (step S305): When a predetermined time (for example, 1.000 seconds) has passed and it has been decided to win, the value of the special symbol process flag is shifted to step S306. To change. Otherwise, the value of the special symbol process flag is changed so as to proceed to step S300.

  Preliminary winning opening opening process (step S306): Control for opening the large winning opening is started. Specifically, the counter and flag are initialized, and the solenoid 54 is driven to open the special winning opening. Then, the value of the special symbol process flag is changed so as to proceed to step S307.

  Processing for opening a special winning opening (step S307): A process for confirming the closing condition of the special winning opening is performed. If the closing condition for the big prize opening is satisfied, the value of the special symbol process flag is changed so as to proceed to step S308.

  Specific area valid time process (step S308): The presence / absence of passing of the V winning switch 22 is monitored, and the process of confirming that the big hit gaming state continuation condition is satisfied is performed. If the condition for continuation of the big hit gaming state is satisfied and there are still remaining rounds, the value of the special symbol process flag is changed so as to proceed to step S307. Further, when the big hit gaming state continuation condition is not satisfied within the predetermined effective time, or when all rounds are finished, the value of the special symbol process flag is changed so as to proceed to step S309.

  Big hit end processing (step S309): Control is performed to cause the lamp control means or the like to display to notify the player that the big hit gaming state has ended. Then, the value of the special symbol process flag is changed so as to proceed to step S300.

  FIG. 23 is a flowchart showing a part related to special symbol start winning memory in the starting winning memory process (step S33) in the game control process shown in FIG. When the hit ball wins the start winning opening 14 provided in the game board 6, the start opening switch 14a is turned on. When the CPU 56 determines that the start port switch 14a is turned on via the switch circuit 58 and the input port 578 (step S41), the CPU 56 checks whether or not the start memory number has reached the upper limit value (4 in this example) (step S41). S42). If the starting memory number has not reached the upper limit value, the starting memory number is increased by 1 (step S43), and the value of each random number such as a big hit determination random number is extracted. Then, they are stored in a random value storage area corresponding to the value of the starting memory number (step S44). When the starting memory number has reached the upper limit value, the process for increasing the starting memory number is not performed.

  Then, the CPU 56 checks whether or not the variable display device 9 can start variable display (variation) of the symbol (special symbol) (step S45). For example, when the special symbol process flag has a value corresponding to the normal process in step S300, it is determined that the special symbol variable display can be started. If the special symbol variable display cannot be started, the lamp control board 35 is controlled to transmit a lamp control command for increasing the display number of the start memory display 18 (the number of lit LEDs) by one. This is performed (step S46).

  In the special symbol process of step S25, the CPU 56 checks the value of the start memory number as shown in FIG. 24 (step S51). If the starting memory number is not 0, the value stored in the random number storage area corresponding to the starting memory; 1 (first starting memory) is read (step S52), and the value of the starting memory number is decreased by 1, And the value of each random value storage area is shifted (step S53). That is, each value stored in the random number value storage area corresponding to the start memory; n (n = 2,..., 4) is stored in the random number value storage area corresponding to the start memory: n−1. Note that the contents of the random number storage area corresponding to the start memory number at that time are cleared. For example, when the start memory number is 4, the contents of the special symbol random number storage area corresponding to the start memory; 4 are cleared.

  Further, since the starting memory number is decremented by 1, processing for sending a starting memory number designation command is performed in order to notify the lamp control means of the new starting memory number (step S65).

  Then, the CPU 56 determines the winning / losing based on the value read in step S52, that is, the value of the extracted jackpot determination random number (special symbol determination random number) (step S54). Here, the jackpot determination random number takes a value in the range of 0 to 316. Then, as shown in FIG. 25, in the normal state, for example, when the value is “3”, it is determined as “big hit”, and when it is other than that, it is determined as “out”. Further, in the high probability state (probability variation state), for example, when the value is any of “3”, “7”, “79”, “103”, “107”, it is determined as “big hit”, otherwise If it is the value of, it is determined as “out of”.

FIG. 26 is an explanatory diagram showing each random number. Each random number is used as follows.
(1) Random 1: Decide whether or not to generate a big hit (for big hit judgment)
(2) Random 2-1 to 2-3: For determining the off-right symbol in the left and right of the special symbol (special symbol right and left)
(3) Random 3: Determines the combination of special symbols that generate a big hit (for determining big hit symbols)
(4) Random 4: Determine the variation pattern of the special symbol (for variation pattern determination)
(5) Random 5: Determines whether or not to generate a hit based on a normal symbol (for normal symbol hit determination)
(6) Random 6: Determine the initial value of random 1 (for determining the random 1 initial value)
(7) Random 7: Determine the initial value of random 5 (for determining the random 5 initial value)

  In step S23 in the game control process shown in FIG. 21, the CPU 56 obtains (1) big hit determination random number, (3) big hit symbol determination random number, and (5) normal symbol determination random number. The counter for generating is incremented (added by 1). That is, they are determination random numbers, and other random numbers are display random numbers or initial value random numbers. In order to enhance the game effect, random numbers related to ordinary symbols other than the random numbers (1) to (7) are also used.

  In step S54 shown in FIG. 24, when it is determined that the jackpot is a jackpot symbol is determined according to the value of the jackpot symbol random number (random 3) (step S55). In this embodiment, each symbol of the symbol number set in the jackpot symbol table corresponding to the value of random 3 is determined as a jackpot symbol. In the jackpot symbol table, left and right symbol numbers corresponding to combinations of a plurality of types of jackpot symbols are set. Further, the random number for determining the variation pattern (random 4) is extracted, and the variation pattern of the special symbol is determined based on the random 4 value (step S56).

  When it is determined that there is a loss, the CPU 56 determines a stop symbol when it is not a big hit. In this embodiment, the left symbol is determined according to the value read in step S52, that is, the extracted random 2-1 value (step S57). Further, the medium symbol is determined according to the value of random 2-2 (step S58). Then, the right symbol is determined according to the random 2-3 value (step S59). Here, if the determined middle symbol matches the left and right symbols, the symbol corresponding to the value obtained by adding 1 to the random number corresponding to the middle symbol is set as the stop symbol of the middle symbol so that it does not match the jackpot symbol. To do.

  Further, the CPU 56 confirms whether or not it is determined to reach (whether or not the left and right stop symbols are aligned) (step S60). A random number (random 4) value is extracted, and a symbol variation pattern is determined based on random 4 (step S61).

  If it is not decided to reach, it is confirmed whether or not it is in the probability variation state (step S62). If it is in the probability variation state, the variation pattern is determined to be the off-time variation variation pattern (step S63). If it is not the probability variation state, the variation pattern is determined to be the normal variation pattern at the time of detachment (step S64). In addition, the fluctuation pattern shortened at the time of detachment is a fluctuation pattern in which the fluctuation period is shorter than the normal fluctuation pattern in which the fluctuation time of the left and right symbols is 4.0 seconds, for example.

  As described above, it is determined whether the pattern variation mode based on the start winning is the reach mode or the off mode, and the combination of the respective stop symbols is determined. That is, as a variation pattern of the special symbol, it is determined whether or not the reach effect is performed, and the combination of the stop symbols is determined.

  The process shown in FIG. 24 corresponds to the process in the case where the processes of steps S301 to S303 in the special symbol process shown in FIG. 22 are collectively shown. In this embodiment, a big hit occurs when the left and right middle symbols are aligned. Reach when only left and right symbols are available.

  27 and 28 are flowcharts showing an example of the determination random number update process (step S23) executed in the game control process shown in FIG. In the determination random number update process, the CPU 56 increments the count value of a counter (random 1 generation counter) for generating random 1 (big hit determination random number) (step S101). When the count value of the counter for generating random 1 is equal to or greater than (maximum value + 1) (step S102), the value is returned to 0 (step S103). In this embodiment, (maximum value + 1) is 317. A value read from a counter (random 1 generation counter) for generating random 1 at a predetermined timing is the extracted random 1 (big hit determination random number). Similarly, the value read from the counter for generating other random 2 etc. is the extracted random 2 etc. Hereinafter, a counter for generating random n (n: 1, 2,...) May be referred to as a random n generating counter.

  Next, the CPU 56 checks whether or not the count value of the random 1 generation counter matches the value stored in the random 1 initial value buffer as an initial value (step S104). If they do not match, the count value remains unchanged. If they match, random 6 (random 1 initial value determination random number) is extracted (step S105). That is, a count value of a counter for generating random 6 (random 6 generation counter) is input. Then, the extracted value is stored as an initial value in the initial value buffer for random 1 (step S106), and the extracted value is set in a counter for generating random 1 (step S107). Therefore, at this time, the initial value of the counter for generating random 1 (random 1 generating counter) is changed.

  Next, +1 is added to the count value of a counter (random 3 generation counter) for generating random 3 (a big hit symbol determination random number) (step S108). When the count value of the random 3 generation counter is equal to or greater than (maximum value + 1) (step S109), the count value is returned to 0 (step S110). In this embodiment, (maximum value + 1) is 12.

  Also, the count value of a counter (random 5 generation counter) for generating random 5 (normal random number for determination per symbol) is incremented by 1 (step S121). When the count value of the counter for generating random 5 is equal to or greater than (maximum value + 1) (step S122), the count value is returned to 3 (step S123). In this embodiment, (maximum value + 1) is 14.

  Then, the CPU 56 checks whether or not the count value of the random 5 generation counter matches the value stored in the random 5 initial value buffer as an initial value (step S124). If they do not match, the count value remains unchanged. If they match, random 7 (random 5 initial value determination random number) is extracted (step S125). That is, the count value of a counter for generating random 7 (random 7 generation counter) is input. The extracted value is stored as an initial value in the random 5 initial value buffer (step S126), and the extracted value is set in the random 5 generation counter (step S127). Therefore, at this time, the initial value of the random 5 generation counter is changed. When the game machine is turned on, “3” is set as an initial value to the counter for generating random 5, but if the value of random 5 is stored in the backup RAM, the power is turned on. Sometimes restored to saved value. A random 5 initial value buffer is also formed in the backup RAM.

  FIG. 29 is executed once in the game control process shown in FIG. 21 (step S25), and the interrupt surplus time in the main process shown in FIG. It is a flowchart showing an example of an initial value random number update process (step S18) that is repeatedly executed at a time until the occurrence of the error.

  In the initial value random number update process, the CPU 56 increments the count value of the counter (random 6 generation counter) for generating random 6 (random 1 initial value determination random number) (step S131). If the count value of the random 6 generation counter is equal to or greater than (maximum value + 1) (step S132), the count value is returned to 0 (step S133). Note that (maximum value + 1) is 317 as in the case of random 1.

  Also, the count value of the random 7 generation counter is incremented by 1 (step S134). If the count value of the random 7 generation counter is equal to or greater than (maximum value + 1) (step S135), the count value is returned to 3 (step S136). Note that (maximum value + 1) is 14 as in the case of random 5.

  FIG. 30 is executed once in the game control process shown in FIG. 21 (step S24), and is repeatedly executed in the surplus interruption time in the main process shown in FIG. 19 (step S17). It is a flowchart which shows an example of an update process.

  In the display random number update process, the CPU 56 increments the count value of the counter (random 4 generation counter) for generating random 4 (variation pattern determining random number) (step S151). When the count value of the random 4 generation counter is 251 or more (step S152), the count value of the random 4 generation counter is decreased by 251 (step S153).

  In this embodiment, the maximum value of random 4 is 250, but the count value of the random 4 generation counter is incremented by 3. Therefore, if the value starts from 0, it will be 249. Becomes 252. Then, when 251 is decreased, the value becomes 1. When the value starts from 1, it becomes 253 after it becomes 250. Then, when 251 is reduced, the value becomes 2. When the value starts from 2, it becomes 251 after becoming 248. Then, when 251 is decreased, the value becomes 0. That is, the initial value of the random 4 value (the value after the value is returned beyond the maximum value) is also somewhat random.

  Next, +1 is added to the count value of a counter (random 2-1 generation counter) for generating random 2-1 (left off symbol determination random number) (step S154). When the count value of the random 2-1 generation counter is equal to or greater than (maximum value + 1) (step S155), the count value is returned to 0 (step S156). In this embodiment, (maximum value + 1) is 12.

  When the count value of the random 2-1 generation counter becomes (maximum value +1) or more and the value is returned to 0, that is, when a carry occurs, random 2-2 (for determining the out of symbol) The count value of a counter (random 2-2 generation counter) for generating (random number) is incremented by 1 (step S157). When the count value of the random 2-2 generation counter is equal to or greater than (maximum value + 1) (step S158), the count value is returned to 0 (step S159). In this embodiment, (maximum value + 1) is 12.

  When the count value of the random 2-2 generation counter becomes (maximum value +1) or more and the value is returned to 0, that is, when a carry occurs, random 2-3 (for determining the right off symbol) The counter value for generating (random number) (random 2-3 generation counter) is incremented by 1 (step S160). When the count value of the random 2-3 generation counter is (maximum value + 1) or more (step S161), the count value is returned to 0 (step S162). In this embodiment, (maximum value + 1) is 12.

  FIG. 31 is an explanatory diagram illustrating an example of a value of a counter (random 1 generation counter) for generating random 1 (big hit determination random number) that is changed by the determination random number update process illustrated in FIGS. 27 and 28. It is. When the power supply to the gaming machine is started and the initialization process is executed, the initial value of the random 1 generation counter becomes the count value (undefined value) of the counter 931 input via the latch circuit 932. Yes. Also, since “0” is initially set in the random 1 initial value buffer, the count value of the random 1 generation counter advances to “316”, and is incremented by 1 to return to 0 (step S101, (S102, S103) and the processing of step S104, it is detected that the count value of the random 1 generation counter matches the initial value. Then, random 6 (random 1 initial value determination random number) is extracted in the process of step S105. This time point is indicated by A in FIG.

  Here, it is assumed that the count value of the random 6 generation counter at that time is “19”. Then, “19” is extracted as random 6, the value is stored (step S106), and the value is set in the random 1 generation counter. Therefore, from this time point, the counter for generating random 1 advances from the initial value “19”.

  When the count value of the random 1 generation counter advances to “19”, it is detected in step S104 that the count value matches the initial value. Then, random 6 is extracted by the process of step S105. This time point is indicated by B in FIG. Assume that the count value of the random 6 generation counter at that time is “195”. Then, “195” is extracted as random 6, the value is stored (step S106), and the value is set in the random 1 generation counter. Therefore, from this point, the random 1 generation counter advances from the initial value “195”.

  When the value of the random 1 generation counter advances to “195”, it is detected in step S104 that the count value matches the initial value. Then, random 6 is extracted by the process of step S105. This time point is indicated by C in FIG. Assume that the count value of the random 6 generation counter at that time is “n”. Then, “n” is extracted as random 6, the value is stored (step S106), and the value is set in the random 1 generation counter. Therefore, from this point, the random 1 generation counter advances from the initial value “n”. In FIG. 31, an asterisk (☆) indicates a position where the count value is “3 (big hit determination value at low probability)”.

  As described above, the random 1 generation counter is set to a random value in the initialization process. That is, when executing the initialization process, the game control means updates the numerical value for determining whether or not to enter a specific gaming state (in this example, a big hit gaming state). The update of the random 1 generating counter as the numerical value updating means) is started based on the count value of the counting means (in this example, the counter 931 and the latch circuit 932), that is, the numerical value of the second numerical value updating means. Therefore, it is difficult to detect the timing at which the count value coincides with the big hit determination value in the first round of the count of the random 1 generation counter (until the maximum value 316 is initially exceeded).

  Thereafter, each time the count value of the random 1 generation counter makes one round (317 counts), a new initial value is generated as the count value of the random 1 generation counter based on the extracted value from the random 6 generation counter. After that, the counter advances from that value. That is, the game control means updates the game control process after starting the updating of the determination numerical value update means as the first numerical value update means based on the count value of the counting means (the numerical value of the second numerical value update means). The initial value of the random 1 generation counter is updated using the numerical value (count value) of the random 6 generation counter as the initial value numerical value updating means. The counter for determining the initial value of the random 1 generation counter (random 6 generation counter) is an extra time for the game control process executed by the CPU 56 (the next 2 ms timer interrupt occurs after the game control process is completed) The time is counted up. The extra time varies depending on the progress of the game, and is a random period. As a result, since the generated random 6 value is also a random value, the initial value of the jackpot determination counter also changes randomly.

  That is, a random initial value is set based on the count value of the hardware circuit in the first round of the count of the random 1 generation counter as the big hit determination counter, and thereafter the count value of the random 1 generation counter is Every time one round is made, the random 1 generation counter starts incrementing from a random initial value based on the count value of the counter by software. Then, even if the illegal board is connected to the main board 31 and the big hit determination count value update timing is recognized based on the signal output from the main board 31, the count value of the random 1 generation counter becomes the big hit determination value. It is difficult to send an incorrect start winning signal to the main board 31 at the timing. This is because, according to this embodiment, as indicated by an asterisk in FIG. 31, the timing at which the count value of the random 1 generation counter becomes the big hit determination value has no regularity and is random.

  Next, a command transmitted from the game control means to each electric component control board will be described. 32 shows control commands (lamp control command, sound control command, display control command, and payout control command) transmitted from the main board 31 to the lamp control board 35, the payout control board 37, the sound control board 70, and the symbol control board 80. ) Is an explanatory diagram showing an example of a command form. In this embodiment, the command data of the control command has a 2-byte configuration, the first byte represents MODE (command type), and the second byte represents EXT (specific instruction content). The first bit (bit 7) of the MODE data is always “1”, and the first bit (bit 7) of the EXT data is always “0”. As described above, the control commands transmitted to the lamp control board 35, the payout control board 37, the sound control board 70, and the symbol control board 80 are composed of a plurality of command data, and can be distinguished from each other by the first bit. ing. Note that the command form shown in FIG. 32 is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used.

  As shown in FIG. 33, the control command includes 8-bit control signals CD0 to CD7 (command data) and an INT signal (capture signal). The lamp control means, payout control means, sound control means, and display control means mounted on the lamp control board 35, the payout control board 37, the sound control board 70, and the symbol control board 80 detect that the INT signal has risen. Then, the 1 byte data capturing process is started by the interrupt process.

  FIG. 34 is an explanatory diagram showing an example of the content of a display control command sent to the symbol control board 80. The display control command has a 2-byte structure of MODE and EXT. In the example shown in FIG. 21, commands 8000 (H) to 8031 (H) are display control commands for designating a special symbol variation pattern. Note that a command for specifying a variation pattern (variation pattern designation command) also serves as a variation start instruction.

  The command 88XX (H) (X = any value of 4 bits) is a display control command related to a normal symbol variation pattern. The command 89XX (H) is a display control command for designating a normal symbol stop symbol. Command 8AXX (H) (X = any value of 4 bits) is a display control command for instructing stop of variable symbol normal display.

  Commands 91XX (H), 92XX (H), and 93XX (H) are display control commands for designating a left middle right stop symbol of a special symbol. Command A0XX (H) is a display control command for instructing stop of variable symbol special display. The command BXXX (H) is a display control command that is sent from the start of the big hit game to the end of the big hit game.

  The command C000 (H) is a display control command related to a display state that is not related to special symbol fluctuations and jackpot games.

  When the display control means of the symbol control board 80 receives the above-described display control command from the game control means of the main board 31, the display state of the display area 150 in the variable display device 9 is changed according to the contents shown in FIG. Control.

  FIG. 35 is an explanatory diagram showing an example of the contents of a lamp control command sent from the main board 31 to the lamp control board 35. The lamp control command also has a 2-byte configuration of MODE and EXT. In the example shown in FIG. 35, commands 8000 (H) to 8031 (H) are lamp controls that specify control patterns of lamps and LEDs (each light emitter provided in the gaming machine) corresponding to the variation pattern of the special symbol. It is a command. The command A0XX (H) (X = any value of 4 bits) is a lamp control command for instructing a lamp / LED control pattern when the variable symbol special display is stopped. The command BXXX (H) is a lamp control command for instructing a lamp / LED control pattern from the start of the jackpot game to the end of the jackpot game. The command C000 is a lamp control command for instructing a lamp / LED control pattern during a customer waiting demonstration.

  Note that the commands 8XXX (H), AXXX (H), BXXX (H), and CXXX (H) are instructions to notify the ramp control command sent from the game control means according to the game progress status, that is, the game state. This is the lamp control command to be performed. When the lamp control means receives the above-described lamp control command from the game control means of the main board 31, the lamp / LED display state (lighted, turned off, and blinking) is changed according to the contents shown in FIG.

  In this embodiment, when the lamp control means receives a lamp control command instructing to notify the gaming state, a part or all of the decorative lamp 25, the top frame lamp 28a, and the left and right frame lamps 28b, 28c are received. Use to perform lighting / extinguishing control for notifying the gaming state. Note that the decorative lamp 25, the top frame lamp 28a, and the left and right frame lamps 28b and 28c may each be formed of a collection of a plurality of light emitters. In this case, the decorative lamp 25, the top frame lamp 28a, and the left and right frame lamps. Notifying the gaming state using a part of 28b and 28c also means that a part of a plurality of light emitters constituting the decorative lamp 25 may be used, for example.

  Command E0XX (H) is a lamp control command indicating the starting memory number (special symbol starting memory number). The lamp control means displays information related to the special symbol start memory number on the start memory display 18 so that the player can recognize the number designated by “XX (H)”. The command E1XX (H) is a lamp control command indicating the normal symbol start memory number. The lamp control means displays information related to the normal symbol start memory number on the normal symbol start memory display 41 so that the player can recognize the number designated by “XX (H)”.

  Commands E200 (H) and E201 (H) are lamp control commands related to the display state of the prize ball lamp 51, and commands E300 (H) and E301 (H) are lamp control commands related to the display state of the ball-out lamp 52. is there. When the lamp control means receives the lamp control command of “E201 (H)” from the game control means of the main board 31, the display state of the prize ball lamp 51 is changed to a display state determined in advance as a case where there is a prize ball remaining. When the lamp control command of “E200 (H)” is received, the display state of the prize ball lamp 51 is set to a display state that is determined in advance as a case where no prize ball remains.

  When the lamp control command “E300 (H)” is received from the game control means of the main board 31, the display state of the ball break lamp 52 is changed to the display state with a ball, and the lamp control command “E301 (H)” is When received, the display state of the ball-out lamp 52 is changed to the display state during the ball-out. That is, the commands E200 (H) and E201 (H) are commands indicating control of a light emitter provided to notify a player or the like that there is an unawarded game ball. (H) and E301 (H) are commands indicating control of a light emitter provided to notify a player or game clerk that the supply ball is out.

  The command “E500 (H)” is a lamp control command designated by the fraud notification lamp transmitted from the game control means when the game control means detects an illegal act. When receiving the lamp control command designated by the fraud notification lamp, the lamp control means controls the lighting of the lamp / LED in a manner predetermined as the manner of fraud notification. For example, all the lamps / LEDs are blinked at a predetermined cycle. Alternatively, a light emitting means for fraud notification may be provided, and the light emitting means may be turned on.

  FIG. 36 is an explanatory diagram showing an example of the contents of a sound control command sent to the sound control board 70. The sound control command also has a 2-byte structure of MODE and EXT. In the example shown in FIG. 36, the command 8XXX (H) (X = any value of 4 bits) is a sound control command for designating a sound generation pattern during a special symbol variation period. Commands 8000 (H) to 8031 (H) are sound control commands for designating sound generation patterns corresponding to the variation patterns of special symbols. The command BXXX (H) (X = any value of 4 bits) is a sound control command for designating a sound generation pattern from the start of the big hit game to the end of the big hit game. The other commands are sound control commands that are not related to special symbol changes and jackpot games. When the sound control means of the sound control board 70 receives the above-described sound control command from the game control means of the main board 31, the sound output state is changed according to the contents shown in FIG.

  The command “E500 (H)” is a sound control command for designating a fraud notification sound transmitted from the game control means when the game control means detects an illegal act. When the sound control means receives the sound control command for specifying the unauthorized notification sound, the sound control means performs control to output the sound from the speaker 27 in a predetermined manner as the unauthorized notification mode.

  When a control command is to be output from the game control means of the main board 31 to each sub-board (lamp control board 35, payout control board 37, sound control board 70, symbol control board 80), the command transmission table is set. Is called. Alternatively, addressing of a command transmission table formed in the ROM 54 is performed. FIG. 37 is an explanatory diagram of a configuration example of the command transmission table. One command transmission table is composed of 3 bytes, and INT data described later is set in the first byte. In the command data 1 of the second byte, MODE data of the first byte of the control command is set. Then, in the command data 2 of the third byte, the EXT data of the second byte of the control command is set.

  Although the EXT data itself may be set in the area of the command data 2, the command data 2 includes data (designated in the ROM 54) for designating the address of the table (formed in the ROM 54). Buffer designation data) may be set. In this embodiment, as shown in FIG. 38A, if bit 7 (work area reference bit) of command data 2 is 0, it indicates that EXT data itself is set in command data 2. Such EXT data is data in which bit 7 is 0. Also, as shown in FIG. 38B, if the work area reference bit is 1, it indicates that the other 7 bits are an offset for designating the address of the table storing the EXT data. In the example shown in FIG. 38B, since bits 4 to 0 are used, 32 types of buffers can be designated. The 32 types of buffers include, for example, a special symbol variation pattern buffer, a special symbol left symbol buffer, a special symbol middle symbol buffer, and a special symbol right symbol buffer.

  FIG. 39 is an explanatory diagram showing a configuration example of INT data. Bit 0 in the INT data indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is “1”, it indicates that a payout control command should be sent. Accordingly, the CPU 56 sets “01 (H)” in the INT data, for example, in the prize ball process (game control process step S32).

  Bit 1 in the INT data indicates whether a display control command should be sent to the symbol control board 80. If bit 1 is “1”, it indicates that a display control command should be sent. Accordingly, the CPU 56 sets “02 (H)” in the INT data, for example, in the special symbol process or the normal symbol process (game control process steps S26 and S27).

  Bits 2 and 3 of the INT data are bits indicating whether or not a lamp control command and a sound control command should be sent, respectively, and the CPU 56 performs special symbol process processing when it is time to send those commands. Etc., INT data, command data 1 and command data 2 are set in the command transmission table pointed to by the pointer (for example, special symbol command transmission pointer). When these commands are transmitted, the corresponding bit of the INT data is set to “1”, and MODE data and EXT data are set to the command data 1 and the command data 2.

  In this embodiment, a plurality of command transmission tables are prepared for each control command, and the command transmission table to be used is set before command transmission. Alternatively, addressing of a command transmission table formed in the ROM 54 is performed. A plurality of command transmission tables may be set as one table. For example, as shown in FIG. 40, one table including a plurality of command transmission tables capable of storing a plurality of display control commands is prepared. For example, in the command control process, the CPU 56 reads INT data, command data 1 and command data 2 from the command transmission table pointed to by the pointer, and transmits a display control command. Then, the pointer is updated. Thereafter, the display control command transmission process is repeated until the command transmission table designated by the pointer indicates the end code. A part of a table prepared for each control command (for example, a table in which a payout number designation command for the payout control board 37 is set) may be configured in a ring buffer format.

  FIG. 41 is a flowchart showing an example of command control processing in the game control processing shown in FIG. The command control process is a process including a command output process and an INT signal output process. In the command control process, the CPU 56 first saves the address of the command transmission table to the stack or the like (step S331). Then, the INT data of the command transmission table pointed to by the pointer is loaded into the argument 1 (step S332). The argument 1 is input information for a command transmission process to be described later. Also, the address indicating the command transmission table is incremented by 1 (step S333). Therefore, the address indicating the command transmission table matches the address of the command data 1. The display control command is set in, for example, the command transmission table shown in FIG.

  Next, the CPU 56 reads the command data 1 and sets it to the argument 2 (step S334). The argument 2 is also input information for a command transmission process to be described later. Then, the command transmission processing routine is called (step S335).

  FIG. 42 is a flowchart showing a command transmission processing routine. In the command transmission processing routine, the CPU 56 first sets the data set as the argument 1, that is, the INT data, in the work area determined as the comparison value (step S351). Next, the number of transmissions = 4 is set in the work area determined as the number of processes (step S352). Then, the address of port 1 is set to the IO address (step S353). In this embodiment, the port 1 address is the output port address for outputting the payout control command data, and the ports 2 to 4 are the display control command data, lamp control command data, and sound control command data. It is assumed that the output port address is for output.

  Next, the CPU 56 shifts the comparison value to the right by 1 bit (step S354). As a result of the shift processing, it is confirmed whether or not the carry bit has become 1 (step S355). When the carry bit becomes 1, it means that the rightmost bit in the INT data is “1”. In this embodiment, four shift processes are performed. For example, when it is specified that a display control command should be sent, the carry bit is set to 1 in the second shift process.

  When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (that is, MODE data) is output to the address set as the IO address (step S 356). When the second shift process is performed, the port 2 address is set as the IO address. At this time, the MODE data of the display control command is output to the port 2.

  Next, the CPU 56 adds 1 to the IO address (step S357) and subtracts 1 from the number of processes (step S358). If port 2 is indicated before addition, the address of port 3 is set as the IO address by the addition processing for the IO address. Port 3 is a port for outputting a lamp control command. Then, the CPU 56 checks the value of the number of processes (step S359), and if the value is not 0, returns to step S354. In step S354, the shift process is performed again.

  In the second shift process, the value of bit 1 in the INT data is pushed out, and the carry flag is set to “1” or “0” depending on the value of bit 1. Therefore, it is checked whether or not it is specified that the display control command should be sent. Similarly, it is checked whether or not the lamp control command and the sound control command are to be sent by the third and fourth shift processes. Thus, when each shift process is performed, an IO address corresponding to a command (payout control command, display control command, lamp control command, sound control command) checked by the shift process is set in the IO address. Has been.

  Therefore, when the carry flag becomes “1”, a control command is sent to the corresponding output port (port 1 to port 4). That is, a single common module can perform control command transmission processing to the control means of each sub-board.

  In addition, as described above, since it is determined to which control means of each sub-board should the control command be output only by the shift process, the process for determining which control means should be output of the control command is simplified. It has become.

  Next, the CPU 56 reads the content of the argument 1 in which the INT data before the start of the shift process is stored (step S360), and outputs the read data to the port 0 (step S361). In this embodiment, the address of port 0 is a port for outputting an INT signal for each control signal, and bits 0 to 4 of port 0 are a payout control INT signal, a display control INT signal, and a ramp, respectively. This is a port for outputting a control INT signal and a sound control INT signal. In the INT data, the bit corresponding to the output bit of the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output in the processing of steps S351 to S359 is “1”. It has become. Therefore, the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output to any of the ports 1 to 4 is turned off (low level).

  Next, the CPU 56 sets a predetermined value in the wait counter (step S362), and subtracts one by one until the value becomes 0 (steps S363 and S364). When the value of the wait counter becomes 0, clear data (00) is set (step S365), and the data is output to port 0 (step S366). Therefore, the INT signal is turned off. Then, a predetermined value is set in the wait counter (step S362), and 1 is subtracted one by one until the value becomes 0 (steps S368 and S369).

  As described above, the MODE data of the first byte of the control command is transmitted. Therefore, the CPU 56 adds 1 to the value indicating the command transmission table in step S336 shown in FIG. Therefore, the command data 2 area of the third byte is designated. The CPU 56 loads the contents of the indicated command data 2 into the argument 2 (step S337). Further, it is confirmed whether or not the value of bit 7 (work area reference bit) of the command data 2 is “0” (step S339). If not 0, the head address of the command extended data address table is set in the pointer (step S339), and the value of bit 6 to bit 0 of the command data 2 is added to the pointer to calculate the address (step S340). Then, the data of the area indicated by the address is loaded into the argument 2 (step S341).

  In the command extension data address table, EXT data that can be sent to the control means of each sub-board is sequentially set. Therefore, if the value of the work area reference bit is “1” by the above processing, the EXT data in the command extended data address table corresponding to the contents of the command data 2 is loaded into the argument 2 and the work area reference bit If the value is “0”, the contents of the command data 2 are loaded into the argument 2 as they are. Even when EXT data is read from the command extension data address table, bit 7 of the data is “0”.

  Next, the CPU 56 calls a command transmission processing routine (step S342). Therefore, the EXT data is transmitted at the same timing as the transmission of MODE data. Thereafter, the CPU 56 restores the address of the command transmission table (step S343) and updates the value of the read pointer indicating the command transmission table (step S344). If there are more commands to be sent (step S345), the process returns to step S331.

  As described above, the control command (payout control command, display control command, lamp control command, sound control command) having a 2-byte structure is transmitted to the control means of each corresponding sub-board. When the control means of each sub-board detects a change in the level of the INT signal, the control command capturing process is started. For any control means, a new signal from the game control means is received before the capturing process is completed. It is not output to the signal line. That is, reliable command reception processing is performed in each control means such as a display control means. The polarity of the INT signal may be reversed from that shown in FIG.

  43 to 45 are flowcharts showing a processing example of a non-maskable interrupt process (power supply stop process) executed in response to a power-off signal from the power supply board 910. When a non-maskable interrupt occurs when the XNMI terminal of the CPU 56 changes from a high level to a low level, the interrupt control mechanism built in the CPU 56 causes the address of the program being executed when the non-maskable interrupt occurs ( Specifically, the next address after completion of execution is saved in the stack area pointed to by the stack pointer, and the value of the stack pointer is increased. That is, the stack pointer value is updated to point to the next address in the stack area. In this embodiment, an interrupt occurs when a change from the high level to the low level occurs at the XNMI terminal. However, even if a microcomputer that generates an interrupt in response to a level change in another aspect is used, Such control can be executed.

  In the power supply stop process, the CPU 56 saves the AF register (accumulator and flag register) in the stack area of the backup RAM area (step S451). Further, the interrupt flag is copied to the parity flag (step S452). The parity flag is formed in the backup RAM area. The interrupt flag is a flag indicating whether the interrupt is permitted or the interrupt prohibited state, and is in a control register built in the CPU 56. The on state of the interrupt flag indicates that the interrupt is prohibited. As described above, the parity flag is referred to in the gaming state restoration process. In the gaming state recovery process, if the parity flag is on, the interrupt permission state is not set.

  Also, the BC register, DE register, HL register, IX register, and stack pointer are saved in the stack area of the backup RAM area (steps S454 to S458). Note that the processing in steps S451 to S458 corresponds to data saving processing for saving the data necessary for restoring the control state in the fluctuation data storage means in accordance with the detection signal of the power supply monitoring means.

  Next, in this embodiment, the detection signal of the prize ball count switch 301A is checked for a predetermined period (during the input monitoring time). When the prize ball count switch 301A is turned on, the content of the total prize ball number buffer is reduced by one. The total prize-ball number buffer is an area for storing the number of unpaid prize balls in the RAM 55, and is added when a payout control command indicating the number of prize balls is transmitted to the payout control board 37 in response to winning, and the prize ball count is increased. Data to be subtracted based on the detection signal of the switch 301A is set.

  In this embodiment, an input monitoring time measuring counter is used to measure the input monitoring time. The value of the counter for measuring the input monitoring time is decremented by 1 every time a switch detection processing loop (a loop starting from S461 and returning to S461) described below is executed once from the initial value m. It is assumed that the input monitoring time is over. In the detection processing loop, although there is an exception, almost constant processing is performed, and therefore, m times the time required for one round of the loop corresponds to the input monitoring time.

  In order to measure the input monitoring time, a built-in timer of the CPU 56 may be used. That is, a predetermined value (corresponding to the input monitoring time) is set in the built-in timer at the start of the switch detection process. Each time the switch detection processing loop is executed once, the count value of the built-in timer is checked. Then, when the count value becomes 0, it is assumed that the input monitoring time has ended. An interrupt by the internal timer can be used to detect that the value of the internal timer has reached 0, but at this stage, the control content (such as each value stored in the RAM) should not be changed. A program configuration is preferred in which the count value of the built-in timer is read and checked instead of using a program.

  Also, the input monitoring time is set to be equal to or longer than the time from when the game ball falls from the ball payout device 97 until it reaches the prize ball count switch 301A. If the distance from the ball payout device 97 to the prize ball count switch 301A is L, the fall time t during that time is t = √ (2L / g) (g: gravitational acceleration), so the input monitoring time is longer than that. Set to When the ball payout device 97 illustrated in FIG. 5 is used, L corresponds to the distance from the position where the game ball falls from the recess of the sprocket 292 to the position of the prize ball count switch 301A. As described above, the input monitoring time is set to a time longer than the time from when the game medium is paid out from the payout means until it is detected by the payout detection means.

  At least during the input monitoring time when the switch detection process is executed, the prize ball count switch 301A must be in a state where it can detect the game ball. Therefore, as shown in FIG. 13, a capacitor 923 serving as a relatively large capacity auxiliary drive power supply is connected to the input side of the converter IC 924 in the power supply substrate 910. Therefore, even when the power supply to the gaming machine is stopped, the + 12V power supply voltage is maintained in a range in which the switch can be driven for a certain period, and the winning ball count switch 301A becomes operable. The capacitance of the capacitor is determined so that the period is equal to or longer than the time until the input monitoring process is completed.

  Since the input port and the CPU 56 are also driven by the + 5V power source created by the converter IC 924, they can operate for a relatively long period even when the power supply is stopped.

  In step S461, an initial value n corresponding to a time of 2 ms is set in the 2 ms measurement counter. Then, until the value of the 2 ms measurement counter becomes 0 (step S462), the value of the 2 ms measurement counter is decremented by 1 (step S463).

  When the value of the 2 ms measurement counter becomes 0, the input of the detection signal of the prize ball count switch 301A is checked. Specifically, the data input to the input port 1 is input (step S464). Next, clear data (00) is set (step S465). Further, port input data, in this case, input data from the input port 1 is set as a “comparison value” (step S466). Further, the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S467).

  Then, the switch timer indicated by the pointer (the address of the switch timer is set) is loaded (step S468), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S469). Data of the input port 1 is set as the comparison value. In this case, the detection signal of the winning ball count switch 301A is pushed out to the carry flag.

  If the value of the carry flag is “1” (step S470), that is, if the detection signal of the prize ball count switch 301A is ON, the value of the switch timer is incremented by 1 (step S471). If the value of the carry flag is “0”, that is, if the detection signal of the prize ball count switch 301A is OFF, clear data is set in the switch timer (step S472). That is, if the switch is off, the value of the switch timer returns to zero.

  When the value of the switch timer becomes 2 (step S473), 1 is subtracted from the value stored in the total prize ball number storage buffer (step S474), and the value of the prize ball information counter is incremented by 1 (step S475). . If the value of the prize ball information counter is 10 or more (step S476), the value of the prize ball information output counter is incremented by 1 (step S477), and the value of the prize ball information counter is incremented by -10 (step S478).

  Next, the value of the input monitoring time measurement counter is decremented by -1 (step S479). If the value is not 0, the process returns to step S461.

  If the prize ball count switch 301A is turned on within the input monitoring time by the above processing, the value of the total prize ball number storage buffer is decremented by one. Since the processing for saving the contents of the backup RAM is performed after such switch detection processing, the total winning ball number storage buffer is always decremented by 1 for winning balls that have been paid out. Therefore, it is possible to prevent a contradiction in the stored control state with respect to the game ball payout. In the above switch detection process, a timer process using a detection period counter is performed. That is, the detection output of the prize ball count switch 301A is checked every 2 ms, and it is considered that the prize ball count switch 301A is reliably turned on when it is detected to be turned on twice in succession. Therefore, erroneous switch-on detection is prevented. In addition, in the switch detection process, the calculation of a prize ball information output number counter for outputting prize ball information to the outside of the gaming machine is also performed, so the prize ball information output to the outside and the actual number of paid-out prize balls are different. There is no such thing.

  Here, the input monitoring process is executed only for the input monitoring time (predetermined time more than the time from when the ball is dropped from the ball payout device 97 until it reaches the prize ball count switch 301A) in the power supply stop process. The input monitoring process may be executed for a long time. For example, the input monitoring process may be continued until the power supply is completely stopped.

  The payout control means mounted on the payout control board 37 also executes power supply stop processing according to the power-off signal. The driving of the payout motor 289 is stopped at an early stage in the power supply stop process (at least before the input monitoring process is started in the power supply stop process in the game control means).

  Further, in this embodiment, the switch detection process of only the prize ball count switch 301A is performed, but the same switch detection process is also performed for the V winning switch 22 and the count switch related to the start winning opening switch and the big winning opening. May be performed. The same switch detection process may be performed for other winnings. When such an on-check is also performed, even if a power failure occurs immediately after a game ball wins a winning opening, the winning is reliably detected and reflected in the saved game state.

  When the input monitoring time elapses (step S480), that is, when the value of the input monitoring time measurement counter becomes 0, the backup specified value ("55 (H)" in this example) is stored in the backup flag (step S481). ). The backup flag is formed in the backup RAM area. Next, parity data is created (steps S482 to S491). That is, first, the clear data (00) is set in the checksum data area (step S482), and the checksum calculation start address is set in the pointer (step S483). Also, the number of checksum calculations is set (step S484).

  Then, an exclusive OR between the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S485). The calculation result is stored in the checksum data area (step S486), the pointer value is incremented by 1 (step S487), and the checksum calculation count value is decremented by 1 (step S488). The processing of steps S485 to S488 is repeated until the value of the checksum calculation count becomes 0 (step S489).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S490). Then, the inverted data is stored in the checksum data area (step S491). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S492). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the CPU 56 sets the clear data (00) in an appropriate register (step S493), and sets the number of processes (in this example, “7”) in another register (step S494). Further, the address of the output port 0 is set in the IO pointer (step S495). Another register is used as the IO pointer.

  Then, clear data is set at the address pointed to by the IO pointer (step S496), the value of the IO pointer is incremented by 1 (step S497), and the value of the processing number is decremented by 1 (step S498). The processes in steps S496 to S498 are repeated until the value of the number of processes becomes zero. As a result, clear data is set in all the output ports 0 to 6 (see FIGS. 16 and 17). As shown in FIGS. 16 and 17, in this example, “1” is in the on state and “00”, which is the clear data, is set in each output port, so all the output ports are in the off state.

  If the determination signal from the determination circuit 950 input to the input port is confirmed and the determination signal is on (eg, high level) (step S171), an unauthorized notification command (lamp control command or sound control command, or The processing for transmitting (both) is performed (step S172).

  At this stage, since the RAM access prohibited state is set, in the process for transmitting the lamp control command and the sound control command, the CPU 56, for example, stores predetermined data (lamp control command and sound control command in the register). 1 byte of the command data of 2 bytes constituting 1) is set, and the value of the register is directly output to the output port. Further, in order to create an ON period (see FIG. 33) of the INT signal, for example, a predetermined value is set in the register and the process of subtracting until 0 is repeated, thereby creating the period. Such processing is executed for the MODE data and the EXT data constituting the fraud notification command.

  Thereafter, the CPU 56 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

  In this embodiment, after the processing for saving the gaming state (in this example, checksum generation and RAM access prevention) is executed, each output port is immediately turned off. In this embodiment, the RAM area in which data used in the game control process is stored is all backed up. Therefore, the checksum generation process indicating whether or not the contents are correctly stored and the RAM access prevention process for preventing the contents from being rewritten correspond to the process for storing the gaming state.

  Since each output port is turned off immediately after the processing for saving the gaming state is executed, it is reliably prevented that a situation that does not match the saved gaming state occurs. When the processes shown in FIGS. 43 to 45 are executed, the power supply to the gaming machine is stopped, so that the voltage applied to the electrical components decreases. When the applied voltage falls below the drivable voltage, the driving of the electrical component is stopped. Therefore, when the power supply to the gaming machine is stopped, the driving of the electrical components is stopped although there is a short delay.

  However, if the clear process for the output port as in this embodiment is not performed, the variable winning ball device 15 is further added while the game control means waits for the power supply to stop after the game state is saved. You may win a prize. In such a case, when the power supply is resumed, the saved gaming state is restored, so that the starting winning memory number at the time of saving is displayed on the starting memory display 18. Then, from the viewpoint of the player, it seems that the stored value of the start winning prize has been reduced, which may cause trouble. However, in this embodiment, there is no possibility of such a trouble occurring.

  In addition, after the game state is stored, there may be a case where a winning in a big winning opening as a variable winning ball apparatus occurs. In such a case, there is a possibility that a trouble may occur due to a difference between the number of winnings recognized by the player and the number of winnings displayed on the display unit based on the stored gaming state when power supply is restored. However, in this embodiment, there is no possibility of such a trouble occurring.

  Further, in this embodiment, the register saving process is performed at the beginning of the process activated in response to the power-off signal, but when the register is not used in the switch detection process, after executing the switch detection process, That is, the register saving process can be performed before the backup flag setting and the checksum calculation process. In this case, the register saving process, the backup flag setting process, the checksum calculation process, and the output port off setting process can be regarded as a power supply stop process. Further, even when several registers are used in the switch detection process, the register storage process can be performed before the backup flag setting process and the checksum calculation process for the unused registers.

  The output port clear process may be performed before the switch detection process is executed (before step S460). During execution of the power supply stop process, the CPU 56 and switches are driven by the charging power of the capacitor. When the output port clear process is performed before the switch detection process is executed, even if the big prize opening, variable prize winning device, etc. are configured to be driven by electrical components such as solenoids, they are driven. In other words, the charging power of the capacitor can be effectively used for the power supply stop process.

  However, in the case where the V winning switch 22 is detected after it is detected that the power is cut off, the output port of the solenoid 21 (which operates the member for guiding the large winning opening to the V winning switch) Clear after switch detection processing. In such a case, when a power failure occurs in a state where the V winning, which is a condition for generating the continuation right, is not generated, the game ball that has entered the big winning opening just before the power failure occurs is guided to the V winning switch 22 side. Can do. Therefore, it is possible to prevent the lapse of the unjust right to continue. In this case, the period during which the power is held is a period longer than the time until the game ball that has won the grand prize opening reaches the V winning switch 22. When a latch type solenoid is used, the output port clear process is not necessary.

  In addition, even when the big prize opening is closed by clearing the output port, there is a possibility that there is a game ball in the big prize opening. Therefore, in the switch detection process executed in response to the power-off signal, the count switch 23 is also detected. It is desirable to do. The output port clearing process may be performed before the switch detection process, and the above exceptional process is not limited to the first type pachinko gaming machine but the second type pachinko gaming machine or the third type. The same applies to seed pachinko machines.

  In this embodiment, the power supply stop process is executed according to the NMI. However, the power supply stop signal is connected to the maskable terminal of the CPU 56 and the power supply stop process is executed by the maskable interrupt process. May be. Alternatively, a power-off signal may be input to the input port and the power supply stop process may be executed according to the input port check result.

  FIG. 46 is an explanatory diagram showing an address map of the RAM area in this embodiment. As shown in FIG. 46, the head of the RAM area is assigned to the backup flag area. A checksum buffer area is allocated at the end. An area from the backup flag to the checksum buffer corresponds to a work area, and a stack area is set in an area after the checksum buffer. In this embodiment, the entire RAM area is backed up.

  FIG. 47 is an explanatory diagram for explaining an example of a checksum creation method. However, in the example shown in FIG. 47, for the sake of simplicity, the size of data in the backup RAM area is 3 bytes. In the power supply stop process based on the power supply voltage drop, as shown in FIG. 47, initial data (00 (H) in this example) is set as the checksum data. Next, an exclusive OR of “00 (H)” and “F0 (H)” is taken, and an exclusive OR of “16 (H)” is taken with the result. Further, an exclusive OR of the result and “DF (H)” is taken. Then, a value (“C6 (H)” in this example) obtained by logically inverting the result (“39 (H)” in this example) is set in the checksum buffer.

  FIG. 47 shows a state where the data “39 (H)” before the logic inversion is stored in the checksum buffer for easy explanation. Note that 00 (H) as the initial data is a value corresponding to the clear data for the checksum data set in step S460, but in actuality, exclusive OR with 00 (H) is before and after the operation. And the value does not change, it is not necessary to perform an exclusive OR operation with 00 (H).

  In this embodiment, the checksum buffer is stored at the last address of the backup RAM area (variable data storage means). Therefore, for example, when checking whether there is an error in the program of the checksum creation method, it is possible to easily check it. This is because it is sufficient to confirm whether or not the value of the final address in the RAM area is correct. In this embodiment, the checksum calculation start address is an address where a backup flag is set, and the checksum calculation final address is the last address in the prize ball control flag buffer (see FIG. 46). . Therefore, if the last address in the backup RAM area is used as the checksum buffer area after the prize ball control flag buffer, there is no waste in the RAM area.

  In consideration of ease of confirmation and prevention of waste of the RAM area, the first address of the backup RAM area may be used as the checksum buffer area.

  Further, at the start of power supply to the gaming machine, it is determined whether or not the parity check is OK (step S9 in FIG. 19). In this determination, the parity data creation process (steps S482 to S491) in the power supply stop process is performed. ) Is performed, and if the processing result, that is, the operation result matches the contents of the checksum buffer, it is determined that the parity check is OK.

  Although the last or first address of the backup RAM area is used as the checksum buffer area here, the checksum buffer area may be allocated to an intermediate area of the backup RAM area. In this embodiment, the checksum is generated based on the work area data. However, the checksum may be generated including the stack area data.

  Further, in this embodiment, at the start of power supply, a checksum is generated by the same process as the process at the time of power supply stop, and the generated checksum is compared with the checksum stored in the backup RAM. Other methods may be used. For example, using the checksum stored in the backup RAM as an initial value, the calculation is performed for each data that is a calculation target in the power supply stop process, and if the calculation result matches a predetermined value (for example, 00 (H)), the parity is You may make it determine with check OK. The check data for the parity check is not limited to the checksum, and other check data may be used as long as it can be determined whether the contents of the backup RAM are properly stored.

  FIG. 48 is a timing chart showing a state of a power supply voltage drop or an NMI signal (= power supply interruption signal: electric power supply stop signal) when power supply to the gaming machine is stopped. When the power supply to the gaming machine is stopped, the voltage value of VSL, which is the highest DC power supply voltage, gradually decreases. In this example, when the voltage drops to +22 V, a power cut-off signal is output from the power monitoring IC 902 mounted on the power board 910 (becomes a low level).

  The power-off signal is introduced into the electrical component control board (in this embodiment, the main board 31 and the payout control board 37) and input to the NMI terminals of the CPU 56 and the payout control CPU 371. The CPU 56 and the payout control CPU 371 execute predetermined power supply stop processing by NMI processing.

  When the voltage value of VSL further decreases to a predetermined value (+9 V in this example), the output of the system reset circuit mounted on the main board 31 and the payout control board 37 becomes low level, and the CPU 56 and payout control CPU 371 enters a system reset state. Note that the CPU 56 and the payout control CPU 371 have completed the power supply stop process before being set to the system reset state.

  When the voltage value of VSL is further decreased to be lower than a voltage capable of generating Vcc (+5 V for driving various circuits), each circuit cannot be operated on each substrate. However, at least the main board 31 and the payout control board 37 execute the power supply stop process, and the CPU 56 and the payout control CPU 371 are in the system reset state.

  As described above, in this embodiment, the power supply monitoring circuit monitors the voltage of the highest power supply VSL among the DC voltages used in the gaming machine, and the voltage drops when the voltage of the power supply falls below a predetermined value. Generates a signal (power failure detection signal). As shown in FIG. 48, at the timing when the power-off signal is output, the IC drive voltage is still a voltage value that can sufficiently drive various circuit elements. Therefore, an operation time is ensured for the CPU 56 of the main board 31 operating with the IC drive voltage to perform a predetermined power supply stop process.

  In this case, the power supply monitoring circuit monitors the voltage of the highest power supply VSL among the DC voltages used in the gaming machine, but the timing for generating the power-off signal is the electrical component control that operates with the IC drive voltage. The monitoring target voltage may not be the highest voltage of the power source VSL as long as the operation time for the means to perform the predetermined power supply stop process is ensured. That is, if at least a voltage higher than the IC drive voltage is monitored, the power-off signal can be generated at such a timing that the operation time for the electrical component control means to perform the predetermined power supply stop process is secured. .

In this case, as described above, the monitoring target voltage is preferably a voltage that can be expected to prevent erroneous switch-on detection when power supply is stopped. That is, since the voltage (switch voltage) supplied to the various switches of the gaming machine is + 12V, it is preferable that the voltage drop can be detected before the + 12V power supply voltage starts to drop. Therefore, it is preferable to monitor a voltage higher than at least the switch voltage.
Stop.

  Next, display control means including the display control CPU 101 will be described. FIG. 49 is a flowchart illustrating main processing executed by the display control CPU 101. In the main process, an initialization process is first performed for clearing the RAM area, setting various initial values, and initializing a 2 ms timer for determining the display control activation interval (step S701). Thereafter, in this embodiment, the display control CPU 101 shifts to a loop process for monitoring the timer interrupt flag (step S703). In the loop, a process for updating a counter for generating a predetermined random number is also performed (step S702). As shown in FIG. 50, when a timer interrupt occurs, the display control CPU 101 sets a timer interrupt flag (step S715). If the timer interrupt flag is set in the main process, the display control CPU 101 clears the flag (step S704) and executes the following variable display control process.

  In this embodiment, it is assumed that the timer interrupt takes every 2 ms. That is, the variable display control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the specific variable display control process is executed in the main process. However, the variable display control process may be executed in the timer interrupt process. .

  In the variable display control process, the display control CPU 101 first analyzes the received display control command (command analysis execution process: step S705). Next, it is confirmed whether or not an initialization notification command has been received (step S706). Specifically, it is confirmed whether or not a command reception flag corresponding to the initialization notification command is set. If the initialization notification command has been received, the initialization notification for notifying the execution of the initialization process is started (step S707). In this example, as the initialization notification, the variable notification device 9 displays an initialization notification screen composed of characters and figures such as “Initialization process in progress!”. The initialization notification screen is a screen for notifying the execution of the initialization process, and data indicating the initialization notification screen is stored in, for example, the character ROM 86. The display control CPU 101 turns on the initialization notification flag (step S708) and sets an initialization notification period timer (step S709). The initialization notification in progress flag is a flag for confirming whether or not the initialization notification is being executed, and is stored in a RAM provided in the display control board 80. The initialization notification period timer is a timer for measuring the execution period of the initialization notification. The initialization notification execution period is set to a relatively long period (for example, 5 minutes) in order to ensure notification.

  Next, the display control CPU 101 checks whether or not the initialization notification flag is on (step S710). If the initialization notification flag is on, it is checked whether or not the initialization notification period timer has timed out (step S711). If it has timed out, the initialization notification flag is turned off (step S712). Then, the display of the initialization notification screen on the variable display device 9 is terminated (step S713).

  Further, the display control CPU 101 performs display control process processing (step S714). In the display control process process, a process corresponding to the current control state is selected and executed from among the processes corresponding to the control state. Thereafter, the process returns to step S702.

  Next, display control command reception processing from the main board 31 will be described. FIG. 51 is an explanatory diagram showing a configuration example of a command reception buffer for storing a display control command received from the main board 31. In this example, a command reception buffer of a ring buffer format capable of storing six display control commands having a 2-byte configuration is used. Therefore, the command reception buffer is configured by a 12-byte area of reception command buffers 1 to 12. A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11. It is not always necessary to use the ring buffer format. For example, three symbol designating command storage areas (2 × 3 = 6 byte command receiving buffer) and other command storing areas for designating other fluctuation patterns ( (2 × 1 = 2-byte command reception buffer). Similarly, the sound control means and the lamp control means may have a buffer format other than the ring buffer format. In this case, the display control means, the sound control means, and the lamp control means are controlled based on the latest command stored in the storage area such as the variation pattern. Thereby, it is possible to quickly respond to an instruction from the main board 31.

  FIG. 52 is a flowchart showing display control command reception processing by interrupt processing. An INT signal for display control from the main board 31 is input to an interrupt terminal of the CPU 101 for display control. For example, when the INT signal from the main board 31 is turned on, the display control CPU 101 is interrupted. Then, the display control command reception process shown in FIG. 52 is started.

  In the display control command reception process, the display control CPU 101 first saves each register to the stack (step S670). When an interrupt occurs, the display control CPU 101 automatically sets the interrupt prohibited state. However, if a CPU that does not automatically enter the interrupt prohibited state is used, before executing the process of step S670. It is preferable to issue an interrupt prohibition instruction (DI instruction). Next, data is read from an input port assigned to input of display control command data (step S671). And it is confirmed whether it is the 1st byte of the display control command of 2 bytes composition (Step S672).

  Whether or not it is the first byte is confirmed by whether or not the first bit of the received command is “1”. The first bit of “1” is supposed to be MODE data (first byte) in the display control command having a 2-byte configuration (see FIG. 32). Therefore, if the first bit is “1”, the display control CPU 101 stores the received command in the reception command buffer indicated by the command reception number counter in the reception buffer area, assuming that the first valid byte has been received (step S1). S673).

  If it is not the first byte of the display control command, it is confirmed whether or not the first byte has already been received (step S674). Whether or not it has already been received is confirmed by whether or not valid data is set in the reception buffer (reception command buffer).

  If the first byte has already been received, it is confirmed whether or not the first bit of the received 1 byte is “0”. If the first bit is “0”, it is determined that a valid second byte has been received, and the received command is stored in the reception command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S675). The first bit of “0” is supposed to be EXT data (second byte) in the display control command having a 2-byte configuration (see FIG. 32). If the confirmation result in step S674 indicates that the first byte has already been received, the process ends unless the first bit of the data received as the second byte is “0”.

  In step S675, when the command data of the second byte is stored, 2 is added to the command reception number counter (step S676). Then, it is confirmed whether or not the command reception counter is 12 or more (step S677), and if it is 12 or more, the command reception number counter is cleared (step S678). Thereafter, the saved register is restored (step S679), and interrupt permission is set (step S680).

  The display control command has a two-byte configuration, and the first byte (MODE) and the second byte (EXT) are configured to be immediately distinguishable on the receiving side. In other words, the reception side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. Therefore, as described above, it can be easily determined whether or not appropriate data has been received. This also applies to the payout control command, the lamp control command, and the sound control command.

  FIG. 53 is a flowchart illustrating a specific example of command analysis processing (step S705). The display control command received from the main board 31 is stored in the reception command buffer. In the command analysis process, the contents of the command stored in the reception command buffer are confirmed.

  In the command analysis process, the display control CPU 101 first checks whether or not a reception command is stored in the command reception buffer (step S681). Whether it is stored or not is determined by comparing the value of the command reception counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the display control CPU 101 confirms whether or not the initialization processing flag is on (step S682). If the initialization processing flag is on, the reception command stored in the command reception buffer is cleared (step S683). In other words, the display control CPU 101 does not execute processing based on the received command while the initialization notification is being executed. When the received command is cleared, the value of the read pointer is incremented by one. If the initialization processing flag is off, the display control CPU 101 reads the received command from the command reception buffer (step S684). When read, the value of the read pointer is incremented by one.

  If the received received command is a left symbol designation command (step S685), the EXT data of the command is stored in the left stop symbol storage area (step S686), and the corresponding valid flag is set (step S687). Whether or not it is a left symbol designation command can be immediately recognized by the first byte (MODE data) of the 2-byte display control command.

  If the received received command is a middle symbol designation command (step S688), the display control CPU 101 stores the EXT data of the command in the middle stop symbol storage area (step S689) and sets the corresponding valid flag (step S689). Step S690). If the received received command is a right symbol designation command (step S691), the EXT data of the command is stored in the right stop symbol storage area (step S692), and the corresponding valid flag is set (step S693). The left middle right stop symbol storage area is provided in, for example, a RAM provided in the display control board 80.

  If the received reception command is a variation pattern command (step S694), the display control CPU 101 stores the EXT data of the command in the variation pattern storage area (step S695) and sets the variation pattern reception flag (step S696). ). The variation pattern storage area is provided in, for example, a RAM provided in the display control board 80.

  If the read reception command is an initialization notification command (step S697), the display control CPU 101 sets an initialization notification reception flag (step S698). In this embodiment, since the jackpot start display command is used as the initialization notification command, it is necessary to confirm whether or not the received command is a command transmitted as the initialization notification command. In this case, for example, after the start of power supply to the gaming machine and before receiving the variation pattern command, if the big hit start display command is received, the initialization notification command is received. It may be determined. It should be noted that other methods may be used such as confirmation that an initialization notification command has been received when a jackpot start display command is received before a predetermined period of time has elapsed after power supply to the gaming machine has started. It may be.

  If the received command read in step S684 is another display control command, a flag corresponding to the received command is set (step S699).

  As described above, when the initialization process is executed, the variable display device 9 is configured to perform the initialization notification. Therefore, even if an illegal act such as illegally sending a signal to the game control means is performed, Such an illegal act can be easily detected, and even when the fraudster notices the notification and immediately leaves his / her seat, there is an effect that it is difficult to execute the illegal act again. It is unlikely that the initialization process will be executed unless the amusement store is in operation, even when it is restored from a power failure. Nevertheless, the fact that the initialization process is being executed is highly likely that the system has been reset by an illegal act such as causing a stack overflow or inputting a reset signal to the game control means. Therefore, when the initialization operation is not performed by the game shop clerk even when the power failure is restored, but the initialization notification is given during the business hours of the game shop, an illegal act (clearing the RAM to the initial state) It is possible to determine that an act or the like has been performed, and to prevent subsequent fraudulent acts (acts such as generating jackpots).

  Further, as described above, the game control means (CPU 56) transmits an initialization notification command indicating that the initialization notification is performed to the display control means (display control CPU 101), and the display control means is for the initialization notification. Since the above processing is executed, the processing load for performing the initialization notification in the game control means is reduced.

  In addition, as described above, the initialization notification is continuously executed for a predetermined period (a period set in the initialization notification period timer, for example, a predetermined period such as 5 minutes). Discovery of actions can be facilitated.

  In addition, as described above, even when the display control unit receives a new command during the execution of the initialization notification, the display control unit is configured not to execute the control based on the newly received command. Even if a command is transmitted illegally, the process based on the command is not executed and the initialization notification is continued, so that the notification is stopped based on the command transmitted illegally. This can be prevented.

  In addition, as described above, since the configuration is made using the jackpot start display command as the initialization notification command for specifying the initialization notification, even if an illegal act that interferes with the initialization notification is performed, Acts can be easily discovered. That is, if the initialization notification command is illegally masked and the specification by the initialization notification command is illegally disabled, the jackpot start display command is also masked at the same time, so the jackpot game is started. Sometimes the big hit start will not be displayed. As described above, when the initialization notification command is illegally masked, the normal game is affected. Therefore, it can be easily found that the designation by the initialization notification command is illegally disabled.

  Note that another existing command may be used as an initialization notification command for specifying initialization notification. Even in this case, if the initialization notification command is illegally masked, it will affect the normal game, so that illegal acts can be easily detected. In this case, as an initialization notification command, a command that designates a relatively conspicuous effect such as a command related to a jackpot game (for example, a display command when the big winning opening is opened, a display command when the big winning opening is opened, a big winning end display command, or the like) is used. By doing so, cheating can be detected more easily.

  In addition, a dedicated command different from other existing commands may be used as the initialization notification command for specifying initialization notification. With this configuration, when the initialization notification command is received, the display control means has been transmitted as a command for designating initialization notification as to whether it has been transmitted as another commonly used command. It is possible to immediately recognize that the command is for specifying the initialization notification without confirming whether the command has been received.

  In addition, as described above, the game control means (CPU 56) is configured to output an initialization signal indicating that initialization processing is being performed to the outside of the gaming machine, so that the game store side or the like is performing initialization processing. Can be recognized. Therefore, if a signal indicating that the initialization process is being performed despite the fact that the power supply has not actually stopped is output from the gaming machine, it can be determined that fraud has occurred, Will be able to easily discover fraudulent activity away from the gaming machine that has committed fraud.

  Note that the game control means (CPU 56) may output a signal indicating that power supply stop processing is being performed to the outside of the gaming machine. For example, the information output signal is output to a hall computer or the like. When a signal indicating that processing is being performed when power supply is stopped is output to the hall computer or the like, it is possible for the amusement shop to recognize that processing when power supply is stopped. Therefore, when a signal indicating that the power supply stop process is being performed is output from the gaming machine even though the power supply has not actually stopped, it can be determined that an illegal act has been performed.

  In this way, if the amusement store is configured so that it can recognize that the gaming machine is in the initialization process or in the process of stopping power supply, the amusement store will illegally detect that an illegal act has been detected. It is possible to identify a person who is cheating without the agent being aware.

  In the above-described embodiment, the variable display device 9 is configured to notify the execution of the initialization process by performing the initialization notification. However, display means other than the variable display device 9 (for example, for initialization notification) It is good also as a structure alert | reported by a display apparatus for exclusive use. Moreover, it is good also as a structure which alert | reports initialization notification by a lamp | ramp, a sound, etc., for example.

  Next, a configuration in which initialization notification is notified by a light emitter such as a lamp or LED will be described. Here, the operation of the lamp control means, which is an example of the electrical component control means, and serves as the light emitter control means including the lamp control CPU 351 mounted on the lamp control board 35 will be described.

  FIG. 54 is a flowchart showing main processing executed by the lamp control CPU 351. In the main process, the lamp control CPU 351 first executes an initialization process for initializing a register, a RAM including a work area, an output port, and the like (step S441). Thereafter, in this embodiment, the lamp control CPU 351 proceeds to a loop process for checking the timer interrupt flag (step S443). In the loop, a process for updating a counter for generating a predetermined random number is also performed (step S442). As shown in FIG. 55, when a timer interrupt occurs, the lamp control CPU 351 sets a timer interrupt flag (step S457). If the timer interrupt flag is set in the main process, the lamp control CPU 351 clears the flag (step S444) and executes the following lamp control process.

  In this embodiment, it is assumed that the timer interrupt takes every 2 ms. That is, the lamp control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the specific lamp control process is executed in the main process, but the lamp control process may be executed in the timer interrupt process.

  In the lamp control process, the lamp control CPU 351 first checks whether a lamp control command has been received from the main board 31 (step S445: command recognition process). Next, it is confirmed whether or not an initialization notification command has been received (step S446). Specifically, it is confirmed whether or not a command reception flag corresponding to the initialization notification command is set. Here, for example, a big hit start lamp designation command (see FIG. 35) is used as the initialization notification command. If the initialization notification command has been received, the initialization notification for notifying the execution of the initialization process is started (step S447). In this example, as initialization notification, a process of turning on or blinking the light emitter controlled by the lamp control board 35 is performed. The lamp control CPU 351 turns on the initialization notification flag (step S448) and sets an initialization notification period timer (step S449). The initialization notification flag is a flag for confirming whether or not the initialization notification is being executed, and is stored in a RAM provided in the lamp control board 35. The initialization notification period timer is a timer for measuring the execution period of the initialization notification. The initialization notification execution period is set to a relatively long period (for example, 5 minutes) in order to ensure notification.

  Next, the lamp control CPU 351 confirms whether or not the initialization notification flag is on (step S450). If the initialization notification flag is on, it is checked whether the initialization notification period timer has timed out (step S451), and if it has timed out, the initialization notification flag is turned off (step S452). Then, the execution of the initialization notification using the light emitter is terminated (step S453).

  Further, the lamp control CPU 351 performs a command execution process such as a process of changing lamp data to be used in accordance with the received lamp control command (step S454). The lamp control command from the main board 31 is taken in by an interrupt process activated in response to the input of the INT signal and stored in an input buffer formed in the RAM. Thereafter, in this embodiment, the lamp control CPU 351 performs lamp process update processing and port output processing (steps S455 and S456). Thereafter, the process returns to step S442.

  In this embodiment, the lighting pattern of the lamp / LED that is controlled to blink according to the progress of the game is controlled according to the lamp data stored in the ROM. Ramp data is prepared for each type of control pattern (control commands that specify an effect pattern by lamps and LEDs during the change of special symbols, and other game effects sent from the game control means according to the game progress status. Prepared for each control command). In the lamp data, data indicating that the lamp / LED is turned on or off and data indicating a lighting or extinguishing period (process timer value) are set. That is, data indicating the lighting pattern of the light emitter is stored in the control data area.

  In the lamp process update process, it is determined whether or not the process timer has timed out based on the value of the effect timer stored in the timer state storage area. Specifically, the process timer value corresponding to the data set to turn off or turn on the lamp / LED is added to the value of the effect timer stored in the timer state storage area, and the effect based on the data is started. The process end determination value is calculated and stored in a predetermined area of the RAM. The effect timer is updated by timer interruption processing. Then, it is checked whether or not the value of the effect timer matches the calculated process end determination value. If they match, it is determined that the process timer has timed out. If it is determined that the process timer has timed out, it is decided to turn off or turn on the lamp / LED according to the data set at the next address in the lamp data, and the process according to the decision result The timer value is added to the value of the production timer, and a new process end determination value is calculated and stored. When a new process end determination value is set, it is a time of switching on / off, so that data for turning on / off the lamp / LED is output to the corresponding output port in the port output processing.

  As described above, when the initialization process is executed, even when the initialization notification is made using the illuminant, the signal is illegally transmitted to the game control means as in the case of the notification by the variable display device 9. Even if a fraudulent act such as sending a message is made, such a fraudulent act can be easily detected, and even if the fraudulent notices the notification and immediately leaves the office, the fraudulent act is performed again. It has the effect of making it difficult. Moreover, since it is possible to easily find out that a fraudulent act (an act such as clearing the RAM to the initial state) has been performed, subsequent fraudulent acts (acts such as generating a big hit) are prevented in advance. be able to.

  Next, a configuration in which initialization notification is notified by an audio output device such as a speaker will be described. Here, the operation of the sound control means including the sound control CPU 701 mounted on the sound control board 70 will be described as an example of the electrical component control means.

  FIG. 56 is a flowchart showing main processing executed by the sound control CPU 701. In the main process, the sound control CPU 701 first executes an initialization process for initializing a register, a RAM including a work area, an output port, and the like (step S471). Thereafter, in this embodiment, the sound control CPU 701 proceeds to a loop process for checking the timer interrupt flag (step S473). In the loop, a process for updating a counter for generating a predetermined random number is also performed (step S472). As shown in FIG. 57, when a timer interrupt occurs, the sound control CPU 701 sets a timer interrupt flag (step S487). If the timer interrupt flag is set in the main process, the sound control CPU 701 clears the flag (step S474) and executes the following sound control process.

  In this embodiment, it is assumed that the timer interrupt takes every 2 ms. That is, the sound control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the specific sound control process is executed in the main process, but the sound control process may be executed in the timer interrupt process.

  In the sound control process, the sound control CPU 701 first checks whether or not a sound control command has been received from the main board 31 (step S475: command recognition process). Next, it is confirmed whether or not an initialization notification command has been received (step S476). Specifically, it is confirmed whether or not a command reception flag corresponding to the initialization notification command is set. Here, for example, a jackpot start sound designation command (see FIG. 36) is used as the initialization notification command. If the initialization notification command has been received, the initialization notification for notifying the execution of the initialization process is started (step S477). In this example, as the initialization notification, a predetermined sound output process is performed using the speaker 27 controlled by the sound control board 70. Further, the sound control CPU 701 turns on the initialization notification flag (step S478) and sets an initialization notification period timer (step S479). The initialization notification flag is a flag for confirming whether or not the initialization notification is being executed, and is stored in the RAM provided in the sound control board 70. The initialization notification period timer is a timer for measuring the execution period of the initialization notification. The initialization notification execution period is set to a relatively long period (for example, 5 minutes) in order to ensure notification.

  Next, the sound control CPU 701 confirms whether or not the initialization notification flag is on (step S480). If the initialization notification flag is on, it is checked whether the initialization notification period timer has timed out (step S481), and if it has timed out, the initialization notification flag is turned off (step S482). Then, the initialization notification using the sound output means (speaker 27) is terminated (step S483).

  Furthermore, the sound control CPU 701 performs a command execution process, which is a process of changing sound data to be used, in accordance with the received sound control command (step S484). Note that the sound control command from the main board 31 is captured by an interrupt process activated in response to the input of the INT signal, and stored in an input buffer formed in the RAM. Thereafter, in this embodiment, the sound control CPU 701 performs a sound process update process and a port output process (steps S485 and S486). Thereafter, the process returns to step S472.

  In this embodiment, the sound pattern output from the speaker 27 in accordance with the progress of the game is controlled according to the sound data stored in the ROM. Audio data is prepared for each type of control pattern (a control command for specifying an effect pattern by the sound output means during the change of the special symbol and other game effects sent from the game control means according to the game progress status) Prepared for each control command).

  The voice synthesis circuit 702 is controlled by a transfer request signal (SIRQ), a serial clock signal (SICK), a serial data signal (SI), and a transfer end signal (SRDY). When the SIRQ goes low, the speech synthesis circuit 702 takes in SI one bit at a time in synchronization with SICK, and when SRDY goes low, interprets the data composed of the SIs received so far as one voice playback data. To do.

  In each audio data, data corresponding to the serial data signal output to the audio synthesis circuit 702 and data indicating the duration (process timer value) of the audio generated according to the data are set. That is, the control data stores data indicating the output pattern from the sound generating means (the speaker 27 in this example).

  In the audio process update process, the value of the timer corresponding to the process timer value is initially subtracted, and when the timer times out, it is output according to the data set at the next address in the audio data It is determined to change to voice, and a process timer value corresponding to the determination result is set in the timer. In addition, since the output voice is switched when the process timer value is set in the timer, in the port output process (step S486), via the output port for outputting data to the voice synthesis circuit 702, Data corresponding to the new output voice is output to the voice synthesis circuit 702.

  In the audio process update process, it is determined whether or not the process timer has timed out based on the value of the effect timer stored in the timer state storage area. Specifically, the process timer value corresponding to the data set to be output by the speaker 27 is added to the value of the effect timer when starting the effect based on the data, and the process end determination value is set. Calculated and stored in a predetermined area of the RAM. The effect timer is updated by timer interruption processing. Then, it is checked whether or not the value of the production timer stored in the timer state storage area matches the calculated process end judgment value. If they match, the process timer has timed out Is determined. When it is determined that the process timer has timed out, it is determined to output audio according to the data set at the next address in the audio data, and the process timer value corresponding to the determination result is produced. A new process end determination value is calculated and added to the timer value and stored. When a new process end determination value is set, the output voice is switched. Therefore, in the port output process (step S486), the voice is sent via the output port for outputting data to the voice synthesis circuit 702. Data corresponding to the new output sound is output to the synthesis circuit 702.

  Specifically, in the port output process, the sound control CPU 701 turns on SIRQ (low level) and outputs data (voice command) read from ROM (voice command data area) as SI in synchronization with SICK. When the output is completed, SRDY is set to a low level. When the voice synthesis circuit 702 receives data by SI, the voice synthesis circuit 702 generates voice corresponding to the received data.

  As described above, when the initialization process is executed, the case where the initialization notification is performed using the sound output unit is also illegally transmitted to the game control unit in the same manner as in the case of the notification by the variable display device 9. Even if a fraudulent act such as sending a signal is performed, such a fraudulent activity can be easily detected, and even if the fraudulent person notices the notification and immediately leaves his / her seat, This has the effect of making it difficult to execute. Moreover, since it is possible to easily find out that a fraudulent act (an act such as clearing the RAM to the initial state) has been performed, subsequent fraudulent acts (acts such as generating a big hit) are prevented in advance. be able to.

  As described above, in this embodiment, the gaming machine has a game control means for performing control related to the game, and a backup capable of retaining the stored contents for a predetermined period even when power supply to the gaming machine is stopped. A main board 31 on which a RAM is mounted; power supply monitoring means (monitoring power supply IC 902 in this embodiment) for monitoring the output voltage of a power supply of a predetermined potential and outputting a detection signal when a detection condition is satisfied; And a determination numerical value updating means (in this embodiment, a random 1 generation counter) for updating a determination numerical value used for determining whether or not to give a predetermined game value to a person within a predetermined numerical value range. The main board 31 includes a first oscillation circuit 92 that generates an oscillation signal used for the operation of the game control means, and a second oscillation circuit 930 that is configured separately from the first oscillation circuit 92 and generates a predetermined oscillation signal. When Counting means (counter 931 in this embodiment) for counting the oscillation signal of the second oscillation circuit 930 is mounted, and the game control means restores the control state in relation to the output of the detection signal from the power supply monitoring means. It is possible to execute a power supply stop process including a process for saving data necessary for backup to the backup RAM, and initialize the control state according to a predetermined condition when power supply to the gaming machine is started. Either the initialization process or the restoration process that restores the control state based on the stored contents of the backup RAM can be executed. When the initialization process is executed, it is determined based on the count value of the counting means. It is configured to start updating the numerical value updating means. The predetermined condition is, for example, that the stored contents of the backup RAM are stored in the state when the power supply is stopped when the power supply is started.

  In addition, the game control means includes initial value numerical value updating means (in this embodiment, a random 6 generation counter) for updating a numerical value within a predetermined numerical value range in the game control processing executed by the game control means. After the updating of the determination numerical value updating means is started based on the count value, the initial value is updated using the numerical value of the initial value numerical value updating means.

  Specifically, in accordance with the game control program, the CPU 56 generates a counter (931 in the above example) for generating a big hit determination random number in the initialization process (step S101 shown in FIG. 19). Is initialized to an indefinite value based on the count value of the random number, and when the count value of the random 1 generation counter reaches the maximum value, a new initial value is set based on the value of the random number for initial value (any of 0 to 316: see FIG. 26). Set. Therefore, in the first round after initialization, it is difficult to grasp the timing at which the count value of the counter for generating the jackpot determination random number matches the predetermined jackpot determination value.

  Further, the count value of the counting means is stored even if the power supply to the gaming machine is stopped. That is, even if the power supply to the gaming machine is stopped, it is not initialized. Therefore, it is possible to make it more difficult to receive fraud related to the stop of power supply to the gaming machine.

  Further, when executing the restoration process, the game control means starts updating based on the update value of the determination numerical value update means stored in the backup RAM that is not a specific value.

  Note that when the counter for generating the big hit determination random number is the first round after the initialization process, even if there is a start win, for example, the big hit determination random number is not extracted in step S44 described above. Another lottery value may be used, or a lottery based on the big hit determination random number may not be performed, for example, it is always judged as a miss in step S54. With this configuration, even if the initial value of the counter for generating the jackpot determination random number in the initialization process is not indefinite, the initial value of the jackpot determination random number cannot be specified. Even when the update is the first round after the initialization, it is possible to prevent the jackpot determination value from being targeted by an illegal act.

  In the above embodiment, the counter for generating the determination random number and the initial value determining random number other than the counter for generating the big hit determination random number is used in the initialization process (step S101 shown in FIG. 19). Although initialized to 0, the counter value may not be initialized to 0 in the initialization process. By doing so, even if the initialization process is executed, the initial value of each counter varies, so that it is possible to prevent the jackpot determination value from being targeted by fraud.

  For example, a circuit corresponding to the system reset circuit 65 (referred to as a reset circuit) is provided not on the main board 31 but on a board outside the main board 31 such as the power source board 910, and the system reset signal is sent from the reset circuit to the main board 31. In the configuration in which the signals are input to the substrates 31, there is a possibility that the illegal acts as described above are performed between the substrates. In other words, there is a possibility that an illegal circuit that causes a system reset signal to be illegally input to the main board 31 is connected to the cable between the boards and the illegal action is performed. When a system reset signal is illegally input to the CPU 56 of the main board 31, the control state returns to the initial state as in the case where power supply to the gaming machine is started. That is, the CPU 56 enters a state in which the main process shown in FIG. 9 is executed from the beginning. In this case, since the power supply stop process is not executed, the gaming state restoration process (step S10 in FIG. 19) is not executed, and the CPU 56 executes the initialization process.

  In the initialization process, when the count value of the counter for generating the determination random number is initialized to 0, the counter for generating the big hit determination random number (random 1) from the time when the system reset signal is illegally input This makes it easy to predict the timing at which the count value matches the jackpot determination value. The fraudulent person illegally generates a big hit by sending an illegal signal that causes a start prize at that timing to the main board 31.

  However, as described above, in the initialization process, the count value of the counter for generating the determination random number is initialized to an indefinite value, or when the determination random number is updated in the first round, the big hit lottery If it is not performed, such illegal acts can be prevented. Then, after the power supply stop process is executed, when the power supply is restored and the game state recovery process is executed, in the game state recovery process, the CPU 56 determines from the count value stored in the backup RAM. Resume counter stepping.

  Also, in the initialization process, if the counter update for generating the big hit determination random number is the first round, if the big hit lottery is not performed, the system reset signal is input incorrectly. Even if the control state returns to the initial state, the update of the first cycle is completed immediately, and the count value of the counter for generating the determination random number is updated by the counter value for generating the initial value determining random number. As a result, it becomes difficult to predict the timing when the count value of the counter for generating random 1 matches the jackpot determination value. Then, after the power supply stop process is executed, when the power supply is restored and the game state recovery process is executed, in the game state recovery process, the CPU 56 determines from the count value stored in the backup RAM. The stepping of the counter for generating the initial value determining random number is resumed.

  In addition to a counter for generating a random number for determination and a counter for generating a random number for determining an initial value, an infinite counter by software (for example, constantly updated by timer interrupt processing) is provided to perform initialization processing. The count value of the infinite counter may be set to a counter for generating random 1 as an initial value. Even in such a case, it becomes difficult to predict the timing when the count value of the random 1 generation counter matches the jackpot determination value. The infinite counter is composed of, for example, 2 bytes. In the initialization process, for example, the lower 8 bits of the infinite counter are set in the random 1 generation counter.

  As described above, when the initial value of the big hit determination random number is set to an indefinite value, or when the big hit determination random number is updated in the first round, the big hit lottery is not performed. In addition to an illegal act that causes a stack overflow or an illegal act that forcibly inputs a reset signal, for example, an illegal act that clears the RAM by turning off the control power (5V) or backup power supplied to the gaming machine is performed. Even in such a case, it is possible to prevent a big hit from occurring due to such an illegal act.

Embodiment 2. FIG.
In the first embodiment, the counter 931 and the like are backed up by the backup power source 933, and when the power supply to the gaming machine is resumed by continuing counting even if the power supply to the gaming machine is stopped, the counter The count value of 931 was undefined. Then, when power supply to the gaming machine is resumed, the count value of the counter 931 is set in the random 1 generation counter, thereby setting the initial value of the random 1 generation counter (the initial value set in the initialization process). Value) was undefined. However, other embodiments may be used as long as the initial value of the random 1 generation counter is randomized using a hardware circuit.

  FIG. 58 is a block diagram showing a configuration example for randomizing the initial value of the random 1 generation counter according to another embodiment of the present invention. In this embodiment, on the main board 31, a RAM 934 is mounted outside the CPU 56 as second variation data storage means that can hold the stored contents for a predetermined period even when power supply to the main board 31 is stopped. The RAM 934 is backed up by a backup power source 933. Therefore, the contents of the RAM 934 are saved even when the power supply to the gaming machine is stopped. Note that the RAM built in the CPU 56 and backed up by a backup power source (in this example, the capacitor 923) mounted on the power supply board 910 can retain the stored contents even if the power supply to the gaming machine is stopped. It corresponds to one variation data storage means.

  FIG. 59 is a flowchart showing main processing executed by the CPU 56 in this embodiment. As shown in FIG. 59, in the initialization process (steps S181 to S193 and S190), the CPU 56 performs a RAM clear process (step S181). Also, a work area setting process for setting an initial value in a predetermined work area is performed (step S182).

  Next, the CPU 56 outputs an initialization signal to an external device such as a hall computer via the information output circuit 64, for example (step S183). Further, a process of transmitting a payout permission state designation command instructing that payout from the ball payout device 97 is possible to the payout control board 37 is performed (step S184).

  Further, a process of transmitting an initialization command for initializing each sub board to each sub board is executed (step S185). As an initialization command, a command indicating the initial symbol displayed on the variable display device 9 (for the symbol control board 80) and a command for instructing the extinction of the prize ball lamp 51 and the ball-out lamp 52 (to the lamp control board 35) Etc). Further, the CPU 56 performs a process of transmitting an initialization notification command designating notification of execution of the initialization process to the symbol control board 80 (step S186). In this embodiment, a big hit start display command (see FIG. 39) is used as the initialization notification command. When the notification control for executing the initialization process is executed by the lamp control unit or the sound control unit, an initialization notification command is transmitted to the lamp control board 35 and the sound control board 70 in step S186. In this case, for example, a big hit start lamp designation command (see FIG. 40) is used as the initialization notification command transmitted to the lamp control board 35. As the initialization notification command to be transmitted to the sound control board 70, for example, a big hit start sound designation command (see FIG. 41) is used.

  Further, the CPU 56 inputs the determination random number initial value and the initial random number initial value from the RAM 934 (steps S191 and S192). Then, the input initial random number for determination is set in a random 1 generation counter for generating a big hit determination random number, and the input initial random number initial value is stored in a random 1 initial value buffer (shown in FIG. 27). In step S104, the value is compared with the count value of the random 1 generation counter) (step S193).

  Further, the CPU 56 sets a CTC register provided in the CPU 56 so that a timer interrupt is periodically generated every 2 ms (step S190). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

  The configuration and processing other than the configuration shown in FIG. 58 and the initialization processing in the main processing shown in FIG. 59 are the same as those in the first embodiment.

  The CPU 56 writes the count value of the random 1 generation counter at that time as a determination random number initial value into the RAM 934, for example periodically (every second), and the random 6 generation counter count value is the initial value random number. Write as initial value. Even if it is not periodic, it may be written in the RAM 934 when an event occurs. For example, when the variable display on the variable display device 9 is started, when the variable display on the variable display device is finished, or when a game ball is won at a specific winning opening, etc. Write initial value and random number for initial value. In addition, the opportunity illustrated here is only an example, Comprising: It is good also considering generation | occurrence | production of the other event which may arise during game progress as an opportunity.

  Further, in this embodiment, when a certain event occurs, the determination random number initial value and the initial random number initial value are written in the RAM 934, and the initial determination random number stored in the RAM 934 in the initialization process. The initial random number for initial value is set in the random 1 generation counter and the random 6 generation counter. However, when an event occurs, only the initial random number for determination is written in the RAM 934 and the determination is made in the RAM 934. Only the random number initial value for use may be stored, and in the initialization process, the determination random number initial value stored in the RAM 934 may be set in the random 1 generation counter.

  Furthermore, in this embodiment, the RAM 934 that is backed up by the backup power source 933 is exemplified as the second variable data storage means that can retain the stored contents even if the power supply to the gaming machine is stopped. Other random accessible non-volatile memories such as EEPROM and flash ROM may be used as the storage means. When the RAM 934 that is backed up by the backup power source 933 is used, the backup power source 933 is preferably mounted on the main board 31 as in this embodiment. This is because the main board 31 on which the game control means is mounted cannot be easily removed on the back side of the gaming machine and is covered with a cover that can show the removal history, so that it is difficult to receive fraud.

  FIG. 60 is an explanatory diagram showing an example of the value of a counter (random 1 generation counter) for generating random 1 (big hit determination random number) that changes by the determination random number update processing shown in FIGS. 27 and 28. It is. When power supply to the gaming machine is started and initialization processing is executed, the initial value of the random 1 generation counter is a value read from the RAM 934 (an indefinite value). Further, when it is detected in the process of step S104 that the count value of the random 1 generation counter matches the stored value of the random 1 initial value buffer, the process of step S105 performs random 6 (for determining the random 1 initial value). Random number) is extracted, and the count value of the random 1 generation counter is updated. This time point is indicated by A in FIG. Subsequent operations are the same as those in the first embodiment (see FIG. 31).

  As described above, in this embodiment, the gaming machine is equipped with a game control means for performing control related to the game and a fluctuation data storage means for storing data that fluctuates according to the progress of the game. Main board 31, power supply monitoring means (power supply monitoring IC 902 in this embodiment) for monitoring the output voltage of the power supply of a predetermined potential and outputting a detection signal when a detection condition is satisfied, and a predetermined game for the player Fluctuation data storage means, comprising: a determination numerical value update means (in this embodiment, a random 1 generation counter) that updates a determination numerical value used for determining whether or not to add value within a predetermined numerical value range Is provided separately from a backup RAM (RAM built in the CPU 56) that can retain the stored contents for a predetermined period even when power supply to the gaming machine is stopped, and the backup RAM. A RAM 934 capable of retaining the stored contents for a predetermined period even when the power supply to the gaming machine is stopped, and the game control means controls the control state in relation to the output of the detection signal from the power supply monitoring means. When the supply of power to the gaming machine is started, the contents of the backup RAM can be executed when the power supply to the gaming machine is started. Can be executed based on the stored contents of the RAM 934 when the initialization process is executed. The update of the judgment numerical value updating means is started.

  In addition, the game control means writes the random number initial value for determination to the RAM 934 that can retain the stored contents even when power supply to the game machine is stopped periodically or triggered by the occurrence of a predetermined event. Then, the determination random number initial value stored in the RAM 934 when the power supply to the gaming machine is stopped is an indefinite value. As a result, when the initialization process is executed when the power supply to the gaming machine is resumed, the determination random number initial value that is an indefinite value is set as the initial value in the determination numerical value updating means. The update value of the determination numerical value updating means (in this embodiment, the count value of the random generation counter) matches the predetermined value (in this embodiment, the jackpot determination value) that gives the player a predetermined game value. The timing to do so is indefinite, and fraudulent acts aimed at such timing can be prevented.

  In each of the above embodiments, the random 1 generation counter for generating a random number for determining whether or not to win is formed in the RAM. However, the random 1 generation counter is set using a register of the CPU 56. It may be formed. For example, the IX register may be used as a random 1 generation counter. In this case, the register used as the random 1 generation counter is not used for other purposes.

  Further, in each of the above embodiments, even if an illegal act of clearing the RAM is performed by turning off the control power (5V) or backup power supplied to the gaming machine, the initialization notification is performed. , Such fraud can be easily detected.

  In each of the above-described embodiments, the initialization notification is performed under the control of the display control CPU 101, the lamp control CPU 351, or the sound control CPU 701. However, the CPU 56 controls the display and the like to perform the initialization notification. It is good also as composition which performs.

  In each of the above embodiments, when the data to be stacked exceeds the storage capacity of the stack area provided in the RAM 55, the data is stacked up to the data area of the work area (RAM area other than the stack area). It is conceivable that the program overflows from the stack area (overflows) and the program runs out of control. For example, as a result of rewriting the data storage destination address specified by a certain instruction (opcode) on the program with data overflowing from the stack area, the program jumps to an incorrect address and then runs away. In such a case, the program is started from the top address even if the power supply is not stopped or restarted due to a timeout of the watchdog timer or the like. In this case, since the backup flag and checksum data that should be executed in the NMI processing (power supply stop processing) are not set, the initialization processing is executed by the processing in steps S8 and S9. .

  Monitoring by a watchdog timer as an initialization means for initializing the operation state of the game control means when the operation state of the game control means has been stopped for a predetermined period of time uses a watchdog function built in the CPU 56. Alternatively, the system reset circuit 65 may be used. FIG. 61 is a block diagram showing the CPU 56 mounted on the main board 31 and the main components connected to it when monitoring by the watchdog timer using the system reset circuit 65. A reset signal from the system reset circuit 65 having the reset IC 652 is input to the reset terminal of the CPU 56. When the power supply is started, the reset IC 652 sets the level of the reset signal to a low level (reset level) for a predetermined period (a time determined by an external capacitor and a built-in resistor), and resets when the period elapses. Set the signal level to high. The CPU 56 becomes operable when the reset signal becomes high level. In the example shown in FIG. 61, a signal is supplied to the CK terminal of the reset IC 652 from the output port of the CPU 56 at a certain time interval. When the signal is interrupted and no signal is input for a predetermined period (watchdog timer time-out period), the reset IC 652 once sets the reset signal level to the reset level (low level) and then the non-reset level (high level). Level). Therefore, the CPU 56 enters a state for executing the initialization process based on such a reset signal. Note that the watchdog timer circuit does not use the system reset circuit 65 but may be provided independently or may be provided outside the substrate.

  In the example shown in FIG. 61, when the signal output from the game control means is not input for a predetermined period, the monitoring circuit that outputs a signal (a signal that once becomes a reset level and then becomes a non-reset level) to the game control means This is realized by a system reset circuit 65.

  In each of the above embodiments, the game control means (CPU 56) outputs a command indicating that the power supply stop process is in progress, and the display control means (display control CPU 101) performs the power supply stop process. The notification control indicating the execution is performed, but the notification control indicating the execution of the power supply stop process may be performed in the other sub-boards 35 and 70. Note that in the case where notification indicating the execution of the power supply stop process is performed, it is desirable to continue the notification until the power supply to the gaming machine is stopped. If an illegal act of causing a stack overflow or illegally inputting a reset signal to the CPU 56 is performed, power is continuously supplied even when the main board 31 is initialized. In the sub-boards 35, 70, and 80, notification indicating the execution of the power supply stop process can be continuously performed. Therefore, it becomes possible to easily find fraud.

  In the above embodiment, the power-off signal (NMI signal) is input to the non-maskable interrupt terminal, but may be input to the maskable interrupt terminal or input to the input port. Also good. When input to the input port, the game control means executes processing corresponding to the non-maskable interrupt processing described above if the power-off signal is on as a result of the port check.

  In the above-described embodiment, the power supply monitoring unit is mounted on the power supply board 910. However, the power supply monitoring means may be set on a board other than the main board 31 or in another place in the gaming machine. In addition, the system reset unit is mounted on the main board 31, but may be mounted on another board such as the power board 910.

  In the above embodiment, the display control CPU 101, the lamp control CPU 351, or the sound control CPU 701 discards the received command during the initialization notification execution period, and does not execute the control based on the command. However, the command received during the initialization notification execution period may be stored and held, and control based on the command stored and held after the completion of the initialization notification may be executed.

  In the above-described embodiment, the backup power supply for supplying power to the backup RAM is created on the power supply board 910. However, the backup power supply may be created on the main board 31. Further, a backup power source may be provided on another board provided in the gaming machine. For example, when another electrical component control board 35, 70, 80 is configured to be able to back up power, the electrical power supply control board 35, 70, 80 may be configured to create a backup power source. Further, it may be provided outside the substrate instead of on any substrate.

  In each of the above embodiments, the “specific game state” means a state that is advantageous for a player who is given a predetermined game value. Specifically, the “specific game state” is, for example, a right for a variable winning ball apparatus to be in a state advantageous to a player who easily hits a ball (a big hit gaming state) or a state advantageous to a player. A state in which a predetermined game value has been given, such as a state in which a condition has occurred, a condition in which a prize game medium payout condition is easily established, or a condition in which a score is awarded to a player is easily established. .

  In each of the above embodiments, a predetermined game value can be given to a player according to the establishment of a predetermined condition. Specifically, a specific game advantageous to the player when a specific condition is satisfied. Electric parts control that is controllable to a state and in which the game control means sends a command (for example, a big hit start display command) sent in association with the occurrence of a specific gaming state in the notification process as a command indicating notification Although the gaming machine is configured to be sent to the means, the “specific condition” as the predetermined condition means a condition for setting the control state of the gaming machine to the specific gaming state. Therefore, when a specific condition is satisfied, the control state of the gaming machine becomes the specific game state. Specifically, the “specific condition” is, for example, “variable display (for example, scroll display, frame advance display, switching display, etc.) of multiple types of identification information (for example, symbols, pictures, numerical values, etc.) is possible. The display device includes a variable display device (for example, a liquid crystal display device, a dot matrix display device, a segment display device, a drum display device, etc.), and the display result of identification information in the variable display device is a specific display result (for example, all Is a display result in which the identification information is the same. Specifically, for example, a display result in which the identification information on the left middle right is all “1”.) Further, for example, the “specific condition” may be a condition that is satisfied when a game ball is detected by a ball detection means (for example, a photo sensor, a proximity switch, etc.) provided in a specific area in the game area. . For example, a predetermined game value may be given to a player in accordance with the winning (passing or detection) of a game ball in a specific winning area such as a specific winning opening. The game value given to the player in response to the establishment of a specific condition is the right to cause a more advantageous state for the player based on the winning of the game ball at the start opening provided in the gaming machine. It may be a state of occurrence.

  In addition, a specific condition (for example, a big hit determination value) may be extracted as a specific random number (for example, a big hit determination random number) as a specific condition that is a condition for giving a predetermined game value to a player. .

  Note that the pachinko gaming machine 1 of each of the above embodiments mainly has a predetermined game value when the stop symbol of the special symbol variably displayed on the variable display device 9 based on the start winning is a combination of the predetermined symbols. The first type pachinko gaming machine that can be given to a player, but if there is a winning in a predetermined area of an electric accessory that is released based on a start winning, a second gaming value can be given to the player When a winning is given to a predetermined electric game that is released when a stop symbol of a symbol variably displayed based on a seed pachinko gaming machine or a start winning combination becomes a predetermined symbol combination, a predetermined right is generated or continued. The present invention can be applied even to a seed pachinko gaming machine. Further, the present invention can be applied not only to a pachinko gaming machine but also to a slot machine or the like that is advantageous to the player based on random numbers.

  In the above embodiment, the following gaming machines are also disclosed.

(1) When the control means executes the recovery process, the update value of the first numerical value update means stored in the fluctuation data storage means (for example, a random 1 generation counter stored in the power-backed RAM 55) Game machines that are configured to start updating from the count value.
According to such a configuration, updating of the numerical value is started from the update value of the first numerical value updating means stored in the fluctuation data storage means, and it is possible to make it difficult to illegally generate a big hit.

(2) A gaming machine provided with numerical value holding means (for example, by a backup power source 933) for holding the numerical value of the second numerical value updating means even when power supply to the gaming machine is stopped.
According to such a configuration, the numerical value at the start of power supply to the gaming machine is not constant, and the initial value of the first numerical value updating means can be made random by executing the initialization process.

(3) A numerical value output means (for example, a latch circuit 932) is provided for outputting the numerical value of the second numerical value updating means to the control means in response to a request signal from the control means (for example, a latch signal output from the output port 576). Gaming machine.
According to such a configuration, a numerical value can be reliably input when the control means needs the numerical value of the second numerical value updating means.

(4) A gaming machine in which system reset means (eg, system reset circuit 65) for generating a signal (eg, system reset signal) for initializing the operation of the control means is mounted on the control board.
According to such a configuration, it is possible to prevent an illegal act on the signal for initializing the operation of the control means.

(5) A gaming machine in which the oscillation frequency of the first oscillation means and the oscillation frequency of the second oscillation means are different.
According to such a configuration, the update start value of the first numerical value update means set in the initialization process can be made more random.

(6) The update upper limit value of the first numerical value updating means (for example, the maximum value of the count value of the random 1 generation counter) and the update upper limit value of the second numerical value update means (for example, the maximum value of the count value of the counter 931) are the same. Is a gaming machine.
According to such a configuration, the numerical value of the second numerical value updating means can be set as the update start value of the first numerical value updating means as it is.

(7) Initial value numerical value updating means for updating a numerical value for determining an initial value of the first numerical value updating means within a predetermined numerical value range in processing executed by the control means (for example, game control processing: steps S21 to S33). (For example, a random 6 generation counter), and the control means executes initialization processing (for example, S181 to S190), and determines a numerical value for starting the update of the first numerical value updating means based on the numerical value of the second numerical value updating means. Then, after starting the updating of the numerical value of the first numerical value updating means, the gaming machine is configured to update the initial value using the numerical value of the initial value numerical value updating means (for example, step S107).
According to such a configuration, it is possible to reduce the burden of processing for making the initial value of the first numerical value updating means after execution of initialization processing random.

(8) A gaming machine in which a player plays a predetermined game and can give a predetermined game value to the player in accordance with the establishment of a specific condition, and includes control means (for example, including a CPU 56) that controls the game. A control board (for example, main board 31) on which a game control means) and a fluctuation data storage means for storing data that fluctuates according to the progress of the game, and an output voltage of a power source of a predetermined potential are monitored and detected conditions When the above is established, the power supply monitoring means (for example, the power supply monitoring IC 902) that outputs a detection signal (for example, power-off signal) and the process executed by the control means (for example, game control processing: steps S21 to S33) And a determination numerical value updating means (for example, a random 1 generation counter) that updates a determination numerical value used for determining whether or not to give the game value within a predetermined numerical range. A first fluctuation data storage means (for example, a RAM 55 backed up by a power source) capable of retaining the stored contents for a predetermined period even when power supply to the gaming machine is stopped; A second variation data storage means (for example, a power-backed-up RAM 934 or EEPROM) that is provided separately from the means and can retain the stored contents for a predetermined period even when the power supply to the control board is stopped. In connection with the output of the detection signal from the power supply monitoring means, the control means saves data necessary for restoration of the control state in the first fluctuation data storage means (for example, steps S451 to S499 and step S171). , S172) can be executed, and when power supply to the gaming machine is started, a predetermined condition (for example, determined in steps S7 to S9) is determined. Initialization process (for example, steps S183 to S193) for initializing the contents of the first fluctuation data storage means based on the establishment of the condition) and a recovery process for restoring the control state based on the storage contents of the first fluctuation data storage means (For example, steps S80 to S95) can be executed, and when the initialization process is executed, the determination numerical value updating means is updated based on the stored contents of the second variation data storage means. A gaming machine characterized by starting (for example, step S193).
According to such a configuration, the update start value of the determination numerical value updating means after execution of the initialization process becomes random, and the stored contents of the first variation data storage means are initialized, thereby causing an illegal big hit. Can make it difficult.

(9) A gaming machine provided with initialization means (for example, a watchdog timer circuit) for initializing the operation state of the control means when the operation state of the control means has been stopped for a predetermined period.
According to such a configuration, it is possible to prevent the control from continuing in an abnormal state.

1 Pachinko machine 31 Main board (game control board)
35 Lamp control board 55 RAM (first variation data storage means)
56 CPU
70 Sound Control Board 80 Symbol Control Board 92 First Oscillation Circuit 902 Power Supply Monitoring IC (Power Supply Monitoring Means)
910 Power supply board 916 Capacitor (backup power supply)
930 Second oscillation circuit 931 Counter 932 Latch circuit 933 Backup power supply 934 RAM (second data storage means)
950 judgment circuit

Claims (1)

A gaming machine in which a player plays a predetermined game and can give a predetermined game value to the player when a specific condition is established,
Game control means for controlling the progress of the game ;
Effect control means for controlling the effect device based on a command output from the game control means;
Fluctuating data storage means for storing data that fluctuates according to the progress of the game;
Storage holding means capable of holding the storage contents of the variation data storage means for a predetermined period even when power supply to the gaming machine is stopped;
A power supply monitoring means for outputting a detection signal when the Tokoro constant potential monitoring detects conditions the output voltage of the power supply is established,
An operation means for outputting an operation signal according to the operation ,
The game control means includes
Wherein when the detection signal from the power supply monitoring means it is output, a data necessary for restoration of the control state capable of executing power supply stop process to make holding the variation data storage means,
When power supply to the gaming machine is started, when the operation signal from the operation means is input, the storage contents of the variation data storage means are initialized, and the operation signal from the operation means is input. An initialization process for initializing the storage contents of the fluctuation data storage means based on the establishment of a predetermined condition, and a recovery process for restoring the control state based on the storage contents of the fluctuation data storage means You can do either one,
In the case of execution of the initialization process, an initialization notification command indicating the execution of the initialization process is output to the effect control means,
The production control means includes
Based on the input of the initialization notification command, the presentation device performs initialization notification indicating execution of the initialization process,
When a command indicating execution of predetermined control is received from the game control means while the initialization notification is being executed, the command is invalidated .

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