JP2003033544A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reliably store necessary data in a storage means and control the input of signals such as an unlawful interrupt signal even if an unlawful act such as the unlawful transmission of the interrupt signal is committed. SOLUTION: In the case that an NMI signal is unlawfully inputted, a reset signal to be provided for a CPU56 does not reach a reset level. But a control circuit by a flip flop for receiving the input of the NMI signal to generate an interrupt signal does not transmit an unlawful signal except an initially inputted NMI signal to output. As a result, only one fall is inputted to an XNMI terminal of the CPU56, and a plurality of interrupts are not applied. Even if a plurality of NMI signals occur due to the instability, etc., of a source voltage at a normal service interruption of power supply by the control circuit, only one non-maskable interrupt is applied in the CPU56. Therefore, processing at the service interruption of power supply is reliably executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine in which a player plays a predetermined game and gives a predetermined gaming value to the player when a predetermined condition is satisfied.

[0002]

2. Description of the Related Art As a game machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium is won in a prize area such as a winning opening provided in the game area, a predetermined number of prize balls are provided. There are things that are paid out to the player.
Further, a variable display device whose display state can be changed is provided, and is configured to give a predetermined game value to the player when the display result of the variable display device becomes a predetermined specific display mode. There is.

It is usually called "big hit" that the display result of the variable display device for displaying the special symbol is a combination of predetermined specific display modes. Note that the game value is the right for the state of the variable winning ball device provided in the game area of the gaming machine to be in an advantageous state for a player who easily wins a hit ball, or to be in an advantageous state for a player. Is to be generated.

When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and a big hit game state in which a hit ball is easy to win is entered. Then, in each opening period, when a predetermined number (for example, 10) of winning holes are won, the winning holes are closed. The number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and the special winning opening is closed when the opening time elapses even if the number of winnings does not reach a predetermined number. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied when the special winning opening is closed, the jackpot gaming state ends.

When the game balls are won in the winning openings provided on the game board, a predetermined number of prize balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of prize balls based on the winning is determined by the game control means,
It is transmitted to the payout control means for controlling the payout mechanism for paying out game balls as a prize. In the following, the game control means and the other control means may be referred to as electric component control means. In addition, the electric component is a component (mechanical component, circuit, etc.) provided in the gaming machine and electrically operates.

[0006]

Various kinds of electric component control means such as game control means are mounted on a game machine, and generally, each electric component control means is composed of a microcomputer. That is, the program is stored in the ROM or the like, and the data temporarily generated in the control or the data that changes with the progress of the control are stored in the RAM. Then, when a power failure occurs in the gaming machine due to a power failure, R
The data in AM will be lost. Therefore, at the time of recovery from a power outage, there is no choice but to return to the initial state (for example, the state when the game machine was first turned on at the game store on that day), which may be disadvantageous to the player. There is. For example, if the power is cut off during the big hit game and the gaming machine returns to the initial state, the player cannot receive the profit based on the big hit occurrence.

In order to avoid such a situation, when an unexpected stop of the power supply such as a power failure occurs, the game control means saves necessary data in the backup RAM backed up by the power source and restores the power source. It is only necessary to restore the data saved when the game is played, restore the game state, and restart the game. Generally, when a backup RAM is provided, a detection circuit for detecting that power supply is stopped is provided, and a signal from the detection circuit (hereinafter referred to as a power-off signal) is used as an interrupt signal to generate a micro signal. Input to the interrupt terminal of the computer, the microcomputer executes a process of detecting the stop of the power supply by the interrupt and saving necessary data in the backup RAM. Since the necessary data stored in the backup RAM includes information for restoring the game state, it is general that the value of the program counter, the value of the register, etc. are stored in the stack area. The processing for storing the necessary data in the backup RAM is executed while the power supply voltage is at a voltage at which the microcomputer can operate when the power supply voltage drops due to the stop of power supply.
After the execution of the processing for storing the data necessary for the power supply is completed, the power supply voltage becomes 0 after the voltage has dropped to a voltage at which the microcomputer cannot operate.

In the gaming machine configured as described above,
When the power supply is stopped, the value of the power supply voltage becomes unstable, so that the power-off signal may continuously occur.
When the power-off signal is continuously generated, the microcomputer is continuously interrupted, so that the process of saving necessary data in the backup RAM cannot be performed reliably. Therefore, a means (specifically, a circuit or the like) for preventing the power-off signal from being continuously generated.
May be provided on the side of the detection circuit.

However, when the power-off signal is continuously input to the signal line from the detection circuit side to the interrupt terminal of the microcomputer even though the power supply is not stopped, the following occurs. There may be some inconvenience. That is, although the size of the stack area is limited, the repeated interruption processing causes the data to be stored in the stack area repeatedly, and eventually a stack overflow occurs. as a result,
A RAM error occurs and the contents of the RAM area are initialized.
Alternatively, if a microcomputer that uses a watchdog timer is used, the contents of the RAM area may be destroyed due to stack overflow, causing a program runaway and resetting to the microcomputer. It takes time to initialize the contents of the RAM area. Also, at the end of the interrupt processing based on the power-off signal, loop processing is performed to wait for the power supply voltage to drop to a voltage at which the microcomputer cannot operate, or to wait for the reset signal input based on the power supply voltage drop. If the power supply voltage is not lowered and the reset signal is not generated, the loop processing continues, and as a result, the watchdog timer times up, the microcomputer is reset, and R
The contents of the AM area are initialized.

Whether or not the above-described big hit is generated is generally determined by a count value of a random number generation counter formed in the RAM area at a predetermined timing (for example, when a start winning is generated, that is, when a start winning signal is input). It is determined by whether or not it matches a predetermined jackpot determination value. As described above, when the power-off signal is continuously input, the contents of the RAM are initialized, so the count value of the random number generation counter for determining whether or not to generate a big hit is also initialized. (Returned to 0.). Then,
Since the step count starts from 0, the timing at which the count value matches the predetermined jackpot determination value can be easily grasped.

That is, a fraudulent means such as a fraudulent board is mounted on a game machine, a power-off signal (interrupt signal) is continuously input to the microcomputer from the fraudulent means, and the count value of the random number generation counter It is possible to illegally generate a big hit by illegally sending a start winning signal to the game control board on which the microcomputer is mounted at a timing that coincides with the big hit judgment value.

Therefore, the present invention is necessary in the case where the necessary data is stored in the storage means whose power is backed up by the interruption process when an unexpected stop of the power supply such as a power failure occurs. In addition to being able to reliably execute processing to save various data in the storage means, even if fraudulent acts such as illegally sending an interrupt signal are performed, restrict the input of such signals to prevent the fraudulent acts from being effective. It is an object of the present invention to provide a gaming machine that can

[0013]

A gaming machine according to the present invention comprises:
A game machine that allows a player to play a predetermined game and give a predetermined game value to the player in accordance with the establishment of a predetermined condition, and a control board (for example, a main board) equipped with a control unit that controls the game. Substrate 31), a variable data storage means (for example, backup RAM) capable of retaining stored contents for a predetermined period even when power supply to the game machine is stopped, and a power supply of a predetermined potential provided outside the control substrate. A power supply monitoring means (for example, a power supply monitoring IC 902) that monitors the output voltage and outputs a detection signal when the detection condition is satisfied, and a detection signal from the power supply monitoring means that is mounted on the control board and is input and controlled based on the detection signal. An interrupt signal output circuit (for example, a flip-flop 950b) for outputting a predetermined interrupt signal to the means, and the control means is based on the state change of the interrupt signal from the interrupt signal output circuit. It is possible to execute power supply stop processing (for example, steps S451 to S499) in which the data necessary for restoration of the control state is saved in the variable data storage means, and the interrupt signal output circuit performs the interrupt based on the input detection signal. It is characterized in that the output state of the interrupt signal is maintained even after the detection signal is input for at least a predetermined period (for example, until a reset signal for system reset is input) after the output of the interrupt signal. .

A payout means (for example, a ball payout device 97) for paying out a game medium used for a game, and a payout detection means (for example, a prize ball count switch 301A) for detecting the game medium paid out from the payout means. The control means can execute an input monitoring process (for example, steps S460 to S480) for monitoring the input of the detection signal from the payout detecting device in the power supply stop process, and the input monitoring process is performed during a predetermined period. The input monitoring time being executed (the execution time of steps S460 to S480) may be included.

The input monitoring time is preferably set to a time longer than the time from when the game medium is paid out from the payout means to when it is detected by the payout detection means.

When the control means executes the access prohibition processing (for example, step S492) for prohibiting access to the fluctuation data storage means in the power supply stoppage processing, the access is started from the start of the power supply stoppage processing for a predetermined period. It is preferable to include a period until the prohibition process is executed.

A filter circuit (for example, a low-pass filter) for removing a change in the detection signal below the effective period between the input portion (for example, the connector 950C) of the detection signal from the power source monitoring means on the control board and the interrupt signal output circuit. A filter 950a) may be provided.

A power supply board (for example, a power supply board 910) for creating a power supply used in the gaming machine may be provided, and the power supply monitoring means may be mounted on the power supply board.

A system reset circuit (for example, reset IC 651) that outputs a reset signal for stopping the operation of the control means may be provided.

The interrupt signal output circuit may be configured to change the interrupt signal based on the reset signal from the system reset circuit.

The control means may be configured to use a non-maskable interrupt terminal (for example, the XNMI terminal of the CPU 56) as an input terminal for inputting an interrupt signal from the interrupt signal output circuit.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of a pachinko gaming machine as seen from the front, and FIG. 2 is a front view showing the front surface of the gaming board.

The pachinko gaming machine 1 is composed of an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame mounted inside the outer frame so as to be openable and closable. In addition, the pachinko gaming machine 1 has a frame-shaped glass door frame 2 that is provided in the game frame so as to be openable and closable. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanical parts and the like are attached, and various parts attached to them (excluding a game board described later). It is a structure including and.

As shown in FIG. 1, the pachinko gaming machine 1 is
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply plate (upper plate) 3. Below the hitting ball supply tray 3, there are provided a surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball feed tray 3 and a hitting ball operation handle (operation knob) 5 for firing the hit ball. Glass door frame 2
A game board 6 is detachably attached to the back surface of the. The game board 6 is a structure including a plate-shaped body that constitutes the game board 6 and various parts attached to the plate-shaped body. A game area 7 is formed on the front surface of the game board 6.

In the vicinity of the center of the game area 7, a variable display device (special variable display device) 9 including a plurality of variable display portions for variably displaying symbols as identification information is provided. The variable display device 9 includes, for example, “left”, “middle”,
There are three "right" variable display parts (symbol display areas).
A start winning opening 14 is provided below the variable display device 9. The winning ball that has entered the starting winning opening 14 is guided to the rear surface of the game board 6 and detected by the starting opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the starting winning opening 14. Variable winning ball device 1
The solenoid 5 is opened by the solenoid 16.

At the lower part of the variable winning ball device 15, an opening / closing plate 20 is provided which is opened by a solenoid 21 in a specific game state (big hit state). Opening plate 20
Is a means for opening and closing the special winning opening. One of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 (V winning area)
The entered winning balls are detected by the V winning switch 22, and the winning balls from the opening / closing plate 20 are detected by the count switch 23. On the back surface of the game board 6, a solenoid 21A for switching the route inside the special winning opening is also provided. Further, on the upper part of the variable display device 9, a special symbol starting memory indicator (hereinafter, referred to as starting memory indicator) 18 by four LEDs for displaying the number of effective winning balls that have entered the starting winning port 14, that is, the number of starting memories. Is provided. Each time there is an effective start prize, the start memory indicator 18 increases the number of LEDs to be turned on by one.
Then, each time the variable display of the variable display device 9 is started,
Decrease the number of lit LEDs by 1.

When a game ball wins the gate 32 and is detected by the gate switch 32a, a predetermined random number value is extracted unless the normal symbol starting memory has reached the upper limit. And
Normally, if the variable display in which the display state changes in the symbol display 10 can be started, the variable display of the display of the normal symbol display 10 is started. Normally, if the variable display whose display state changes in the symbol display 10 cannot be started, the value of the normal symbol starting memory is incremented by 1. In the vicinity of the normal symbol display device 10, there is provided a normal symbol starting memory display device 41 having a display unit of four LEDs for displaying the normal symbol starting memory number. Each time there is a prize in the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Then, each time the variable display of the normal symbol display device 10 is started, the number of LEDs to be turned on is reduced by 1.

In this embodiment, the variable display is performed by alternately illuminating the left and right lamps (the pattern becomes visible when illuminated), and the variable display is performed for a predetermined time (for example, 2
9 seconds) Continue. Then, if the left lamp is lit at the end of the variable display, it is a win. Whether or not to win is determined by whether or not the value of the random number extracted when the game ball wins the gate 32 matches a predetermined hit determination value. When the display result of the variable display on the normal symbol display device 10 is a hit, the variable winning ball device 15 is opened for a predetermined number of times and for a predetermined time, and the game ball is in a state where it is easy to win. In other words, the state of the variable winning ball device 15 changes from a disadvantageous state to an advantageous state for the player when the stop symbol of the normal symbol is a winning symbol.

Furthermore, in the probability changing state, the normal symbol display 1
The probability that the stop symbol at 0 becomes a winning symbol is increased, and one or both of the opening time and the number of times of opening the variable winning ball device 15 are increased, which is more advantageous for the player. In addition, in a certain state such as the probability change state,
Variable display period (variation time) on the normal symbol display 10
May be further shortened to give a further advantage to the player.

The game board 6 has a plurality of winning openings 29, 30,
33, 39 are provided, and the winning openings 29, 30, 3 for gaming balls
The prizes for 3 are prize winning opening switches 29a, 30 respectively.
a, 33a, 39a. Around the left and right of the game area 7, decoration lamps 25 that are displayed blinking during the game
Is provided, and at the lower part, there is an outlet 26 for absorbing hit balls that have not been won. In addition, two speakers 27 that emit a sound effect are provided on the upper left and right sides outside the game area 7. A top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided on the outer periphery of the game area 7. Further, a decorative LED is installed around each structure (a special winning opening, etc.) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of the decorative light-emitting body provided in the game machine.

In this example, the prize ball lamp 51 that lights up when there is a remaining number of prize balls near the left frame lamp 28b.
Is provided, and a ball-out lamp 52 that is turned on when the supply ball runs out is provided near the top frame lamp 28a.
Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming machine 1 and enables a ball lending by inserting a prepaid card. Not only the magnetic card as a prepaid card, but I
Other recording media such as a C card can also be used. The shape of the recording medium is not limited to the thin card shape of a business card, and various shapes such as an IC coin can be used.

In the card unit 50, a usable indicator lamp 151 indicating whether or not the card unit 50 is usable, and a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. A fraction display switch 1 for displaying on a frequency display LED provided in the vicinity of the hit ball supply tray 3
52, the connection stand direction indicator 15 showing which side the pachinko gaming machine 1 the card unit 50 corresponds to
3, a card insertion display lamp 154 indicating that a card has been inserted into the card unit 50, a card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back surface of the card insertion slot 155. A card unit lock 156 is provided for releasing the card unit 50 when checking the mechanism of the writer.

The game ball shot from the hitting ball launching device enters the game area 7 through the hit ball rail, and then descends from the game area 7. When the ball hits the starting winning opening 14 and is detected by the starting opening switch 14a, if the variable display of the symbol can be started, the variable display device 9 starts the variable display (variation) of the special symbol. If it is not in a state where variable display of symbols can be started, the number of starting memories is increased by 1.

The variable display of the special symbol on the variable display device 9 is stopped when a certain time has elapsed. When the combination of special symbols at the time of stop is a big hit symbol (specific display mode), the big hit game state is entered. That is, the opening / closing plate 2
0 is released until a fixed time elapses or a predetermined number (for example, 10) of hit balls are won. Then, when the hit ball enters the V winning area while the opening / closing plate 20 is open and is detected by the V winning switch 22, the continuation right is generated and the opening / closing plate 20
Is released again. The continuation right can be generated a predetermined number of times (for example, 15 rounds).

A combination of special symbols in the variable display device 9 at the time of stop is a big hit symbol with probability variation (probability variation symbol)
In the case of the combination of, the probability of the next big hit is high. That is, the state of probability change is more advantageous for the player.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a rear view of the gaming machine viewed from the back side. FIG. 4 is a rear view of the mechanism plate to which various members are attached as seen from the rear side of the gaming machine.

As shown in FIG. 3, on the back side of the gaming machine, a variable display control unit 49 including a symbol control board 80 for controlling the variable display device 9, a gaming control board (mainly a gaming control microcomputer, etc.) is mounted. Substrate) 31 is installed. Further, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. Furthermore, various decorations L provided on the game board 6
ED, special symbol starting memory display (starting memory display) 18
And a normal pattern starting memory display 41, a decorative lamp 25,
Top frame lamp 28a and left frame lamp 2 provided on the frame side
8b, a right frame lamp 28c, a prize ball lamp 51, and a lamp control board for mounting a lamp control means for controlling lighting of the out-of-ball lamp 52, and sound control for mounting sound control means for controlling sound generation from the speaker 27. A substrate 70 is also provided. Further, a power supply board 910 as a power supply board on which a power supply circuit for producing DC30V, DC21V, DC12V and DC5V is mounted and a firing control board 91 are provided.

On the back side of the game machine, a terminal board 160 having terminals for outputting various information to the outside of the game machine is installed above. Terminal board 160
At least, the terminal for ball breakage for introducing the output of the ball breakage detection switch and outputting it externally, the terminal for prize balls for externally outputting the prize ball number signal and the external output for the ball lending number signal A ball lending terminal is provided. Further, in the vicinity of the center, an information terminal board 34 provided with each terminal for outputting various information from the main board 31 to the outside of the gaming machine is installed.

Further, a fluctuation data storage means (for example, a backup R capable of holding the contents even when the power supply is stopped) included in each board (main board 31, payout control board 37, etc.)
There is provided a switch board 190 having a clear switch 921 as an initialization operation means for clearing the backup data stored in (AM). The switch board 190 includes a clear switch 921 and a main board 3
A connector 922 that is connected to another substrate such as 1 is provided.

The game balls stored in the storage tank 38 pass through the guide rail 39, and as shown in FIG. 4, the curve gutter 1
After 86, the ball payout device covered with the prize ball case 40A is reached. At the upper part of the ball payout device, a ball break switch 187 is provided as a game medium cut detection means. When the out-of-ball switch 187 detects out-of-ball, the payout operation of the ball payout device is stopped. The out-of-ball switch 187 is a switch that detects the presence or absence of a game ball in the game ball passage, but the out-of-ball detection switch 167 that detects a shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rail 39 (the storage tank 38). (Provided near). When the out-of-ball detection switch 167 detects a shortage of game balls, the supply mechanism provided on the game machine installation island supplies game balls to the game machine.

The ball break switch 187 is locked at a position where it is possible to detect the presence of about 27 to 28 game balls in the payout ball passage leading to the ball payout device. That is, the out-of-ball switch 187 has a maximum payout amount of one unit of prize balls (15 in this embodiment) and a maximum payout amount of one unit of ball lending (100 yen: 25 in this embodiment).
It is installed at a position where it can be confirmed that the above items are secured.

The game balls paid out from the ball payout device are guided to the hitting ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. A surplus ball passage 46 communicating with the surplus ball tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45.

A large number of game balls as prizes based on winnings and game balls based on ball lending requests are paid out, and the hitting ball supply plate 3 becomes full. Eventually, after the game balls reach the contact port 45, further game balls are provided. When paid out, the game ball is guided to the surplus ball receiving tray 4 through the surplus ball passage 46. Further, when the game ball is paid out, the sensing lever 47 presses the full tank switch 48 as the storage state detection means, and the full tank switch 48 as the storage state detection means is turned on. In that state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the launching device is also stopped.

As shown in FIG. 4, a ball removing passage 191 extending from the curve gutter 186 to the discharge port 192 at the lower portion of the game machine is formed on the side of the ball payout device. Ball passage 19
1 is provided with a ball removing lever 193, and when the ball removing lever 193 is operated by a game store clerk or the like, a game ball passage from the guide rail 39 to the ball removing passage 191 is formed and stored in the storage tank 38. The played game ball is discharged from the discharge port 192 to the outside of the game machine.

FIG. 5 is an exploded perspective view showing a structural example of the ball payout device 97. In this example, a ball payout device 97 is formed inside the three cases 140, 141, 142 as the prize ball case 40A. Holes 170, 171 communicating with the ball passage at the bottom of the ball break switch 187 are provided in the upper part of the cases 140, 141, and the game ball has holes 170, 171.
It flows into the ball payout device 97 from 171.

The ball payout device 97 includes a payout motor (eg, stepping motor) 289 serving as a drive source. The rotational force of the dispensing motor 289 is transmitted to the gear 290 fitted to the rotation shaft of the dispensing motor 289, and further transmitted to the gear 291 that meshes with the gear 290. A sprocket 292 having a recess is fitted on the central axis of the gear 291. The game balls that have flowed in from the holes 170 and 171 are dropped one by one into the ball passage 293 below the sprocket 292 by the recess of the sprocket 292.

The ball passage 293 is provided with a distribution member 311 for switching the flow path of the game balls. The distribution member 311 is driven by the solenoid 310, and when paying out a prize ball, the game ball falls down along one of the flow paths in the ball passage 293, and when lending the ball, the game ball flows down through the other flow path in the ball passage 293. To fall down. The payout motor 289 and the solenoid 310 are controlled by the payout control CPU mounted on the payout control board 37. The payout control CPU is the main board 31.
The payout motor 289 and the solenoid 310 are controlled in accordance with a command from the game control CPU mounted on the.

A prize ball sensor (prize ball count switch) as payout detecting means for detecting game balls paid out by the ball payout device is provided below the downflow path selected at the time of paying out prize balls.
301A is provided, and a ball lending sensor (ball lending count switch) 301B that detects a game ball paid out by a ball payout device is provided below the flow-down path selected when the ball is lended. The detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301B are input to the payout control CPU of the payout control board 37. The payout control CPU counts the number of game balls actually paid out based on the detection signals.

A plurality of protrusions 295 forming the payout motor position sensor 296 are formed around the gear 291. The protrusion 295 transmits or shields the light from the light emitting body (not shown) with the rotation of the gear 291 or the rotation of the payout motor 289 with respect to the light receiving portion (not shown) of the payout motor position sensor. Or The payout control CPU can recognize the position of the payout motor 289 from the detection signal from the light receiving unit.

Further, in this embodiment, the ball payout device 97 as the payout means has a structure capable of executing both the ball lending and the prize ball payout, but the mechanism for lending the ball and the mechanism for paying out the prize ball are independent. However, the present invention can be applied. When the mechanism for lending the balls and the mechanism for paying out the prize balls are independent, the prize ball payout and the ball lending can be executed simultaneously, so that the relative payout speed of the game balls can be increased. In addition, the distribution member 311 for switching the flow path of the game ball
And the solenoid 310 is unnecessary. Furthermore, as the payout means, for example, a structure in which a prize ball is paid out when the motor rotates in the normal direction and a ball is loaned when the motor rotates in the reverse direction can be used.

FIG. 6 is a front view showing a portion of the switch board 190 installed on the game board 6. As shown in FIG. 6, the switch substrate 190 is provided with a connector 922 for connecting the output of the clear switch 921 to another substrate such as the main substrate 31 via a cable.

FIG. 7 is a configuration diagram showing an example of the configuration of the clear switch 921 mounted on the switch board 190. FIG. 7A shows a clear switch 921 having a push button structure. When the clear switch 921 is pressed, a low level (on state) clear switch signal (operation signal) is output, and is output to the main board 31, the payout control board 37, and the like via the connector 922. That is, the operation signal output from the clear switch 921 to the main board 31, the payout control board 37, etc. is turned on.
If the clear switch 921 is not pressed, a high level (off state) signal is output. In this embodiment, since the clear switch signal is output to at least the main board 31 and the payout control board 37, the connector 922 is a connector for outputting the clear switch signal to the main board 31, and the payout control board. A connector for outputting a clear switch signal to 37 may be separately provided.

FIG. 7B is a configuration diagram showing another configuration example of the clear switch 921. The clear switch 921 shown in FIG. 7B has a switching operation unit 921a for performing selective switching of "OFF", "ON", and "clear". When "OFF" is selected by the switching operation unit 921a, no signal is generated. "ON"
When is selected, a high level signal is output.
The clear switch 921 may also serve as a switch for switching on / off the power supply to the gaming machine 1. In that case, when "OFF" is selected, the gaming machine 1
The power supply to is stopped (the power of the gaming machine is off). If "ON" or "clear" is selected, the game machine 1 is in a state where power is supplied (the game machine is powered on). Also, when "clear" is selected, a low level clear switch signal is output.

In this embodiment, the switch board 190 on which the clear switch 921 is mounted is provided separately from other boards (game control board, etc.), but the clear switch 921 is mounted on the other board. You may. For example, it may be mounted on the power supply board 910. In the case where the clear switch 921 is mounted on the power board 910, even if the power board 910 is used as it is for the game board 6 after replacement when the game board 6 is replaced, the game board 6 after replacement is still used. In, the game state recovery processing and the like can be executed as it is. That is, the power supply board 910 can be reused.

Further, the clear switch 921 is used for the game board 6
May be installed on the side of, but may be installed on the game frame side.

FIG. 8 is a block diagram showing an example of the circuit configuration of the main board 31. Note that FIG. 8 also shows the payout control board 37, the lamp control board 35, the sound control board 70, the firing control board 91, and the symbol control board 80.
On the main board 31, the pachinko gaming machine 1 according to the program
Control circuit 53, a gate switch 32a, a starting opening switch 14a, a V winning switch 22, a count switch 23, winning opening switches 29a, 30a, 33a,
39a, full tank switch 48, out of ball switch 187,
Prize ball count switch 301A and clear switch 9
Switch circuit 5 for giving the signal from 21 to the basic circuit 53
8 and a solenoid 16 for opening and closing the variable winning ball device 15,
A solenoid 21 for opening / closing the opening / closing plate 20 and a solenoid circuit 59 for driving a solenoid 21A for switching the path in the special winning opening according to a command from the basic circuit 53 are mounted.

Although not shown in FIG. 8, the count switch short circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58. Further, the gate switch 32a, the starting port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 29a, 30a, 33a,
39a, full tank switch 48, out of ball switch 187,
Switches such as the prize ball count switch 301A may be called a sensor. That is, a game medium detecting means capable of detecting a game ball (a game ball detecting means in this example)
If so, the name does not matter. It is the same in other embodiments that what is called a switch may be what is called a sensor, that is, the switch is an example of the game medium detecting means.

Further, according to the data given from the basic circuit 53, the big hit information indicating the occurrence of the big hit, the effective starting information indicating the number of the starting winning balls used to start the variable display of the symbols on the variable display device 9, and the probability variation. An information output circuit 64 that outputs an information output signal such as probability variation information indicating that it has occurred to an external device such as a hall computer is mounted.

The basic circuit 53 is a ROM 54 for storing a game control program and the like, and an R as a storage means (means for storing variation data) used as a work memory.
AM55, CPU5 which controls according to the program
6 and I / O port section 57. In this embodiment, the ROM 54 and the RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. Note that the 1-chip microcomputer only needs to have at least the RAM 55 built therein, and
The OM 54 and the I / O port unit 57 may be external or built-in.

Further, at least a part of the RAM (which may be a RAM with built-in CPU) 55 is a backup RAM backed up by a backup power supply created in the power supply board 910. In other words, even if the power supply to the gaming machine is stopped, the RAM remains for a predetermined period.
At least some of the contents of 55 are saved. However, in this embodiment, the entire RAM is backed up by the backup power supply.

The hit ball launching device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 controls the ball to be fired at a speed according to the operation amount of the operation knob 5.

In this embodiment, the lamp control board 35 is used.
The lamp control means mounted on the game board is provided with a starting memory display 18, a normal symbol starting memory display 4
1 and the decoration lamp 25 are controlled, and the top frame lamp 28a and the left frame lamp 28 provided on the frame side are provided.
b, the right frame lamp 28c, the prize ball lamp 51, and the out-of-ball lamp 52 are displayed. Each lamp may be an LED or other type of light emitting body, and the LEDs used in this embodiment and other embodiments may be another type of light emitting body. That is, the lamp and the LED are examples of the light emitting body. Also, a variable display device 9 for variably displaying special symbols
And the display control of the normal symbol display 10 which variably displays the ordinary symbol is performed by the display control means mounted on the symbol control board 80.

FIG. 9 shows the circuit configuration in the symbol control board 80, an LCD (liquid crystal display) 82 which is an example of realizing the variable display device 9, an ordinary symbol display device 10, an output port of the main substrate 31 (port 0). , 2) 570 and 572 and output buffer circuits 620 and 62A.
8-bit data is output from the output port (output port 2) 572, and a 1-bit strobe signal (INT signal) is output from the output port 570.

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and when the INT signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105B, the display control command is received via the input buffer circuit 105A. As the input buffer circuits 105A and 105B, for example, general-purpose ICs 74HC540 and 74HC14 can be used. If the display control CPU 101 does not include an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

Then, the display control CPU 101 controls the display of the screen displayed on the LCD 82 in accordance with the received display control command. Specifically, the VDP 103 is given a command according to the display control command. VDP103
Reads out the necessary data from the character ROM 86. The VDP 103 displays the LCD 8 according to the input data.
Image data to be displayed on the LCD 2 is generated, and R, G, B signals and synchronizing signals are output to the LCD 82.

FIG. 9 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for giving an operating clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image including characters, figures, symbols, or the like displayed on the LCD 82.

The input buffer circuits 105A and 105B are
The signal can be passed only in the direction from the main board 31 to the display control board 80. Therefore, the display control board 8
There is no room for signals to be transmitted from the 0 side to the main board 31 side. That is, the input buffer circuits 105A and 105B form an irreversible information input unit together with the input port. Even if the circuit in the display control board 80 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side.

Noise filter 10 for cutting off high frequency signals
For example, a 3-terminal capacitor or a ferrite bead is used as 7, but the presence of the noise filter 107 eliminates the influence of noise on the display control command between the substrates. A noise filter may be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

FIG. 10 is a block diagram showing signal transmitting / receiving portions of the main board 31 and the lamp control board 35. In this embodiment, the top frame lamp 28a, the left and right frame lamps 28b, 28c provided outside the game area 7
Lighting and extinguishing of the decorative lamp 25, the starting memory indicator 18 and the normal symbol starting memory indicator 41 provided on the game board, and lighting of the prize ball lamp 51 and the out-of-ball lamp 52.
A lamp control command indicating turning off is output from the main board 31 to the lamp control board 35.

As shown in FIG. 10, the lamp control command relating to the lamp control is the output port (output port 0, 3) 570 of the I / O port section 57 in the basic circuit 53.
It is output from 573. Output port (output port 3) 5
73 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. Lamp control board 35
, The control command from the main board 31 is sent to the lamp control CP via the input buffer circuits 355A and 355B.
Input to U351. The lamp control CPU 351
Does not include an I / O port, the input buffer circuits 355A and 355B and the lamp control CPU 351.
An I / O port is provided between and.

In the lamp control board 35, the lamp control CPU 351 has a top frame lamp 28a, left and right frame lamps 28b and 28c, which are defined according to each control command.
A lighting / lighting-off signal is output to the top frame lamp 28a, the left and right frame lamps 28b and 28c, and the decoration lamp 25 according to the lighting / lighting-out pattern of the decoration lamp 25. The lighting / extinguishing signal is transmitted from the top frame lamp 28a and the left and right frame lamps 28b and 28.
c, output to the decoration lamp 25. The lighting / extinguishing pattern is stored in the built-in ROM or the external ROM of the lamp control CPU 351.

On the main board 31, the CPU 56 controls the RA
When there is an unpaid remaining number of prize balls in the stored contents of M55, a control command for instructing lighting of the prize ball lamp 51 is output, and the ball break switch installed upstream of the pay ball passage on the back surface of the game board described above. When 187 (see FIG. 3) no longer detects a game ball, it outputs a control command for instructing lighting of the out-of-ball lamp 52. In the lamp control board 35, each control command is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the out-of-ball lamp 52 according to the control commands.
It should be noted that the lighting / extinguishing pattern is the lamp control CPU 35.
It is stored in one built-in ROM or an external ROM.

The input buffer circuits 355A and 355B are, for example, 74HC54 which is a general-purpose CMOS-IC.
0.74HC14 is used. Input buffer circuit 35
5A and 355B are the main board 31 and the lamp control board 35.
The signal can only be passed in the direction towards. Therefore, there is no room for signals to be transmitted from the lamp control board 35 side to the main board 31 side. Even if the circuit in the lamp control board 35 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

On the main board 31, the output port 5
Buffer circuits 620 and 63A are provided outside the 70 and 573. The buffer circuits 620 and 63A are, for example, 74HC250 and 7 that are general-purpose CMOS-ICs.
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that a signal line that may give a signal from the lamp control board 70 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 63A.

FIG. 11 is a block diagram showing a configuration example of the signal transmission portion of the sound control command on the main board 31 and the sound control board 70. In this embodiment, the speaker 2 provided outside the game area 7 as the game progresses.
A sound control command for instructing sound output of No. 7 is output from the main board 31 to the sound control board 70.

As shown in FIG. 11, the sound control command is
It is output from the output ports (output ports 0, 4) 570 and 574 of the I / O port unit 57 in the basic circuit 53.
8-bit data is output from the output port (output port 4) 574, and 1-bit I is output from the output port 570.
The NT signal is output. In the sound control board 70, signals from the main board 31 are input buffer circuits 705A, 7
Input to the sound control CPU 701 via 05B. When the sound control CPU 701 does not have an I / O port built therein, an I / O port is provided between the input buffer circuits 705A and 705B and the sound control CPU 701.

Then, for example, the voice synthesizing circuit 702 by a digital signal processor has
The volume switching circuit 7 generates a sound or a sound effect according to the instruction of 1.
Output to 03. The volume switching circuit 703 is a sound control CP.
The output level of U701 is set to a level according to the set volume and output to the volume amplification circuit 704. The volume amplifier circuit 704 outputs the amplified sound signal to the speaker 27.

The input buffer circuits 705A and 705B are, for example, 74HC54 which is a general-purpose CMOS-IC.
0.74HC14 is used. Input buffer circuit 70
5A and 705B can pass signals only in the direction from the main board 31 to the sound control board 70. Therefore, there is no room for signals to be transmitted from the sound control board 70 side to the main board 31 side. Therefore, even if the circuit in the sound control board 70 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

In the main board 31, the output port 5
Buffer circuits 620 and 67A are provided outside 70 and 574, respectively. The buffer circuits 620 and 67A are, for example, 74HC250 and 7 that are general-purpose CMOS-ICs.
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that the signal line that may give a signal from the sound control board 70 to the main board 31 is further surely removed. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 67A.

FIG. 12 is a block diagram showing components related to payout, such as the components of the payout control board 37 and the ball payout device 97. As shown in FIG. 12, the detection signal from the full switch 48 is input to the I / O port section 57 of the main board 31 via the relay board 71. The detection signal from the ball break switch 187 is also transmitted via the relay boards 72 and 71 to the I / O port section 5 of the main board 31.
Input to 7.

The CPU 56 of the main board 31 determines whether the detection signal from the ball break switch 187 indicates the ball break condition.
Alternatively, when the detection signal from the full tank switch 48 indicates the full state, a payout control command instructing that the payout should be stopped is sent. When receiving the payout control command instructing that the payout should be stopped, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is input to the I / O port section 57 of the main board 31 via the relay boards 72 and 71, and the payout control is also performed via the relay board 72. It is input to the input port 372b of the substrate 37. Prize ball count switch 30
1A is provided in the payout mechanism portion of the ball payout device 97, and detects the actually paid award ball.

When a prize is won, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
A payout control command indicating the number of prize balls is input from. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. The payout control command indicating the number of prize balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 is an I / O port 372a.
The payout control command is input via the, and the ball payout device 97 is driven according to the payout control command to perform the prize ball payout. In this embodiment, the payout control CPU 371 is
1-chip microcomputer, at least RA
M is built in.

On the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside the 70 and 571. The buffer circuits 620 and 68A are, for example, 74HC250 and 7 which are general-purpose CMOS-ICs.
4HC14 is used. According to such a configuration, a signal input from the outside to the inside of the main board 31 is blocked, so that the signal line that may give a signal from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 uses the output port 3
A lent ball number signal indicating the number of lent balls is output to the terminal board 160 via 72c. Furthermore, the output port 37
An error signal is output to the error display LED 374 via 2d.

Further, the input port 3 of the payout control board 37
Detection signals from the ball lending count switch 301B and a payout motor position sensor 296 for detecting the rotational position of the payout motor 289 are input to the 72b via the relay board 72. Ball lending count switch 301B
Is provided in the payout mechanism portion of the ball payout device 97, and detects the actually paid out lending ball. The drive signal from the payout control board 37 to the payout motor 289 is output to the output port 372.
The driving signal transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via c and the relay board 72, and the drive signal to the distribution solenoid 310, the payout of the ball payout device 97 via the output port 372e and the relay board 72. It is transmitted to the distribution solenoid 310 in the mechanical portion. The output of the clear switch 921 is also input to the input port 372b.

A card unit control microcomputer is mounted on the card unit 50. Also,
The card unit 50 is provided with a connecting table direction indicator 153, a card insertion indicator lamp 154 and a card insertion slot 155 (see FIG. 1). On the balance display board 74,
A frequency display LED provided in the vicinity of the hit ball supply tray 3,
The ball lending switch and the return switch are connected.

From the balance display board 74 to the card unit 50
A ball lending switch signal and a return switch signal are given to the player through the payout control board 37 according to the operation of the player. In addition, the balance display board 74 from the card unit 50
A card balance display signal indicating the balance of the prepaid card and a ball lending allowance display signal are given to the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal) and a unit operation signal (B
RDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (P
RDY signal) is input port 372b and output port 3
It is exchanged via 72e.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. Further, the card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected state / unconnected state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the card unit controlling microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point in time, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

Then, the payout control C of the payout control board 37 is used.
When the PU 371 raises the EXS signal to the card unit 50 and detects the fall of the BRQ signal from the card unit 50, it drives the payout motor 289 to pay out a predetermined number of lending balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the card unit 5
The EXS signal for 0 is dropped. After that, if the BRDY signal from the card unit 50 is not on,
The prize ball payout control is executed.

As described above, all the signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input to the main board 31 from 0, and there is no room for the signal to be illegally input to the basic circuit 53 of the main board 31 from the card unit 50 side. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

In this embodiment, a power-off signal is also input from the power supply board 910 to the payout control board 37. The power-off signal is input to the non-maskable interrupt (NMI) terminal of the payout control CPU 371. Furthermore, the payout control board 3
At least a part of the RAM (may be a RAM with a built-in CPU) existing in 7 is backed up by a backup power supply created in the power supply board 910. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM is saved for a predetermined period. However, in this embodiment, all the RAMs are backed up by the backup power supply.

In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 is integrated with the gaming machine. May be. Further, the present invention can be applied even when a game ball corresponding to the amount of coins is lent out in response to the coin insertion.

FIG. 13 is a block diagram showing a configuration example of the power supply board 910. The power supply board 910 includes a main board 31,
Design control board 80, sound control board 70, lamp control board 3
5 and the payout control board 37 and other electric part control boards are installed independently of each other, and each electric part control board in the gaming machine and the voltage used by the mechanical parts are generated. In this example, AC2
4V, VSL (DC + 30V), DC + 21V, DC + 1
Generates 2V and DC + 5V. Further, the backup power source, that is, the capacitor 916 serving as a memory holding unit,
It is charged from DC + 5V, that is, from the line of the power supply that drives the ICs on each substrate. Note that VSL is a rectifier circuit 912.
At, the rectifying element rectifies and boosts AC 24V. VSL serves as a solenoid drive power source.

The transformer 911 converts the AC voltage from the AC power supply into 24V. 24V AC voltage is applied to connector 9
It is output to 15. In addition, the rectifier circuit 912 is an AC 24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
C converter 913 may include one or more converters I
VSL with C922 (only one shown in FIG. 13)
Based on the above, + 21V, + 12V and + 5V are generated and output to the connector 915. A relatively large-capacity capacitor 923 is connected to the input side of the converter IC 922. Therefore, when the power supply to the game machine from the outside is stopped, the DC voltage of + 30V, + 12V, + 5V, etc., decreases relatively gently. The connector 915 is connected to, for example, a relay board, and the relay board supplies electric power of a required voltage to each electric component control board and mechanical components.

However, the power supply board 910 may be provided with each connector reaching each electric component control board, and each voltage may be supplied from the power supply board 910 to each board without the relay board. Further, although one connector 915 is representatively shown in FIG. 13, the connector is provided for each electric component control board.

+ 5V from the DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is a backup RAM of the electric component control board when the power supply to the game machine is stopped (RAM whose power is backed up, that is, backup storage means that can be in a storage content holding state even when the power supply is stopped).
It becomes a backup power supply that supplies electric power so that the memory state can be maintained. In addition, a diode 9 for preventing backflow is provided between the + 5V line and the backup + 5V line.
17 is inserted. In this embodiment, the backup + 5V is applied to the main board 31 and the payout control board 3
7 is supplied.

A power supply monitoring IC (power supply monitoring means) 902 is mounted on the power supply board 910. The power supply monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+ 22V in this example), it is determined that the power supply will be stopped, and a power-off signal is output. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is the voltage immediately after conversion from AC to DC, is used.
The power off signal from the power monitoring IC 902 is sent to the main board 31.
And the payout control board 37 and the like.

The predetermined value for the power supply monitoring IC 902 to detect the stop of power supply is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. Further, the power supply monitoring IC 902 is a CPU
For driving circuit elements such as (+5 in this example)
The voltage is higher than V) and is configured to monitor the voltage immediately after the conversion from AC to DC, so that the monitoring range can be expanded with respect to the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V
Therefore, it can be expected to prevent erroneous detection of switch-on at the moment of power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in + 12V generated after + 30V is generated, before the voltage starts to drop.

When the voltage of the + 12V power supply drops, the switch output comes to be in the ON state, but if the + 30V power supply voltage that drops earlier than + 12V is monitored and the stop of the power supply is recognized, the switch output will show the ON state. It is possible to enter the state of waiting for the restoration of the power supply before entering the state where the switch output is not detected.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric part control board, the power supply cutoff circuit can supply a power-off signal to the plurality of electric part control boards. Even if there are any number of electrical component control boards that require a power-off signal, one power source monitoring means may be provided, so that even if each electrical component control means in each electrical component control board performs recovery control described below. , The cost of gaming machines does not rise so much.

In the configuration shown in FIG. 13, the detection signal (power-off signal) of the power supply monitoring IC 902 is transmitted through the buffer circuits 918 and 919 to the respective electric component control boards (for example, the main board 31 and the payout control circuit). Although it is transmitted to the substrate 37), for example, one detection signal may be transmitted to the relay substrate and the same signal may be distributed from the relay substrate to each electric component control substrate. In addition, a buffer circuit may be provided according to the number of substrates that require a power-off signal. Further, the main substrate 31
Regarding the power-off signal output to the payout control board 37, the monitoring voltage of the power-source monitoring circuit that outputs the power-off signal may be different.

FIG. 14 shows the CPU 56 in the main board 31.
It is a block diagram showing an example of the circumference. As shown in FIG. 14, the power-off signal from the power supply monitoring circuit of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the CPU 56 via the buffer circuit 900. Therefore, the CPU 56 can confirm the occurrence of the stop of the power supply to the gaming machine by the non-maskable interrupt (NMI) process. The power-off signal is also input to the determination circuit 950. Since the signal output from the buffer circuit 900 is substantially the same as the detection signal from the power supply monitoring circuit 910 (only amplified), the buffer circuit 90 will be described below.
The signal output from 0 may be called a detection signal or an NMI signal. The determination circuit 950 is an example of system reset determination means. Note that the CPU 56 is XN
When the input signal of the MI terminal becomes low level, the interrupt is accepted at the falling edge.

A system reset circuit 65 is also shown in FIG. The reset IC 651 is
The output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level when the predetermined time elapses. That is, the reset signal is raised to the high level to bring the CPU 56 into the operable state. Further, the reset IC 651 monitors the power supply voltage of VSL, which is a power supply voltage equal to the power supply voltage monitored by the power supply monitoring circuit of the power supply board 910, and has a predetermined voltage value (the power supply voltage at which the power supply monitoring circuit outputs a power-off signal). When the value is lower than the value), the output goes low. Therefore, the CPU 56 is reset in the system after performing a predetermined power supply stoppage process in response to the power-off signal from the power supply monitoring circuit.

As shown in FIG. 14, the reset IC 651 is used.
The reset signal from is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level.
Then, the Q5 output of the counter IC 941 is the NOT circuit 9
It is input to the NAND circuit 947 via 45 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed to the high level, and the Q output is input to the logical sum circuit (OR circuit) 949. The NAND circuit 9 is connected to the other input of the OR circuit 949.
The output of 47 is introduced via the NOT circuit 948. The output of the OR circuit 949 is C as a reset signal.
It is connected to the reset terminal of the PU 56. With such a configuration, since the reset signal (low level signal) is applied twice to the reset terminal of the CPU 56 when the power is turned on, the CPU 56 surely starts the operation.

Then, for example, the detection voltage of the power supply monitoring circuit of the power supply substrate 910 (the voltage at which the power-off signal is output) is set to + 22V, and the detection voltage for setting the reset signal to the low level is set to + 9V. In such a configuration, since the power supply monitoring circuit and the system reset circuit 65 monitor the voltage of the same power supply VSL, the timing at which the voltage monitoring circuit outputs the power cutoff signal and the system reset circuit 65 resets the system. It is possible to reliably set the difference between the timings of outputting the signals in a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop time process to the reliable completion of the power supply stop time process in response to the power off signal from the power supply monitoring circuit. In addition,
The voltage of the power supply monitored by the power supply monitoring circuit and the system reset circuit 65 may be different.

At least part of the RAM is backed up by the backup power supply supplied from the power supply board while the power is not supplied from the + 5V power supply which is the drive power supply of the CPU 56 and the like, and the power supply to the gaming machine is stopped. Content is saved. When the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to the normal operating state. At that time, since necessary data is stored in the backup RAM, it is possible to restore the game state at the time of occurrence of a power failure or the like at the time of recovery from the power failure or the like.

In the structure shown in FIG. 14, the reset terminal of the CPU 56 is supplied with the reset signal twice (low level is the reset level) when the power is turned on. However, even if the reset signal rises only once, the reset signal is surely generated. When using a CPU that is released from reset, the code 9
The circuit elements indicated by 41 to 949 are unnecessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

The reset signal is also input to the determination circuit 950. The determination circuit 950 is a circuit that inputs the NMI signal and the reset signal and outputs the determination signal to the input port of the CPU 56, but the details will be described later.

The CPU used in this embodiment
The 56 also includes an I / O port (PIO) and a timer / counter circuit (CTC).

15 and 16 are explanatory views showing the allocation of output ports in this embodiment. Figure 1
As shown in FIG. 5, the output port 0 is an output port of the INT signal of the control command sent to each electric component control board. In addition, 8-bit data of the payout control command sent to the payout control board 37 (payout control signals CD0 to CD
7) is output from the output port 1 and 8-bit data (display control signals CD0 to CD7) of the display control command sent to the symbol control board 80 is output from the output port 2 and sent to the lamp control board 35. 8-bit data of the lamp control command (lamp control signals CD0 to CD
7) is output from the output port 3. Then, as shown in FIG. 16, 8-bit data (sound control signals CD0 to CD7) of the sound control command sent to the sound control board 70 is output from the output port 4.

Also, from the output port 5, the information output circuit 6
Various information output signals reaching the information terminal board 34 and the terminal board 160 via 4, that is, output data of information relating to control are output. Then, from the output port 6, a solenoid 16 for opening and closing the variable winning ball device 15, a solenoid 21 for opening and closing the opening and closing plate 20 of the special winning opening, and a solenoid 2 for switching the path inside the special winning opening.
The drive signal for 1A is output.

As shown in FIGS. 15 and 16, each INT signal (payout control signal INT, display control signal) output to the payout control board 37, the pattern control board 80, the lamp control board 35, and the sound control board 70. Output port (output port 0) for outputting INT, lamp control signal INT and sound control signal INT, and payout control signals CD0 to CD
7, display control signals CD0 to CD7, lamp control signal CD
0 to CD7 and the output ports (output ports 1 to 4) for outputting the sound control signals CD0 to CD7 are different ports.

Therefore, when outputting the INT signal, the payout control signals CD0 to CD7 and the display control signals CD0 to CD0 are mistakenly output.
The possibility of changing the CD7, the lamp control signals CD0 to CD7, and the sound control signals CD0 to CD7 is reduced. Also, when the payout control signals CD0 to CD7, the display control signals CD0 to CD7, the lamp control signals CD0 to CD7, or the sound control signals CD0 to CD7 are output, the IN
The possibility of changing the T signal is reduced. As a result, the command to the electric component control board from the game control means of the main board 31 is more reliably transmitted. Further, since each INT signal is configured to be output from the output port 0, I of the game control means
The load of NT signal output processing is reduced.

FIG. 17 is an explanatory diagram showing bit allocation of input ports in this embodiment. As shown in FIG. 17, bits 0 to 7 of the input port 0 have respective winning opening switches 33a, 39a, 29a, 30a, and
The detection signals of the starting port switch 14a, the count switch 23, the V winning switch 22, and the gate switch 32a are input. In addition, the detection signals of the prize ball count switch 301A, the full tank switch 48, the ball cut switch 187, the count switch short circuit signal, and the detection signal of the clear switch 921 are input to bits 0 to 4 of the input port 1, respectively. The detection signal from each switch is logically inverted in the switch circuit 58. Thus, the detection signal of the clear switch 921, that is, the operation input of the initialization operation means, is the same input port as the input port (the input unit of 8-bit configuration) to which the detection signal of the switch for detecting the game ball is input. Is input to the bit (input port circuit) in.

Next, the operation of the gaming machine will be described. Figure 1
8 is a flowchart showing main processing executed by the game control means (CPU 56 and peripheral circuits such as ROM and RAM) on the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts the main processing after step S1. In the main processing, the CPU 56 first
Make the necessary initial settings.

In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to the interrupt mode 2 (step S2), and the stack pointer designated address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). After initializing the built-in device (built-in peripheral circuit) CTC (counter / timer) and PIO (parallel input / output port) (step S5), the RAM is set to the accessible state (step S6).

CPU 56 used in this embodiment
Also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). Also, the CTC has two external clock / timer trigger inputs CLK / TRG2,3.
And two timer outputs ZC / TO0,1.

CPU 5 used in this embodiment
6 has the following three types of maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

Interrupt mode 0: The built-in device that issued the interrupt request has the RST instruction (1 byte) or the CALL instruction (3
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction of the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, CPU 56 automatically sets interrupt mode 0
become. Therefore, when it is desired to set the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
It is a mode which always flies to the address 0038 (H).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device is the interrupt address. Is a mode indicating. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, the interrupt processing can be installed at an arbitrary (although discrete) even address. Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, it becomes possible to easily process the interrupt request from each built-in device, and the interrupt processing can be installed at an arbitrary position in the program. It will be possible. Further, unlike the interrupt mode 1, it is easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

Next, the CPU 56 confirms the state of the output signal of the clear switch 921 input via the input port 1 only once (step S7). If ON is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S11 to S1).
5). When the clear switch 921 is on (when pressed), a low level clear switch signal is output. In the input port 1, the clear switch signal is on at a high level (see FIG. 15). Further, for example, the game shop clerk uses the clear switch 92.
By starting power supply to the gaming machine while turning 1 on, the initialization process can be easily executed. That is, the RAM clear or the like can be performed.

If the clear switch 921 is not in the ON state, the data protection processing of the backup RAM area (for example, processing when power supply is stopped such as addition of parity data) is performed when power supply to the gaming machine is stopped. It is confirmed whether or not (step S8). In this embodiment, when the power supply is stopped, a process for protecting the data in the backup RAM area is performed. When such a protection process is performed, backup is made. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

In this embodiment, the backup RAM
Whether or not there is backup data in the area is confirmed by the state of the backup flag set in the backup RAM area during the power supply stop process. In this example, as shown in FIG. 19, if "55 (H)" is set in the backup flag area, it means that backup is in progress (ON state), and a value other than "55 (H)" is set. If so, it means no backup (off state).

After confirming that there is a backup, the CPU 5
6 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Further, the number of checksum calculations corresponding to the number of checksum target data is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area indicated by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above process is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area,
The data after inversion is used as the checksum.

In the power supply stop process, the checksum is calculated by the same process as the above process, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. If the power is restored after an unexpected power outage such as a power outage, backup RA
Since the data in the M area should have been saved, the check result (comparison result) becomes normal (match). If the check result is not normal, it means that the data in the backup RAM area is different from the data when the power supply was stopped. In such a case, since the internal state cannot be returned to the state when the power supply was stopped, the initialization process that is executed when the power is turned on, not when the power supply is restored from the stop, is executed.

If the check result is normal, the CPU 56
Performs a game state recovery process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state when the power supply was stopped (step S10). Then, the saved value of the PC (program counter) saved in the backup RAM area is set in the PC and the address is restored.

As described above, the backup RA is backed up using the backup flag and the check data such as the checksum.
By checking whether or not the data in the M area is saved, it is possible to accurately return the game state to the state when the power supply was stopped. That is, the certainty of the state restoration process based on the data in the backup RAM area is improved. In this embodiment, it is confirmed whether or not the data in the backup RAM area is stored by using both the backup flag and the check data, but only one of them may be used. That is, either the backup flag or the check data may be used as a trigger for executing the state restoration process.

In the initialization process, the CPU 56 first executes R
AM clear processing is performed (step S11). Further, a predetermined work area (for example, a random number counter for normal symbol determination, a normal symbol determination buffer, a special symbol left middle right symbol buffer,
Special symbol process flag, payout command storage pointer,
Work area setting processing for setting an initial value to a prize ball flag, out-of-ball flag, payout stop flag, or other flag for selectively performing processing according to the control state is performed (step S1).
2). Further, a process of transmitting a payout permission state designation command (hereinafter, referred to as a payable state designation command) for instructing that the ball can be paid out from the ball payout device 97 to the payout control board 37 (step S13). . Also,
Other sub-boards (lamp control board 35, sound control board 70,
A process of transmitting an initialization command for initializing the pattern control board 80) to each sub-board is executed (step S1).
4). As an initialization command, a command indicating the initial symbol displayed on the variable display device 9 (for the symbol control board 80) and a command for instructing to turn off the prize ball lamp 51 and the ball out lamp 52 (for the lamp control board 35) Etc.)

In the initialization process, the payable state designating command is always transmitted to the payout control board 37. what if,
Even if the state of the gaming machine is a state in which the payout from the ball payout device 97 is not possible, the fact is detected in the game control process executed immediately after that, and a payout instructing that the payout is not possible is issued. Command for specifying prohibited state (hereinafter,
It is called a payout stop state designation command. ) Is sent, so there is no problem.

Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S15). That is,
A value corresponding to 2 ms as an initial value is set in a predetermined register (time constant register).

As described above, in this embodiment, the CP
When U56 detects that the clear switch 921 is on, the initialization process (steps S11 to S11) is performed regardless of whether data is stored in the backup RAM.
Since S15) is executed, the game control means can be forcibly initialized on the game shop side. That is, the initialization of the game control means is realized by software. Also,
Even if the clear switch 921 is not on, the game control means can be initialized by software using the backup flag and the check data such as the checksum. Therefore, when the power supply is restored, the wrong game is played. It is prevented that the state is restored.

When it is not detected that the clear switch 921 is on, if it is confirmed that the data is not correctly stored in the backup RAM, the CPU 5
6 executes initialization processing (steps S11 to S15). Therefore, the CPU 56 stores the contents stored in the fluctuation data storage means when the predetermined initialization condition is satisfied even if the initialization operation means is not operated (“N” in step S8 or S9 in this example). To initialize.

Execution of initialization processing (steps S11 to S1)
When 5) is completed, the display random number updating process (step S17) and the initial value random number updating process (step S18) are repeatedly executed in the main process. When the display random number updating process and the initial value random number updating process are executed, the interrupt disabled state is set (step S16), and when the display random number updating process and the initial value random number updating process are completed, the interrupt enabled state is set. (Step S19). The display random number is a random number for determining the symbol displayed on the variable display device 9, and the display random number updating process is a process of updating the count value of the counter for generating the display random number. . The initial value random number updating process is a process of updating the count value of the counter for generating the initial value random numbers. The initial value random number is a random number for determining an initial value of a count value of a counter (big hit determination random number generation counter) for generating a random number for determining whether or not to make a big hit. In the game control process described later, when the count value of the big hit determination random number generation counter makes one round, the initial value is set to the counter.

The interrupt-prohibited state is set when the display random number updating process is executed, because the display random number updating process is also executed in the timer interrupt process described later. This is to avoid competing with. That is, if a timer interrupt occurs during the process of step S17 and the count value of the counter for generating the display random number is updated during the timer interrupt process, the continuity of the count value is lost. There are cases. However, such an inconvenience does not occur if the interrupt prohibition state is set during the process of step S17.

FIG. 20 is a flow chart showing an example of the game state recovery processing. In the game state recovery process, C
The PU 56 first performs a stack pointer restoration process (step S81). The value of the stack pointer is saved in a predetermined RAM area (power source is backed up) in a power supply stoppage process which will be described later in detail. Therefore, in step S81, the value of the RAM area is set in the stack pointer to restore the value. In the area pointed to by the restored stack pointer (that is, the stack area), the register value and the value of the program counter (PC) when the power supply is stopped are saved.

Next, the CPU 56 confirms whether or not the payout is stopped (step S82). Whether or not the payout has been stopped is determined by the RAM whose power is backed up.
Predetermined work area stored in the area (for example, random symbol for normal symbol determination, normal symbol determination buffer, special symbol left middle right symbol buffer, special symbol process flag,
The payout stop flag as the payout state data in the payout command storage pointer, the award ball flag, the out-of-ball flag, the payout stop flag, etc.) is confirmed. When it is in the payout stop state, a payout control command (payout stop state designation command) for instructing the stop of payout is transmitted to the payout control means mounted on the payout control board 37 (step S83). If the payout is not stopped, the payout control unit sends a payout control command (payable state designation command) to the payout control means (step S84).

Since the payout control means cannot recognize the shortage of the supply balls and the full capacity of the surplus ball receiving tray 4, the game control means must notify the shortage of the supply ball or the surplus ball receiving tray 4 when the power is restored. There is a risk that the game ball payout process will be started despite the fact that it is a ton. However, in this embodiment, in the game state recovery process, since the payout control command for instructing the stop of the payout or the payout control command for instructing that the payout is possible, the payout control means causes the shortage of the supply balls. And even if the surplus ball receiving tray 4 is full, the game ball payout process is never started.

Here, if the payout state determination means (a part of the game control means) for determining whether or not the game medium can be paid out detects that the payout is not possible, regardless of the cause. Although one type of payout stop state designation command is transmitted, it may be transmitted separately for each cause-specific command (in this example, a command indicating a shortage of replenishing balls and a command indicating bottom plate full). . Furthermore, when the payout of the game ball is not possible, a command instructing to prohibit the launch of the game ball to prohibit the continuation of the game may be transmitted to the payout control board 37. Discharge control board 3
When the payout control means mounted in 7 receives a command instructing to prohibit the launch of a game ball, it stops driving the hitting ball launching device. Further, when the payout of the game ball is not possible, the game control means may directly give the launch control means a signal instructing to prohibit the launch of the game ball. Further, the payout control means may stop the driving of the hitting ball launching device when the payout stop state designation command is received.

Next, the CPU 56 confirms whether or not the special symbol is being changed in the variable display device 9 when the power supply is stopped (step S85). Whether or not the special symbol is changing when the power supply is stopped can be confirmed by, for example, the value of the special symbol process flag stored in the RAM area where the power is backed up. If the special symbol is changing, to the display control means mounted on the symbol control board 80, a special symbol power failure recovery command and a display control command designating the symbol in the left and right are transmitted (step S86, S8
7). Here, the symbols in the left and right designated by the display control command are the symbols that should have been stopped and displayed due to the special symbol fluctuation that was performed when the power supply was stopped.

Upon receipt of the special symbol power failure recovery command, the display control means performs a predetermined notification process. For example, the variable display device 9 displays that a power failure has occurred. Based on various information that was backed up power supply, the game state returns to the state before the power supply was stopped, but after that, when the fluctuation period of the special symbol ends, the game control means sends a confirmation command to the display control means. Send. The display control means is
Based on the receipt of the confirmation command, the next special symbol can be changed.

If the special symbol is not changing, CP
U56 performs a process of transmitting a display control command designating a symbol in the left and right, a confirmation command, and a customer waiting demo command to the display control means (steps S88 to S9).
0). The symbols in the left and right specified by the display control command are
It is the symbol displayed on the variable display device 9 when the power supply is stopped.

When the confirmation command is received, the display control means controls the variable display device 9 to display the special symbol designated by the display control command for designating the symbols in the left and right. Further, when the customer waiting demo command is received, the display state of the background of the variable display device 9 is controlled to the standby state.

After that, the CPU 56 clears the backup flag (step S91), that is, resets the flag indicating that a predetermined storage protection process has been executed at the previous power supply stop. Further, the saved values of various registers are read from the stack area and set in various registers (step S92). That is, register restoration processing is performed. Then, when the parity flag is not turned on, the interrupt permission state is set (steps S93 and S94).
Finally, the AF register (accumulator and flag register) is restored from the stack area (step S9).
5).

Then, the RET command is executed, but the return destination here is not the part that called the game state recovery processing. This is because the stack pointer restoration process is performed in step S81, and the return address stored in the stack area pointed to by the restored stack pointer is the address at which the NMI occurred when the power supply was previously stopped in the program. Therefore, the next RET instruction in step S95 returns to the address where the NMI occurred when the power supply was stopped. That is, the recovery control is executed based on the address saved in the stack area.

When a timer interrupt occurs, the CPU 56
After performing the register save process (step S20), the game control process of steps S21 to S32 shown in FIG. 21 is executed. In the game control process, the CPU 56 first
Via the switch circuit 58, the detection signals of the switches such as the gate switch 32a, the starting opening switch 14a, the count switch 23, and the winning opening switches 29a, 30a, 33a, 39a are input to determine their states (switch processing: Step S21).

Next, various abnormality diagnosis processing is performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error processing: step S22).

Next, a process of updating the count value of each counter for generating each judgment random number such as a big hit judgment random number used for game control is performed (step S23).
The CPU 56 further performs a process of updating the count value of the counter for generating the display random number (step S
24) Further, a process of updating the count value of the counter for generating the initial value random number is performed (step S2).
5).

Further, the CPU 56 carries out special symbol process processing (step S26). In the special symbol process control, the corresponding process is selected and executed according to the special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. Then, the value of the special symbol process flag is updated during each process according to the game state. Also, a normal symbol process process is performed (step S27). In the normal symbol process process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display device 10 in a predetermined order. And the value of the normal symbol process flag,
It is updated during each process according to the game state.

Next, the CPU 56 performs a process of transmitting a display control command or the like (command control process: step S28). The command control process may be configured to be executed in a special symbol process process or a normal symbol process process.

Further, the CPU 56 performs an information output process for outputting data such as big hit information, starting information, probability variation information, etc. supplied to the hall management computer (step S30).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S31). In order to open or close the variable winning ball device 15 or the opening / closing plate 20 or to switch the game ball passage in the special winning opening, the solenoid circuit 59 drives the solenoids 16, 21, 21A according to the drive command. To do.

Then, the CPU 56 causes the starting opening switch 1
4a, winning opening switch 29a, 30a, 33a, 39a
And prize ball processing for setting the number of prize balls based on the detection signal of the count switch 23 (step S).
32). Specifically, a payout control command indicating the number of prize balls is sent to the payout control board 37 in response to the winning detection based on that the starting opening switch 14a, the winning opening switches 29a, 30a, 33a, 39a and the count switch 23 are turned on. Output. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 in response to a payout control command indicating the number of prize balls. After that, the contents of the register are restored (step S33), and the interrupt enabled state is set (step S34).

According to the above control, in this embodiment, the game control process is activated every 2 ms.
In this embodiment, the game control process is executed in the timer interrupt process, but in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set,
The game control process may be executed in the main process.

FIG. 22 is a flow chart showing an example of a special symbol process processing program executed by the CPU 56. The special symbol process process shown in FIG. 22 is shown in FIG.
This is a specific process of step S26 in the flowchart of FIG. CPU56, when performing the special symbol process processing, fluctuation reduction timer subtraction processing (step S310) and starting opening switch passage confirmation processing (step S311)
After performing, the processing of any of steps S300 to S309 is performed according to the internal state (special symbol process flag in this example).

The fluctuation shortening timer subtraction processing is a processing of subtracting the fluctuation shortening timers provided in the number corresponding to the maximum storable number in the starting memory (memory that the starting port switch 14a is turned on). Then, in a special symbol big hit determination process (step S301) described later, for example, the value of the fluctuation reduction timer is 0, and in a low probability state (normal state), the starting memory number is the maximum value of the starting memory, the probability change In the state, if the number of starting memories is "2" or more, it is determined to use a pattern in which the variation time is shortened as the symbol variation pattern. The starting port switch passage confirmation process is a process of acquiring and storing each predetermined random number value when the starting port switch 14a is turned on.

In steps S300 to S309, the following processing is performed.

Special symbol normal processing (step S300):
Check the starting memory number, if the starting memory number is not 0, change the value of the special symbol process flag so as to move to step S301.

Special symbol big hit determination processing (step S30
1): The contents of a buffer or the like that stores various random numbers stored when a start winning is won are shifted. The result of the shift,
Based on the contents of the buffer pushed out, it is determined whether or not to be a big hit. In addition, the buffer is prepared by the maximum number of memorable start winnings. Also, the contents of the buffer pushed out by the shift are contents corresponding to the starting winning that occurred first. When it is decided to make a big hit, a big hit flag is set. afterwards,
The value of the special symbol process flag is changed so as to shift to step S302.

Stop symbol setting process (step S302):
The stop symbol of the left and right middle symbols which is the display result of the variable display of the special symbol is determined. Then, the value of the special symbol process flag is changed so as to move to step S303.

Fluctuation pattern setting process (step S30
3): A variable display pattern of the special symbol, that is, a variable display pattern (variation pattern) is determined. Then, a process for outputting a display control command for notifying the determined variation pattern and the stop symbol to the symbol control board 80 and the like is performed. After that, the value of the special symbol process flag is changed so as to shift to step S304.

Special symbol variation process (step S304):
It is confirmed whether or not the fluctuation time determined according to the fluctuation pattern has elapsed. If it has elapsed, step S305
Change the value of the special symbol process flag so as to shift to.

Special symbol design stop processing (step S30
5): After a certain time (for example, 1.000 seconds) has passed,
If it is determined to be a big hit, the value of the special symbol process flag is changed so as to move to step S306. If not, the value of the special symbol process flag is changed so as to shift to step S300.

Pre-opening processing for the special winning opening (step S30
6): Start the control for opening the special winning opening. Specifically, the counter and the flag are initialized, and the solenoid 54 is driven to open the special winning opening. Then, the value of the special symbol process flag is changed so as to move to step S307.

Processing during opening of the special winning opening (step S30
7): The process of confirming the establishment of the closing condition of the special winning opening is performed. If the conditions for closing the special winning opening are met, step S30
The value of the special symbol process flag is changed so as to shift to 8.

Specific area effective time processing (step S30
8): The presence or absence of passage of the V winning switch 22 is monitored, and the processing for confirming the establishment of the jackpot gaming state continuation condition is performed. The condition for continuing the jackpot gaming state is established, and if there are still remaining rounds, the value of the special symbol process flag is changed so as to move to step S307. Further, if the jackpot gaming state continuation condition is not satisfied within a predetermined effective time, or if all rounds are finished, the value of the special symbol process flag is changed so as to shift to step S309.

Big hit end processing (step S309): control for causing the lamp control means or the like to display to notify the player that the big hit game state has ended. Then, the value of the special symbol process flag is changed so as to shift to step S300.

FIG. 23 is a flow chart showing the starting opening switch passage confirmation processing (step S311). When the ball hits the starting winning opening 14 provided on the game board, the starting opening switch 14a is turned on. The CPU 56
When it is determined that the starting port switch 14a is turned on via the switch circuit 58 (step S41), it is confirmed whether or not the number of stored memories reaches the upper limit value (4 in this example) (step S42). If the number of stored memories has not reached the upper limit, the number of stored memories is increased by 1 (step S43),
Extract the value of each random number such as the big hit determination random number. And
These are stored in the random value storage area corresponding to the value of the number of stored memories (step S44).

Further, control is carried out for a request for sending out a command for specifying the number of stored starting memory (step S45). The start memory number designation command is a lamp control command transmitted to the lamp control means mounted on the lamp control board 35 to notify the new start memory number, and will be specifically described later. The process of specifying the command transmission table is performed. It should be noted that if the number of starting memories has reached the upper limit value, the process of increasing the number of starting memories is not performed.

In the special symbol process process of step S25, the CPU 56 confirms the value of the starting memory number as shown in FIG. 24 (step S51). If the number of starting memories is not 0, the value stored in the random number storage area corresponding to starting memory; 1 (first starting memory) is read (step S52), and the value of the number of starting memories is decreased by 1,
At the same time, the value in each random value storage area is shifted (step S53). That is, starting memory; n (n = 2, ...,
Each value stored in the random value storage area corresponding to 4) is stored in the random value storage area corresponding to start memory: n-1. Note that the contents of the random value storage area corresponding to the number of starting memories at that time are cleared. For example, when the number of starting memory is 4, the content of the special symbol random value storage area corresponding to the starting memory; 4 is cleared.

Further, since the number of starting memories is reduced by 1, a process for sending out a starting memory number designation command is performed in order to notify the new starting memory number to the lamp control means (step S65).

Then, the CPU 56 determines the hit / departure based on the value read in step S52, that is, the value of the extracted big hit determination random number (special symbol judgment random number) (step S54). Here, the big hit determination random number takes a value in the range of 0 to 316. Then, as shown in FIG. 25, in the normal state, for example, when the value is “3”, it is determined as “big hit”, and when it is any other value, it is determined as “out”. In the high probability state (probability change state), for example, the value is “3”,
If it is any one of "7", "79", "103", and "107", it is determined as "big hit", and if it is any other value, it is determined as "outlier".

FIG. 26 is an explanatory diagram showing each random number. Each random number is used as follows. (1) Random 1: Decide whether to generate a big hit (for big hit judgment) (2) Random 2-1 to 2-3: For deviating symbols in the left and right of the special symbol (left and right in the special symbol) (3) ) Random 3: Determine the combination of special symbols that generate big hits (for big hit symbols determination) (4) Random 4: Determine the fluctuation pattern of special symbols (for fluctuation pattern determination) (5) Random 5: Normal symbol Determine whether or not to generate a base hit (for normal symbol hit determination) (6) Random 6: Determine the initial value of Random 1 (For determining the initial value of Random 1) (7) Random 7: Initial value of Random 5 Determine (for random 5 initial value determination)

Incidentally, in step S23 in the game control process shown in FIG. 21, the CPU 56 determines the random number for jackpot determination of (1), the random number for jackpot symbol determination of (3), and the regular symbol hit determination of (5). A counter for generating a random number for use is incremented (addition by 1). That is, those are the judgment random numbers, and the other random numbers are the display random numbers or the initial value random numbers. In addition, in order to enhance the game effect, random numbers related to ordinary symbols other than the above random numbers (1) to (7) are also used.

The values of the counter for generating each random number and the counter for generating each initial value determining random number are the same as those in step S1 in the main process shown in FIG.
It is initialized with 1 (value is set to 0).

In step S54 shown in FIG. 24, when it is determined that the big hit, the big hit symbol is determined according to the value of the random number for the big hit symbol (random 3) (step S).
55). In this embodiment, each symbol of the symbol numbers set in the jackpot symbol table corresponding to the value of Random 3 is determined as the jackpot symbol. In the big hit symbol table, symbol numbers in the left and right corresponding to each of a combination of a plurality of kinds of big hit symbols are set. Further, the random number for determining the variation pattern (random 4) is extracted, and the variation pattern of the special symbol is determined based on the value of the random 4 (step S56).

If it is determined that the data is out of alignment, the CPU 56
Decides the stop symbol when it is not a big hit. In this embodiment, the left symbol is determined according to the value read out in step S52, that is, the value of the extracted random 2-1 (step S57). Also, random 2-2
The middle symbol is determined according to the value of (step S58). Then, the right symbol is determined according to the value of Random 2-3 (step S59). Here, when the determined middle symbol matches the left and right symbols, the symbol corresponding to the value obtained by adding 1 to the value of the random number corresponding to the middle symbol is set as the middle symbol stop symbol so that it does not match the big hit symbol. To do.

Further, the CPU 56 confirms whether or not it has been decided to reach (whether or not the left and right stop symbols are aligned) (step S60), and if it is decided to reach, it changes. The value of the random number for pattern determination (random 4) is extracted, and the variation pattern of the symbol is determined based on random 4 (step S61).

If it is not decided to reach, it is confirmed whether or not it is in the probability variation state (step S62). If it is the probability variation state, it is determined that the variation pattern is the out-of-time shortened variation pattern (step S63). If it is not the probability variation state, the variation pattern is determined to be the normal variation pattern at the time of deviation (step S64). The shortening variation pattern at the time of deviation is a variation pattern in which the variation period of the symbols in the left and right is, for example, 4.0 seconds, which is shorter than the normal variation pattern.

As described above, it is determined whether the variation mode of the symbols based on the starting winning is the reach mode or the outlier mode, and the combination of the respective stop symbols is determined. That is, as a variation mode of the special symbol, whether the reach effect is performed or not is determined and the combination of the stopped symbols is determined.

The processing shown in FIG. 24 is step S30 in the special symbol process processing shown in FIG.
This corresponds to the process when the processes of 1 to S303 are collectively shown. Further, in this embodiment, a big hit occurs when the stop symbols of the left and right middle symbols are aligned. Reach is reached when only the left and right symbols are available.

Next, the command transmitted from the game control means to each electric component control board will be described. FIG. 27 shows
From the main board 31, the lamp control board 35, the payout control board 3
FIG. 7 is an explanatory diagram showing an example of command forms of control commands (lamp control command, sound control command, display control command, and payout control command) transmitted to the sound control board 70 and the pattern control board 80. In this embodiment, the command data of the control command has a 2-byte structure, the first byte represents MODE (command type),
The second byte represents EXT (specific instruction content). MOD
The first bit (bit 7) of E data is always "1", and the first bit (bit 7) of EXT data is always "0". Thus, the lamp control board 35, the payout control board 37, the sound control board 70, and the symbol control board 8
The control command transmitted to 0 is composed of a plurality of command data, and can be distinguished by the leading bit. Note that the command form shown in FIG. 27 is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used.

As shown in FIG. 28, the control command is 8
It is composed of bit control signals CD0 to CD7 (command data) and an INT signal (acquisition signal). The lamp control board 35, the payout control board 37, the sound control board 70, and the lamp control means, the payout control means, the sound control means, and the display control means mounted on the pattern control board 80 detect that the INT signal has risen. Then, the interrupt process starts the process of fetching 1-byte data.

FIG. 29 is an explanatory diagram showing an example of the contents of the display control command sent to the symbol control board 80. The display control command has a 2-byte structure of MODE and EXT. In the example shown in FIG. 21, the command 8000 (H)
8031 (H) is a display control command for designating a variation pattern of the special symbol. The command for designating the variation pattern (variation pattern designation command) also serves as a variation start instruction.

The command 88XX (H) (X = arbitrary value of 4 bits) is a display control command relating to a variation pattern of a normal symbol. The command 89XX (H) is a display control command for designating a stop symbol of a normal symbol. The command 8AXX (H) (X = an arbitrary value of 4 bits) is a display control command for instructing to stop the variable display of the normal symbols.

Commands 91XX (H), 92XX (H)
And 93XX (H) is a display control command for designating the left middle right stop symbol of the special symbol. Also, command A
0XX (H) is a display control command for instructing to stop the variable display of the special symbol. The command BXXX (H) is
It is a display control command sent from the start of the big hit game to the end of the big hit game.

The command C000 (H) is a display control command relating to a variation of the special symbol and a display state not related to the big hit game.

When the display control means of the symbol control board 80 receives the above-mentioned display control command from the game control means of the main board 31, the display of the display area 150 in the variable display device 9 according to the contents shown in FIG. Control to change the state.

FIG. 30 is an explanatory diagram showing an example of the contents of the lamp control command sent from the main board 31 to the lamp control board 35. Lamp control commands are also MODE and EX
It is a 2-byte structure of T. In the example shown in FIG. 30, commands 8000 (H) to 8031 (H) are lamp controls that specify the control pattern of the lamp / LED (each light emitting element provided in the gaming machine) corresponding to the variation pattern of the special symbol. It is a command. Also, the command A0XX (H)
(X = arbitrary value of 4 bits) is a lamp control command for instructing the control pattern of the lamp / LED when the variable display of the special symbol is stopped. The command BXXX (H) is a ramp / L from the start of the big hit game to the end of the big hit game.
It is a lamp control command for instructing the control pattern of the ED. The command C000 is a lamp control command for instructing the lamp / LED control pattern during the customer waiting demonstration.

Incidentally, the command 8XXX (H), AXXX
(H), BXXX (H) and CXXX (H) are lamp control commands sent from the game control means in accordance with the game progress situation, that is, lamp control commands for informing the gaming state. When the lamp control means receives the above-mentioned lamp control command from the game control means of the main board 31, the lamp / L according to the contents shown in FIG. 30.
Change the ED display status (lit, extinguished, and blinking).

In this embodiment, the lamp control means is
When a lamp control command instructing to notify the gaming state is received, a part or all of the decoration lamp 25, the top frame lamp 28a, and the left and right frame lamps 28b and 28c are used to light to notify the gaming state. / Turn off the light. The decorative lamp 25, the ceiling frame lamp 28a, and the left and right frame lamps 28b and 28c may each be composed of a group of a plurality of luminous bodies. In that case, the decorative lamp 25, the ceiling frame lamp 28a, and the left and right frame lamps. 28
Notifying the gaming state by using a part of b and 28c also means that, for example, a part of a plurality of light emitting bodies forming the decoration lamp 25 may be used.

The command E0XX (H) is a lamp control command indicating the number of starting memories (the number of special symbol starting memories). The lamp control means displays information on the special symbol starting memory number on the starting memory indicator 18 so that the player can recognize the number designated by "XX (H)". Further, the command E1XX (H) is a lamp control command which normally indicates the number of symbols starting memory. The lamp control means is "XX
Information about the normal symbol starting memory number is displayed on the normal symbol starting memory indicator 41 so that the player can recognize the number designated by "(H)".

Commands E200 (H) and E201
(H) is a lamp control command relating to the display state of the prize ball lamp 51, and includes commands E300 (H) and E3.
01 (H) is a lamp control command related to the display state of the out-of-bulb lamp 52. The lamp control means is the main board 3
When the lamp control command of "E201 (H)" is received from the game control means of No. 1, the display state of the prize ball lamp 51 is changed to a predetermined display state when there is a prize ball remaining, and the lamp of "E200 (H)" is displayed. When the control command is received, the display state of the prize ball lamp 51 is changed to a predetermined display state as when there is no prize ball remaining.

Also, from the game control means of the main board 31, "E
When the lamp control command of "300 (H)" is received, the display state of the out-of-bulb lamp 52 is changed to the display state with a sphere,
When the lamp control command of "E301 (H)" is received, the display state of the out-of-bulb lamp 52 is changed to the display state of out-of-bulb. That is, the commands E200 (H) and E201
(H) is a command indicating that a light emitting body provided to notify a player or the like that there is a non-prize game ball, and commands E300 (H) and E30.
1 (H) is a command indicating that the light emitter provided to notify the player or the game store staff that the supply ball has run out is controlled.

The command "E500 (H)" is a lamp control command for designating an injustice notification lamp, which is transmitted from the game control means when the game control means detects an illegal act. When the lamp control means receives the lamp control command for designating the fraud notification lamp, the lamp control means controls the lighting of the lamp / LED in a predetermined manner as the fraud notification mode.
For example, all the lamps / LEDs are blinked in a predetermined cycle. Alternatively, a light emitting means for notifying of fraud may be provided in particular, and the light emitting means may be turned on.

FIG. 31 is an explanatory diagram showing an example of the contents of the sound control command sent to the sound control board 70. The sound control command also has a 2-byte structure of MODE and EXT. In the example shown in FIG. 31, the command 8XXX (H) (X =
4-bit arbitrary value) is a sound control command that specifies a sound generation pattern in the variable period of the special symbol. The commands 8000 (H) to 8031 (H) are sound control commands that specify a sound generation pattern corresponding to the variation pattern of the special symbol. Command BXXX (H) (X
= Arbitrary value of 4 bits) is a sound control command that specifies a sound generation pattern from the start of the big hit game to the end of the big hit game. Other commands are sound control commands that are not related to special symbol variations and jackpot games. When the sound control means of the sound control board 70 receives the above-mentioned sound control command from the game control means of the main board 31, FIG.
The sound output state is changed according to the contents shown in 3.

The command "E500 (H)" is a sound control command for designating an injustice notification sound, which is transmitted from the game control means when the game control means detects an illegal act. When the sound control means receives the sound control command specifying the injustice notification sound, the sound control means controls the sound output from the speaker 27 in a predetermined mode as the injustice notification mode.

When trying to output a control command from the game control means of the main board 31 to each sub board (lamp control board 35, payout control board 37, sound control board 70, symbol control board 80), the command transmission table Settings are made. Alternatively, the command transmission table formed in the ROM 54 is addressed. FIG. 32 is an explanatory diagram showing a configuration example of the command transmission table. One command transmission table is composed of 3 bytes, and INT data described later is set in the 1st byte. Also, 2
MODE data of the first byte of the control command is set in the command data 1 of the byte. Then, in the command data 2 of the third byte, the EXT data of the second byte of the control command is set.

The EXT data itself may be set in the command data 2 area, but the command data 2
Is a table (ROM that stores EXT data).
54. Data for specifying the address of () (buffer specifying data) may be set. In this embodiment, as shown in FIG.
If bit 7 (work area reference bit) of the command data 2 is 0, it indicates that the EXT data itself is set in the command data 2. Note that such EXT data is data in which bit 7 is 0. Further, as shown in FIG. 33B, when the work area reference bit is 1, it indicates that the other 7 bits are offsets for designating the address of the table in which the EXT data is stored. In the example shown in FIG. 33B, since bits 4 to 0 are used, 32 types of buffers can be designated. Also, 32
Types of buffers include, for example, a special symbol variation pattern buffer, a special symbol left symbol buffer, a special symbol middle symbol buffer, a special symbol right symbol buffer, and the like.

FIG. 34 is an explanatory diagram showing a structural example of INT data. Bit 0 in the INT data indicates whether or not the payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that the payout control command should be sent. Therefore, the CPU 56 sets "01 (H)" to the INT data in the prize ball process (step S32 of the game control process), for example.

Bit 1 in the INT data is
It shows whether or not a display control command should be sent to the symbol control board 80. If bit 1 is "1", it indicates that the display control command should be sent. Therefore, the CPU 56
For example, in the special symbol process process or the normal symbol process process (steps S26 and S27 of the game control process), "02 (H)" is set to the INT data.

Bits 2 and 3 of the INT data are bits indicating whether or not to send a lamp control command and a sound control command, respectively, and the CPU 56 outputs a special command at the timing to send these commands. In the symbol process processing, etc., in the command transmission table pointed by the pointer (for example, special symbol command transmission pointer),
INT data, command data 1 and command data 2 are set. When sending those commands,
The corresponding bit of INT data is set to "1", and MODE data and EXT data are set to command data 1 and command data 2.

In this embodiment, a plurality of command transmission tables are prepared for each control command, and the command transmission table to be used is set before command transmission. Alternatively, the command transmission table formed in the ROM 54 is addressed. Also, a plurality of command transmission tables may be set in one table. For example, as shown in FIG. 35, one table including a plurality of command transmission tables capable of storing a plurality of display control commands is prepared.
In the command control processing, the CPU 56 selects INT from the command transmission table pointed by the pointer.
The data, the command data 1 and the command data 2 are read and the display control command is transmitted. Then, the pointer is updated. After that, the display control command transmission process is repeated until the command transmission table designated by the pointer indicates the end code. A part of the table prepared for each control command (for example, the payout control board 37
Table for setting the payout amount specification command for
May be configured in a ring buffer format.

FIG. 36 is a flow chart showing a processing example of command control processing in the game control processing shown in FIG. Command control processing includes command output processing and INT
This is processing including signal output processing. In the command control processing, the CPU 56 first saves the address of the command transmission table to the stack or the like (step S33).
1). Then, the INT data of the command transmission table pointed to by the pointer is loaded into the argument 1 (step S
332). The argument 1 is input information for the command transmission process described later. Further, the address indicating the command transmission table is incremented by 1 (step S333). Therefore, the address indicating the command transmission table matches the address of the command data 1. The display control command is set in the command transmission table shown in FIG. 32, for example.

Next, the CPU 56 sends the command data 1
Is read out and is set to the argument 2 (step S334).
The argument 2 is also input information for the command transmission process described later. Then, the command transmission processing routine is called (step S335).

FIG. 37 is a flow chart showing the command transmission processing routine. In the command transmission processing routine, the CPU 56 first sets the data set in the argument 1, that is, the INT data, in the work area determined as the comparison value (step S351).
Next, the number of transmissions = 4 is set in the work area determined as the number of processes (step S352). Then, the address of port 1 is set to the IO address (step S353). In this embodiment, port 1
Is the address of the output port for outputting the payout control command data, and the addresses of ports 2 to 4 are the addresses of the output ports for outputting the display control command data, the lamp control command data, and the sound control command data. Suppose

Next, the CPU 56 shifts the comparison value right by 1 bit (step S354). As a result of the shift processing, it is confirmed whether the carry bit has become 1 (step S355). The carry bit has become 1, which means that the rightmost bit in the INT data is "1".
It means that it was. In this embodiment, the shift process is performed four times. For example, when it is specified that the display control command should be sent, the carry bit becomes 1 in the second shift process.

When the carry bit becomes 1, the data set in the argument 2, in this case, the command data 1 (that is, MODE data) is output to the address set as the IO address (step S3
56). Since the address of the port 2 is set as the IO address when the second shift processing is performed, the MODE data of the display control command is output to the port 2 at that time.

Next, the CPU 56 sets the IO address to 1
While adding (step S357), 1 is subtracted from the processing number (step S358). When the port 2 is shown before the addition, the address of the port 3 is set to the IO address by the addition processing for the IO address. Port 3 is a port for outputting a lamp control command. Then, the CPU 56 confirms the value of the processing number (step S359), and if the value is not 0, returns to step S354. The shift process is performed again in step S354.

In the second shift processing, the value of bit 1 in the INT data is pushed out and the carry flag becomes "1" or "0" depending on the value of bit 1. Therefore,
A check is made to see if it is specified that a display control command should be sent. Similarly, by the third and fourth shift processes, it is checked whether or not the lamp control command and the sound control command should be sent. In this way, when each shift process is performed, the command (payout control command,
An IO address corresponding to a display control command, a lamp control command, a sound control command) is set.

Therefore, when the carry flag becomes "1", the corresponding output port (port 1 to port 4)
A control command is sent to. That is, one common module can perform a control command transmission process to the control means of each sub-board.

In addition, since the control command of each sub-board to which the control command should be output is determined only by the shift processing in this manner, it is determined to which control means the control command should be output. Processing has been simplified.

Next, the CPU 56 reads the content of the argument 1 in which the INT data before the shift processing is started (step S360), and outputs the read data to the port 0 (step S361). In this embodiment,
The address of port 0 is a port for outputting the INT signal for each control signal, and bit 0 of port 0
4 to 4 are the payout control INT signal and the display control IN, respectively.
It is a port for outputting a T signal, a lamp control INT signal, and a sound control INT signal. In the INT data, the bit corresponding to the output bit of the INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output in the processing of steps S351 to S359 becomes “1”. Has become. Therefore,
The INT signal corresponding to the control command (payout control command, display control command, lamp control command, sound control command) output to any of the ports 1 to 4 is turned off (low level).

Next, the CPU 56 sets a predetermined value in the wait counter (step S362), and decrements by 1 until the value becomes 0 (steps S363, S36).
4). When the value of the wait counter becomes 0, clear data (00) is set (step S365) and the data is output to port 0 (step S366). Therefore, the INT signal is turned off. Then, a predetermined value is set in the wait counter (step S362), and 1 is subtracted until the value becomes 0 (steps S368, S).
369).

As described above, the 1st byte MODE data of the control command is transmitted. Therefore, CPU5
In step S336 shown in FIG. 36, 6 adds 1 to the value indicating the command transmission table. Therefore, the area of the command data 2 in the third byte is designated. The CPU 56
The contents of the indicated command data 2 are loaded into the argument 2 (step S337). Further, it is confirmed whether or not the value of bit 7 (work area reference bit) of the command data 2 is "0" (step S339). If not 0, the head address of the command extension data address table is set in the pointer (step S339), and the value of bits 6 to 0 of the command data 2 is added to the pointer to calculate the address (step S340). Then, the data of the area pointed to by the address is loaded into the argument 2 (step S341).

In the command extension data address table, EXT data which can be sent to the control means of each sub-board is sequentially set. Therefore, by the above processing,
If the value of the work area reference bit is "1", the EXT data in the command extension data address table corresponding to the content of the command data 2 is loaded into the argument 2 and the value of the work area reference bit is "0". For example, the content of the command data 2 is loaded into the argument 2 as it is. In addition,
Even when the EXT data is read from the command extension data address table, bit 7 of the data is "0".

Next, the CPU 56 calls the command transmission processing routine (step S342). Therefore, M
EXT at the same timing as when transmitting ODE data
Data is sent out. After that, the CPU 56 restores the address of the command transmission table (step S34
3) Update the value of the read pointer that points to the command transmission table (step S344). Then, if there is a command to be transmitted (step S345), the process returns to step S331.

As described above, the 2-byte control command (payout control command, display control command, lamp control command, sound control command) is transmitted to the control means of the corresponding sub-board. When the control means of each sub-board detects the level change of the INT signal, it starts the processing for fetching the control command, but for each control means, a new signal from the game control means is received before the fetching processing is completed. It is not output to the signal line. That is, reliable command reception processing is performed in each control unit such as the display control unit. The polarity of the INT signal may be reversed from that shown in FIG.

38 to 40 are flow charts showing an example of a non-maskable interrupt process (power supply stop process) executed in response to a power-off signal from the power supply board 910. When the XNMI terminal of the CPU 56 changes from high level to low level and a non-maskable interrupt occurs, C
The interrupt control mechanism incorporated in the PU 56 saves the address of the program being executed at the time of occurrence of the non-maskable interrupt (specifically, the next address after the completion of execution) in the stack area pointed to by the stack pointer. , Increase the stack pointer value. That is, the value of the stack pointer is updated to point to the next address in the stack area. In this embodiment, when the XNMI terminal changes from the high level to the low level, an interrupt occurs. However, even if a microcomputer that generates an interrupt in response to a level change of another mode is used, Such control can be executed.

In the power supply stop processing, the CPU 56
Saves the AF register (accumulator and flag register) in the stack area of the backup RAM area (step S451). Also, the interrupt flag is copied to the parity flag (step S452). The parity flag is formed in the backup RAM area. The interrupt flag is a flag indicating whether the interrupt is enabled or disabled, and is in the control register built in the CPU 56. The ON state of the interrupt flag indicates that the interrupt is disabled. As described above, the parity flag is referred to in the game state recovery process. Then, in the game state recovery process, if the parity flag is in the on state, it is not set to the interrupt permission state.

Further, BC register, DE register, HL
The registers, IX register, and stack pointer are saved in the stack area of the backup RAM area (steps S454 to S458). Note that steps S451-
The process of S458 corresponds to the data saving process for saving the data necessary for restoring the control state in the variable data storage unit according to the detection signal of the power supply monitoring unit.

Next, in this embodiment, the prize ball count switch 301A for a predetermined period (during the input monitoring time).
Check the detection signal of. When the prize ball count switch 301A is turned on, the content of the total prize ball count buffer is set to 1
cut back. The total prize ball number buffer is an area for storing the number of unpaid prize balls in the RAM 55, and is added when a payout control command indicating the number of prize balls is transmitted to the payout control board 37 in response to winning, and the prize ball count is calculated. Switch 301A
The data to be subtracted based on the detection signal of is set.

In this embodiment, an input monitoring time measuring counter is used to measure the input monitoring time. The value of the input monitoring time measuring counter is the initial value m
From the loop of the switch detection processing described below (S4
The loop starting from 61 and returning to S461 is decremented by 1 every time it is executed, and when the value becomes 0, it is assumed that the input monitoring time has ended. Although there is an exception in the detection processing loop, almost constant processing is performed, and therefore a time that is m times the time required for one round of the loop is approximately equivalent to the input monitoring time.

To measure the input monitoring time, the CPU 5
A built-in timer of 6 may be used. That is, a predetermined value (corresponding to the input monitoring time) is set in the built-in timer at the start of the switch detection process. Then, the count value of the built-in timer is checked every time the loop of the switch detection processing is executed once. Then, when the count value becomes 0, it is assumed that the input monitoring time has ended. An interrupt by the built-in timer can be used to detect that the value of the built-in timer has become 0. It is preferable to use a program configuration in which the count value of the built-in timer is read out and checked without using the program.

The input monitoring time is set to be longer than the time from when the game ball falls from the ball payout device 97 to when it reaches the prize ball count switch 301A. When the distance from the ball payout device 97 to the prize ball count switch 301A is L, the fall time t during that time is t = √ (2L
/ G) (g: gravitational acceleration), the input monitoring time is set longer than that. When the ball payout device 97 illustrated in FIG. 5 is used, L is the sprocket 29.
It corresponds to the distance from the position where the game ball drops from the concave portion 2 to the position of the prize ball count switch 301A. As described above, the input monitoring time is set to a time equal to or longer than the time from when the game medium is paid out from the payout means to when it is detected by the payout detection means.

At least during the input monitoring time during which the switch detection process is executed, the prize ball count switch 301A must be in a state where it can detect a game ball. Therefore,
As shown in FIG. 13, the input side of the converter IC 922 on the power supply board 910 is connected to a capacitor 923 as an auxiliary drive power supply having a relatively large capacity. Therefore, even when the power supply to the gaming machine is stopped, the + 12V power supply voltage is maintained within the switchable range for a certain period of time, and the prize ball count switch 301A becomes operable. The capacitance of the capacitor is determined so that the period is equal to or longer than the time until the input monitoring process is completed.

Since the input port and the CPU 56 are also driven by the + 5V power source created by the converter IC 922, they can be operated for a relatively long period even when the power supply is stopped.

In step S461, the initial value n corresponding to the time of 2 ms is set in the 2 ms measurement counter. Then, until the value of the 2 ms measurement counter becomes 0 (step S462), the value of the 2 ms measurement counter becomes −.
1 (step S463).

When the value of the 2 ms measurement counter becomes 0,
The input check of the detection signal of the prize ball count switch 301A is performed. Specifically, the data input to the input port 1 is input (step S464). Then
Set clear data (00) (step S46)
5). Further, the port input data, in this case, the input data from the input port 1 is set as the "comparison value" (step S466). Furthermore, prize ball count switch 30
The address of the switch timer for 1A is set in the pointer (step S467).

Then, the switch timer pointed by the pointer (the address of the switch timer is set) is loaded (step S468), and the comparison value is shifted to the right (direction from the higher bit to the lower bit) (step S469). ). The data of the input port 1 is set as the comparison value. Then, in this case, the detection signal of the prize ball count switch 301A is pushed out to the carry flag.

If the value of the carry flag is "1" (step S470), that is, the prize ball count switch 30.
If the 1A detection signal is in the ON state, the value of the switch timer is incremented by 1 (step S471). If the value of the carry flag is "0", that is, if the detection signal of the prize ball count switch 301A is in the off state, clear data is set in the switch timer (step S472).
That is, if the switch is in the off state, the value of the switch timer returns to 0.

When the value of the switch timer becomes 2 (step S473), the value stored in the total prize ball storage buffer is decremented by 1 (step S474), and the value of the prize ball information counter is incremented by 1 (step S474). Step S475).
When the value of the prize ball information counter is 10 or more (step S476), the value of the prize ball information output counter is incremented by 1 (step S477), and the value of the prize ball information counter is decremented by 10 (step S478).

Next, the value of the input monitoring time measuring counter is decremented by 1 (step S479), and if the value is not 0, the process returns to step S461.

With the above processing, when the prize ball count switch 301A is turned on within the input monitoring time, the value of the total prize ball number storage buffer is decremented by one. Since the process for saving the contents of the backup RAM is performed after such a switch detection process,
The total prize ball number storage buffer is always decremented by one. Therefore, regarding the payout of the game balls, it is possible to prevent the stored control state from being inconsistent. Further, in the above switch detection processing, timer processing using a detection period counter is performed. That is, the detection output of the prize ball count switch 301A is checked every 2 ms, and when the ON detection is performed twice in succession, it is considered that the prize ball count switch 301A is surely turned on. Therefore, erroneous switch-on detection can be prevented. Further, in the switch detection process, since the prize ball information output frequency counter for outputting the prize ball information to the outside of the gaming machine is also calculated, the prize ball information output to the outside and the actual number of payout prize balls are inconsistent. It doesn't happen.

Here, in the power supply stop process, the input monitoring process is executed only for the input monitoring time (a predetermined time from the time of dropping from the ball payout device 97 to the time of reaching the prize ball counting switch 301A). ,further,
The input monitoring process may be executed for a long time. For example, the input monitoring process may be continued until the power supply is completely stopped.

The payout control means mounted on the payout control board 37 also executes the power supply stop time process in response to the power-off signal. Then, the driving of the payout motor 289 is stopped at an early stage in the power supply stop process (at least before the input monitoring process is started in the power supply stop process in the game control means).

Further, in the present embodiment, the switch detection processing is performed only for the prize ball count switch 301A, but the same applies to the switch for the starting winning opening and the V winning switch 22 and the count switch related to the special winning opening. Switch detection processing may be performed. Further, similar switch detection processing may be performed for other prizes. When such an on-check is also performed, even if a power failure occurs immediately after the game ball has won the winning opening, the winning is surely detected and reflected in the saved game state.

When the input monitoring time elapses (step S4
80), that is, when the value of the input monitoring time measuring counter becomes 0, the designated value with backup (in this example, "5
5 (H) ”) is stored in the backup flag (step S481). Backup flag is backup R
It is formed in the AM region. Next, the parity data is created (steps S482 to S491). That is,
First, the clear data (00) is set in the checksum data area (step S482), and the checksum calculation start address is set in the pointer (step S48).
3). Further, the number of checksum calculations is set (step S484).

Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S485). The calculation result is stored in the checksum data area (step S48).
6), increment the pointer value by 1 (step S487),
The value of the checksum calculation count is subtracted by 1 (step S4
88). The processes of steps S485 to S488 are repeated until the value of the checksum calculation count becomes 0 (step S489).

When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S490). Then, the inverted data is stored in the checksum data area (step S491). This data becomes the parity data that is checked when the power is turned on. Then R
An access prohibition value is set in the AM access register (step S492). After that, the built-in RAM 55 cannot be accessed.

Further, the CPU 56 clears the clear data (0
0) is set in an appropriate register (step S49
3), the number of processes (“7” in this example) is set in another register (step S494). Further, the address of the output port 0 is set in the IO pointer (step S49).
5). Another register is used as the IO pointer.

Then, the clear data is set to the address pointed to by the IO pointer (step S49).
6), the value of the IO pointer is incremented by 1 (step S49
7), 1 is subtracted from the value of the number of processes (step S498).
In the processes of steps S496 to S498, the value of the number of processes is 0.
Is repeated until. As a result, clear data is set to all output ports 0 to 6 (see FIGS. 15 and 16). As shown in FIGS. 15 and 16, in this example, “1” is in the ON state and the clear data “0”.
Since "0" is set to each output port, all output ports are turned off.

Then, the judgment signal from the judgment circuit 950 input to the input port is confirmed, and if the judgment signal is in the ON state (for example, high level) (step S171),
Processing for transmitting an injustice notification command (lamp control command, sound control command, or both) is performed (step S172).

Since the RAM access prohibition state is set at this stage, the CPU 56 executes the processing for transmitting the lamp control command and the sound control command.
For example, predetermined data (1 byte of 2 bytes of command data forming a lamp control command or a sound control command) is set in the register, and the value of the register is directly output to the output port. Further, in order to create the ON period of the INT signal (see FIG. 28), the period is created by, for example, setting a predetermined value in the register and repeating the subtraction process until it becomes 0. Then, such processing is executed for the MODE data and the EXT data forming the injustice notification command.

After that, the CPU 56 enters a standby state (loop state). Therefore, until the system is reset
It becomes a state where nothing is done.

In this embodiment, a process for saving the game state (in this example, checksum generation and R
After (AM access prevention) is executed, each output port is immediately turned off. In this embodiment, a RAM that stores data used in the game control process
All areas are backed up by power. Therefore, the checksum generation process indicating whether or not the contents are correctly saved, and the RAM access prevention process for preventing the contents from being rewritten correspond to the process for saving the game state.

Since each output port is turned off immediately after the processing for saving the game state is executed, it is possible to surely prevent the occurrence of the situation that does not match the saved game state. When the processing shown in FIG. 38 to FIG. 40 is executed, the power supply to the gaming machine is stopped, so that the voltage applied to the electric components decreases. Then, when the applied voltage falls below the drivable voltage, the driving of the electric component is stopped. Therefore, when the power supply to the gaming machine is stopped, the driving of the electric parts is stopped although there is a short delay.

However, if the clearing process for the output port as in this embodiment is not performed, the variable winning ball device while the game control means is waiting for the power supply to be stopped after the game state is saved. In some cases, the prize will be 15 more. In such a case, when the power supply is restarted, the saved game state is restored, so that the number of memory for winning the winning prize at the time of saving is displayed on the starting memory indicator 18. Then, from the player's point of view, it seems that the reserved memory value of the starting winnings has decreased, and a trouble may occur.
However, in this embodiment, such a trouble is unlikely to occur.

Further, after the game state is saved, there may be a case where a winning is made to the special winning opening as the variable winning ball device. In such a case, there is a possibility that the number of winning prizes recognized by the player and the number of winning prizes displayed on the display unit based on the saved game state at the time of power supply recovery are inconsistent with each other, causing a trouble. However, in this embodiment, such a trouble is unlikely to occur.

Further, in this embodiment, the register saving process is performed at the beginning of the process started in response to the power-off signal. However, if the register is not used in the switch detecting process, the switch detecting process is performed. The register saving process can be performed after the execution, that is, before the process of setting the backup flag and calculating the checksum. In that case, the register saving process, the backup flag setting process, the checksum calculation process, and the output port off setting process can be regarded as the power supply stop process. Further, even when some registers are used in the switch detection process, the register saving process can be performed on the unused registers before the backup flag setting and the checksum calculation process.

The output port clearing process may be performed before the switch detection process is executed (before step S460). During execution of the power supply stop process, the CPU 56
The switches and switches are driven by the charging power of the capacitors. If the output port clearing process is performed before the switch detection process is executed, even if the special winning opening and the variable winning device are configured to be driven by electric parts such as solenoids, they are driven. Therefore, the charging power of the capacitor and the like can be effectively used for the processing when the power supply is stopped.

However, when the V winning switch 22 is detected after the power is cut off, the output port of the solenoid 21 (which operates the member for guiding the special winning opening to the V winning switch) Is cleared after the switch detection process is executed. By doing so, when a power outage occurs in a state where the V winning that is the condition of continuation right is not generated, guide the game ball that entered the special winning opening just before the power outage to the V winning switch 22 side. You can Therefore, it is possible to prevent the unjustified extinction of the continuation right. In this case, the period during which the power source is held is a period of time or longer until the gaming ball that has won the special winning opening reaches the V winning switch 22. When a latch type solenoid is used, it is not necessary to clear the output port.

Further, even when the special winning opening is closed by clearing the output port, it is possible that there is a game ball in the special winning opening. Therefore, in the switch detection processing executed in response to the power-off signal, the count switch 23 It is desirable to detect The clearing process of the output port may be performed before the switch detection process, and the exceptional process described above is not limited to the first type pachinko gaming machine, but also the second type pachinko gaming machine and the third type pachinko gaming machine. The same applies to the seed pachinko game machine.

In this embodiment, the power supply stoppage process is executed according to the NMI, but the power-off signal is changed to C
You may connect to the maskable terminal of PU56 and may perform a power supply stop process by a maskable interrupt process. Alternatively, a power-off signal may be input to the input port, and the power supply stoppage process may be executed according to the check result of the input port.

FIG. 41 shows a RAM according to this embodiment.
It is explanatory drawing which shows the address map of an area | region. As shown in FIG. 41, the head of the RAM area is assigned to the backup flag area. Then, the area of the checksum buffer is allocated at the end. The area from the backup flag to the checksum buffer corresponds to the work area, and the stack area is set in the area after the checksum buffer. In addition, in this embodiment, the entire RAM area is backed up by power supply.

FIG. 42 is an explanatory diagram for explaining an example of the checksum creating method. However, in the example shown in FIG. 42, the size of the data in the backup RAM area is 3 bytes for simplicity. In the process at the time of stopping the power supply based on the power supply voltage drop, as shown in FIG. 42, as the checksum data, the initial data (00 in this example)
(H)) is set. Next, "00 (H)" and "F0
(H) "is exclusive ORed and the result and" 16 "
(H) "is exclusive-ORed. Furthermore, the exclusive OR of the result and "DF (H)" is taken. And
A value (“C6 (H)” in this example) obtained by logically inverting the result (“39 (H)” in this example) is set in the checksum buffer.

For ease of explanation, FIG. 42 shows that the data "39 (H)" before logical inversion is stored in the checksum buffer. In addition,
00 (H) as the initial data is a value corresponding to the clear data with respect to the checksum data set in step S460, but in reality, the exclusive OR with 00 (H) is obtained before and after the operation. Since the value does not change, the exclusive OR operation with 00 (H) does not have to be performed.

In this embodiment, the checksum buffer is a backup RAM area (variable data storage means).
It is stored at the last address of. So, for example,
When confirming whether or not there is an error in the program of the checksum creation method, the confirmation can be easily performed.
This is because it is sufficient to confirm whether the value of the final address in the RAM area is correct. Further, in this embodiment, the checksum calculation start address is the address to which the backup flag is set, and the checksum calculation end address is the last address in the prize ball control flag buffer (see FIG. 41). . Therefore, after the prize ball control flag buffer, that is, if the last address of the backup RAM area is set to the checksum buffer area, RA
No waste occurs in the M area.

In consideration of ease of confirmation and prevention of waste of the RAM area, the first address of the backup RAM area may be the checksum buffer area.

Further, at the start of power supply to the gaming machine, it is judged whether or not the parity check is OK (step S9 in FIG. 18). In that judgment, the parity data creation process in the power supply stop process (step) is carried out. S4
82 to S491), and if the processing result, that is, the operation result matches the contents of the checksum buffer, it is determined that the parity check is OK.

Although the last or first address of the backup RAM area is used as the checksum buffer area here, the checksum buffer area may be assigned to the middle area of the backup RAM area. Further, in this embodiment, the checksum is generated based on the data in the work area, but the checksum may be generated also including the data in the stack area.

Further, in this embodiment, at the start of power supply, a checksum is generated by the same processing as the processing at power supply stop, and the generated checksum and the checksum stored in the backup RAM are combined. Although compared, other methods may be used. For example, by using the checksum stored in the backup RAM as an initial value, each data that is a calculation target in the power supply stop process is calculated, and if the calculation result matches a predetermined value (for example, 00 (H)), the parity It may be determined that the check is OK. The check data for the parity check is not limited to the checksum, and other check data may be used as long as it can determine whether the contents of the backup RAM are properly stored.

FIG. 43 is a timing chart showing the state of the power supply voltage drop and the NMI signal (= power cutoff signal: power supply stop signal) when the power supply to the gaming machine is stopped. When the power supply to the gaming machine is stopped, the voltage value of VSL, which is the highest DC power supply voltage, gradually decreases. Then, in this example, when the voltage drops to + 22V, the power supply cutoff signal is output from the power supply monitoring IC 902 mounted on the power supply board 910 (becomes a low level).

The power-off signal is introduced to the electric component control board (in this embodiment, the main board 31 and the payout control board 37), and the CPU 56 and the payout control CPU 371 have N levels.
It is input to the MI terminal. CPU 56 and payout control C
The PU 371 executes a predetermined power supply stop process by the NMI process.

When the voltage value of VSL further decreases to a predetermined value (+ 9V in this example), the output of the system reset circuit mounted on the main board 31 or the payout control board 37 becomes low level, and the CPU 56 And the payout control CPU 371 enters the system reset state. Note that C
The PU 56 and the payout control CPU 371 have completed the power supply stoppage process before being brought into the system reset state.

When the voltage value of VSL further decreases and falls below the voltage capable of generating Vcc (+ 5V for driving various circuits), each circuit becomes inoperable in each substrate. However, at least on the main board 31 and the payout control board 37, the processing at the time of power supply stop is executed, and
56 and the payout control CPU 371 are in the system reset state.

As described above, in this embodiment, the power supply monitoring circuit monitors the voltage of the power supply VSL, which is the highest DC voltage used in the gaming machine, and the voltage of the power supply falls below the predetermined value. Generates a voltage drop signal (power cut detection signal). As shown in FIG. 43, at the timing when the power-off signal is output, the IC drive voltage is still at a voltage value that can sufficiently drive various circuit elements. Therefore, an operation time is ensured for the CPU 56 of the main board 31 operating with the IC drive voltage to perform a predetermined power supply stoppage process.

Here, the power supply monitoring circuit monitors the voltage of the power supply VSL, which is the highest of the DC voltages used in the gaming machine, but the timing of generating the power-off signal is I
The voltage to be monitored is the highest power supply V at the timing such that the operation time for the electric component control means operating at the C drive voltage to perform the predetermined power supply stop processing is secured.
It does not have to be the voltage of SL. That is, if at least a voltage higher than the IC drive voltage is monitored, the power-off signal can be generated at such a timing that the operation time for the electric component control means to perform the predetermined power supply stoppage process is secured. .

In this case, as described above, it is preferable that the monitored voltage is a voltage that can be expected to prevent erroneous switch-on detection when power supply is stopped. That is, the voltage (switch voltage) supplied to the various switches of the gaming machine is +1
Since it is 2V, it is preferable that the voltage drop can be detected at a stage before the + 12V power supply voltage starts to drop. Therefore, it is preferable to monitor at least a voltage higher than the switch voltage.

FIG. 44 is a block diagram showing a configuration example of the determination circuit 950. In the configuration example shown in FIG. 44, in the determination circuit 950, the NMI signal is input to the input terminal of the timer 951 (the trigger terminal to which the signal for starting the timer is input), and the output of the timer 951 is set in the flip-flop 952. It is input to the terminal. A reset signal is input to the other input (reset terminal) of the flip-flop 952. Then, the output of the flip-flop 952 is input to the input port of the CPU 56 as a determination signal. The flip-flop 952 is, for example, such that the output is turned on when the input signal of the set terminal falls and the output is turned off when a low level is input to the reset terminal.

In the structure shown in FIG. 44, the input terminal of the timer 951 corresponds to the detection signal input section for inputting the detection signal from the power supply monitoring means, and the reset terminal of the flip-flop 952 is from the system reset means. Corresponds to the reset signal input section for inputting the reset signal, and the output terminal can determine whether the signal is output to the reset signal input section within a predetermined period after the signal is input to the detection signal input section. It corresponds to a determination signal output unit that outputs a signal to the game control means (specifically, the CPU 56).

In determination circuit 950, timer 951
Starts timing from the falling timing of the NMI signal. The time out of the timer 951 is set longer than the time until the reset signal is output when the power supply is stopped. The flip-flop 952 is
When the output signal of the timer 951, which is a signal in which the falling edge of the NMI signal is delayed, is input, the determination signal is turned on (high level) as shown in FIG. As shown in (A) of FIG. 45, when the NMI signal is illegally input, the power supply to the gaming machine is not cut off, so the CPU 5
The reset signal applied to 6 does not reach the reset level. Therefore, the CPU 56 determines that the reset signal has not been input within the predetermined time based on the determination signal being in the ON state, and starts the fraudulent notification mode by the sound output from the lamp / LED or the speaker 27 (Fig. 40, steps S171 and S172). On the other hand, FIG.
As shown in (B), when the NMI signal is not improperly input and the power supply is stopped, the flip-flop 952 enters the reset state, and as a result, the reset signal does not turn on without the determination signal turning on. Since it is output, the injustice notification mode is not started.

As described above, in this embodiment, the control means relates to the output of the detection signal from the power supply monitoring means,
It is possible to perform a power supply stoppage process for saving the data necessary for restoring the control state to the fluctuation data storage means, and the system after the signal is input to the detection signal input section for inputting the detection signal from the power supply monitoring means. For notifying by the notifying means provided in the gaming machine based on the judgment of the system reset judging means for judging whether or not the signal is inputted to the reset signal input portion for inputting the reset signal from the reset means Execute the process. Then, the control means, when the system reset determination means determines that the reset signal is not input to the reset signal input portion within a predetermined period after the signal is input to the detection signal input portion, the notification provided on the gaming machine The notification is started using the means.
Further, the system reset determination means outputs a determination signal to the control means, which can determine whether or not the signal is input to the reset signal input portion within a predetermined period after the signal is input to the detection signal input portion. It has a section.

FIG. 46 is a block diagram showing another configuration example of the determination circuit 950. In the configuration example shown in FIG. 46, in the determination circuit 950, the reset signal is input to the timer 951 and the output of the timer 951 is the flip-flop 952.
Input to the reset terminal of. The NMI signal is input to the other input (set terminal) of the flip-flop 952. And the flip-flop 952
Is output to the input port of the CPU 56 as a determination signal.

In the decision circuit 950, when the NMI signal is input to the flip-flop 952, the decision signal is turned on and the decision signal is turned off by the time out of the timer 951, as shown in FIG. The time-out of the timer is set shorter than the time until the reset signal is output when the power supply is stopped. Therefore, while the determination signal is in the on state, step S171
The judgment signal input process of is executed and the injustice notification command is
It is transmitted to the lamp control means or the sound control means as a lamp control command or a sound control command. The lamp control means and the sound control means respond to the lamp
The state of the LED and the state of sound output from the speaker 27 are controlled in an unauthorized notification mode. As shown in (A) of FIG. 47, when the NMI signal is illegally input, the power supply to the gaming machine is not cut off, and therefore the reset signal given to the CPU 56 does not reach the reset level. Therefore, the lamp / LE
The illegitimate notification mode by sound output from D or the speaker 27 continues. As described above, the game control means is the detection signal input section (NMI signal input section) of the system reset determination means.
The notification is started by the notification means provided in the gaming machine on the condition that the signal is input to. Further, when the reset signal is not input to the reset signal input unit of the system reset determination unit within a predetermined period, the notification by the notification unit provided in the gaming machine is continued.

However, in a normal state, the power supply to the gaming machine is cut off after the reset signal reaches the reset level in a very short time after the illegal notification mode by the sound output from the lamp / LED or the speaker 27 is started. Sauce (see Figure 43),
The output state of the lamp / LED or the speaker 27, which is an electric component, is turned off. Therefore, the gaming shop clerk or the like can immediately recognize that the fraudulent activity has been performed on the gaming machine by the continuous appearance of the fraudulent notification mode.

Thus, the control means keeps the notification by the notification means until a signal is input to the reset signal input section. Note that the control means executes the processing for the notification by the notification means based on the determination by the system reset determination means in the power supply stop processing.

FIG. 48 is a block diagram showing another configuration example of the determination circuit 950. In the configuration example shown in FIG. 48, the determination circuit 950 is a 74HC123 which is a general-purpose CMOS-IC.
(Multivibrator) 953. 74
When there is a trigger input (falling of the B input signal) to the B input terminal, the HC 123 has a resistance value of an external resistor (not shown in FIG. 48) and a capacitance of a capacitor (not shown in FIG. 48). Time (t in FIG. 48) determined by
The output (Q output from the Q output terminal) is set to the high level only for the period indicated by 1. If the reset signal to the reset terminal becomes low level before the time has elapsed, the Q output also becomes low level.

In the configuration shown in FIG. 48, 74H
The B input terminal of C123 corresponds to the detection signal input section for inputting the detection signal from the power supply monitoring means, the reset terminal corresponds to the reset signal input section for inputting the reset signal from the system reset means, and Q The output terminal outputs to the game control means (specifically, the CPU 56) a determination signal capable of specifying whether or not the signal is output to the reset signal input section within a predetermined period after the signal is input to the detection signal input section. It corresponds to the determination signal output unit.

The latter half of the non-maskable interrupt process (see FIG. 38).
To the processing of steps S451 to S492 shown in FIG. 40) may be configured as shown in the flowchart of FIG. 50, for example. That is, when the process for saving the game state is executed and then the output port clearing process is executed (steps S493 to S49).
9), the CPU 56 executes loop processing for a predetermined period (step S170). Then, in a normal state (when an NMI signal is generated due to the stop of power supply), step S1
The loop period is set so that the reset signal becomes the reset level while the loop processing of 70 is being performed. With such a configuration, at the normal time, step S1
During the process of 70, the CPU 56 is in the reset state, and then the power supply is stopped.

However, if it is not normal (unauthorized NMI
Signal is input), the reset signal does not reach the reset level before the loop processing is completed, and the step S
The process of 172 is executed. That is, the CPU 56
A process for transmitting an injustice notification command (a lamp control command, a sound control command, or both) is executed. Note that FIG. 49 (A) shows an example of processing timing when an NMI signal is illegally input, and FIG. 49 (B) shows an example of processing timing in a normal state.

Therefore, the determination circuit 950 is, in effect, the system reset means (each circuit for generating the reset signal shown in FIG. 14) within a predetermined period after the NMI signal corresponding to the power-off signal is output. Means for determining whether or not the reset signal from the device is output (specifically, whether or not the reset level has been reached), that is, the signal is input to the reset signal input unit after the signal is input to the detection signal input unit. It constitutes a system reset judging means for judging whether or not there is. That is, if the reset signal is output within the predetermined period indicated by t1 in FIG. 49, the output state of the determination signal is turned off. Then, the game control means causes the lamp control means and the sound control means to make an illegal notification based on the result (judgment signal) of the judgment of the judgment circuit 950. That is, the game control means is provided in the gaming machine when the system reset determination means determines that the reset signal has not been input to the reset signal input portion within a predetermined period after the signal has been input to the detection signal input portion. The processing for performing the notification is performed using the notification means that is present. Therefore, illegally NM
When the I signal is sent to the CPU 56, the fact can be easily recognized from the outside of the gaming machine.

FIG. 51 is a block diagram showing another example of the configuration around the CPU. In the example shown in FIG. 51, the NM from the buffer circuit 900 is different from the configuration example shown in FIG.
The I signal is input only to the regulation circuit 950A, and the CPU 56
A signal is supplied from the restriction circuit 950A to the non-maskable interrupt terminal. FIG. 52 is a block diagram showing a configuration example of the regulation circuit 950A. In the configuration example shown in FIG. 52, the regulation circuit 950A is provided with a cable (not shown) from the power supply board 910 and a connector 950C as an input section of a detection signal from the power supply monitoring means provided on the main board 31. The NMI signal is input.

In the restriction circuit 950A, the NMI signal is first input to the low pass filter 950a. The output of the low-pass filter 950a is input to the flip-flop 950b that sets the output to the low level when the input signal falls. Then, the output of the flip-flop 950b is input to the non-maskable interrupt terminal of the CPU 56. In this example, flip-flop 950b
Corresponds to an interrupt signal output circuit that holds the output state of the interrupt signal at least for a predetermined period after outputting the interrupt signal based on the input detection signal, even if the detection signal is input. .

FIG. 53 is a timing chart showing an example of processing timing. In this example, the non-maskable interrupt process is executed as shown in FIGS. 38 to 40. However, since the determination signal is not used in this example, step S17
1 and S172 are not executed. Then, if normal, as shown in FIG. 53A, after the process for saving the game state and the output port clear process are executed, after the reset signal becomes the reset level, the game machine Is cut off (see FIG. 43).

When an NMI signal is illegally input,
As shown in FIG. 53B, the power supply to the gaming machine is not cut off, so that the reset signal supplied to the CPU 56 does not reach the reset level. However, the flip-flop 950b in the regulation circuit 950A is the NM input first time.
Illegal signals other than the I signal (low level pulse shown in FIG. 53B) are not transmitted to the output. As a result, the CPU 56
Only one falling edge is input to the XNMI terminal of, and interrupts are not generated a plurality of times. Therefore, stack overflow does not occur even if the NMI signal is repeatedly input to the main board 31 from outside the board without authorization. Therefore, the program does not run away and the game control does not start from the initial state. That is, the situation in which the timing that matches the jackpot determination value can be easily grasped does not occur.

Further, by providing the regulation circuit 950A, even when the NMI signal is generated a plurality of times due to instability of the power supply voltage or the like when the normal power supply is stopped, the CPU
56 has only one non-maskable interrupt. Therefore, the processing when the power supply is stopped is surely executed.

Further, since the low-pass filter 950a is provided in the preceding stage of the flip-flop 950b, noise having a predetermined pulse width or less is not transmitted to the flip-flop 950b. That is, the influence of noise is also removed. Although the low-pass filter 950a is used here, another filter circuit such as a three-terminal capacitor or a ferrite bead is used in order to remove a change in the detection signal from the power supply monitoring unit which is equal to or less than the effective period. It can also be used. Here, the term of validity is
If the low level continues for at least that period, the CPU 5
6 is a period during which the non-maskable interrupt is accepted (non-maskable interrupt acceptable period).

As described above, in this embodiment, even if the NMI signal is generated a plurality of times on the main substrate 31, C
The PU 56 is provided with a restriction circuit 950A for preventing the non-maskable interrupt from occurring only once. The restriction circuit 950A outputs a signal indicating that the detection signal is input from the power supply monitoring means to the game control means (specifically, the CPU 56) when the detection signal from the power supply monitoring means is input, Even when the detection signal is input again, the output state of the signal indicating that the detection signal is input is held. That is, the output state of the signal (interrupt signal) applied to the non-maskable interrupt terminal of the CPU 56 is held.

Therefore, even if an illegal board or the like that generates an illegal signal is installed on the cable or the like between the power supply board 910 and the main board 31, the illegal act by the illegal signal can be nullified. In addition to preventing fraudulent activities, it also prevents multiple non-maskable interrupts in situations where NMI signals are generated multiple times due to instability of the power supply voltage during normal power supply interruption. Therefore, the process at the time of stopping the power supply is always executed reliably.

Although regulation circuit 950A shown in FIG. 52 does not output the determination signal, regulation circuit 950B that outputs the determination signal may be provided as shown in FIG. FIG. 54
FIG. 9 is a block diagram showing a configuration of a regulation circuit 950B.
As shown in FIG. 54, the NMI signal is input to the restriction circuit 950B via a cable (not shown) from the power supply board 910 and a connector 950C provided on the main board 31.

In the restriction circuit 950B, the NMI signal is first input to the low pass filter 950a. The output of the low-pass filter 950a is the general-purpose CMO.
74HC123 (multivibrator) which is S-IC
953 is input. When there is a trigger input (B input falling), the 74HC123 has an external resistor (see FIG. 55).
The Q output is set to the high level and the Q output is set to the low level for a time determined by the resistance value of the capacitor (not shown) and the capacitance of the capacitor (not shown in FIG. 55). It should be noted that if the reset signal becomes low level before the time has elapsed, the Q output also becomes low level. Then, the Q output is input to the input port of the CPU 56 as a determination signal, and the Q output is input to the non-maskable interrupt terminal of the CPU 56. Therefore, in this example, after the 74HC123 outputs an interrupt signal based on the input detection signal,
It corresponds to an interrupt signal output circuit that holds the output state of the interrupt signal even when the detection signal is input for at least a predetermined period.

56 and 57 are timing charts showing an example of processing timing. In this example, the non-maskable interrupt process is executed as shown in FIGS. 38 to 40. That is, after the processing for saving the game state and the output port clear processing are executed, the CPU 56 executes the processing for transmitting the injustice notification command (the lamp control command, the sound control command, or both). Then, in the normal time, as shown in FIG. 56, after the illegitimate notification mode by the sound output from the lamp / LED or the speaker 27 is started, the reset signal becomes the reset level in a very short time, that is, After the reset signal is generated, the power supply to the gaming machine is cut off (see FIG. 43),
The output state of the lamp / LED or the speaker 27, which is an electric component, is turned off. When the reset signal is generated, the regulation circuit 950B shown in FIG. 55 also changes the states of the interrupt signal and the determination signal input to the XNMI terminal of the CPU 56.

However, when the NMI signal is illegally input, as shown in FIG. 57, the power supply to the gaming machine is not cut off, so that the reset signal given to the CPU 56 does not become the reset level. Therefore, the injustice notification mode by the sound output from the lamp / LED or the speaker 27 continues.

That is, as shown in FIG. 57, N
If the MI signal is illegally input, 74HC123
Since the (multivibrator) 953 is triggered again (the time determined by the resistance value and the capacitance of the capacitor starts from 0 again), the interrupt signal is input to the CPU 56 only once at the first time. If the NMI signal is continuously input illegally and the non-maskable interrupt process is executed many times, stack overflow may occur and the program may run out of control. At that time, there is a possibility that a lamp control command different from the injustice notification command is sent to the lamp control means, and the lamp control means interrupts the injustice notification. However, as shown in FIG.
If B outputs an interrupt signal only once at the beginning, there is no possibility of stack overflow.

As described above, the restriction circuit 950B outputs the interrupt signal based on the input detection signal, and then outputs the interrupt signal for at least a predetermined period even if the detection signal is input. Hold. That is, the output state of the interrupt signal is continued. Then, even when the detection signal is input again within a predetermined period (the time determined by the resistance value and the capacitance of the capacitor in the above example), the output state of the signal indicating that the detection signal is input (interruption) Signal output status)
Does not change.

It should be noted that during the above-mentioned predetermined period, the input monitoring process of the detection signal of the prize ball count switch 301A in the power supply stop process (steps S460 to S460 in FIG. 39).
The input monitoring time during which S480) is executed is included. Therefore, the output state of the interrupt signal does not change while the input monitoring process is being performed. Further, during a predetermined period, the access prohibition process (see FIG.
The period until step S492) in 0 is executed is included. Therefore, before access prohibition processing is performed,
The output state of the interrupt signal does not change.

Since the input monitoring process of the detection signal of the prize ball count switch 301A is executed in the power supply stop process, the system reset waiting loop process (for example, the loop of step S171) takes a relatively long time. ing. Therefore, there is an increased possibility that the NMI signals that may occur with the voltage drop when the power supply is stopped enter the CPU 56 during the execution of the power supply stop process. Therefore, even if the detection signal is input for at least a predetermined period after the interrupt signal is output based on the detection signal input by the interrupt signal output circuit as in the above-described embodiments, the interrupt signal is input. The configuration for holding the output state of is particularly effective when configured to execute the input monitoring process in the power supply stop process.

In the above embodiment, the power-off signal (NMI signal) is input to the non-maskable interrupt terminal.
It may be input to the maskable interrupt terminal or may be input to the input port. When inputting to the input port, the game control means executes a process corresponding to the non-maskable interrupt process described above if the power-off signal is in the ON state as a result of the port check.

Further, in the above embodiment, the main substrate 3
Although the control in 1 has been described, the payout control board 37
The RAM installed in the CPU also has an area where the power is backed up, and the payout control CPU 371 performs the control state saving process based on the power-off signal. Therefore, the above-described determination unit and the control based on the determination result of the determination unit are applied. can do. In addition to the payout control board 37, if there is another control means for performing the control state saving process based on the power-off signal, the above-mentioned determination means and the control based on the determination result of the determination means are applied to that control means. be able to.

In the above embodiment, the power supply monitoring means is mounted on the power supply board 910, but it may be set on a board other than the main board 31 or at another place in the gaming machine. Further, the system reset means is the main board 31.
However, it may be mounted on another substrate such as the power supply substrate 910.

Further, in the above embodiment, the counter for generating the judgment random number and the initial value determination random number is initialized to 0 in the initialization process (step S11 shown in FIG. 18). The counter value may not be initialized to 0 in the conversion processing. By doing so, the initial value of each counter varies even if the initialization process is executed, so that the effect of the present invention can be reinforced.

For example, a circuit corresponding to the system reset circuit 65 (referred to as a reset circuit) is provided not on the main substrate 31 but on a substrate outside the main substrate 31 such as the power source substrate 910, and the system reset is performed from the reset circuit. In a configuration in which a signal is input to the main board 31, between the boards,
There is a possibility of cheating. For example, there is a possibility that a fraudulent act will be performed by connecting a fraudulent circuit for fraudulently inputting a system reset signal to the main board 31 to the cable between the boards. When the system reset signal is illegally input to the CPU 56 of the main board 31, the control state returns to the initial state as in the case where the power supply to the gaming machine is started. That is, the CPU 56
The main processing shown in FIG. 18 is ready to be executed from the beginning. In this case, since the power supply stop process is not executed, the game state recovery process (step S in FIG. 18)
10) is not executed, and the CPU 56 executes the initialization process.

In the initialization processing, if the count value of the counter for generating the random number for determination is initialized to 0, the random number for random determination (random 1) is generated from the time when the system reset signal is illegally input. Therefore, it becomes easy to predict the timing when the count value of the counter coincides with the jackpot determination value. Then, the cheating person sends a fraudulent signal to the main board 31 such that a start winning occurs at that timing, thereby fraudulently causing a big hit.

However, such an illegal act can be prevented by not initializing the count value of the counter for generating the judgment random number to 0 in the initialization processing. Then, when the power supply is restored and the game state restoration process is performed after the power supply stop process is performed, the CPU 56 in the game state restoration process.
Restarts the counter from the count value stored in the backup RAM.

Alternatively, in the initialization processing, if the count value of the counter for generating the random number for initial value determination is not initialized to 0, the control state may be changed due to the illegal input of the system reset signal. Even after returning to the initial state, the count value of the counter for generating the random number for determination is immediately updated with the count value of the counter for generating the random number for initial value determination. It becomes difficult to predict the timing at which the count value of the counter of (1) matches the jackpot determination value. Then, when the power supply is restored and the game state restoration process is performed after the power supply stop process is performed, in the game state restoration process, the CPU 56 determines from the count value stored in the backup RAM. , Restart the stepping of the counter for generating the random number for determining the initial value.

In addition to the counter for generating the random number for determination and the counter for generating the random number for initial value determination, an infinite counter (which is constantly updated by the timer interrupt process) is provided to perform the initialization process. The count value of the infinite counter may be set to a counter for generating random 1 as an initial value. Even in such a case, it becomes difficult to predict the timing when the count value of the counter for generating the random 1 matches the big hit determination value. Although the infinite counter is composed of, for example, 2 bytes, the value of the lower 8 bits of the infinite counter is set to the counter for generating the random 1 in the initialization process.

Further, the CPU 56 may output to the outside of the gaming machine a signal indicating that the power supply stop time process or the initialization process is being executed. For example, the information output signal is output to a hall computer or the like. When the signal indicating that the power supply stop processing is being performed is output to the hall computer or the like, it becomes possible for the gaming shop to recognize that the power supply stop processing is being performed. Therefore, it is possible to determine that a fraudulent act has been performed when a signal indicating that the power supply stop processing is being executed is output from the gaming machine even though the power supply is not actually stopped. Further, when the signal indicating that the initialization process is being performed is output to the hall computer or the like, it becomes possible for the gaming shop side to recognize that the initialization process is being performed. Therefore, if a signal indicating that the initialization process is in progress is output from the gaming machine even though the power supply is not actually stopped, it can be determined that a fraudulent act has been performed.

In this way, in the case where the gaming machine side can recognize that the gaming machine is in the process of power supply stoppage or in the initialization process, the fraudulent person is It is possible to identify a person who is committing fraud without noticing that he is aware of it.

Further, in the initialization processing, the fact that the initialization processing is being performed may be notified by sound, lamp, or display (for example, display by the variable display device 9). With such a configuration, when the power supply is not actually stopped, the notification is made only in the gaming machine to which the system reset signal is illegally input. Therefore, while fraudulent activity can be easily detected,
Even if the dishonest person notices the notification and immediately leaves the desk, there is an effect that it becomes difficult to execute the dishonest act again. It should be noted that the notification that the initialization process is being performed is performed for a predetermined period (for example, 5
It is preferable to continue for (minutes).

Although the watchdog timer is not used in the above embodiment, the present invention can be applied to the control means using the watchdog timer. That is, the present invention can be applied to the case where the operation of the control means is stopped by the time-out of the watchdog timer. For example, in the case where a circuit that generates a reset signal based on the time-out of the watchdog timer is installed on a board other than the main board 31, even if an illegal board is connected to the wiring of such a reset signal, the illegal act is effective. In order to prevent this, a regulation circuit may be provided so that the reset signal is given only once to the microcomputer even if the reset signal is input a plurality of times.

Further, as shown in FIG. 58, the power supply board 91
When a relay board 930 that relays a signal (including a power supply line) between 0 and the main board 31 is provided, the relay board 930 may be housed in the board box. The lid portion 931 of the board box is fixed to the box body 932 with a one-way screw and another screw (not shown) screwed into one mounting hole in each mounting portion. A one-way screw is a screw that turns only in the screw tightening direction. Therefore, once tightened, the screw cannot be removed.

When the lid 931 is to be removed from the box body 932 to expose the relay board 930, it is necessary to cut the mounting portion of the one-way screw in the mounting portion. Therefore, from the history of cutting the attachment portion, the relay board 93
You can see how many times 0 was exposed. When the actual number of times of cutting is larger than the history (number of times) of cutting of the mounting portion known by the administrator or the like, the lid 931 is illegally removed, the relay board 930 is exposed, and the illegal board is mounted. It turns out that there was a possibility that it was done. Since the mounting portions are provided with three mounting holes, the lid 931 can be removed up to three times.

The relay board 930 may be housed in a transparent clear box. In that case, the relay board 930
Since the state of can be visually recognized from the outside, it is possible to easily find out even if an unauthorized board is mounted.

The pachinko gaming machine 1 of each of the above-described embodiments is mainly a predetermined game when the stop symbol of the special symbol variably displayed on the variable display device 9 based on the start winning is a combination of the predetermined symbols. It was a first-class pachinko game machine that can be given value to the player, but if there is a prize in the predetermined area for the electric auditors to be released based on the starting prize, the predetermined game value can be given to the player. The second kind of pachinko gaming machine and the symbols that are variably displayed based on the starting winnings will be released when the combination of the predetermined symbols is the combination of the predetermined symbols. The present invention can be applied to a third-class pachinko gaming machine that does.

[0318]

As described above, according to the first aspect of the invention, the gaming machine monitors the output voltage of the power supply provided outside the control board and has a predetermined potential, and outputs the detection signal when the detection condition is satisfied. The control means includes a power supply monitoring means and an interrupt signal output circuit which is mounted on the control board and which inputs a detection signal from the power supply monitoring means and outputs a predetermined interrupt signal to the control means based on the detection signal. , It is possible to execute the power supply stop processing that saves the data necessary for the restoration of the control state to the variable data storage means based on the change in the status of the interrupt signal from the interrupt signal output circuit. , After the interrupt signal is output based on the input detection signal, the output state of the interrupt signal is held for at least a predetermined period even if the detection signal is input. Storage means There is an effect that the saving process can be surely executed and the input of such a signal can be regulated even if an illegal act such as illegally sending a signal corresponding to the detection signal from the power supply monitoring means is performed. .

According to the second aspect of the present invention, the control means can execute the input monitoring processing for monitoring the input of the detection signal from the payout detecting means in the power supply stop processing, and the input monitoring processing is performed for a predetermined period. Since it is configured to include the input monitoring time during which the game medium is executed, it becomes possible to detect the game medium paid out until immediately before the stop of the power supply, and the game medium is saved with respect to the payout of the game medium. Inconsistency in the control state is prevented.

In the invention according to claim 3, since the input monitoring time is set to a time longer than the time from when the game medium is paid out from the payout means to when it is detected by the payout detection means, the power supply is stopped. It is possible to reliably detect the game medium paid out until just before.

According to the fourth aspect of the invention, since the predetermined period includes the period from the start of the power supply stop process to the access prohibition process, before the access prohibition process of the variable data storage means is executed. Therefore, the process at the time of stopping the power supply is not started again, and the contents of the variable data storage means can be surely protected at the time of stopping the power supply.

According to a fifth aspect of the present invention, a filter circuit is provided between the input portion of the detection signal from the power supply monitoring means in the control board and the interrupt signal output circuit to remove a change in the detection signal within the effective period. Is provided, it is possible to prevent an incorrect interrupt signal from being output due to noise.

According to the sixth aspect of the present invention, the power supply board for producing the power supply used in the gaming machine is provided, and the power supply monitoring means is mounted on the power supply board. Therefore, the power supply is monitored on the upstream side of the power supply path. It can be performed.

According to the invention described in claim 7, since the system reset circuit for outputting the reset signal for stopping the operation of the control means is provided, when the power supply is stopped,
After the power supply stop processing is executed, the control means is surely brought into the operation stop state.

According to the eighth aspect of the invention, since the interrupt signal output circuit is configured to change the interrupt signal based on the reset signal from the system reset circuit, the unnecessary signal output state is released. be able to.

According to the ninth aspect of the present invention, the control means is configured to use the non-maskable interrupt terminal as an input terminal for inputting the interrupt signal from the interrupt signal output circuit. The high processing can surely execute the power supply stop processing.

[Brief description of drawings]

FIG. 1 is a front view of a pachinko gaming machine as viewed from the front.

FIG. 2 is a front view showing the front surface of the game board with the glass door frame removed.

FIG. 3 is a rear view of the gaming machine viewed from the back side.

FIG. 4 is a rear view of a mechanism plate to which various members are attached as seen from the rear side of the gaming machine.

FIG. 5 is an exploded perspective view showing a configuration example of a ball payout device.

FIG. 6 is a front view showing a portion of a switch board installed on the game board.

FIG. 7 is a configuration diagram showing an example of a configuration of a clear switch.

FIG. 8 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 9 is a block diagram showing a circuit configuration example of a symbol control board.

FIG. 10 is a block diagram showing a circuit configuration in a lamp control board.

FIG. 11 is a block diagram showing a circuit configuration in the sound control board.

FIG. 12 is a block diagram showing a circuit configuration example of a payout control board.

FIG. 13 is a block diagram showing a circuit configuration example of a power supply board.

FIG. 14 is a block diagram showing an example of the configuration around a CPU for power supply monitoring and power supply backup.

FIG. 15 is an explanatory diagram showing an example of bit allocation of output ports.

FIG. 16 is an explanatory diagram showing an example of bit allocation of output ports.

FIG. 17 is an explanatory diagram showing an example of bit allocation of input ports.

FIG. 18 is a flowchart showing a main process executed by a CPU on a main board.

FIG. 19 is an explanatory diagram showing an example of a relationship between a backup flag and whether or not to execute a game state recovery process.

FIG. 20 is a flowchart showing a game state recovery process.

FIG. 21 is a flowchart showing a 2 ms timer interrupt process.

FIG. 22 is a flowchart showing a special symbol process process.

FIG. 23 is a flowchart showing a starting opening switch passage confirmation process.

FIG. 24 is a flowchart showing a process for determining a variable display stop symbol and a process for determining a reach type.

FIG. 25 is a flowchart showing a process of determining whether or not to make a big hit.

FIG. 26 is an explanatory diagram showing an example of random numbers.

FIG. 27 is an explanatory diagram showing an example of a command form of a control command.

FIG. 28 is a timing diagram showing a relationship between an 8-bit control signal forming a control command and an INT signal.

FIG. 29 is an explanatory diagram showing an example of the contents of a display control command.

FIG. 30 is an explanatory diagram showing an example of contents of a lamp control command.

FIG. 31 is an explanatory diagram showing an example of the content of a sound control command.

FIG. 32 is an explanatory diagram showing a configuration example of a command transmission table.

FIG. 33 is an explanatory diagram showing one configuration example of command data 2 and another configuration example.

FIG. 34 is an explanatory diagram showing a configuration example of INT data.

FIG. 35 is an explanatory diagram showing a configuration example of a command transmission table.

FIG. 36 is a flowchart showing command control processing.

FIG. 37 is a flowchart showing a command transmission processing routine.

FIG. 38 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

FIG. 39 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

FIG. 40 is a flowchart showing non-maskable interrupt processing (power supply stop processing).

FIG. 41 is an explanatory diagram showing an RAM address map.

FIG. 42 is an explanatory diagram illustrating an example of a checksum creation method.

FIG. 43: Power supply drop and N when power supply to a gaming machine is stopped
It is a timing diagram which shows a mode of MI signal.

FIG. 44 is a block diagram illustrating a configuration example of a determination circuit.

FIG. 45 is a timing chart showing a processing timing example of unmaskable interrupt processing.

FIG. 46 is a block diagram illustrating another configuration example of the determination circuit.

FIG. 47 is a timing chart showing a processing timing example of unmaskable interrupt processing.

FIG. 48 is a block diagram showing another configuration example of the determination circuit.

FIG. 49 is a timing chart showing a processing timing example of unmaskable interrupt processing.

FIG. 50 is a flowchart showing another example of unmaskable interrupt processing (power supply stop processing).

FIG. 51 is a block diagram showing another configuration example around the CPU.

FIG. 52 is a block diagram showing a configuration example of a regulation circuit.

FIG. 53 is a timing chart showing a processing timing example of unmaskable interrupt processing.

FIG. 54 is a block diagram showing another configuration example around the CPU.

FIG. 55 is a block diagram showing another configuration example of the regulation circuit.

FIG. 56 is a timing chart showing a processing timing example of unmaskable interrupt processing.

FIG. 57 is a timing chart showing a processing timing example of unmaskable interrupt processing.

FIG. 58 is a block diagram showing a configuration example of a relay board.

[Explanation of symbols]

1 Pachinko machine 31 Main board 35 lamp control board 37 Discharge control board 53 Basic circuit 55 RAM (change data storage means) 56 CPU 70 sound control board 80 symbol control board 371 CPU for payout control 902 Power supply monitoring IC (power supply monitoring means) 910 Power board 916 Capacitor (backup power supply) 950 Judgment circuit 950A, 950B Regulator circuit 950C connector 950a low pass filter 950b flip-flop

Claims (9)

[Claims] 1. A game machine in which a player plays a predetermined game and gives a predetermined game value to the player according to the establishment of a predetermined condition, and a control means for performing control relating to the game is mounted. A control board, a variable data storage means capable of retaining stored contents for a predetermined period even when power supply to a gaming machine is stopped, and an output voltage of a power supply provided outside the control board and having a predetermined potential Then, a power supply monitoring means that outputs a detection signal when the detection condition is satisfied, and a detection signal that is mounted on the control board and that receives the detection signal from the power supply monitoring means and that a predetermined interrupt is given to the control means based on the detection signal. An interrupt signal output circuit for outputting a signal, the control means, based on the state change of the interrupt signal from the interrupt signal output circuit, the data required for recovery of the control state the fluctuation data Save to storage means It is possible to perform a power supply stop process, the interrupt signal output circuit, after outputting an interrupt signal based on the input detection signal, at least for a predetermined period, when the detection signal is input, A gaming machine characterized in that it also holds the output state of the interrupt signal. 2. A payout means for paying out a game medium used for a game, and a payout detection means for detecting the game medium paid out from the payout means, wherein the control means is a power supply stop time process. 2. The game according to claim 1, wherein an input monitoring process for monitoring the input of the detection signal from the payout detecting means can be executed, and the predetermined period includes an input monitoring time during which the input monitoring process is executed. Machine. 3. The game machine according to claim 2, wherein the input monitoring time is set to be a time equal to or longer than a time from when the game medium is paid out from the payout means to when it is detected by the payout detection means. 4. The control means can execute access prohibition processing for prohibiting access to the variable data storage means in the power supply stoppage processing, and the access is started from the start of the power supply stoppage processing for a predetermined period. The gaming machine according to any one of claims 1 to 3, including a period until execution of prohibition processing. 5. A filter circuit is provided between the input portion of the detection signal from the power supply monitoring means on the control board and the interrupt signal output circuit to remove a change in the detection signal within the effective period. 5. The gaming machine according to claim 4. 6. The game according to claim 1, further comprising a power supply board that creates a power supply used in the game machine, wherein the power supply monitoring means is mounted on the power supply board. Machine. 7. The gaming machine according to claim 1, further comprising a system reset circuit that outputs a reset signal for stopping the operation of the control means. 8. The gaming machine according to claim 7, wherein the interrupt signal output circuit changes the interrupt signal based on a reset signal from the system reset circuit. 9. The gaming machine according to claim 1, wherein a non-maskable interrupt terminal is used as an input terminal for inputting an interrupt signal from the interrupt signal output circuit in the control means. .